123 lines
4.0 KiB
LLVM
123 lines
4.0 KiB
LLVM
; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 < %s | FileCheck %s
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; Check support for returning a float in GPR with soft float ABI
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define arm_aapcscc float @zerobits_float_soft() #0 {
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; CHECK-LABEL: zerobits_float_soft
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; CHECK: mov r0, #0
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%1 = tail call float asm "mov ${0}, #0", "=&r"()
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ret float %1
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}
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; Check support for returning a double in GPR with soft float ABI
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define arm_aapcscc double @zerobits_double_soft() #0 {
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; CHECK-LABEL: zerobits_double_soft
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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%1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"()
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; soft float ABI
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define arm_aapcscc float @flt_gpr_matching_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_in_op_soft
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; CHECK: mov r0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_in_op_soft
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; CHECK: mov r1, r0
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
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ret double %1
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}
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; Check support for returning a float in specific GPR with matching float input
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; with soft float ABI
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define arm_aapcscc float @flt_gpr_matching_spec_reg_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r3
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%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
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ret float %1
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}
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; Check support for returning a double in specific GPR with matching double
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; input with soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_spec_reg_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r2
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
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ret double %1
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}
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attributes #0 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="true" }
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; Check support for returning a float in GPR with hard float ABI
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define float @zerobits_float_hard() #1 {
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; CHECK-LABEL: zerobits_float_hard
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; CHECK: mov r0, #0
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; CHECK: vmov s0, r0
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%1 = tail call float asm "mov ${0}, #0", "=&r"()
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ret float %1
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}
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; Check support for returning a double in GPR with hard float ABI
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define double @zerobits_double_hard() #1 {
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; CHECK-LABEL: zerobits_double_hard
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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; CHECK: vmov d0, r0, r1
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%1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"()
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; hard float ABI
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define float @flt_gpr_matching_in_op_hard(float %f) #1 {
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; CHECK-LABEL: flt_gpr_matching_in_op_hard
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; CHECK: vmov r0, s0
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; CHECK: mov r0, r0
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; CHECK: vmov s0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; hard float ABI
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define double @dbl_gpr_matching_in_op_hard(double %d) #1 {
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; CHECK-LABEL: dbl_gpr_matching_in_op_hard
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; CHECK: vmov r0, r1, d0
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; CHECK: mov r1, r0
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; CHECK: vmov d0, r0, r1
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
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ret double %1
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}
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; Check support for returning a float in specific GPR with matching float
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; input with hard float ABI
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define float @flt_gpr_matching_spec_reg_in_op_hard(float %f) #1 {
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; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_hard
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; CHECK: vmov r3, s0
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; CHECK: mov r3, r3
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; CHECK: vmov s0, r3
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%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
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ret float %1
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}
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; Check support for returning a double in specific GPR with matching double
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; input with hard float ABI
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define double @dbl_gpr_matching_spec_reg_in_op_hard(double %d) #1 {
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; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_hard
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; CHECK: vmov r2, r3, d0
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; CHECK: mov r3, r2
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; CHECK: vmov d0, r2, r3
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
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ret double %1
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}
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attributes #1 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="false" }
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