129 lines
4.3 KiB
LLVM
129 lines
4.3 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.fabs.f32(float) #1
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declare double @llvm.fabs.f64(double) #1
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; SI-LABEL: {{^}}test_isinf_pattern:
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; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x204{{$}}
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; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
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; SI-NOT: v_cmp
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; SI: s_endpgm
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define void @test_isinf_pattern(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%fabs = tail call float @llvm.fabs.f32(float %x) #1
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%cmp = fcmp oeq float %fabs, 0x7FF0000000000000
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%ext = zext i1 %cmp to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_not_isinf_pattern_0:
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; SI-NOT: v_cmp_class
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; SI: s_endpgm
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define void @test_not_isinf_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%fabs = tail call float @llvm.fabs.f32(float %x) #1
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%cmp = fcmp ueq float %fabs, 0x7FF0000000000000
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%ext = zext i1 %cmp to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_not_isinf_pattern_1:
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; SI-NOT: v_cmp_class
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; SI: s_endpgm
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define void @test_not_isinf_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%fabs = tail call float @llvm.fabs.f32(float %x) #1
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%cmp = fcmp oeq float %fabs, 0xFFF0000000000000
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%ext = zext i1 %cmp to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_isfinite_pattern_0:
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; SI-NOT: v_cmp
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; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1f8{{$}}
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; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
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; SI-NOT: v_cmp
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; SI: s_endpgm
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define void @test_isfinite_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp une float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; Use negative infinity
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; SI-LABEL: {{^}}test_isfinite_not_pattern_0:
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; SI-NOT: v_cmp_class_f32
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; SI: s_endpgm
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define void @test_isfinite_not_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp une float %x.fabs, 0xFFF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; No fabs
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; SI-LABEL: {{^}}test_isfinite_not_pattern_1:
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; SI-NOT: v_cmp_class_f32
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; SI: s_endpgm
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define void @test_isfinite_not_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%ninf = fcmp une float %x, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; fabs of different value
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; SI-LABEL: {{^}}test_isfinite_not_pattern_2:
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; SI-NOT: v_cmp_class_f32
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; SI: s_endpgm
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define void @test_isfinite_not_pattern_2(i32 addrspace(1)* nocapture %out, float %x, float %y) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %y) #1
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%ninf = fcmp une float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; Wrong ordered compare type
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; SI-LABEL: {{^}}test_isfinite_not_pattern_3:
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; SI-NOT: v_cmp_class_f32
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; SI: s_endpgm
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define void @test_isfinite_not_pattern_3(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp uno float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp une float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; Wrong unordered compare
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; SI-LABEL: {{^}}test_isfinite_not_pattern_4:
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; SI-NOT: v_cmp_class_f32
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; SI: s_endpgm
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define void @test_isfinite_not_pattern_4(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp one float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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