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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel
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Amara Emerson 97c426394a [AArch64][GlobalISel] Implement moreElements legalization for G_SHUFFLE_VECTOR. 
Differential Revision: https://reviews.llvm.org/D103301
 		2021-07-10 00:25:26 -07:00
..
arm64-atomic-128.ll [AtomicExpand] Merge cmpxchg success and failure ordering when appropriate. 2021-06-03 11:34:35 -07:00
arm64-atomic.ll Revert "GlobalISel/AArch64: don't optimize away redundant branches at -O0" 2021-07-09 08:23:36 +05:00
arm64-callingconv-ios.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
arm64-callingconv.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
arm64-fallback.ll GlobalISel: Preserve memory type when reducing load/store width 2021-06-30 17:05:29 -04:00
arm64-irtranslator-fmuladd.ll
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arm64-irtranslator-gep.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
arm64-irtranslator-stackprotect.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
arm64-irtranslator-switch.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
arm64-irtranslator.ll Revert "GlobalISel/AArch64: don't optimize away redundant branches at -O0" 2021-07-09 08:23:36 +05:00
arm64-regbankselect.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
artifact-combine-unmerge.mir [GlobalISel] LegalizationArtifactCombiner: Fix a bug in tryCombineMerges 2020-02-14 10:45:58 -08:00
artifact-find-value.mir [GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions. 2021-07-09 22:35:00 -07:00
builtin-return-address-pacret.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
byval-call.ll Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier" 2021-06-23 09:54:16 +03:00
call-lowering-const-bitcast-func.ll [GlobalISel][CallLowering] Look through bitcasts from constant function pointers. 2020-02-07 15:32:54 -08:00
call-lowering-i128-on-stack.ll [AArch64][GlobalISel] Fall back on attempts to allocate split types on the stack. 2019-09-11 23:53:23 +00:00
call-lowering-i256-crash.ll
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call-lowering-signext.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
call-lowering-vectors.ll [GlobalISel][CallLowering] Fix crash when handling a v3s32 type that's being passed as v2s64. 2021-05-14 16:30:51 -07:00
call-lowering-zeroext.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
call-translator-cse.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
call-translator-ios.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
call-translator-musttail.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
call-translator-tail-call-sret.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
call-translator-tail-call-weak.ll [NFC] Removed unused prefixes in llvm/test/CodeGen/AArch64 2020-12-09 12:47:51 -08:00
call-translator-tail-call.ll GlobalISel: Use LLT in call lowering callbacks 2021-07-01 12:15:54 -04:00
call-translator-variadic-musttail.ll [AArch64][GlobalISel] Select G_ADD_LOW into a MOVaddr pseudo. 2020-06-09 16:47:58 -07:00
call-translator.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
combine-anyext-crash.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
combine-build-vector.mir [GlobalISel] Fold away G_BUILD_VECTOR with all elements extracted. 2021-03-09 11:34:26 -08:00
combine-copy.mir [GlobalISel] CombinerHelper: Fix a bug in matchCombineCopy 2019-12-02 12:05:09 -08:00
combine-ext-debugloc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
combine-ext.mir GlobalISel: Add combines for extend operations 2020-09-01 08:50:06 -07:00
combine-extract-vec-elt.mir [AArch64][GlobalISel] Add combine for extract_vector_elt(build_vector, cst) 2021-03-09 11:08:02 -08:00
combine-fabs.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-fconstant.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
combine-flog2.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-fneg.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-fptrunc.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-fsqrt.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-insert-vec-elt.mir [GISel]: Few InsertVecElt combines 2020-10-28 12:27:07 -07:00
combine-inttoptr-ptrtoint.mir [GISel] Add combiners for G_INTTOPTR and G_PTRTOINT 2020-07-31 10:13:36 -07:00
combine-mul-to-shl.mir [GlobalISel] Add new combine to convert scalar G_MUL to G_SHL. 2020-01-29 13:39:00 -08:00
combine-mul.mir [GISel] Add new GISel combiners for G_MUL 2020-09-15 16:08:47 -07:00
combine-ptradd-int2ptr.mir [GISel] Add combine for constant G_PTR_ADD offsets. 2020-10-13 17:26:12 -07:00
combine-ptradd-reassociation.mir [GlobalISel] Add re-association combine for G_PTR_ADD to allow better addressing mode usage. 2021-07-02 12:31:21 -07:00
combine-ptrtoint.mir [GISel] Add combiners for G_INTTOPTR and G_PTRTOINT 2020-07-31 10:13:36 -07:00
combine-select.mir [GISel] Add new GISel combiners for G_SELECT 2020-08-27 09:40:15 -07:00
combine-sext-debugloc.mir [GlobalISel] Assign the correct location when combining G_SEXT. 2020-05-12 15:32:18 -07:00
combine-sext-trunc-sextload.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
combine-shift-immed-mismatch-crash.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
combine-shl.mir GlobalISel: Combine `op undef, x` to 0 2020-09-08 09:46:38 -07:00
combine-trunc.mir GlobalISel: Fix truncating shift amount in trunc (shl) combine 2020-09-23 09:07:50 -04:00
combine-unmerge.mir [GlobalISel] Add a `X, Y = G_UNMERGE(G_ZEXT Z)` -> X = G_ZEXT Z; Y = 0 combine 2020-09-14 17:27:23 -07:00
combiner-load-store-indexing.ll [GIsel][CombinerHelper] Fix for missed ElideBrByInvertingCond/CombineIndexedLoadStore combines [4/14] 2020-04-22 17:03:40 -07:00
constant-dbg-loc.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
constant-mir-debugify.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
contract-store.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
darwin-tls-call-clobber.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
debug-cpp.ll Revert "[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field" 2020-02-06 14:41:40 +00:00
debug-insts.ll [GlobalISel][test] Add REQUIRES: asserts after D76934 2020-06-11 13:50:56 -07:00
debug-loc-legalize-tail-call.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
dynamic-alloca-lifetime.ll
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dynamic-alloca.ll [Alignment][NFC] Convert MachineIRBuilder::buildDynStackAlloc to Align 2020-04-03 09:05:19 +00:00
fallback-nofastisel.ll
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fconstant-dbg-loc.ll [GlobalISel] Remove debug locations when emitting G_FCONSTANT. 2020-05-11 16:25:03 -07:00
fold-brcond-fcmp.mir [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs 2020-10-01 15:34:16 -07:00
fold-fp-select.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
fold-global-offsets-target-features.mir Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" 2021-03-18 16:01:02 -07:00
fold-global-offsets.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fold-select.mir [AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering 2020-10-22 15:27:36 -07:00
form-bitfield-extract-from-and.mir [GlobalISel][AArch64] Combine and (lshr x, cst), mask -> ubfx x, cst, width 2021-06-01 10:56:17 -07:00
form-bitfield-extract-from-sextinreg.mir [AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX 2021-04-29 21:54:19 -04:00
fp16-copy-gpr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fp128-legalize-crash-pr35690.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
freeze.ll [AArch64][GlobalISel] Add legalizer & selector support for G_FREEZE. 2020-05-18 16:25:33 -07:00
gisel-abort.ll
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gisel-commandline-option-fastisel.ll
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gisel-commandline-option.ll [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0. 2021-05-07 17:01:27 -07:00
gisel-fail-intermediate-legalizer.ll GlobalISel: Implement widenScalar for G_SITOFP/G_UITOFP sources 2019-10-01 01:06:48 +00:00
huge-switch.ll GlobalISel: check type size before getZExtValue()ing it. 2021-02-01 12:43:33 +00:00
implicit_def_rbs_crash.mir [GlobalISel] Fix crash in RBS with a non-generic IMPLICIT_DEF. 2021-03-24 23:08:51 -07:00
inline-asm.ll
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inline-memcpy-forced.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
inline-memcpy.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
inline-memmove.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
inline-memset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
inline-small-memcpy.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
integration-shuffle-vector.ll [AArch64] Provide Darwin variants of most calling conventions 2020-05-20 16:03:48 -07:00
irtranslator-arguments.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-atomic-metadata.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-bitcast.ll
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irtranslator-block-order.ll
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irtranslator-condbr-lower-tree.ll [SimplifyCFG] Tail-merging all blocks with `ret` terminator 2021-06-24 13:15:39 +03:00
irtranslator-convert-fp16-intrinsics.ll GlobalISel: Translate llvm.convert.{to|from}.fp16 intrinsics 2020-07-28 11:46:05 -04:00
irtranslator-dilocation.ll
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irtranslator-duplicate-types-param.ll
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irtranslator-exceptions.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-extends.ll
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irtranslator-extract-used-by-dbg.ll [[GlobalISel][IRTranslator] Fix a crash when the use of an extractvalue is a non-dominated metadata use. 2020-12-12 14:58:54 -08:00
irtranslator-fixed-point-intrinsics.ll GlobalISel: Define mulfix/divfix opcodes 2020-07-24 20:02:20 -04:00
irtranslator-fp-min-max-intrinsics.ll
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irtranslator-indirect-br-repeated-block.ll [GlobalISel] Don't add duplicate successors to MBBs when translating indirectbr 2020-05-08 13:40:02 -07:00
irtranslator-inline-asm.ll [GlobalISel][InlineAsm] Fix matching input constraint to physreg 2020-08-06 14:35:51 +02:00
irtranslator-invoke-probabilities.ll [CodeGen] Add "noreturn" attirbute to _Unwind_Resume 2020-12-24 18:14:18 +07:00
irtranslator-load-metadata.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-localescape.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-max-address-space.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-memcpy-inline.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-memfunc-undef.ll
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irtranslator-no-op-intrinsics.ll Try to fix buildbots after d3205bbca3 2020-10-26 11:49:21 +01:00
irtranslator-no-unwind-inline-asm.ll Support unwinding from inline assembly 2021-05-13 19:13:03 +01:00
irtranslator-one-by-n-vector-ptr-add.ll [GlobalISel] Translate <1 x N> getelementptrs to scalar G_PTR_ADDs 2021-07-01 16:38:47 -07:00
irtranslator-reductions.ll GlobalISel: Use DAG call lowering infrastructure in a more compatible way 2021-05-05 17:35:02 -04:00
irtranslator-split-vector-arg.ll [GISel][CallLowering] Enable vector support in argument lowering 2019-10-11 20:22:57 +00:00
irtranslator-stack-evt-bug47619.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-stack-objects.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-stackprotect-check.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-store-metadata.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-switch-bittest.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-tbaa.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irtranslator-unwind-inline-asm.ll Support unwinding from inline assembly 2021-05-13 19:13:03 +01:00
irtranslator-volatile-load-pr36018.ll
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irtranslator-weird-alloca-size.ll
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labels-are-not-dead.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-abs.mir [AArch64][GlobalISel] Mark some vector G_ABS cases as legal 2021-04-21 18:10:40 -07:00
legalize-add.mir GlobalISel: Avoid use of G_INSERT in insertParts 2021-06-08 14:44:24 -04:00
legalize-and.mir
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legalize-atomicrmw.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-bitreverse.mir [AArch64][GlobalISel] Mark some G_BITREVERSE types as legal + select them 2021-06-10 10:33:52 -07:00
legalize-blockaddress.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-bswap.mir [AArch64][GlobalISel] Tweak legalization rule for G_BSWAP to handle widening s16. 2019-09-25 04:52:42 +00:00
legalize-build-vector.mir [AArch64][GlobalISel] Make <8 x s8> of G_BUILD_VECTOR legal. 2020-09-18 10:32:33 -07:00
legalize-bzero-unsupported.mir [AArch64][GlobalISel] Emit bzero on Darwin 2021-03-25 17:14:25 -07:00
legalize-bzero.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-ceil.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-cmp.mir GlobalISel: Allow CSE of G_IMPLICIT_DEF 2020-02-05 17:47:21 -05:00
legalize-cmpxchg-128.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-cmpxchg-with-success.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-cmpxchg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-combines.mir
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legalize-concat-vectors.mir
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legalize-constant.mir [GlobalISel] Use GCDTy when extracting GCD ty from leftover regs in insertParts 2021-07-09 14:15:44 -07:00
legalize-cos.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-ctlz.mir [AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF. 2021-03-23 12:49:10 -07:00
legalize-ctpop-no-implicit-float.mir [AArch64][GlobalISel] Implement custom legalization for s32 and s64 G_CTPOP 2021-04-19 10:56:02 -07:00
legalize-ctpop.mir [AArch64][GlobalISel] Legalize narrow type G_CTPOPs 2021-05-07 14:52:23 -07:00
legalize-cttz-zero-undef.mir [AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF 2021-06-10 15:29:51 -07:00
legalize-cttz.mir [AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF 2021-06-10 15:29:51 -07:00
legalize-div.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-divrem.mir AArch64: expand G_DIVREM operations in GlobalISel 2021-04-22 15:03:17 +01:00
legalize-dyn-alloca.mir [update_mir_test_checks] Handle MI flags properly 2019-10-14 22:01:58 +00:00
legalize-exceptions.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-exp.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-ext-cse.mir
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legalize-ext-csedebug-output.mir GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper 2021-01-13 10:44:31 -05:00
legalize-ext.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-extload.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-extract-vector-elt.mir GlobalISel: Preserve memory type when reducing load/store width 2021-06-30 17:05:29 -04:00
legalize-extracts.mir
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legalize-fcmp.mir
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legalize-fexp2.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-fma.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-fp-arith.mir [AArch64][GlobalISel] Clamp oversize FP arithmetic vectors. 2020-09-30 18:03:37 -07:00
legalize-fp16-fconstant.mir [AArch64][GlobalISel] Mark G_FCONSTANT as legal when there is full fp16 support 2020-11-11 13:25:11 -08:00
legalize-fp128-fconstant.mir [AArch64][GlobalISel] Add support for FCONSTANT of FP128 type 2021-01-13 10:46:10 -05:00
legalize-fpext.mir GlobalISel: Preserve memory type when reducing load/store width 2021-06-30 17:05:29 -04:00
legalize-fptoi.mir GlobalISel: Restrict narrow scalar for fptoui/fptosi results 2021-04-20 10:54:40 -04:00
legalize-fptrunc.mir GlobalISel: Preserve memory type when reducing load/store width 2021-06-30 17:05:29 -04:00
legalize-freeze.mir [AArch64][GlobalISel] Add some more legal types for G_PHI, G_IMPLICIT_DEF, G_FREEZE. 2020-09-30 17:25:33 -07:00
legalize-frint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-fshl.mir [AArch64][GlobalISel] Lower G_FSHL and G_FSHR. 2021-03-23 16:09:19 -07:00
legalize-fshr.mir [AArch64][GlobalISel] Add test for G_FSHR legalization. 2021-03-23 16:11:45 -07:00
legalize-global-pic.mir Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" 2021-03-18 16:01:02 -07:00
legalize-global.mir Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" 2021-03-18 16:01:02 -07:00
legalize-ignore-hint.mir [GlobalISel] Add G_ASSERT_ZEXT 2021-01-28 13:58:37 -08:00
legalize-ignore-non-generic.mir
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legalize-insert-vector-elt.mir [AArch64][GlobalISel] Make <8 x s16> for G_INSERT_VECTOR_ELT legal. 2020-09-25 01:59:16 -07:00
legalize-inserts.mir [GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions. 2021-07-09 22:35:00 -07:00
legalize-intrinsic-min-max.mir [AArch64][GlobalISel] Lower scalar G_{SMIN, SMAX, UMIN, UMAX}. 2021-03-09 10:03:16 -08:00
legalize-intrinsic-round.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-intrinsic-trunc.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-inttoptr-xfail-1.mir Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
legalize-inttoptr-xfail-2.mir Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
legalize-itofp.mir GlobalISel: Handle arbitrary FewerElementsVector for G_IMPLICIT_DEF 2020-08-03 09:14:08 -04:00
legalize-load-store-fewerElts.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-load-store-vector-of-ptr-debugloc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-load-store-vector-of-ptr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-load-store.mir GlobalISel: Use LLT in memory legality queries 2021-06-30 17:44:13 -04:00
legalize-load-trunc.mir GlobalISel: Use LLT in memory legality queries 2021-06-30 17:44:13 -04:00
legalize-log.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-log2.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-log10.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-lrint.mir [AArch64][GlobalISel] Add legalization & selection support for G_INTRINSIC_LRINT. 2020-07-30 16:14:56 -07:00
legalize-memcpy-et-al.mir GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
legalize-memcpy-with-debug-info.mir GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
legalize-memlib-debug-loc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-merge-values.mir [AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64. 2020-09-27 01:53:26 -07:00
legalize-min-max.mir [AArch64][GlobalISel] Lower vector types for min/max 2021-07-07 15:34:03 +01:00
legalize-mul.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-nearbyint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-non-pow2-load-store.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-or.mir
…
legalize-phi-insertpt-decrement.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-phi.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-pow.mir [AArch64] Fix GlobalISel tests on non-darwin platforms 2020-05-20 16:26:58 -07:00
legalize-property.mir
…
legalize-ptr-add.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-reduce-add.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-reduce-fadd.mir [GlobalISel] Implement fewerElements legalization for vector reductions. 2021-03-30 11:19:21 -07:00
legalize-rem.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-rotr-rotl.mir [AArch64][GlobalISel] Define some legalization rules for G_ROTR and G_ROTL. 2021-03-30 11:11:19 -07:00
legalize-s128-div.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-sadde.mir [Test][AArch64] Test SADDE/SSUBE/UADDE/USUBE narrowing legalization 2021-02-22 19:59:36 -05:00
legalize-saddo.mir [Test][AArch64] Test SADDO/SSUBO narrowing legalization 2021-02-24 02:41:04 -05:00
legalize-sbfx.mir [GlobalISel] Allow different types for G_SBFX and G_UBFX operands 2021-04-02 11:11:06 -04:00
legalize-select.mir [AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with scalar mask. 2020-11-30 16:37:49 -08:00
legalize-sext-128.ll
…
legalize-sext-128.mir
…
legalize-sext-copy.mir
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legalize-sext-zext-128.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-sext.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-sextload.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-shift-imm-promote-dloc.mir [AArch64][GlobalISel] Add more specific debug info tests for 613f12dd8e. 2020-07-09 17:13:16 -07:00
legalize-shift.mir [AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support. 2020-10-01 14:21:18 -07:00
legalize-shuffle-vector.mir [AArch64][GlobalISel] Implement moreElements legalization for G_SHUFFLE_VECTOR. 2021-07-10 00:25:26 -07:00
legalize-simple.mir GlobalISel: Verify G_BITCAST changes the type 2020-07-08 17:16:27 -04:00
legalize-sin.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-sqrt.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-ssube.mir [Test][AArch64] Test SADDE/SSUBE/UADDE/USUBE narrowing legalization 2021-02-22 19:59:36 -05:00
legalize-ssubo.mir [Test][AArch64] Test SADDO/SSUBO narrowing legalization 2021-02-24 02:41:04 -05:00
legalize-sub.mir [Test][AArch64] Move overflow add/sub tests to their own file. NFC 2021-01-25 22:02:31 -05:00
legalize-uadd-sat.mir [AArch64][GlobalISel] Lower G_USUBSAT and G_UADDSAT for scalars. 2021-02-23 11:54:52 -08:00
legalize-uadde.mir [Test][AArch64] Test SADDE/SSUBE/UADDE/USUBE narrowing legalization 2021-02-22 19:59:36 -05:00
legalize-uaddo.mir [AArch64][GlobalISel] Make overflow legalization use clampScalar 2021-02-22 19:59:36 -05:00
legalize-ubfx.mir [GlobalISel] Allow different types for G_SBFX and G_UBFX operands 2021-04-02 11:11:06 -04:00
legalize-undef.mir GlobalISel: Handle arbitrary FewerElementsVector for G_IMPLICIT_DEF 2020-08-03 09:14:08 -04:00
legalize-unmerge-values.mir [AArch64][GlobalISel] Use the look-through constant helper for the shift s32->s64 custom legalization. 2020-09-27 01:25:03 -07:00
legalize-usub-sat.mir [AArch64][GlobalISel] Lower G_USUBSAT and G_UADDSAT for scalars. 2021-02-23 11:54:52 -08:00
legalize-usube.mir [Test][AArch64] Test SADDE/SSUBE/UADDE/USUBE narrowing legalization 2021-02-22 19:59:36 -05:00
legalize-usubo.mir [AArch64][GlobalISel] Make overflow legalization use clampScalar 2021-02-22 19:59:36 -05:00
legalize-vaarg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalize-vector-cmp.mir [AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP. 2020-10-01 15:20:09 -07:00
legalize-vector-ctpop.mir [AArch64][GlobalISel] Fix a crash during unsuccessful G_CTPOP <2 x s64> legalization. 2021-05-13 17:28:11 -07:00
legalize-vector-shift.mir [AArch64][GlobalISel] Make <4 x s32> G_ASHR and G_LSHR legal. 2019-09-21 09:21:10 +00:00
legalize-xor.mir
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legalize-zextload.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalizer-combiner-zext-trunc-crash.mir [Legalizer] Making artifact combining order-independent 2019-12-13 15:45:18 -08:00
legalizer-combiner.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalizer-info-validation.mir Relax newly added opcode check to check only for a number instead of a specific opcode. 2021-07-01 23:09:25 -07:00
lifetime-marker-no-dce.mir [GlobalISel] Don't DCE LIFETIME_START/LIFETIME_END markers. 2021-03-17 18:02:08 -07:00
load-addressing-modes.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
load-wro-addressing-modes.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
localizer-arm64-tti.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
localizer-in-O0-pipeline.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
localizer.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
lower-neon-vector-fcmp.mir [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps 2021-05-10 15:40:06 -07:00
machine-cse-mid-pipeline.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
memcpy_chk_no_tail.ll Add an operand to memory intrinsics to denote the "tail" marker. 2019-09-28 05:33:21 +00:00
no-neon-no-fp.ll [AArch64][GlobalISel] Fall back if disabling neon/fp in the translator. 2021-03-17 15:08:08 -07:00
no-regclass.mir
…
non-pow-2-extload-combine.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
observer-change-crash.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
opt-and-tbnz-tbz.mir [AArch64][GlobalISel] Select Bcc when it's better than TB(N)Z 2020-12-01 15:45:14 -08:00
opt-fold-and-tbz-tbnz.mir [AArch64][GlobalISel] Avoid copies to target register bank for subregister copies 2020-03-05 11:13:02 -08:00
opt-fold-compare.mir [AArch64][GlobalISel] Don't explicitly write to the zero register in emitCMN 2020-12-08 10:42:05 -08:00
opt-fold-ext-tbz-tbnz.mir [AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT 2021-05-18 10:00:00 -07:00
opt-fold-shift-tbz-tbnz.mir [AArch64][GlobalISel] Avoid copies to target register bank for subregister copies 2020-03-05 11:13:02 -08:00
opt-fold-trunc-tbz-tbnz.mir [AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg 2020-01-31 11:09:55 -08:00
opt-fold-xor-tbz-tbnz.mir [AArch64][GlobalISel] Fold G_XOR into TB(N)Z bit calculation 2020-02-03 15:22:24 -08:00
opt-overlapping-and.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
opt-shifted-reg-compare.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
phi-mir-debugify.mir [Debugify] Support checking Machine IR debug info 2020-12-16 22:17:25 -08:00
postlegalizer-combiner-and-trivial-mask.mir [GlobalISel] Implement computeKnownBits for G_ASSERT_ZEXT 2021-01-28 16:34:34 -08:00
postlegalizer-combiner-copy-prop.mir [GlobalISel] Enable copy-propagation in post-legalizer combiner. 2020-08-15 13:44:30 -07:00
postlegalizer-combiner-redundant-sextinreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
postlegalizer-combiner-store-undef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
postlegalizer-lowering-adjust-icmp-imm.mir [AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering 2020-10-22 15:27:36 -07:00
postlegalizer-lowering-build-vector-to-dup.mir [AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP 2021-03-08 13:01:10 -08:00
postlegalizer-lowering-ext.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-rev.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-shuf-to-ins.mir Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt" 2021-02-23 11:55:16 -08:00
postlegalizer-lowering-shuffle-duplane.mir [AArch64][GlobalISel] Form G_DUPLANE32 for <2 x s32> shufflevectors in lowering. 2021-03-09 11:36:26 -08:00
postlegalizer-lowering-shuffle-splat.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-swap-compare-operands.mir [AArch64][GlobalISel] Swap compare operands when it may be profitable 2021-04-09 15:46:48 -07:00
postlegalizer-lowering-trn.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-truncstore.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
postlegalizer-lowering-uzp.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-vashr-vlshr.mir [AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP 2021-03-08 13:01:10 -08:00
postlegalizer-lowering-zip.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizercombiner-extending-loads.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
postlegalizercombiner-extractvec-faddp.mir [AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD. 2020-11-03 17:25:14 -08:00
postlegalizercombiner-hoist-same-hands.mir [GlobalISel] Combine (logic_op (op x...), (op y...)) -> (op (logic_op x, y)) 2020-08-11 10:40:06 -07:00
postlegalizercombiner-mulpow2.mir [AArch64][GlobalISel] Don't perform the mul const combine with G_PTR_ADD 2021-02-10 15:30:45 -08:00
postlegalizercombiner-rotate.mir [AArch64][GlobalISel] Simplify out of range rotate amount. 2021-04-29 14:05:58 -07:00
postselectopt-constrain-new-regop.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
postselectopt-dead-cc-defs-in-fcmp.mir [AArch64][GlobalISel] Introduce a new post-isel optimization pass. 2020-10-23 10:18:36 -07:00
prelegalizer-combiner-divrem-insertpt-crash.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizer-combiner-icmp-to-true-false-known-bits.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizer-combiner-load-or-pattern-align.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizer-combiner-load-or-pattern.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizercombiner-ashr-shl-to-sext-inreg.mir [GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c' 2020-08-18 10:42:15 -07:00
prelegalizercombiner-binop-same-val.mir [GlobalISel] Implement identity transforms for x op x -> x 2020-03-30 18:22:37 -07:00
prelegalizercombiner-br.mir [GlobalISel] Check if branches use the same MBB in matchOptBrCondByInvertingCond 2021-02-02 15:38:48 -08:00
prelegalizercombiner-bzero.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizercombiner-concat-vectors.mir [GISel]: Few InsertVecElt combines 2020-10-28 12:27:07 -07:00
prelegalizercombiner-copy-prop-disabled.mir [gicombiner] Allow disable-rule option to disable all-except-... 2020-06-16 16:57:16 -07:00
prelegalizercombiner-extending-loads-cornercases.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizercombiner-extending-loads-s1.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizercombiner-extending-loads.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizercombiner-funnel-shifts-to-rotates.mir [AArch64][GlobalISel] Combine funnel shifts to rotates. 2021-03-30 11:00:36 -07:00
prelegalizercombiner-hoist-same-hands.mir [GlobalISel] Combine (logic_op (op x...), (op y...)) -> (op (logic_op x, y)) 2020-08-11 10:40:06 -07:00
prelegalizercombiner-icmp-redundant-trunc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizercombiner-invert-cmp.mir [GlobalISel] Extend not_cmp_fold to work on conditional expressions 2020-09-07 09:31:08 +01:00
prelegalizercombiner-not-really-equiv-insts.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizercombiner-prop-extends-phi.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizercombiner-ptradd-chain.mir [AArch64][GlobalISel] Fold a chain of two G_PTR_ADDs of constant offsets. 2020-01-07 14:12:42 -08:00
prelegalizercombiner-select.mir Recommit "[GlobalISel] Walk through hints in getDefIgnoringCopies et al" 2021-01-28 14:43:00 -08:00
prelegalizercombiner-sextload-from-sextinreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prelegalizercombiner-shuffle-vector.mir [GlobalISel] Change representation of shuffle masks in MachineOperand. 2020-01-13 16:55:41 -08:00
prelegalizercombiner-simplify-add.mir [GlobalISel] Simplify G_ADD when it has (0-X) on the LHS or RHS 2020-06-15 09:43:24 -07:00
prelegalizercombiner-trivial-arith.mir [GlobalISel] Combine (x + 0) -> x, G_PTR_ADD edition 2021-02-12 12:09:48 -08:00
prelegalizercombiner-undef.mir [GlobalISel] Port some basic shufflevector undef combines from the DAGCombiner 2020-03-19 16:46:06 -07:00
prelegalizercombiner-xor-of-and-with-same-reg.mir [GlobalISel] Combine (xor (and x, y), y) -> (and (not x), y) 2020-09-28 10:08:14 -07:00
preselect-process-phis.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
reg-bank-128bit.mir
…
regbank-assert-sext.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regbank-assert-zext.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regbank-ceil.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regbank-dup.mir [AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr. 2021-02-21 21:17:29 -08:00
regbank-extract-vector-elt.mir [AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b. 2020-09-17 11:50:33 -07:00
regbank-extract.mir AArch64: support i128 cmpxchg in GlobalISel. 2021-05-14 10:41:38 +01:00
regbank-fcmp.mir [AArch64][GlobalISel] Fix regbankselect for G_FCMP with vector destinations 2021-04-21 18:11:30 -07:00
regbank-fma.mir [update_mir_test_checks] Handle MI flags properly 2019-10-14 22:01:58 +00:00
regbank-fp-use-def.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regbank-inlineasm.mir [GlobalISel][InlineAsm] Add support for basic output operand constraints 2020-05-06 10:06:13 +02:00
regbank-insert-vector-elt.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-intrinsic-round.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-intrinsic-trunc.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-intrinsic.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regbank-nearbyint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-select.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-shift-imm-64.mir
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regbank-trunc-s128.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbankselect-build-vector.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regbankselect-dbg-value.mir
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regbankselect-default.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regbankselect-reductions.mir [AArch64][GlobalISel] Regbankselect reductions to use FPR bank for scalars. 2020-10-16 10:42:15 -07:00
regbankselect-reg_sequence.mir
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regbankselect-unmerge-vec.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
ret-1x-vec.ll GlobalISel: Merge and cleanup more AMDGPU call lowering code 2021-03-02 17:31:13 -05:00
ret-vec-promote.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
retry-artifact-combine.mir [Legalizer] Making artifact combining order-independent 2019-12-13 15:45:18 -08:00
select-abs.mir [AArch64][GlobalISel] Mark some vector G_ABS cases as legal 2021-04-21 18:10:40 -07:00
select-add-low.mir Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" 2021-03-18 16:01:02 -07:00
select-arith-extended-reg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-arith-shifted-reg.mir
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select-atomic-load-store.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-atomicrmw.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-binop.mir [AArch64][GlobalISel] Add tests for pre-existing selection support for <4 x s16> arithmetic/bitwise ops. 2020-09-18 17:13:55 -07:00
select-bitcast-bigendian.mir
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select-bitcast.mir GlobalISel: Verify G_BITCAST changes the type 2020-07-08 17:16:27 -04:00
select-bitfield-insert.ll [AArch64][GISel] and+or+shl => bfi 2021-06-17 12:52:59 -07:00
select-bitreverse.mir [AArch64][GlobalISel] Mark some G_BITREVERSE types as legal + select them 2021-06-10 10:33:52 -07:00
select-blockaddress.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-br.mir
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select-brcond-of-binop.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-bswap.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-build-vector.mir [AArch64][GlobalISel] Select all-zero G_BUILD_VECTOR into a zero mov. 2020-09-30 23:53:38 -07:00
select-cbz.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-ceil.mir
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select-cmp.mir [AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT 2021-05-18 10:00:00 -07:00
select-cmpxchg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-concat-vectors.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-const-pool.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-const-vector.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-constant.mir [GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less. 2020-09-09 13:08:16 -07:00
select-ctlz.mir [AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF. 2021-03-23 12:49:10 -07:00
select-ctpop.mir [AArch64][GlobalISel] Mark G_CTPOP as legal for v16s8 and v8s8 2021-04-13 11:03:39 -07:00
select-dbg-value.mir
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select-dup.mir [AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP 2021-03-08 13:01:10 -08:00
select-ext.mir [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects. 2021-05-11 12:38:53 -07:00
select-extload.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-extract-vector-elt.mir [AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal. 2020-11-20 14:07:45 -08:00
select-extract.mir
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select-fabs.mir
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select-faddp.mir [AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD. 2020-11-03 17:25:14 -08:00
select-fcmp.mir AArch64: fix regression introduced by fcmp immediate selection. 2021-01-15 22:53:25 -08:00
select-floor.mir
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select-fma.mir
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select-fmul-indexed.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-fp-casts.mir AArch64: support mixed-size fp <-> int conversions in GlobalISel. 2021-04-22 15:03:17 +01:00
select-fp16-fconstant.mir [AArch64][GlobalISel] Import FMOV patterns rather than manually selecting it 2021-02-26 16:27:39 -08:00
select-frameaddr.ll Revert "Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: Support @llvm.{return,frame}address selection."" 2020-01-15 10:13:11 -08:00
select-frint-nofp16.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-frint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-gv-cmodel-large.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-gv-cmodel-tiny.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-gv-with-offset.mir Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" 2021-03-18 16:01:02 -07:00
select-hint.mir [GlobalISel] Add G_ASSERT_SEXT 2021-02-17 13:10:34 -08:00
select-imm.mir [AArch64][GlobalISel] Enable use of the optsize predicate in the selector. 2021-03-02 12:55:51 -08:00
select-implicit-def.mir
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select-insert-extract.mir
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select-insert-vector-elt.mir Revert "Revert "[AArch64][GlobalISel] Add selection support for <8 x s16> G_INSERT_VECTOR_ELT with GPR scalar."" 2020-09-28 13:44:51 -07:00
select-int-ext.mir [AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT 2021-05-18 10:00:00 -07:00
select-int-ptr-casts.mir
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select-intrinsic-aarch64-hint.mir
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select-intrinsic-aarch64-sdiv.mir
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select-intrinsic-crypto-aesmc.mir
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select-intrinsic-round.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-intrinsic-trunc.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-intrinsic-uaddlv.mir [AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv 2021-04-19 10:47:49 -07:00
select-jump-table-brjt-constrain.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-jump-table-brjt.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
select-ldaxr-intrin.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-ldxr-intrin.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-load-store-vector-of-ptr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-load.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-logical-imm.mir
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select-logical-shifted-reg.mir
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select-mul.mir
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select-muladd.mir
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select-nearbyint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-neon-vcvtfxu2fp.mir
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select-neon-vector-fcmp.mir [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps 2021-05-10 15:40:06 -07:00
select-phi.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-pr32733.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-property.mir
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select-ptr-add.mir [AArch64][GlobalISel] Optimize G_PTR_ADD with a negated offset to be a G_SUB. 2020-11-11 22:46:53 -08:00
select-reduce-add.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-reduce-fadd.mir [AArch64][GlobalISel] Add selection support for v2s32 and v2s64 reductions for FADD/ADD. 2020-10-16 11:41:57 -07:00
select-redundant-zext-of-load.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-redundant-zext.mir [AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT 2021-05-18 10:00:00 -07:00
select-returnaddr.ll [AArch64][GlobalISel] Implement __builtin_return_address for PAC-RET 2020-09-24 18:04:37 +01:00
select-returnaddress-liveins.mir [AArch64][GlobalISel] Implement __builtin_return_address for PAC-RET 2020-09-24 18:04:37 +01:00
select-rev.mir [AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes 2020-06-12 09:39:46 -07:00
select-saddo.mir Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it." 2021-01-22 17:29:54 -08:00
select-sbfx.mir [AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX 2021-04-29 21:54:19 -04:00
select-scalar-merge.mir
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select-scalar-shift-imm.mir
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select-select.mir [AArch64][GlobalISel] Fold selects fed by G_PTR_ADD 2021-02-10 00:03:13 -08:00
select-sextload.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-shuffle-vector.mir [AArch64][GlobalISel] Selection support for vector DUP[X]lane instructions. 2020-07-29 11:41:37 -07:00
select-shufflevec-undef-mask-elt.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-sqrt.mir
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select-ssubo.mir Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it." 2021-01-22 17:29:54 -08:00
select-static.mir [AArch64][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:03:06 -08:00
select-stlxr-intrin.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-store.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-stx.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-trap.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-trn.mir [AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes 2020-06-12 09:39:46 -07:00
select-trunc.mir
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select-uaddo.mir [AArch64][GlobalISel] Select arith extended add/sub in manual selection code 2020-11-11 09:26:03 -08:00
select-ubfx.mir [AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX 2021-04-29 21:54:19 -04:00
select-unmerge.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-usubo.mir Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it." 2021-01-22 17:29:54 -08:00
select-uzp.mir [AArch64][GlobalISel] Select uzp1 and uzp2 2020-06-03 15:09:41 -07:00
select-vector-icmp.mir [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads. 2020-06-23 19:23:47 -07:00
select-vector-shift.mir [AArch64][GlobalISel] Fix incorrect codegen for <16 x s8> G_ASHR. 2021-04-09 10:41:41 -07:00
select-with-no-legality-check.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-xor.mir [AArch64][GlobalISel] Don't emit a branch for a fallthrough G_BR at -O0. 2020-09-10 15:01:26 -07:00
select-zext-as-copy.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-zextload.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-zip.mir [AArch64][GlobalISel] Select zip1 and zip2 2020-06-02 18:57:11 -07:00
select.mir [test] Split some tests which test both static and pic relocation models 2020-12-04 18:11:35 -08:00
sext-inreg-ldrow-16b.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
speculative-hardening-brcond.mir [AArch64][GlobalISel] Refactor G_BRCOND selection 2020-12-07 17:24:23 -08:00
store-addressing-modes.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
store-wro-addressing-modes.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
subreg-copy.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
swifterror.ll [SimplifyCFG] Tail-merging all blocks with `ret` terminator 2021-06-24 13:15:39 +03:00
swiftself.ll OpaquePtr: Update more tests to use typed sret 2020-11-20 20:08:43 -05:00
tail-call-no-save-fp-lr.ll llc: Don't overwrite frame-pointer attribute 2020-01-15 20:56:46 -05:00
tbnz-slt.mir [AArch64][GlobalISel] Select Bcc when it's better than TB(N)Z 2020-12-01 15:45:14 -08:00
tbz-sgt.mir [AArch64][GlobalISel] Select negative arithmetic immediates in manual selector 2020-11-11 09:20:05 -08:00
translate-constant-dag.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
translate-gep.ll Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types" 2020-03-30 19:30:42 -04:00
ubsantrap.ll AArch64: use correct operand for ubsantrap immediate. 2020-12-09 10:17:16 +00:00
unknown-intrinsic.ll
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unwind-inline-asm.ll Support unwinding from inline assembly 2021-05-13 19:13:03 +01:00
varargs-ios-translator.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vastart.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vec-s16-param.ll [AArch64][GlobalISel] Support lowering <1 x i8> arguments. 2021-02-22 13:58:44 -08:00
widen-narrow-tbz-tbnz.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
xro-addressing-mode-constant.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00