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AsmParser
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[RISCV] Implement support for the Zicbop extension
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2022-06-28 12:43:26 +01:00 |
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Disassembler
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Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
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2022-05-15 08:44:58 +08:00 |
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MCTargetDesc
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[RISCV][NFC] Use nested namespace definations.
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2022-08-13 09:56:59 +08:00 |
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TargetInfo
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[RISCV] Re-enable JIT support
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2022-08-11 11:41:02 +02:00 |
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CMakeLists.txt
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[RISCV] Add a RISCV specific CodeGenPrepare pass.
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2022-07-14 10:20:59 -07:00 |
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RISCV.h
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[RISCV] Pre-RA expand pseudos pass
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2022-07-31 23:19:00 +02:00 |
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RISCV.td
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[RISCV] Add target feature to force-enable atomics
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2022-08-09 16:04:46 +02:00 |
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RISCVAsmPrinter.cpp
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[CodeGen] Move instruction predicate verification to emitInstruction
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2022-07-14 09:33:28 +01:00 |
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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…
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RISCVCallingConv.td
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…
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RISCVCodeGenPrepare.cpp
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[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
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2022-08-12 22:21:05 -07:00 |
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RISCVExpandAtomicPseudoInsts.cpp
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[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
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2022-01-28 09:51:49 -08:00 |
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RISCVExpandPseudoInsts.cpp
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[RISCV] Pre-RA expand pseudos pass
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2022-07-31 23:19:00 +02:00 |
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RISCVFrameLowering.cpp
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Use llvm::none_of (NFC)
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2022-08-14 16:25:39 -07:00 |
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RISCVFrameLowering.h
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[RISCV][NFCI] Set TransientStackAlignment and rely on it rather than RVV-specific logic on RVV-less functions
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2022-08-02 09:46:06 +01:00 |
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RISCVGatherScatterLowering.cpp
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[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
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2022-06-10 13:00:20 -07:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV][NFC] Use nested namespace definations.
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2022-08-13 09:56:59 +08:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Peephole optimization to fold merge.vvm and unmasked intrinsics.
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2022-08-11 17:58:11 +08:00 |
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RISCVISelLowering.cpp
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[RISCV] Fold (sub constant, (setcc x, y, eq/neq)) -> (add constant - 1, (setcc x, y, neq/eq))
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2022-08-13 20:37:57 +08:00 |
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RISCVISelLowering.h
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[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
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2022-08-10 10:50:29 +01:00 |
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RISCVInsertVSETVLI.cpp
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[RISCVInsertVSETVLI] Remove an unsound optimization
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2022-08-05 12:13:08 -07:00 |
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RISCVInstrFormats.td
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[RISCV] Support mask policy for RVV IR intrinsics.
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2022-03-22 01:19:16 -07:00 |
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
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[RISCV][NFC] Use nested namespace definations.
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2022-08-13 09:56:59 +08:00 |
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RISCVInstrInfo.h
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Remove redundaunt virtual specifiers (NFC)
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2022-07-25 23:00:59 -07:00 |
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RISCVInstrInfo.td
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[RISCV] Use SLTIU X, -1 for (setne X, -1).
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2022-08-11 15:36:04 -07:00 |
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RISCVInstrInfoA.td
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[RISCV] Add target feature to force-enable atomics
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2022-08-09 16:04:46 +02:00 |
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RISCVInstrInfoC.td
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[RISCV] Add Predicate to c.lw/c.sw/c.lwsp/c.swsp InstAliases with no offset.
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2022-07-26 11:06:00 -07:00 |
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RISCVInstrInfoD.td
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[RISCV] Explicitly select second operand of branch condition to X0.
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2022-08-01 11:16:48 -07:00 |
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RISCVInstrInfoF.td
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[RISCV] Add ReadFStoreData as a SchedRead.
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2022-08-08 09:33:19 -07:00 |
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RISCVInstrInfoM.td
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[RISCV][Clang] Add support for Zmmul extension
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2022-07-18 20:26:08 -04:00 |
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RISCVInstrInfoV.td
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[RISCV] Add scheduling resources for vector segment instructions.
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2022-07-12 22:51:58 -07:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV] Peephole optimization to fold merge.vvm and unmasked intrinsics.
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2022-08-11 17:58:11 +08:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Increase complexity of RVV element extraction patterns
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2022-07-11 10:53:15 +08:00 |
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RISCVInstrInfoVVLPatterns.td
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[RISCV] Add merge operands to more RISCVISD::*_VL opcodes.
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2022-07-30 10:26:38 -07:00 |
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RISCVInstrInfoZb.td
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[RISCV] Don't use li+sh3add for constants that can use lui+add.
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2022-08-05 12:47:03 -07:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Explicitly select second operand of branch condition to X0.
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2022-08-01 11:16:48 -07:00 |
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RISCVInstrInfoZicbo.td
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[RISCV] Implement support for the Zicbop extension
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2022-06-28 12:43:26 +01:00 |
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RISCVInstrInfoZk.td
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[RISCV] Adjust some comments.
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2022-02-01 22:53:54 +08:00 |
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RISCVInstructionSelector.cpp
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[Target] Remove redundant member initialization (NFC)
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2022-01-06 22:01:44 -08:00 |
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
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[RISCV] Pre-RA expand pseudos pass
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2022-07-31 23:19:00 +02:00 |
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RISCVMachineFunctionInfo.cpp
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llvm-reduce: Add cloning of target MachineFunctionInfo
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2022-06-07 10:14:48 -04:00 |
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RISCVMachineFunctionInfo.h
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llvm-reduce: Add cloning of target MachineFunctionInfo
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2022-06-07 10:14:48 -04:00 |
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RISCVMacroFusion.cpp
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[RISCV] Add macrofusion infrastructure and one example usage.
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2022-06-23 08:38:39 -07:00 |
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RISCVMacroFusion.h
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[RISCV] Add macrofusion infrastructure and one example usage.
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2022-06-23 08:38:39 -07:00 |
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RISCVMakeCompressible.cpp
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[RISCV] Fix wrong register rename for store value during make-compressible optimization
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2022-07-08 18:07:17 +08:00 |
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RISCVMergeBaseOffset.cpp
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[RISCV] Fix operand number in debug message in RISCVMergeBaseOffset.
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2022-08-02 15:27:23 -07:00 |
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RISCVRedundantCopyElimination.cpp
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[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
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2022-02-04 10:43:46 -08:00 |
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RISCVRegisterBankInfo.cpp
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[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
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2022-03-27 22:22:37 -07:00 |
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RISCVRegisterBankInfo.h
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[nfc][codegen] Move RegisterBank[Info].h under CodeGen
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2022-03-01 21:53:25 -08:00 |
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
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2022-07-03 20:18:13 +08:00 |
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RISCVRegisterInfo.h
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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RISCVRegisterInfo.td
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[RISCV] Add llvm.read.register support for vlenb
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2022-05-13 09:12:02 -07:00 |
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RISCVSExtWRemoval.cpp
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[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC
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2022-08-08 11:24:15 -07:00 |
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RISCVSchedRocket.td
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[RISCV] Add ReadFStoreData as a SchedRead.
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2022-08-08 09:33:19 -07:00 |
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RISCVSchedSiFive7.td
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[RISCV] Add ReadFStoreData as a SchedRead.
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2022-08-08 09:33:19 -07:00 |
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RISCVSchedule.td
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[RISCV] Add ReadFStoreData as a SchedRead.
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2022-08-08 09:33:19 -07:00 |
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RISCVScheduleB.td
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[RISCV] Add schedule class for Zbp extension and Zbr extension
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2022-03-01 07:35:59 +00:00 |
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RISCVScheduleV.td
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[RISCV] Add scheduler class to PseudoReadVLENB.
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2022-08-02 09:38:32 -07:00 |
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RISCVSubtarget.cpp
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[RISCV] Disable subregister liveness by default
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2022-07-14 17:04:10 +01:00 |
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RISCVSubtarget.h
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[RISCV] Add target feature to force-enable atomics
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2022-08-09 16:04:46 +02:00 |
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RISCVSystemOperands.td
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[RISCV] Initially support the K-extension instructions on the LLVM MC layer
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2022-01-24 14:45:35 +08:00 |
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RISCVTargetMachine.cpp
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[RISCV] Move Pre-RA pseudo expansion from addMachineSSAOptimization to addPreRegAlloc.
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2022-08-01 13:44:43 -07:00 |
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RISCVTargetMachine.h
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[llvm] Remove redundaunt virtual specifiers (NFC)
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2022-07-24 21:50:35 -07:00 |
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[RISCV] Add cost model for mask vector extend and truncate instruction.
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2022-08-11 10:55:43 +08:00 |
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RISCVTargetTransformInfo.h
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[RISCV] Add cost modelling for vector widenning reduction.
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2022-08-04 15:31:31 +08:00 |
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