llvm-project/llvm/test/Transforms/LoopVectorize/AArch64
Dorit Nuzman bf2c15b5dc Second attempt at r285517.
llvm-svn: 285568
2016-10-31 13:17:31 +00:00
..
aarch64-unroll.ll
arbitrary-induction-step.ll [LV] Unify vector and scalar maps 2016-08-24 18:23:17 +00:00
arm64-unroll.ll
backedge-overflow.ll Re-commit [SCEV] Introduce a guarded backedge taken count and use it in LAA and LV 2016-04-08 14:29:09 +00:00
deterministic-type-shrinkage.ll
first-order-recurrence.ll [LV] Move insertelement sequence after scalar definitions 2016-08-29 20:14:04 +00:00
gather-cost.ll Second attempt at r285517. 2016-10-31 13:17:31 +00:00
interleaved_cost.ll Reapply "[TTI] Refine default cost for interleaved load groups with gaps" 2016-06-10 14:33:30 +00:00
lit.local.cfg
loop-vectorization-factors.ll Revert "[VectorUtils] Query number of sign bits to allow more truncations" 2016-05-10 12:27:23 +00:00
max-vf-for-interleaved.ll [LAA] Rename forwarding conflict detection option (NFC) 2016-05-16 17:00:56 +00:00
predication_costs.ll [LV] Correct misleading comments in test (NFC) 2016-10-28 14:27:45 +00:00
reduction-small-size.ll
sdiv-pow2.ll
type-shrinkage-insertelt.ll [LV] Add support for insertelt/extractelt processing during type truncation 2016-02-15 15:38:17 +00:00