183 lines
7.0 KiB
C++
183 lines
7.0 KiB
C++
//===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that AVR uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_AVR_ISEL_LOWERING_H
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#define LLVM_AVR_ISEL_LOWERING_H
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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namespace AVRISD {
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/// AVR Specific DAG Nodes
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enum NodeType {
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/// Start the numbering where the builtin ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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/// Return from subroutine.
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RET_FLAG,
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/// Return from ISR.
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RETI_FLAG,
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/// Represents an abstract call instruction,
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/// which includes a bunch of information.
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CALL,
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/// A wrapper node for TargetConstantPool,
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/// TargetExternalSymbol, and TargetGlobalAddress.
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WRAPPER,
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LSL, ///< Logical shift left.
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LSR, ///< Logical shift right.
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ASR, ///< Arithmetic shift right.
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ROR, ///< Bit rotate right.
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ROL, ///< Bit rotate left.
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LSLLOOP, ///< A loop of single logical shift left instructions.
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LSRLOOP, ///< A loop of single logical shift right instructions.
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ROLLOOP, ///< A loop of single left bit rotate instructions.
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RORLOOP, ///< A loop of single right bit rotate instructions.
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ASRLOOP, ///< A loop of single arithmetic shift right instructions.
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/// AVR conditional branches. Operand 0 is the chain operand, operand 1
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/// is the block to branch if condition is true, operand 2 is the
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/// condition code, and operand 3 is the flag operand produced by a CMP
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/// or TEST instruction.
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BRCOND,
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/// Compare instruction.
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CMP,
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/// Compare with carry instruction.
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CMPC,
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/// Test for zero or minus instruction.
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TST,
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/// Operand 0 and operand 1 are selection variable, operand 2
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/// is condition code and operand 3 is flag operand.
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SELECT_CC
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};
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} // end of namespace AVRISD
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class AVRSubtarget;
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class AVRTargetMachine;
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/// Performs target lowering for the AVR.
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class AVRTargetLowering : public TargetLowering {
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public:
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explicit AVRTargetLowering(const AVRTargetMachine &TM,
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const AVRSubtarget &STI);
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public:
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MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
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return MVT::i8;
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}
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MVT::SimpleValueType getCmpLibcallReturnType() const override {
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return MVT::i8;
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}
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const char *getTargetNodeName(unsigned Opcode) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
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SDValue &Offset, ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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ConstraintWeight
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getSingleConstraintMatchWeight(AsmOperandInfo &info,
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const char *constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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Register getRegisterByName(const char* RegName, LLT VT,
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const MachineFunction &MF) const override;
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bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL)
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const override {
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return false;
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}
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private:
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SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
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SelectionDAG &DAG, SDLoc dl) const;
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SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
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SelectionDAG &DAG) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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protected:
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const AVRSubtarget &Subtarget;
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private:
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MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
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MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
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};
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} // end namespace llvm
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#endif // LLVM_AVR_ISEL_LOWERING_H
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