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expected-target-index-name.mir
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…
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intrinsics.mir
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…
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invalid-target-index-operand.mir
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…
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lit.local.cfg
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…
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llc-target-cpu-attr-from-cmdline-ir.mir
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Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
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2020-11-11 14:40:14 +00:00 |
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llc-target-cpu-attr-from-cmdline.mir
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Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
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2020-11-11 14:40:14 +00:00 |
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load-store-opt-dlc.mir
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machine-function-info-dynlds-align-invalid-case.mir
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[amdgpu] Add codegen support for HIP dynamic shared memory.
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2020-08-20 21:29:18 -04:00 |
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machine-function-info-no-ir.mir
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[amdgpu] Add codegen support for HIP dynamic shared memory.
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2020-08-20 21:29:18 -04:00 |
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machine-function-info-register-parse-error1.mir
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[AMDGPU] Avoid hard-coded line numbers in error message checks
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2020-04-23 21:06:09 +01:00 |
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machine-function-info-register-parse-error2.mir
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[AMDGPU] Avoid hard-coded line numbers in error message checks
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2020-04-23 21:06:09 +01:00 |
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machine-function-info.ll
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[amdgpu] Add codegen support for HIP dynamic shared memory.
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2020-08-20 21:29:18 -04:00 |
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mfi-frame-offset-reg-class.mir
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[AMDGPU] Avoid hard-coded line numbers in error message checks
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2020-04-23 21:06:09 +01:00 |
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mfi-parse-error-frame-offset-reg.mir
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[AMDGPU] Avoid hard-coded line numbers in error message checks
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2020-04-23 21:06:09 +01:00 |
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mfi-parse-error-scratch-rsrc-reg.mir
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[AMDGPU] Avoid hard-coded line numbers in error message checks
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2020-04-23 21:06:09 +01:00 |
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mfi-parse-error-stack-ptr-offset-reg.mir
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[AMDGPU] Avoid hard-coded line numbers in error message checks
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2020-04-23 21:06:09 +01:00 |
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mfi-scratch-rsrc-reg-reg-class.mir
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[AMDGPU] Avoid hard-coded line numbers in error message checks
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2020-04-23 21:06:09 +01:00 |
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mfi-stack-ptr-offset-reg-class.mir
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[AMDGPU] Avoid hard-coded line numbers in error message checks
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2020-04-23 21:06:09 +01:00 |
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mir-canon-multi.mir
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[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
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2020-09-03 16:13:09 -04:00 |
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mircanon-memoperands.mir
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[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
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2020-09-03 16:13:09 -04:00 |
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parse-order-reserved-regs.mir
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[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
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2020-09-03 16:13:09 -04:00 |
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stack-id-assert.mir
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[MIR] Fix out of bounds access in MIRPrinter.
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2020-10-29 14:35:06 +03:00 |
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stack-id.mir
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…
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subreg-def-is-not-ssa.mir
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MIR: Infer not-SSA for subregister defs
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2020-08-27 16:56:16 -04:00 |
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syncscopes.mir
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target-flags.mir
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[AMDGPU] Fix offset for REL32_HI relocs
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2020-09-02 10:55:55 +01:00 |
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target-index-operands.mir
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