64 lines
2.9 KiB
LLVM
64 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst < %s |\
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; RUN: FileCheck %s -check-prefixes=MMR2
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; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+dsp,+micromips -asm-show-inst < %s |\
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; RUN: FileCheck %s -check-prefixes=MMR2-DSP
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define i64 @test(i32 signext %a, i32 signext %b) {
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; MMR2-LABEL: test:
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; MMR2: # %bb.0: # %entry
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; MMR2-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
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; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-NEXT: # <MCOperand Imm:0>>
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; MMR2-NEXT: li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM
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; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-NEXT: # <MCOperand Imm:1>>
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; MMR2-NEXT: mtlo $3 # <MCInst #{{[0-9]+}} MTLO_MM
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; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-NEXT: mthi $2 # <MCInst #{{[0-9]+}} MTHI_MM
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; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-NEXT: madd $4, $5 # <MCInst #{{[0-9]+}} MADD
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; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-NEXT: mflo16 $2 # <MCInst #{{[0-9]+}} MFLO16_MM
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; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-NEXT: mfhi16 $3 # <MCInst #{{[0-9]+}} MFHI16_MM
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; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
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; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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;
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; MMR2-DSP-LABEL: test:
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; MMR2-DSP: # %bb.0: # %entry
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; MMR2-DSP-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-DSP-NEXT: # <MCOperand Imm:0>>
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; MMR2-DSP-NEXT: li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-DSP-NEXT: # <MCOperand Imm:1>>
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; MMR2-DSP-NEXT: mtlo $3, $ac0 # <MCInst #{{[0-9]+}} MTLO_DSP
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-DSP-NEXT: mthi $2, $ac0 # <MCInst #{{[0-9]+}} MTHI_DSP
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-DSP-NEXT: madd $ac0, $4, $5 # <MCInst #{{[0-9]+}} MADD_DSP
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-DSP-NEXT: mflo $2, $ac0 # <MCInst #{{[0-9]+}} MFLO_DSP
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-DSP-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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; MMR2-DSP-NEXT: mfhi $3, $ac0 # <MCInst #{{[0-9]+}} MFHI_DSP
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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entry:
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%conv = sext i32 %a to i64
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%conv1 = sext i32 %b to i64
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%mul = mul nsw i64 %conv, %conv1
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%add = add nsw i64 %mul, 1
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ret i64 %add
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}
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