144 lines
4.1 KiB
C++
144 lines
4.1 KiB
C++
//===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file includes code for rendering MCInst instances as AT&T-style
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// assembly.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "X86IntelInstPrinter.h"
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#include "X86InstComments.h"
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include <cctype>
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using namespace llvm;
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// Include the auto-generated portion of the assembly writer.
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#define GET_INSTRUCTION_NAME
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#include "X86GenAsmWriter1.inc"
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void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
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printInstruction(MI, OS);
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// If verbose assembly is enabled, we can print some informative comments.
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if (CommentStream)
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EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
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}
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StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
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return getInstructionName(Opcode);
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}
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void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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switch (MI->getOperand(Op).getImm()) {
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default: assert(0 && "Invalid ssecc argument!");
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case 0: O << "eq"; break;
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case 1: O << "lt"; break;
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case 2: O << "le"; break;
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case 3: O << "unord"; break;
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case 4: O << "neq"; break;
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case 5: O << "nlt"; break;
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case 6: O << "nle"; break;
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case 7: O << "ord"; break;
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}
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}
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/// print_pcrel_imm - This is used to print an immediate value that ends up
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/// being encoded as a pc-relative value.
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void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm())
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O << Op.getImm();
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else {
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assert(Op.isExpr() && "unknown pcrel immediate operand");
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O << *Op.getExpr();
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}
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}
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static void PrintRegName(raw_ostream &O, StringRef RegName) {
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for (unsigned i = 0, e = RegName.size(); i != e; ++i)
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O << (char)toupper(RegName[i]);
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}
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void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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PrintRegName(O, getRegisterName(Op.getReg()));
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} else if (Op.isImm()) {
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O << Op.getImm();
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} else {
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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O << *Op.getExpr();
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}
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}
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void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &BaseReg = MI->getOperand(Op);
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unsigned ScaleVal = MI->getOperand(Op+1).getImm();
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const MCOperand &IndexReg = MI->getOperand(Op+2);
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const MCOperand &DispSpec = MI->getOperand(Op+3);
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const MCOperand &SegReg = MI->getOperand(Op+4);
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// If this has a segment register, print it.
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if (SegReg.getReg()) {
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printOperand(MI, Op+4, O);
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O << ':';
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}
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O << '[';
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bool NeedPlus = false;
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if (BaseReg.getReg()) {
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printOperand(MI, Op, O);
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NeedPlus = true;
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}
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if (IndexReg.getReg()) {
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if (NeedPlus) O << " + ";
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if (ScaleVal != 1)
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O << ScaleVal << '*';
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printOperand(MI, Op+2, O);
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NeedPlus = true;
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}
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if (!DispSpec.isImm()) {
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if (NeedPlus) O << " + ";
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assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
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O << *DispSpec.getExpr();
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} else {
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int64_t DispVal = DispSpec.getImm();
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if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
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if (NeedPlus) {
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if (DispVal > 0)
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O << " + ";
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else {
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O << " - ";
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DispVal = -DispVal;
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}
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}
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O << DispVal;
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}
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}
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O << ']';
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}
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