415 lines
13 KiB
C++
415 lines
13 KiB
C++
//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the machine register scavenger. It can provide
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// information, such as unused registers, at any point in a machine basic block.
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// It also provides a mechanism to make registers available by evicting them to
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// spill slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reg-scavenging"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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/// setUsed - Set the register and its sub-registers as being used.
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void RegScavenger::setUsed(unsigned Reg) {
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RegsAvailable.reset(Reg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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RegsAvailable.reset(SubReg);
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}
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/// setUnused - Set the register and its sub-registers as being unused.
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void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
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RegsAvailable.set(Reg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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RegsAvailable.set(SubReg);
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}
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bool RegScavenger::isAliasUsed(unsigned Reg) const {
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if (isUsed(Reg))
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return true;
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for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R)
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if (isUsed(*R))
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return true;
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return false;
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}
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void RegScavenger::initRegState() {
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ScavengedReg = 0;
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ScavengedRC = NULL;
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ScavengeRestore = NULL;
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// All registers started out unused.
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RegsAvailable.set();
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// Reserved registers are always used.
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RegsAvailable ^= ReservedRegs;
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if (!MBB)
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return;
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// Live-in registers are in use.
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for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
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setUsed(*I);
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// Pristine CSRs are also unavailable.
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BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
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for (int I = PR.find_first(); I>0; I = PR.find_next(I))
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setUsed(I);
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}
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void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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MachineFunction &MF = *mbb->getParent();
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const TargetMachine &TM = MF.getTarget();
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TII = TM.getInstrInfo();
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TRI = TM.getRegisterInfo();
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MRI = &MF.getRegInfo();
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assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
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"Target changed?");
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// Self-initialize.
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if (!MBB) {
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NumPhysRegs = TRI->getNumRegs();
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RegsAvailable.resize(NumPhysRegs);
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// Create reserved registers bitvector.
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ReservedRegs = TRI->getReservedRegs(MF);
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// Create callee-saved registers bitvector.
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CalleeSavedRegs.resize(NumPhysRegs);
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const unsigned *CSRegs = TRI->getCalleeSavedRegs();
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if (CSRegs != NULL)
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for (unsigned i = 0; CSRegs[i]; ++i)
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CalleeSavedRegs.set(CSRegs[i]);
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}
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// RS used within emit{Pro,Epi}logue()
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if (mbb != MBB) {
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MBB = mbb;
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initRegState();
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}
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Tracking = false;
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}
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void RegScavenger::restoreScavengedReg() {
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TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
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ScavengingFrameIndex, ScavengedRC);
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MachineBasicBlock::iterator II = prior(MBBI);
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TRI->eliminateFrameIndex(II, 0, this);
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setUsed(ScavengedReg);
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ScavengedReg = 0;
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ScavengedRC = NULL;
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}
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#ifndef NDEBUG
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/// isLiveInButUnusedBefore - Return true if register is livein the MBB not
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/// not used before it reaches the MI that defines register.
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static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
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MachineBasicBlock *MBB,
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const TargetRegisterInfo *TRI,
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MachineRegisterInfo* MRI) {
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// First check if register is livein.
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bool isLiveIn = false;
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for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
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if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
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isLiveIn = true;
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break;
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}
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if (!isLiveIn)
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return false;
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// Is there any use of it before the specified MI?
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SmallPtrSet<MachineInstr*, 4> UsesInMBB;
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
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UE = MRI->use_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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if (UseMO.isReg() && UseMO.isUndef())
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continue;
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MachineInstr *UseMI = &*UI;
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if (UseMI->getParent() == MBB)
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UsesInMBB.insert(UseMI);
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}
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if (UsesInMBB.empty())
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return true;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
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if (UsesInMBB.count(&*I))
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return false;
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return true;
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}
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#endif
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void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
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BV.set(Reg);
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for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
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BV.set(*R);
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}
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void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) {
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BV.set(Reg);
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for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++)
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BV.set(*R);
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}
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void RegScavenger::forward() {
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// Move ptr forward.
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if (!Tracking) {
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MBBI = MBB->begin();
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Tracking = true;
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} else {
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assert(MBBI != MBB->end() && "Already at the end of the basic block!");
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MBBI = next(MBBI);
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}
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MachineInstr *MI = MBBI;
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if (MI == ScavengeRestore) {
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ScavengedReg = 0;
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ScavengedRC = NULL;
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ScavengeRestore = NULL;
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}
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// Find out which registers are early clobbered, killed, defined, and marked
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// def-dead in this instruction.
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BitVector EarlyClobberRegs(NumPhysRegs);
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BitVector KillRegs(NumPhysRegs);
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BitVector DefRegs(NumPhysRegs);
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BitVector DeadRegs(NumPhysRegs);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || isReserved(Reg))
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continue;
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if (MO.isUse()) {
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// Two-address operands implicitly kill.
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if (MO.isKill() || MI->isRegTiedToDefOperand(i))
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addRegWithSubRegs(KillRegs, Reg);
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} else {
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assert(MO.isDef());
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if (MO.isDead())
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addRegWithSubRegs(DeadRegs, Reg);
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else
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addRegWithSubRegs(DefRegs, Reg);
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if (MO.isEarlyClobber())
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addRegWithAliases(EarlyClobberRegs, Reg);
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}
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}
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// Verify uses and defs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || isReserved(Reg))
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continue;
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if (MO.isUse()) {
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assert(isUsed(Reg) && "Using an undefined register!");
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assert((!EarlyClobberRegs.test(Reg) || MI->isRegTiedToDefOperand(i)) &&
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"Using an early clobbered register!");
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} else {
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assert(MO.isDef());
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assert((KillRegs.test(Reg) || isUnused(Reg) ||
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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"Re-defining a live register!");
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}
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}
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// Commit the changes.
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setUnused(KillRegs);
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setUnused(DeadRegs);
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setUsed(DefRegs);
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}
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void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
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if (includeReserved)
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used = ~RegsAvailable;
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else
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used = ~RegsAvailable & ~ReservedRegs;
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}
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/// CreateRegClassMask - Set the bits that represent the registers in the
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/// TargetRegisterClass.
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static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
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++I)
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Mask.set(*I);
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}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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const BitVector &Candidates) const {
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector RegsAvailableCopy(NumPhysRegs, false);
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CreateRegClassMask(RegClass, RegsAvailableCopy);
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RegsAvailableCopy &= RegsAvailable;
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// Restrict the search to candidates.
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RegsAvailableCopy &= Candidates;
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// Returns the first unused (bit is set) register, or 0 is none is found.
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int Reg = RegsAvailableCopy.find_first();
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return (Reg == -1) ? 0 : Reg;
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}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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bool ExCalleeSaved) const {
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector RegsAvailableCopy(NumPhysRegs, false);
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CreateRegClassMask(RegClass, RegsAvailableCopy);
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RegsAvailableCopy &= RegsAvailable;
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// If looking for a non-callee-saved register, mask off all the callee-saved
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// registers.
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if (ExCalleeSaved)
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RegsAvailableCopy &= ~CalleeSavedRegs;
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// Returns the first unused (bit is set) register, or 0 is none is found.
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int Reg = RegsAvailableCopy.find_first();
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return (Reg == -1) ? 0 : Reg;
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}
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/// DistanceMap - Keep track the distance of an MI from the current position.
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typedef DenseMap<MachineInstr*, unsigned> DistanceMap;
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/// Build a distance map for instructions from I to E.
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static void buildDistanceMap(DistanceMap &DM,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator E) {
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DM.clear();
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for (unsigned d = 0; I != E; ++I, ++d)
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DM.insert(DistanceMap::value_type(I, d));
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}
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/// findFirstUse - Calculate the distance to the first use of the
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/// specified register in the range covered by DM.
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static MachineInstr *findFirstUse(const MachineBasicBlock *MBB,
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const DistanceMap &DM,
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unsigned Reg,
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unsigned &Dist) {
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const MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
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MachineInstr *UseMI = 0;
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Dist = ~0U;
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for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
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RE = MRI->reg_end(); RI != RE; ++RI) {
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MachineInstr *UDMI = &*RI;
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if (UDMI->getParent() != MBB)
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continue;
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DistanceMap::const_iterator DI = DM.find(UDMI);
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if (DI == DM.end())
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continue;
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if (DI->second < Dist) {
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Dist = DI->second;
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UseMI = UDMI;
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}
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}
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return UseMI;
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}
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unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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MachineBasicBlock::iterator I,
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int SPAdj) {
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assert(ScavengingFrameIndex >= 0 &&
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"Cannot scavenge a register without an emergency spill slot!");
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector Candidates(NumPhysRegs, false);
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CreateRegClassMask(RC, Candidates);
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// Do not include reserved registers.
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Candidates ^= ReservedRegs & Candidates;
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// Exclude all the registers being used by the instruction.
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = I->getOperand(i);
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if (MO.isReg())
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Candidates.reset(MO.getReg());
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}
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// Prepare to call findFirstUse() a number of times.
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DistanceMap DM;
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buildDistanceMap(DM, I, MBB->end());
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// Find the register whose use is furthest away.
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unsigned SReg = 0;
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unsigned MaxDist = 0;
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MachineInstr *MaxUseMI = 0;
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int Reg = Candidates.find_first();
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while (Reg != -1) {
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unsigned Dist;
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MachineInstr *UseMI = findFirstUse(MBB, DM, Reg, Dist);
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
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unsigned AsDist;
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MachineInstr *AsUseMI = findFirstUse(MBB, DM, *AS, AsDist);
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if (AsDist < Dist) {
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Dist = AsDist;
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UseMI = AsUseMI;
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}
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}
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// If we found an unused register there is no reason to spill it. We have
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// probably found a callee-saved register that has been saved in the
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// prologue, but happens to be unused at this point.
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if (!isAliasUsed(Reg))
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return Reg;
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if (Dist >= MaxDist) {
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MaxDist = Dist;
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MaxUseMI = UseMI;
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SReg = Reg;
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}
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Reg = Candidates.find_next(Reg);
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}
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assert(ScavengedReg == 0 &&
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"Scavenger slot is live, unable to scavenge another register!");
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// Avoid infinite regress
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ScavengedReg = SReg;
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// Spill the scavenged register before I.
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TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
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MachineBasicBlock::iterator II = prior(I);
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TRI->eliminateFrameIndex(II, SPAdj, this);
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// Restore the scavenged register before its use (or first terminator).
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II = MaxUseMI
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? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
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TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
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ScavengeRestore = prior(II);
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// Doing this here leads to infinite regress.
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// ScavengedReg = SReg;
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ScavengedRC = RC;
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return SReg;
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}
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