mirror of https://github.com/RT-Thread/rt-thread
guo
GitHub
commit
00221bd43f
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@ -0,0 +1,19 @@
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# GD32 BSP 说明
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|
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GD32 系列 BSP 目前支持情况如下表所示：
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|
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| **BSP 文件夹名称** | **开发板名称** |
|
||||
|:------------------------- |:-------------------------- |
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| **F4 系列** | |
|
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| [gd32407v-start](gd32407v-start) | 兆易创新 官方 GD32407V-START 开发板 |
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|
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可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
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|
||||
| **BSP 使用教程** | **简介** |
|
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|:-------------------- |:------------------------------------------------- |
|
||||
| [外设驱动使用教程](docs/GD32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 |
|
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| [外设驱动介绍与应用](docs/GD32系列驱动介绍.md) | 讲解 GD32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
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| **BSP 制作与提交** | **简介** |
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| [BSP 制作教程](docs/GD32系列BSP制作教程.md) | 讲解 GD32 系列 BSP 的制作方法 |
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# GD32 系列 BSP 制作教程
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## 1. BSP 框架介绍
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BSP 框架结构如下图所示：
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GD32的BSP架构主要分为三个部分：libraries、tools和具体的Boards，其中libraries包含了GD32的通用库，包括每个系列的HAL以及适配RT-Thread的drivers；tools是生成工程的Python脚本工具；另外就是Boards文件，当然这里的Boards有很多，我这里值列举了GD32407V-START。
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|
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## 2. 知识准备
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制作一个 BSP 的过程就是构建一个新系统的过程，因此想要制作出好用的 BSP，要对 RT-Thread 系统的构建过程有一定了解，需要的知识准备如下所示：
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- 掌握 GD32 系列 BSP 的使用方法
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|
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了解 BSP 的使用方法，可以阅读 [BSP 说明文档](../README.md) 中使用教程表格内的文档。
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- 了解 Scons 工程构建方法
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RT-Thread 使用 Scons 作为系统的构建工具，因此了解 Scons 的常用命令对制作新 BSP 是基本要求。
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- 了解设备驱动框架
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在 RT-Thread 系统中，应用程序通过设备驱动框架来操作硬件，因此了解设备驱动框架，对添加 BSP 驱动是很重要的。
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|
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- 了解 Kconfig 语法
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RT-Thread 系统通过 menuconfig 的方式进行配置，而 menuconfig 中的选项是由 Kconfig 文件决定的，因此想要对 RT-Thread 系统进行配置，需要对 kconfig 语法有一定了解。
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## 3. BSP移植
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### 3.1 Keil环境准备
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目前市面通用的MDK for ARM版本有Keil 4和Keil 5：使用Keil 4建议安装4.74及以上；使用Keil 5建议安装5.20以上版本。本文的MDK是5.30。
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|
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从MDK的官网可以下载得到MDK的安装包，然后安装即可。
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|
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[MDK下载地址](https://www.keil.com/download/product/)
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|
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|
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|
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安装完成后会自动打开，我们将其关闭。
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接下来我们下载GD32F30x的软件支持包。
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[下载地址](http://www.gd32mcu.com/cn/download)
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下载好后双击GigaDevice.GD32F4xx_DFP.2.1.0.pack运行即可：
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|
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|
||||
|
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|
||||
|
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|
||||
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点击[Next]即可安装完成。
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|
||||
|
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|
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|
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安装成功后，重新打开Keil，则可以在File->Device Database中出现Gigadevice的下拉选项，点击可以查看到相应的型号。
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||||
|
||||
|
||||
|
||||
|
||||
|
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### 3.2 BSP工程制作
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|
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**1.构建基础工程**
|
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|
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首先看看RT-Thread代码仓库中已有很多BSP，而我要移植的是Cortex-M4内核。这里我找了一个相似的内核，把它复制一份，并修改文件名为：gd32407v-start。这样就有一个基础的工程。然后就开始增删改查，完成最终的BSP，几乎所有的BSP的制作都是如此。
|
||||
|
||||
**2.修改BSP构建脚本**
|
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|
||||
bsp/gd32/gd32407v-start/Kconfig修改后的内容如下：
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|
||||
```config
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mainmenu "RT-Thread Configuration"
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|
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config BSP_DIR
|
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string
|
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option env="BSP_ROOT"
|
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default "."
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|
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config RTT_DIR
|
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string
|
||||
option env="RTT_ROOT"
|
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default "../../.."
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|
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config PKGS_DIR
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string
|
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option env="PKGS_ROOT"
|
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default "packages"
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|
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "../libraries/Kconfig"
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source "board/Kconfig"
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```
|
||||
|
||||
该文件是获取所有路径下的Kconfig。
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|
||||
|
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|
||||
bsp/gd32/gd32407v-start/SConscript修改后的内容如下：
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|
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```python
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# for module compiling
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|
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import os
|
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Import('RTT_ROOT')
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|
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from building import *
|
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|
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
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|
||||
Return('objs')
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```
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||||
|
||||
|
||||
该文件是用于遍历当前目录的所有文件夹。
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||||
|
||||
|
||||
bsp/gd32/gd32407v-start/SConstruct修改后的内容如下：
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```python
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import os
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import sys
|
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import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
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||||
else:
|
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
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|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
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print(RTT_ROOT)
|
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exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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|
||||
if rtconfig.PLATFORM == 'iar':
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env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
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|
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Export('RTT_ROOT')
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Export('rtconfig')
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|
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SDK_ROOT = os.path.abspath('./')
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|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
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libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
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|
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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|
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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gd32_library = 'GD32F4xx_HAL'
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rtconfig.BSP_LIBRARY_TYPE = gd32_library
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# include libraries
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objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
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# include drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
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# make a building
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DoBuilding(TARGET, objs)
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||||
```
|
||||
该文件用于链接所有的依赖文件，并调用make进行编译。
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||||
|
||||
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||||
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**3.修改开发环境信息**
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bsp/gd32/gd32407v-start/cconfig.h修改后的内容如下：
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```c
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#ifndef CCONFIG_H__
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#define CCONFIG_H__
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||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* compiler configure file for RT-Thread in GCC*/
|
||||
|
||||
#define HAVE_NEWLIB_H 1
|
||||
#define LIBC_VERSION "newlib 2.4.0"
|
||||
|
||||
#define HAVE_SYS_SIGNAL_H 1
|
||||
#define HAVE_SYS_SELECT_H 1
|
||||
#define HAVE_PTHREAD_H 1
|
||||
|
||||
#define HAVE_FDSET 1
|
||||
#define HAVE_SIGACTION 1
|
||||
#define GCC_VERSION_STR "5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]"
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||||
#define STDC "2011"
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||||
|
||||
#endif
|
||||
```
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||||
该文件是是编译BSP的环境信息，需根据实际修改。
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||||
|
||||
|
||||
|
||||
**4.修改KEIL的模板工程**
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||||
|
||||
双击：template.uvprojx即可修改模板工程。
|
||||
|
||||
修改为对应芯片设备:
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
修改FLASH和RAM的配置:
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
修改可执行文件名字：
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
修改默认调试工具：CMSIS-DAP Debugger。
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
修改编程算法：GD32F4xx FMC。
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
**5.修改board文件夹**
|
||||
|
||||
(1) 修改bsp/gd32/gd32407v-start/board/linker_scripts/link.icf
|
||||
|
||||
修改后的内容如下：
|
||||
|
||||
```
|
||||
/*###ICF### Section handled by ICF editor, don't touch! /
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x082FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/ End of ICF editor section. ###ICF###*/
|
||||
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
|
||||
define symbol __region_RAM1_start__ = 0x10000000;
|
||||
define symbol __region_RAM1_end__ = 0x1000FFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
keep { section FSymTab };
|
||||
keep { section VSymTab };
|
||||
keep { section .rti_fn* };
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM1_region { section .sram };
|
||||
```
|
||||
该文件是IAR编译的链接脚本，根据《GD32F407xx_Datasheet_Rev2.1》可知，GD32F407VKT6的flash大小为3072KB，SRAM大小为192KB，因此需要设置ROM和RAM的起始地址和堆栈大小等。
|
||||
|
||||
|
||||
|
||||
(2) 修改bsp/gd32/gd32407v-start/board/linker_scripts/link.ld
|
||||
|
||||
修改后的内容如下：
|
||||
|
||||
```
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
MEMORY
|
||||
{
|
||||
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 3072k /* 3072KB flash */
|
||||
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */
|
||||
}
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x200;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} > CODE = 0
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = .;
|
||||
} > CODE
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >DATA
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >DATA
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > DATA
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
```
|
||||
该文件是GCC编译的链接脚本，根据《GD32F407xx_Datasheet_Rev2.1》可知，GD32F407VKT6的flash大小为3072KB，SRAM大小为192KB，因此CODE和DATA 的LENGTH分别设置为3072KB和192KB，其他芯片类似，但其实地址都是一样的。
|
||||
|
||||
(3) 修改bsp/gd32/gd32407v-start/board/linker_scripts/link.sct
|
||||
修改后的内容如下：
|
||||
|
||||
```
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00300000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00300000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00030000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
```
|
||||
该文件是MDK的连接脚本，根据《GD32F407xx_Datasheet_Rev2.1》手册，因此需要将 LR_IROM1 和 ER_IROM1 的参数设置为 0x00300000；RAM 的大小为192k，因此需要将 RW_IRAM1 的参数设置为 0x00030000。
|
||||
|
||||
|
||||
|
||||
(4) 修改bsp/gd32/gd32407v-start/board/board.h文件
|
||||
|
||||
修改后内容如下：
|
||||
```c
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
#include "drv_usart.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#include "gd32f4xx_exti.h"
|
||||
|
||||
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
|
||||
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
|
||||
|
||||
// <o> Internal SRAM memory size[Kbytes] <8-64>
|
||||
// <i>Default: 64
|
||||
#ifdef __ICCARM__
|
||||
// Use *.icf ram symbal, to avoid hardcode.
|
||||
extern char __ICFEDIT_region_RAM_end__;
|
||||
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
|
||||
#else
|
||||
#define GD32_SRAM_SIZE 192
|
||||
#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
|
||||
#endif
|
||||
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END GD32_SRAM_END
|
||||
|
||||
#endif
|
||||
```
|
||||
值得注意的是，不同的编译器规定的堆栈内存的起始地址 HEAP_BEGIN 和结束地址 HEAP_END。这里 HEAP_BEGIN 和 HEAP_END 的值需要和前面的链接脚本是一致的，需要结合实际去修改。
|
||||
|
||||
|
||||
|
||||
(5) 修改bsp/gd32/gd32407v-start/board/board.c文件
|
||||
|
||||
修改后的文件如下：
|
||||
```c
|
||||
#include <stdint.h>
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void Error_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler */
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
NVIC_SetPriority(SysTick_IRQn, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial GD32 board.
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
/* NVIC Configuration */
|
||||
#define NVIC_VTOR_MASK 0x3FFFFF80
|
||||
#ifdef VECT_TAB_RAM
|
||||
/* Set the Vector Table base location at 0x10000000 */
|
||||
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
|
||||
#else /* VECT_TAB_FLASH */
|
||||
/* Set the Vector Table base location at 0x08000000 */
|
||||
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
|
||||
#endif
|
||||
|
||||
SystemClock_Config();
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SDRAM
|
||||
rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
|
||||
#else
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
}
|
||||
```
|
||||
该文件重点关注的就是SystemClock_Config配置，SystemCoreClock的定义在system_gd32f4xx.c中定义的。
|
||||
|
||||
|
||||
|
||||
(6) 修改bsp/gd32/gd32407v-start/board/Kconfig文件
|
||||
修改后内容如下：
|
||||
```config
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_GD32407V
|
||||
bool
|
||||
select SOC_SERIES_GD32F4
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default y
|
||||
|
||||
config BSP_UART1_RX_USING_DMA
|
||||
bool "Enable UART1 RX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Enable SPI BUS"
|
||||
default n
|
||||
select RT_USING_SPI
|
||||
if BSP_USING_SPI
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable SPI1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_SPI1_TX_USING_DMA
|
||||
bool "Enable SPI1 TX DMA"
|
||||
depends on BSP_USING_SPI1
|
||||
default n
|
||||
|
||||
config BSP_SPI1_RX_USING_DMA
|
||||
bool "Enable SPI1 RX DMA"
|
||||
depends on BSP_USING_SPI1
|
||||
select BSP_SPI1_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C1
|
||||
bool "Enable I2C1 BUS (software simulation)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
select RT_USING_I2C_BITOPS
|
||||
select RT_USING_PIN
|
||||
if BSP_USING_I2C1
|
||||
config BSP_I2C1_SCL_PIN
|
||||
int "i2c1 scl pin number"
|
||||
range 1 216
|
||||
default 24
|
||||
config BSP_I2C1_SDA_PIN
|
||||
int "I2C1 sda pin number"
|
||||
range 1 216
|
||||
default 25
|
||||
endif
|
||||
source "../libraries/HAL_Drivers/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
```
|
||||
这个文件就是配置板子驱动的，这里可根据实际需求添加。
|
||||
|
||||
|
||||
|
||||
(7) 修改bsp/gd32/gd32407v-start/board/SConscript文件
|
||||
|
||||
修改后内容如下：
|
||||
```python
|
||||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
Import('SDK_LIB')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s']
|
||||
|
||||
CPPDEFINES = ['GD32F407xx']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
```
|
||||
该文件主要添加board文件夹的.c文件和头文件路径。另外根据开发环境选择相应的汇编文件，和前面的libraries的SConscript语法是一样，文件的结构都是类似的，这里就没有注释了。
|
||||
|
||||
到这里，基本所有的依赖脚本都配置完成了，接下来将通过menuconfig配置工程。
|
||||
|
||||
|
||||
|
||||
**6.menuconfig配置**
|
||||
关闭套接字抽象层。
|
||||
|
||||
|
||||
|
||||
关闭网络设备接口。
|
||||
|
||||
|
||||
|
||||
关闭LWIP协议栈。
|
||||
|
||||
|
||||
|
||||
GD32407V-START板载没有以太网，因此这里主要是关闭网络相关的内容，当然GD32407V-START的资源丰富，不关这些其实也不影响，如果是其他MCU，根据实际需求自行修改吧。
|
||||
|
||||
|
||||
|
||||
**7.驱动修改**
|
||||
一个基本的BSP中，串口是必不可少的，所以还需要编写串口驱动，这里使用的串口2作为调试串口。
|
||||
板子上还有LED灯，主要要编写GPIO驱动即可。
|
||||
关于串口和LED的驱动可以查看源码，这里就不贴出来了。
|
||||
|
||||
|
||||
|
||||
**8.应用开发**
|
||||
|
||||
笔者在applications的main.c中添加LED的应用代码，
|
||||
```c
|
||||
#include <stdio.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED2 pin: PC6 */
|
||||
#define LED2_PIN GET_PIN(C, 6)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int count = 1;
|
||||
|
||||
/* set LED2 pin mode to output */
|
||||
rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (count++)
|
||||
{
|
||||
rt_pin_write(LED2_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED2_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
```
|
||||
当然，这需要GPIO驱动的支持。
|
||||
|
||||
|
||||
|
||||
**9.使用ENV编译工程**
|
||||
在env中执行：scons
|
||||
|
||||
|
||||
|
||||
编译成功打印信息如下：
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
**10.使用env生成MDK工程**
|
||||
在env中执行：scons --target=mdk5
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
生成MDK工程后，打开MDK工程进行编译
|
||||
|
||||
|
||||
|
||||
|
||||
成功编译打印信息如下：
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
### 3.3 使用GD-Link 下载调试GD32
|
||||
|
||||
前面使用ENV和MDK成功编译可BSP，那么接下来就是下载调试环节，下载需要下载器，而GD32部分开发板自带GD-link，可以用开发板上自带的GD-link调试仿真代码，不带的可外接GD-link模块，还是很方便的。具体操作方法如下。
|
||||
|
||||
|
||||
|
||||
1.第一次使用GD-link插入电脑后，会自动安装驱动。
|
||||
|
||||
在Options for Target -> Debug 中选择“CMSIS-DAP Debugger”，部分客户反馈找不到这一驱动器选项，那是因为MDK版本过低，只有Keil4.74以上的版本和Keil5才支持CMSIS-DAP Debugger选项。
|
||||
|
||||
|
||||
|
||||
2.在Options for Target -> Debug ->Settings勾选SWJ、 Port选择 SW。右框IDcode会出现”0xXBAXXXXX”。
|
||||
|
||||
|
||||
|
||||
3.在Options for Target -> Debug ->Settings -> Flash Download中添加GD32的flash算法。
|
||||
|
||||
|
||||
|
||||
4.单击下图的快捷方式“debug”， 即可使用GD-Link进行仿真。
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
当然啦，也可使用GD-Link下载程序。
|
||||
|
||||
|
||||
|
||||
下载程序成功后，打印信息如下：
|
||||
|
||||
|
||||
|
||||
接上串口，打印信息如下：
|
||||
|
||||
|
||||
|
||||
同时LED会不断闪烁。
|
||||
|
||||
|
||||
|
||||
### 3.4 RT-Thread studio开发
|
||||
|
||||
当然，该工程也可导出使用rt-thread studio开发。
|
||||
|
||||
先使用scons --dist导出工程。
|
||||
|
||||
|
||||
|
||||
再将工程导入rt-thread studio中
|
||||
|
||||
|
||||
|
||||
最后，就可在rt-thread studio就可进行开发工作了。
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
## 4. 规范
|
||||
|
||||
本章节介绍 RT-Thread GD32 系列 BSP 制作与提交时应当遵守的规范 。开发人员在 BSP 制作完成后，可以根据本规范提出的检查点对制作的 BSP 进行检查，确保 BSP 在提交前有较高的质量 。
|
||||
|
||||
### 4.1 BSP 制作规范
|
||||
|
||||
GD32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和 IDE 配置。在已有的 GD32 系列 BSP 的模板中，已经根据下列规范对模板进行配置。在制作新 BSP 的过程中，拷贝模板进行修改时，需要注意的是不要修改这些默认的配置。BSP 制作完成后，需要对新制作的 BSP 进行功能测试，功能正常后再进行代码提交。
|
||||
|
||||
下面将详细介绍 BSP 的制作规范。
|
||||
|
||||
#### 4.1.1 工程配置
|
||||
|
||||
- 遵从RT-Thread 编码规范，代码注释风格统一
|
||||
- main 函数功能保持一致
|
||||
- 如果有 LED 的话，main 函数里**只放一个** LED 1HZ 闪烁的程序
|
||||
- 在 `rt_hw_board_init` 中需要完成堆的初始化：调用 `rt_system_heap_init`
|
||||
- 默认只初始化 GPIO 驱动和 FinSH 对应的串口驱动，不使用 DMA
|
||||
- 当使能板载外设驱动时，应做到不需要修改代码就能编译下载使用
|
||||
- 提交前应检查 GCC/MDK/IAR 三种编译器直接编译或者重新生成后编译是否成功
|
||||
- 使用 `dist` 命令对 BSP 进行发布，检查使用 `dist` 命令生成的工程是否可以正常使用
|
||||
|
||||
#### 4.1.2 ENV 配置
|
||||
|
||||
- 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND）
|
||||
- BSP 中需要打开调试选项中的断言（宏：RT_DEBUG）
|
||||
- 系统空闲线程栈大小统一设置为 256（宏：IDLE_THREAD_STACK_SIZE）
|
||||
- 开启组件自动初始化（宏：RT_USING_COMPONENTS_INIT）
|
||||
- 需要开启 user main 选项（宏：RT_USING_USER_MAIN）
|
||||
- 默认关闭 libc（宏：RT_USING_LIBC）
|
||||
- FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY）
|
||||
|
||||
#### 4.1.3 IDE 配置
|
||||
|
||||
- 使能下载代码后自动运行
|
||||
- 使能 C99 支持
|
||||
- 使能 One ELF Section per Function（MDK）
|
||||
- MDK/IAR 生成的临时文件分别放到build下的 MDK/IAR 文件夹下
|
||||
- MDK/GCC/IAR 生成 bin 文件名字统一成 rtthread.bin
|
||||
|
||||
### 4.2 BSP 提交规范
|
||||
|
||||
- 提交前请认真修改 BSP 的 README.md 文件，README.md 文件的外设支持表单只填写 BSP 支持的外设，可参考其他 BSP 填写。查看文档[《GD32系列驱动介绍》](./GD32系列驱动介绍.md)了解驱动分类。
|
||||
- 提交 BSP 分为 2 个阶段提交：
|
||||
- 第一阶段：基础 BSP 包括串口驱动和 GPIO 驱动，能运行 FinSH 控制台。完成 MDK4、MDK5 、IAR 和 GCC 编译器支持，如果芯片不支持某款编译器（比如MDK4）可以不用做。 BSP 的 README.md 文件需要填写第二阶段要完成的驱动。
|
||||
- 第二阶段：完成板载外设驱动支持，所有板载外设使用 menuconfig 配置后就能直接使用。若开发板没有板载外设，则此阶段可以不用完成。不同的驱动要分开提交，方便 review 和合并。
|
||||
- 只提交 BSP 必要的文件，删除无关的中间文件，能够提交的文件请对照其他 BSP。
|
||||
- 提交 GD32 不同系列的 Library 库时，请参考 f1/f4 系列的 HAL 库，删除多余库文件
|
||||
- 提交前要对 BSP 进行编译测试，确保在不同编译器下编译正常
|
||||
- 提交前要对 BSP 进行功能测试，确保 BSP 的在提交前符合工程配置章节中的要求
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
# GD32系列BSP外设驱动使用教程
|
||||
|
||||
## 简介
|
||||
|
||||
本文档是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
主要包括以下内容：
|
||||
|
||||
1. 如何使用开发板上更多的板载资源
|
||||
2. 如何使用更多的片上资源
|
||||
3. 如何添加更多片上资源选项
|
||||
|
||||
## 前提要求
|
||||
|
||||
- 学会如何使用 ENV 工具，参考：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/programming-manual/env/env/)
|
||||
|
||||
## 如何使用更多的板载资源
|
||||
|
||||
开发板上一般有很多板载资源，如 Flash、SD卡等，但是 BSP 工程默认没有开启这些外设驱动。RT-Thread 提供了 ENV 工具来开启或关闭 BSP 的外设驱动。下面以在GD32407V-START开发板上开启 UART2 驱动为例，一步步的展示如何使用 ENV 工具对 BSP 进行配置。
|
||||
|
||||
### 1）打开配置工具
|
||||
|
||||
在目录 `rt-thread\bsp\gd32\gd32407v-start` 下打开 menuconfig 配置界面。
|
||||
|
||||
|
||||
|
||||
打开的配置工具界面如下所示：
|
||||
|
||||
|
||||
|
||||
通过键盘上的上下键移动光标，选中 `Hardware Drivers Config`然后按回车键进入硬件驱动配置菜单。
|
||||
|
||||
### 2）进入硬件驱动配置菜单
|
||||
|
||||
在硬件配置菜单里有三个选项，分别是 **板载外设配置菜单**、**片上外设配置菜单**和**扩展模块配置菜单**，按回车键进入板载外设配置菜单。
|
||||
|
||||
|
||||
|
||||
### 3）在板载外设配置菜单里开启 UART2 选项
|
||||
|
||||
|
||||
|
||||
### 4）保存退出
|
||||
|
||||
然后右移光标选中 Save 按回车键保存，然后按 Esc 键退出配置工具。
|
||||
|
||||
|
||||
|
||||
### 5）更新软件包
|
||||
|
||||
输入命令 `pkgs --update` 使软件包配置生效。
|
||||
|
||||
|
||||
|
||||
### 6）生成 MDK5 工程
|
||||
|
||||
输入命令 `scons --target=mdk5 -s` 重新生成 MDK5 的工程。
|
||||
|
||||
|
||||
|
||||
### 7）编译下载
|
||||
|
||||
打开生成的 MDK5 工程文件，编译并下载。
|
||||
|
||||
|
||||
|
||||
### 8）查看运行结果
|
||||
|
||||
程序运行后，输入命令 `list_device` 可以看到名为 uart2的设备，此时 `UART2` 设备已经可以使用了。
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
## 总结
|
||||
|
||||
当开发者需要使用未开启的外设时，只要在 ENV 工具中使能相关的外设即可，重新生成的工程中就会添加对应的驱动文件。开发者就可以利用 RT-Thread 提供的驱动开快速开发应用了。
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
# GD32系列驱动介绍
|
||||
|
||||
在 RT-Thread 实时操作系统中，各种各样的设备驱动是通过一套 I/O 设备管理框架来管理的。设备管理框架给上层应用提供了一套标准的设备操作 API，开发者通过调用这些标准设备操作 API，可以高效地完成和底层硬件外设的交互。设备管理框架的结构如下图所示：
|
||||
|
||||
|
||||
|
||||
使用 I/O 设备管理框架开发应用程序，有如下优点：
|
||||
|
||||
- 使用同一套标准的 API 开发应用程序，使应用程序具有更好的移植性
|
||||
- 底层驱动的升级和修改不会影响到上层代码
|
||||
- 驱动和应用程序相互独立，方便多个开发者协同开发
|
||||
|
||||
## 1. 驱动分类介绍
|
||||
|
||||
本小节介绍 BSP 提供的不同类别驱动的概念，对一个 BSP 而言，有如下三类驱动：
|
||||
|
||||
- **板载外设驱动**：指 MCU 之外，开发板上外设，例如 TF 卡、以太网和 LCD 等
|
||||
- **片上外设驱动**：指 MCU 芯片上的外设，例如硬件定时器、ADC 和看门狗等
|
||||
- **扩展模块驱动**：指可以通过扩展接口或者杜邦线连接的开发板的模块，例如 ESP8266 模块
|
||||
|
||||
这三种外设的示意图如下所示：
|
||||
|
||||
|
||||
|
||||
## 2. 外设驱动的使用方法
|
||||
|
||||
点击下表中的驱动名称，即可跳转到对应驱动框架的介绍文档。开发者可以通过阅读相关资料，了解如何在应用开发中通过设备驱动框架来使用这些外设驱动。
|
||||
|
||||
### 2.1 片上外设
|
||||
|
||||
| 序号 | 驱动 | 简介 |
|
||||
| ---- | ------------------------------------------------------------ | ------------------------------------------------ |
|
||||
| 1 | [GPIO](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pin/pin.md) | 操作 GPIO 管脚 |
|
||||
| 2 | [UART](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/uart/uart_v1/uart) | 通过串口收发数据 |
|
||||
| 3 | [soft I2C](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/i2c/i2c.md) | 通过软件 I2C 收发数据 |
|
||||
| 4 | [SPI](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi) | 通过 SPI 收发数据 |
|
||||
| 5 | [ADC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/adc/adc.md) | 测量管脚上的模拟量 |
|
||||
| 6 | SDIO | 通过 SDIO 读写数据 |
|
||||
| 7 | [TIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/hwtimer/hwtimer.md) | 使用硬件定时器实现测量时间和定时执行回调函数功能 |
|
||||
| 8 | [PWM](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm.md) | 在特定的管脚输出 PWM 波形 |
|
||||
| 9 | [RTC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc.md) | 设置和读取时间 |
|
||||
| 10 | [WDT](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog.md) | 看门狗驱动 |
|
||||
| 11 | [QSPI](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi.md) | 通过 SPI（1、2、4线） 收发数据 |
|
||||
|
||||
### 2.2 板载外设
|
||||
|
||||
| 序号 | 驱动 | 简介 |
|
||||
| ---- | ------- | --------------------------------------- |
|
||||
| 1 | SD | 适用于 SPI 接口或 SDIO 接口的 SD(TF) 卡 |
|
||||
| 2 | ETH PHY | 以太网 |
|
||||
| 3 | USB PHY | USB |
|
||||
| 4 | LCD | 显示屏 |
|
||||
|
||||
### 2.3 扩展模块
|
||||
|
||||
| 序号 | 驱动 | 简介 |
|
||||
| ---- | -------- | ---------------------- |
|
||||
| 1 | ESP8266 | 串口转 WIFI 模块 |
|
||||
| 2 | ENC28J60 | SPI 接口的以太网控制器 |
|
||||
|
||||
### 2.4 驱动示例代码
|
||||
|
||||
在 RT-Thread 的 `examples\test` 目录下，有 RT-Thread 提供的基于不同外设驱动的示例代码。在 env 工具中开启 BSP 中要测试的驱动，并将 `examples\test` 中对应的驱动框架测试文件加入工程，即可快速测试 BSP 中提供的驱动。
|
||||
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|
|
@ -0,0 +1,571 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# RT-Thread Configuration
|
||||
#
|
||||
|
||||
#
|
||||
# RT-Thread Kernel
|
||||
#
|
||||
CONFIG_RT_NAME_MAX=8
|
||||
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
|
||||
# CONFIG_RT_USING_SMP is not set
|
||||
CONFIG_RT_ALIGN_SIZE=4
|
||||
# CONFIG_RT_THREAD_PRIORITY_8 is not set
|
||||
CONFIG_RT_THREAD_PRIORITY_32=y
|
||||
# CONFIG_RT_THREAD_PRIORITY_256 is not set
|
||||
CONFIG_RT_THREAD_PRIORITY_MAX=32
|
||||
CONFIG_RT_TICK_PER_SECOND=100
|
||||
CONFIG_RT_USING_OVERFLOW_CHECK=y
|
||||
CONFIG_RT_USING_HOOK=y
|
||||
CONFIG_RT_USING_IDLE_HOOK=y
|
||||
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
|
||||
CONFIG_IDLE_THREAD_STACK_SIZE=256
|
||||
# CONFIG_RT_USING_TIMER_SOFT is not set
|
||||
|
||||
#
|
||||
# kservice optimization
|
||||
#
|
||||
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
|
||||
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
|
||||
CONFIG_RT_DEBUG=y
|
||||
CONFIG_RT_DEBUG_COLOR=y
|
||||
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
|
||||
|
||||
#
|
||||
# Inter-Thread communication
|
||||
#
|
||||
CONFIG_RT_USING_SEMAPHORE=y
|
||||
CONFIG_RT_USING_MUTEX=y
|
||||
CONFIG_RT_USING_EVENT=y
|
||||
CONFIG_RT_USING_MAILBOX=y
|
||||
CONFIG_RT_USING_MESSAGEQUEUE=y
|
||||
# CONFIG_RT_USING_SIGNALS is not set
|
||||
|
||||
#
|
||||
# Memory Management
|
||||
#
|
||||
CONFIG_RT_USING_MEMPOOL=y
|
||||
# CONFIG_RT_USING_MEMHEAP is not set
|
||||
# CONFIG_RT_USING_NOHEAP is not set
|
||||
CONFIG_RT_USING_SMALL_MEM=y
|
||||
# CONFIG_RT_USING_SLAB is not set
|
||||
# CONFIG_RT_USING_USERHEAP is not set
|
||||
# CONFIG_RT_USING_MEMTRACE is not set
|
||||
CONFIG_RT_USING_HEAP=y
|
||||
|
||||
#
|
||||
# Kernel Device Object
|
||||
#
|
||||
CONFIG_RT_USING_DEVICE=y
|
||||
# CONFIG_RT_USING_DEVICE_OPS is not set
|
||||
# CONFIG_RT_USING_INTERRUPT_INFO is not set
|
||||
CONFIG_RT_USING_CONSOLE=y
|
||||
CONFIG_RT_CONSOLEBUF_SIZE=128
|
||||
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
|
||||
# CONFIG_RT_PRINTF_LONGLONG is not set
|
||||
CONFIG_RT_VER_NUM=0x40004
|
||||
# CONFIG_RT_USING_CPU_FFS is not set
|
||||
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
|
||||
|
||||
#
|
||||
# RT-Thread Components
|
||||
#
|
||||
CONFIG_RT_USING_COMPONENTS_INIT=y
|
||||
CONFIG_RT_USING_USER_MAIN=y
|
||||
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
|
||||
CONFIG_RT_MAIN_THREAD_PRIORITY=10
|
||||
|
||||
#
|
||||
# C++ features
|
||||
#
|
||||
# CONFIG_RT_USING_CPLUSPLUS is not set
|
||||
|
||||
#
|
||||
# Command shell
|
||||
#
|
||||
CONFIG_RT_USING_FINSH=y
|
||||
CONFIG_FINSH_THREAD_NAME="tshell"
|
||||
CONFIG_FINSH_USING_HISTORY=y
|
||||
CONFIG_FINSH_HISTORY_LINES=5
|
||||
CONFIG_FINSH_USING_SYMTAB=y
|
||||
CONFIG_FINSH_USING_DESCRIPTION=y
|
||||
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
|
||||
CONFIG_FINSH_THREAD_PRIORITY=20
|
||||
CONFIG_FINSH_THREAD_STACK_SIZE=4096
|
||||
CONFIG_FINSH_CMD_SIZE=80
|
||||
# CONFIG_FINSH_USING_AUTH is not set
|
||||
CONFIG_FINSH_USING_MSH=y
|
||||
CONFIG_FINSH_USING_MSH_DEFAULT=y
|
||||
# CONFIG_FINSH_USING_MSH_ONLY is not set
|
||||
CONFIG_FINSH_ARG_MAX=10
|
||||
|
||||
#
|
||||
# Device virtual file system
|
||||
#
|
||||
# CONFIG_RT_USING_DFS is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
CONFIG_RT_USING_DEVICE_IPC=y
|
||||
CONFIG_RT_PIPE_BUFSZ=512
|
||||
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
|
||||
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
|
||||
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
|
||||
CONFIG_RT_USING_SERIAL=y
|
||||
CONFIG_RT_USING_SERIAL_V1=y
|
||||
# CONFIG_RT_USING_SERIAL_V2 is not set
|
||||
CONFIG_RT_SERIAL_USING_DMA=y
|
||||
CONFIG_RT_SERIAL_RB_BUFSZ=64
|
||||
# CONFIG_RT_USING_CAN is not set
|
||||
# CONFIG_RT_USING_HWTIMER is not set
|
||||
# CONFIG_RT_USING_CPUTIME is not set
|
||||
# CONFIG_RT_USING_I2C is not set
|
||||
# CONFIG_RT_USING_PHY is not set
|
||||
CONFIG_RT_USING_PIN=y
|
||||
# CONFIG_RT_USING_ADC is not set
|
||||
# CONFIG_RT_USING_DAC is not set
|
||||
# CONFIG_RT_USING_PWM is not set
|
||||
# CONFIG_RT_USING_MTD_NOR is not set
|
||||
# CONFIG_RT_USING_MTD_NAND is not set
|
||||
# CONFIG_RT_USING_PM is not set
|
||||
# CONFIG_RT_USING_RTC is not set
|
||||
# CONFIG_RT_USING_SDIO is not set
|
||||
# CONFIG_RT_USING_SPI is not set
|
||||
# CONFIG_RT_USING_WDT is not set
|
||||
# CONFIG_RT_USING_AUDIO is not set
|
||||
# CONFIG_RT_USING_SENSOR is not set
|
||||
# CONFIG_RT_USING_TOUCH is not set
|
||||
# CONFIG_RT_USING_HWCRYPTO is not set
|
||||
# CONFIG_RT_USING_PULSE_ENCODER is not set
|
||||
# CONFIG_RT_USING_INPUT_CAPTURE is not set
|
||||
# CONFIG_RT_USING_WIFI is not set
|
||||
|
||||
#
|
||||
# Using USB
|
||||
#
|
||||
# CONFIG_RT_USING_USB_HOST is not set
|
||||
# CONFIG_RT_USING_USB_DEVICE is not set
|
||||
|
||||
#
|
||||
# POSIX layer and C standard library
|
||||
#
|
||||
# CONFIG_RT_USING_LIBC is not set
|
||||
# CONFIG_RT_USING_PTHREADS is not set
|
||||
CONFIG_RT_LIBC_USING_TIME=y
|
||||
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
|
||||
|
||||
#
|
||||
# Network
|
||||
#
|
||||
|
||||
#
|
||||
# Socket abstraction layer
|
||||
#
|
||||
# CONFIG_RT_USING_SAL is not set
|
||||
|
||||
#
|
||||
# Network interface device
|
||||
#
|
||||
# CONFIG_RT_USING_NETDEV is not set
|
||||
|
||||
#
|
||||
# light weight TCP/IP stack
|
||||
#
|
||||
# CONFIG_RT_USING_LWIP is not set
|
||||
|
||||
#
|
||||
# AT commands
|
||||
#
|
||||
# CONFIG_RT_USING_AT is not set
|
||||
|
||||
#
|
||||
# VBUS(Virtual Software BUS)
|
||||
#
|
||||
# CONFIG_RT_USING_VBUS is not set
|
||||
|
||||
#
|
||||
# Utilities
|
||||
#
|
||||
# CONFIG_RT_USING_RYM is not set
|
||||
# CONFIG_RT_USING_ULOG is not set
|
||||
# CONFIG_RT_USING_UTEST is not set
|
||||
# CONFIG_RT_USING_RT_LINK is not set
|
||||
|
||||
#
|
||||
# RT-Thread Utestcases
|
||||
#
|
||||
# CONFIG_RT_USING_UTESTCASES is not set
|
||||
|
||||
#
|
||||
# RT-Thread online packages
|
||||
#
|
||||
|
||||
#
|
||||
# IoT - internet of things
|
||||
#
|
||||
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
|
||||
# CONFIG_PKG_USING_PAHOMQTT is not set
|
||||
# CONFIG_PKG_USING_UMQTT is not set
|
||||
# CONFIG_PKG_USING_WEBCLIENT is not set
|
||||
# CONFIG_PKG_USING_WEBNET is not set
|
||||
# CONFIG_PKG_USING_MONGOOSE is not set
|
||||
# CONFIG_PKG_USING_MYMQTT is not set
|
||||
# CONFIG_PKG_USING_KAWAII_MQTT is not set
|
||||
# CONFIG_PKG_USING_BC28_MQTT is not set
|
||||
# CONFIG_PKG_USING_WEBTERMINAL is not set
|
||||
# CONFIG_PKG_USING_CJSON is not set
|
||||
# CONFIG_PKG_USING_JSMN is not set
|
||||
# CONFIG_PKG_USING_LIBMODBUS is not set
|
||||
# CONFIG_PKG_USING_FREEMODBUS is not set
|
||||
# CONFIG_PKG_USING_LJSON is not set
|
||||
# CONFIG_PKG_USING_EZXML is not set
|
||||
# CONFIG_PKG_USING_NANOPB is not set
|
||||
|
||||
#
|
||||
# Wi-Fi
|
||||
#
|
||||
|
||||
#
|
||||
# Marvell WiFi
|
||||
#
|
||||
# CONFIG_PKG_USING_WLANMARVELL is not set
|
||||
|
||||
#
|
||||
# Wiced WiFi
|
||||
#
|
||||
# CONFIG_PKG_USING_WLAN_WICED is not set
|
||||
# CONFIG_PKG_USING_RW007 is not set
|
||||
# CONFIG_PKG_USING_COAP is not set
|
||||
# CONFIG_PKG_USING_NOPOLL is not set
|
||||
# CONFIG_PKG_USING_NETUTILS is not set
|
||||
# CONFIG_PKG_USING_CMUX is not set
|
||||
# CONFIG_PKG_USING_PPP_DEVICE is not set
|
||||
# CONFIG_PKG_USING_AT_DEVICE is not set
|
||||
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
|
||||
# CONFIG_PKG_USING_WIZNET is not set
|
||||
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
|
||||
|
||||
#
|
||||
# IoT Cloud
|
||||
#
|
||||
# CONFIG_PKG_USING_ONENET is not set
|
||||
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
|
||||
# CONFIG_PKG_USING_ALI_IOTKIT is not set
|
||||
# CONFIG_PKG_USING_AZURE is not set
|
||||
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
|
||||
# CONFIG_PKG_USING_JIOT-C-SDK is not set
|
||||
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
|
||||
# CONFIG_PKG_USING_JOYLINK is not set
|
||||
# CONFIG_PKG_USING_NIMBLE is not set
|
||||
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
|
||||
# CONFIG_PKG_USING_IPMSG is not set
|
||||
# CONFIG_PKG_USING_LSSDP is not set
|
||||
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
|
||||
# CONFIG_PKG_USING_LIBRWS is not set
|
||||
# CONFIG_PKG_USING_TCPSERVER is not set
|
||||
# CONFIG_PKG_USING_PROTOBUF_C is not set
|
||||
# CONFIG_PKG_USING_DLT645 is not set
|
||||
# CONFIG_PKG_USING_QXWZ is not set
|
||||
# CONFIG_PKG_USING_SMTP_CLIENT is not set
|
||||
# CONFIG_PKG_USING_ABUP_FOTA is not set
|
||||
# CONFIG_PKG_USING_LIBCURL2RTT is not set
|
||||
# CONFIG_PKG_USING_CAPNP is not set
|
||||
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
|
||||
# CONFIG_PKG_USING_AGILE_TELNET is not set
|
||||
# CONFIG_PKG_USING_NMEALIB is not set
|
||||
# CONFIG_PKG_USING_AGILE_JSMN is not set
|
||||
# CONFIG_PKG_USING_PDULIB is not set
|
||||
# CONFIG_PKG_USING_BTSTACK is not set
|
||||
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
|
||||
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
|
||||
# CONFIG_PKG_USING_MAVLINK is not set
|
||||
# CONFIG_PKG_USING_RAPIDJSON is not set
|
||||
# CONFIG_PKG_USING_BSAL is not set
|
||||
# CONFIG_PKG_USING_AGILE_MODBUS is not set
|
||||
# CONFIG_PKG_USING_AGILE_FTP is not set
|
||||
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
|
||||
# CONFIG_PKG_USING_RT_LINK_HW is not set
|
||||
|
||||
#
|
||||
# security packages
|
||||
#
|
||||
# CONFIG_PKG_USING_MBEDTLS is not set
|
||||
# CONFIG_PKG_USING_libsodium is not set
|
||||
# CONFIG_PKG_USING_TINYCRYPT is not set
|
||||
# CONFIG_PKG_USING_TFM is not set
|
||||
# CONFIG_PKG_USING_YD_CRYPTO is not set
|
||||
|
||||
#
|
||||
# language packages
|
||||
#
|
||||
# CONFIG_PKG_USING_LUA is not set
|
||||
# CONFIG_PKG_USING_JERRYSCRIPT is not set
|
||||
# CONFIG_PKG_USING_MICROPYTHON is not set
|
||||
# CONFIG_PKG_USING_PIKASCRIPT is not set
|
||||
|
||||
#
|
||||
# multimedia packages
|
||||
#
|
||||
# CONFIG_PKG_USING_OPENMV is not set
|
||||
# CONFIG_PKG_USING_MUPDF is not set
|
||||
# CONFIG_PKG_USING_STEMWIN is not set
|
||||
# CONFIG_PKG_USING_WAVPLAYER is not set
|
||||
# CONFIG_PKG_USING_TJPGD is not set
|
||||
# CONFIG_PKG_USING_PDFGEN is not set
|
||||
# CONFIG_PKG_USING_HELIX is not set
|
||||
# CONFIG_PKG_USING_AZUREGUIX is not set
|
||||
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
|
||||
# CONFIG_PKG_USING_NUEMWIN is not set
|
||||
# CONFIG_PKG_USING_MP3PLAYER is not set
|
||||
# CONFIG_PKG_USING_TINYJPEG is not set
|
||||
|
||||
#
|
||||
# tools packages
|
||||
#
|
||||
# CONFIG_PKG_USING_CMBACKTRACE is not set
|
||||
# CONFIG_PKG_USING_EASYFLASH is not set
|
||||
# CONFIG_PKG_USING_EASYLOGGER is not set
|
||||
# CONFIG_PKG_USING_SYSTEMVIEW is not set
|
||||
# CONFIG_PKG_USING_SEGGER_RTT is not set
|
||||
# CONFIG_PKG_USING_RDB is not set
|
||||
# CONFIG_PKG_USING_QRCODE is not set
|
||||
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
|
||||
# CONFIG_PKG_USING_ULOG_FILE is not set
|
||||
# CONFIG_PKG_USING_LOGMGR is not set
|
||||
# CONFIG_PKG_USING_ADBD is not set
|
||||
# CONFIG_PKG_USING_COREMARK is not set
|
||||
# CONFIG_PKG_USING_DHRYSTONE is not set
|
||||
# CONFIG_PKG_USING_MEMORYPERF is not set
|
||||
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
|
||||
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
|
||||
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
|
||||
# CONFIG_PKG_USING_BS8116A is not set
|
||||
# CONFIG_PKG_USING_GPS_RMC is not set
|
||||
# CONFIG_PKG_USING_URLENCODE is not set
|
||||
# CONFIG_PKG_USING_UMCN is not set
|
||||
# CONFIG_PKG_USING_LWRB2RTT is not set
|
||||
# CONFIG_PKG_USING_CPU_USAGE is not set
|
||||
# CONFIG_PKG_USING_GBK2UTF8 is not set
|
||||
# CONFIG_PKG_USING_VCONSOLE is not set
|
||||
# CONFIG_PKG_USING_KDB is not set
|
||||
# CONFIG_PKG_USING_WAMR is not set
|
||||
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
|
||||
# CONFIG_PKG_USING_LWLOG is not set
|
||||
# CONFIG_PKG_USING_ANV_TRACE is not set
|
||||
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
|
||||
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
|
||||
# CONFIG_PKG_USING_ANV_BENCH is not set
|
||||
# CONFIG_PKG_USING_DEVMEM is not set
|
||||
# CONFIG_PKG_USING_REGEX is not set
|
||||
# CONFIG_PKG_USING_MEM_SANDBOX is not set
|
||||
# CONFIG_PKG_USING_SOLAR_TERMS is not set
|
||||
# CONFIG_PKG_USING_GAN_ZHI is not set
|
||||
|
||||
#
|
||||
# system packages
|
||||
#
|
||||
|
||||
#
|
||||
# acceleration: Assembly language or algorithmic acceleration packages
|
||||
#
|
||||
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
|
||||
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
|
||||
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
|
||||
# CONFIG_PKG_USING_QFPLIB_M3 is not set
|
||||
|
||||
#
|
||||
# Micrium: Micrium software products porting for RT-Thread
|
||||
#
|
||||
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
|
||||
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
|
||||
# CONFIG_PKG_USING_UC_CRC is not set
|
||||
# CONFIG_PKG_USING_UC_CLK is not set
|
||||
# CONFIG_PKG_USING_UC_COMMON is not set
|
||||
# CONFIG_PKG_USING_UC_MODBUS is not set
|
||||
# CONFIG_PKG_USING_GUIENGINE is not set
|
||||
# CONFIG_PKG_USING_CAIRO is not set
|
||||
# CONFIG_PKG_USING_PIXMAN is not set
|
||||
# CONFIG_PKG_USING_PARTITION is not set
|
||||
# CONFIG_PKG_USING_FAL is not set
|
||||
# CONFIG_PKG_USING_FLASHDB is not set
|
||||
# CONFIG_PKG_USING_SQLITE is not set
|
||||
# CONFIG_PKG_USING_RTI is not set
|
||||
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
|
||||
# CONFIG_PKG_USING_CMSIS is not set
|
||||
# CONFIG_PKG_USING_DFS_YAFFS is not set
|
||||
# CONFIG_PKG_USING_LITTLEFS is not set
|
||||
# CONFIG_PKG_USING_DFS_JFFS2 is not set
|
||||
# CONFIG_PKG_USING_DFS_UFFS is not set
|
||||
# CONFIG_PKG_USING_LWEXT4 is not set
|
||||
# CONFIG_PKG_USING_THREAD_POOL is not set
|
||||
# CONFIG_PKG_USING_ROBOTS is not set
|
||||
# CONFIG_PKG_USING_EV is not set
|
||||
# CONFIG_PKG_USING_SYSWATCH is not set
|
||||
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
|
||||
# CONFIG_PKG_USING_PLCCORE is not set
|
||||
# CONFIG_PKG_USING_RAMDISK is not set
|
||||
# CONFIG_PKG_USING_MININI is not set
|
||||
# CONFIG_PKG_USING_QBOOT is not set
|
||||
# CONFIG_PKG_USING_PPOOL is not set
|
||||
# CONFIG_PKG_USING_OPENAMP is not set
|
||||
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
|
||||
# CONFIG_PKG_USING_LPM is not set
|
||||
# CONFIG_PKG_USING_TLSF is not set
|
||||
# CONFIG_PKG_USING_EVENT_RECORDER is not set
|
||||
# CONFIG_PKG_USING_ARM_2D is not set
|
||||
|
||||
#
|
||||
# peripheral libraries and drivers
|
||||
#
|
||||
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
|
||||
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
|
||||
# CONFIG_PKG_USING_SHT2X is not set
|
||||
# CONFIG_PKG_USING_SHT3X is not set
|
||||
# CONFIG_PKG_USING_AS7341 is not set
|
||||
# CONFIG_PKG_USING_STM32_SDIO is not set
|
||||
# CONFIG_PKG_USING_ICM20608 is not set
|
||||
# CONFIG_PKG_USING_U8G2 is not set
|
||||
# CONFIG_PKG_USING_BUTTON is not set
|
||||
# CONFIG_PKG_USING_PCF8574 is not set
|
||||
# CONFIG_PKG_USING_SX12XX is not set
|
||||
# CONFIG_PKG_USING_SIGNAL_LED is not set
|
||||
# CONFIG_PKG_USING_LEDBLINK is not set
|
||||
# CONFIG_PKG_USING_LITTLED is not set
|
||||
# CONFIG_PKG_USING_LKDGUI is not set
|
||||
# CONFIG_PKG_USING_NRF5X_SDK is not set
|
||||
# CONFIG_PKG_USING_NRFX is not set
|
||||
# CONFIG_PKG_USING_WM_LIBRARIES is not set
|
||||
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
|
||||
# CONFIG_PKG_USING_INFRARED is not set
|
||||
# CONFIG_PKG_USING_AGILE_BUTTON is not set
|
||||
# CONFIG_PKG_USING_AGILE_LED is not set
|
||||
# CONFIG_PKG_USING_AT24CXX is not set
|
||||
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
|
||||
# CONFIG_PKG_USING_AD7746 is not set
|
||||
# CONFIG_PKG_USING_PCA9685 is not set
|
||||
# CONFIG_PKG_USING_I2C_TOOLS is not set
|
||||
# CONFIG_PKG_USING_NRF24L01 is not set
|
||||
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
|
||||
# CONFIG_PKG_USING_MAX17048 is not set
|
||||
# CONFIG_PKG_USING_RPLIDAR is not set
|
||||
# CONFIG_PKG_USING_AS608 is not set
|
||||
# CONFIG_PKG_USING_RC522 is not set
|
||||
# CONFIG_PKG_USING_WS2812B is not set
|
||||
# CONFIG_PKG_USING_EMBARC_BSP is not set
|
||||
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
|
||||
# CONFIG_PKG_USING_MULTI_RTIMER is not set
|
||||
# CONFIG_PKG_USING_MAX7219 is not set
|
||||
# CONFIG_PKG_USING_BEEP is not set
|
||||
# CONFIG_PKG_USING_EASYBLINK is not set
|
||||
# CONFIG_PKG_USING_PMS_SERIES is not set
|
||||
# CONFIG_PKG_USING_CAN_YMODEM is not set
|
||||
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
|
||||
# CONFIG_PKG_USING_QLED is not set
|
||||
# CONFIG_PKG_USING_PAJ7620 is not set
|
||||
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
|
||||
# CONFIG_PKG_USING_LD3320 is not set
|
||||
# CONFIG_PKG_USING_WK2124 is not set
|
||||
# CONFIG_PKG_USING_LY68L6400 is not set
|
||||
# CONFIG_PKG_USING_DM9051 is not set
|
||||
# CONFIG_PKG_USING_SSD1306 is not set
|
||||
# CONFIG_PKG_USING_QKEY is not set
|
||||
# CONFIG_PKG_USING_RS485 is not set
|
||||
# CONFIG_PKG_USING_NES is not set
|
||||
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
|
||||
# CONFIG_PKG_USING_VDEVICE is not set
|
||||
# CONFIG_PKG_USING_SGM706 is not set
|
||||
# CONFIG_PKG_USING_STM32WB55_SDK is not set
|
||||
# CONFIG_PKG_USING_RDA58XX is not set
|
||||
# CONFIG_PKG_USING_LIBNFC is not set
|
||||
# CONFIG_PKG_USING_MFOC is not set
|
||||
# CONFIG_PKG_USING_TMC51XX is not set
|
||||
# CONFIG_PKG_USING_TCA9534 is not set
|
||||
# CONFIG_PKG_USING_KOBUKI is not set
|
||||
# CONFIG_PKG_USING_ROSSERIAL is not set
|
||||
# CONFIG_PKG_USING_MICRO_ROS is not set
|
||||
# CONFIG_PKG_USING_MCP23008 is not set
|
||||
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
|
||||
|
||||
#
|
||||
# AI packages
|
||||
#
|
||||
# CONFIG_PKG_USING_LIBANN is not set
|
||||
# CONFIG_PKG_USING_NNOM is not set
|
||||
# CONFIG_PKG_USING_ONNX_BACKEND is not set
|
||||
# CONFIG_PKG_USING_ONNX_PARSER is not set
|
||||
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
|
||||
# CONFIG_PKG_USING_ELAPACK is not set
|
||||
# CONFIG_PKG_USING_ULAPACK is not set
|
||||
# CONFIG_PKG_USING_QUEST is not set
|
||||
# CONFIG_PKG_USING_NAXOS is not set
|
||||
|
||||
#
|
||||
# miscellaneous packages
|
||||
#
|
||||
# CONFIG_PKG_USING_LIBCSV is not set
|
||||
# CONFIG_PKG_USING_OPTPARSE is not set
|
||||
# CONFIG_PKG_USING_FASTLZ is not set
|
||||
# CONFIG_PKG_USING_MINILZO is not set
|
||||
# CONFIG_PKG_USING_QUICKLZ is not set
|
||||
# CONFIG_PKG_USING_LZMA is not set
|
||||
# CONFIG_PKG_USING_MULTIBUTTON is not set
|
||||
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
|
||||
# CONFIG_PKG_USING_CANFESTIVAL is not set
|
||||
# CONFIG_PKG_USING_ZLIB is not set
|
||||
# CONFIG_PKG_USING_MINIZIP is not set
|
||||
# CONFIG_PKG_USING_DSTR is not set
|
||||
# CONFIG_PKG_USING_TINYFRAME is not set
|
||||
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
|
||||
# CONFIG_PKG_USING_DIGITALCTRL is not set
|
||||
# CONFIG_PKG_USING_UPACKER is not set
|
||||
# CONFIG_PKG_USING_UPARAM is not set
|
||||
|
||||
#
|
||||
# samples: kernel and components samples
|
||||
#
|
||||
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_HELLO is not set
|
||||
# CONFIG_PKG_USING_VI is not set
|
||||
# CONFIG_PKG_USING_KI is not set
|
||||
# CONFIG_PKG_USING_ARMv7M_DWT is not set
|
||||
# CONFIG_PKG_USING_VT100 is not set
|
||||
# CONFIG_PKG_USING_UKAL is not set
|
||||
# CONFIG_PKG_USING_CRCLIB is not set
|
||||
|
||||
#
|
||||
# entertainment: terminal games and other interesting software packages
|
||||
#
|
||||
# CONFIG_PKG_USING_SL is not set
|
||||
# CONFIG_PKG_USING_CAL is not set
|
||||
# CONFIG_PKG_USING_ACLOCK is not set
|
||||
# CONFIG_PKG_USING_THREES is not set
|
||||
# CONFIG_PKG_USING_2048 is not set
|
||||
# CONFIG_PKG_USING_SNAKE is not set
|
||||
# CONFIG_PKG_USING_TETRIS is not set
|
||||
# CONFIG_PKG_USING_DONUT is not set
|
||||
# CONFIG_PKG_USING_LWGPS is not set
|
||||
# CONFIG_PKG_USING_STATE_MACHINE is not set
|
||||
# CONFIG_PKG_USING_MCURSES is not set
|
||||
# CONFIG_PKG_USING_COWSAY is not set
|
||||
CONFIG_SOC_GD32407V=y
|
||||
# CONFIG_BSP_USING_SDRAM is not set
|
||||
# CONFIG_BSP_USING_UART0 is not set
|
||||
CONFIG_BSP_USING_UART1=y
|
||||
# CONFIG_BSP_USING_UART2 is not set
|
||||
# CONFIG_BSP_USING_UART3 is not set
|
||||
# CONFIG_BSP_USING_UART4 is not set
|
||||
# CONFIG_BSP_USING_UART5 is not set
|
||||
# CONFIG_BSP_USING_LPUART1 is not set
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "../libraries/Kconfig"
|
||||
source "board/Kconfig"
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
# GD32407V-START开发板BSP说明
|
||||
|
||||
## 简介
|
||||
|
||||
GD32407V-START是-兆易创新推出的一款GD32F4XX系列的评估板，最高主频高达168M，该开发板具有丰富的板载资源，可以充分发挥 GD32407V 的芯片性能。
|
||||
|
||||
|
||||
开发板外观如下图所示：
|
||||
|
||||
|
||||
|
||||
该开发板常用 **板载资源** 如下：
|
||||
|
||||
- GD32407V，主频 168MHz，3072KB FLASH ，192KB RAM
|
||||
|
||||
- 常用外设
|
||||
|
||||
- LED ：3个，LED1 (电源指示灯），LED2（PC6）
|
||||
- 按键：2个，K1（复位引脚），K2（用户按键，PA0）
|
||||
|
||||
- 常用接口：USB 接口
|
||||
|
||||
- 调试接口：GD-LINK
|
||||
|
||||
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用数据线连接开发板到 PC，使用USB转TTL模块连接PA2(MCU TX)和PA3(MCU RX)，打开电源开关。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用 GD-Link 仿真器下载程序，在通过 GD-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，LED 闪烁。
|
||||
|
||||
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.0.4 build Jan 9 2021
|
||||
2006 - 2021 Copyright by rt-thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口1的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
|
||||
|
||||
## 注意事项
|
||||
|
||||
暂无
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [BruceOu](https://github.com/Ouxiaolong/), 邮箱：<ouxiaolong@bruceou.cn>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
gd32_library = 'GD32F4xx_HAL'
|
||||
rtconfig.BSP_LIBRARY_TYPE = gd32_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = os.path.join(str(Dir('#')), 'applications')
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd, str(Dir('#'))]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-20 BruceOu first implementation
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED2 pin: PC6 */
|
||||
#define LED2_PIN GET_PIN(C, 6)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int count = 1;
|
||||
|
||||
/* set LED2 pin mode to output */
|
||||
rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (count++)
|
||||
{
|
||||
rt_pin_write(LED2_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED2_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_GD32407V
|
||||
bool
|
||||
select SOC_SERIES_GD32F4
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default y
|
||||
|
||||
config BSP_UART1_RX_USING_DMA
|
||||
bool "Enable UART1 RX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Enable SPI BUS"
|
||||
default n
|
||||
select RT_USING_SPI
|
||||
if BSP_USING_SPI
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable SPI1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_SPI1_TX_USING_DMA
|
||||
bool "Enable SPI1 TX DMA"
|
||||
depends on BSP_USING_SPI1
|
||||
default n
|
||||
|
||||
config BSP_SPI1_RX_USING_DMA
|
||||
bool "Enable SPI1 RX DMA"
|
||||
depends on BSP_USING_SPI1
|
||||
select BSP_SPI1_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C1
|
||||
bool "Enable I2C1 BUS (software simulation)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
select RT_USING_I2C_BITOPS
|
||||
select RT_USING_PIN
|
||||
if BSP_USING_I2C1
|
||||
config BSP_I2C1_SCL_PIN
|
||||
int "i2c1 scl pin number"
|
||||
range 1 216
|
||||
default 24
|
||||
config BSP_I2C1_SDA_PIN
|
||||
int "I2C1 sda pin number"
|
||||
range 1 216
|
||||
default 25
|
||||
endif
|
||||
source "../libraries/HAL_Drivers/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
Import('SDK_LIB')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s']
|
||||
|
||||
CPPDEFINES = ['GD32F407xx']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-20 BruceOu first implementation
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void Error_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler */
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
NVIC_SetPriority(SysTick_IRQn, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial GD32 board.
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
/* NVIC Configuration */
|
||||
#define NVIC_VTOR_MASK 0x3FFFFF80
|
||||
#ifdef VECT_TAB_RAM
|
||||
/* Set the Vector Table base location at 0x10000000 */
|
||||
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
|
||||
#else /* VECT_TAB_FLASH */
|
||||
/* Set the Vector Table base location at 0x08000000 */
|
||||
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
|
||||
#endif
|
||||
|
||||
SystemClock_Config();
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SDRAM
|
||||
rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
|
||||
#else
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-20 BruceOu first implementation
|
||||
*/
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
#include "drv_usart.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#include "gd32f4xx_exti.h"
|
||||
|
||||
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
|
||||
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
|
||||
|
||||
// <o> Internal SRAM memory size[Kbytes] <8-64>
|
||||
// <i>Default: 64
|
||||
#ifdef __ICCARM__
|
||||
// Use *.icf ram symbal, to avoid hardcode.
|
||||
extern char __ICFEDIT_region_RAM_end__;
|
||||
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
|
||||
#else
|
||||
#define GD32_SRAM_SIZE 128
|
||||
#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
|
||||
#endif
|
||||
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END GD32_SRAM_END
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*!
|
||||
\file gd32f4xx_libopt.h
|
||||
\brief library optional for gd32f4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2016 GigaDevice
|
||||
|
||||
2016-10-19, V1.0.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_LIBOPT_H
|
||||
#define GD32F4XX_LIBOPT_H
|
||||
#include "gd32f4xx_rcu.h"
|
||||
#include "gd32f4xx_adc.h"
|
||||
#include "gd32f4xx_can.h"
|
||||
#include "gd32f4xx_crc.h"
|
||||
#include "gd32f4xx_ctc.h"
|
||||
#include "gd32f4xx_dac.h"
|
||||
#include "gd32f4xx_dbg.h"
|
||||
#include "gd32f4xx_dci.h"
|
||||
#include "gd32f4xx_dma.h"
|
||||
//#include "gd32f4xx_enet.h"
|
||||
#include "gd32f4xx_exmc.h"
|
||||
#include "gd32f4xx_exti.h"
|
||||
#include "gd32f4xx_fmc.h"
|
||||
#include "gd32f4xx_fwdgt.h"
|
||||
#include "gd32f4xx_gpio.h"
|
||||
#include "gd32f4xx_syscfg.h"
|
||||
#include "gd32f4xx_i2c.h"
|
||||
#include "gd32f4xx_ipa.h"
|
||||
#include "gd32f4xx_iref.h"
|
||||
#include "gd32f4xx_pmu.h"
|
||||
#include "gd32f4xx_rcu.h"
|
||||
#include "gd32f4xx_rtc.h"
|
||||
#include "gd32f4xx_sdio.h"
|
||||
#include "gd32f4xx_spi.h"
|
||||
#include "gd32f4xx_timer.h"
|
||||
#include "gd32f4xx_tli.h"
|
||||
#include "gd32f4xx_trng.h"
|
||||
#include "gd32f4xx_usart.h"
|
||||
#include "gd32f4xx_wwdgt.h"
|
||||
#include "gd32f4xx_misc.h"
|
||||
|
||||
#endif /* GD32F4XX_LIBOPT_H */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x082FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
|
||||
define symbol __region_RAM1_start__ = 0x10000000;
|
||||
define symbol __region_RAM1_end__ = 0x1000FFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
keep { section FSymTab };
|
||||
keep { section VSymTab };
|
||||
keep { section .rti_fn* };
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM1_region { section .sram };
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* linker script for GD32F4xx with GNU ld
|
||||
* bernard.xiong 2009-10-14
|
||||
*/
|
||||
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
MEMORY
|
||||
{
|
||||
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 3072k /* 3072KB flash */
|
||||
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */
|
||||
}
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x200;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} > CODE = 0
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = .;
|
||||
} > CODE
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >DATA
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >DATA
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > DATA
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00300000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00300000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00030000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 96 KiB |
|
|
@ -0,0 +1,758 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread_gd32f4xx</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"CMSIS-DAP" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F407VK$Flash\GD32F4xx_3MB.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,668 @@
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x300000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x300000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>GD3232F407xx, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\HAL_Drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\none-gcc;..\libraries\GD32F4xx_HAL\CMSIS\GD\GD32F4xx\Include;..\libraries\GD32F4xx_HAL\CMSIS;..\libraries\GD32F4xx_HAL\GD32F4xx_standard_peripheral\Include;..\..\..\examples\utest\testcases\kernel</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\gd32_rom.ld</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Applications</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>applications\main.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CPU</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>showmem.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>div0.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>backtrace.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>cpuport.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>context_rvds.S</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>DeviceDrivers</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>pin.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>serial.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>completion.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\completion.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>workqueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>dataqueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>ringbuffer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>pipe.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>waitqueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>ringblk_buf.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\drivers\src\ringblk_buf.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Drivers</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_gd32f4xx.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\libraries\GD32F4xx_HAL\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>board.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>board\board.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>drv_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\HAL_Drivers\drv_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>drv_usart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\HAL_Drivers\drv_usart.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Finsh</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>shell.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>msh.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Kernel</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>object.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\object.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>irq.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\irq.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>mempool.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\mempool.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\timer.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>components.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\components.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>kservice.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\kservice.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>idle.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\idle.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>mem.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\mem.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>device.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\device.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>ipc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\ipc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>thread.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\thread.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>clock.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\clock.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>scheduler.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\src\scheduler.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>libc</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>time.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\components\libc\compilers\common\time.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Libraries</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>gd32f4xx_syscfg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\GD32F4xx_HAL\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_exti.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\GD32F4xx_HAL\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\GD32F4xx_HAL\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_rcu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\GD32F4xx_HAL\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_misc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\GD32F4xx_HAL\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_usart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\GD32F4xx_HAL\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>system_gd32f4xx.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\libraries\GD32F4xx_HAL\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.1" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="rt-thread_gd32f4xx"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayDesc></LayDesc>
|
||||
<LayUrl></LayUrl>
|
||||
<LayKeys></LayKeys>
|
||||
<LayCat></LayCat>
|
||||
<LayLic></LayLic>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
#define RT_DEBUG
|
||||
#define RT_DEBUG_COLOR
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x40004
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
|
||||
/* C++ features */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_DEFAULT
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SYSTEM_WORKQUEUE
|
||||
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_LIBC_USING_TIME
|
||||
#define RT_LIBC_DEFAULT_TIMEZONE 8
|
||||
|
||||
/* Network */
|
||||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
|
||||
/* AT commands */
|
||||
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
|
||||
/* AI packages */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
#define SOC_GD32407V
|
||||
#define BSP_USING_UART1
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='keil'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -DGD32F407'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4.fp '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M4'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M4'
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread_gd32f4xx</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"CMSIS-DAP" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F407VK$Flash\GD32F4xx_3MB.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F407VK$Flash\GD32F4xx_3MB.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000 -FP0($$Device:GD32F407VK$Flash\GD32F4xx_3MB.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,628 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||
|
||||
<SchemaVersion>1.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rt-thread_gd32f4xx</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>GD32F407VK</Device>
|
||||
<Vendor>GigaDevice</Vendor>
|
||||
<Cpu>IRAM(0x20000000-0x2002FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x08000000-0x082FFFFF) CLOCK(16000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile>"Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code")</StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>gd32f4xx0.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>SFD\GD\GD32F4xx\GD32F4xx.SFR</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath>GD\GD32F4xx\</RegisterFilePath>
|
||||
<DBRegisterFilePath>GD\GD32F4xx\</DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\output\</OutputDirectory>
|
||||
<OutputName>rtthread-gd32f4xx</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -REMAP</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<RestoreTracepoints>0</RestoreTracepoints>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>3</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x300000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x300000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Include;..\..\..\Library\Utilities;..\</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Application</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_it.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\gd32f4xx_it.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSIS</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>system_gd32f4xx.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>GD32F4xx_Peripherals</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>gd32f4xx_adc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_can.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_crc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_crc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_ctc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_dac.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_dbg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_dci.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_dma.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_enet.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_exmc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exmc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_exti.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_fmc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_fwdgt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fwdgt.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_ipa.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_iref.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_misc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_pmu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_rcu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_rtc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rtc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_sdio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_spi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_syscfg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_tli.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_tli.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_trng.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_trng.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_usart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_wwdgt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>GD32F4xx_EVAL</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>gd32f450z_eval.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Utilities\gd32f450z_eval.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Startup</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_gd32f4xx.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Doc</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>readme.txt</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\readme.txt</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,417 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rt-thread_gd32f4xx</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>GD32F407VK</Device>
|
||||
<Vendor>GigaDevice</Vendor>
|
||||
<PackID>GigaDevice.GD32F4xx_DFP.2.1.0</PackID>
|
||||
<PackURL>http://gd32mcu.com/data/documents/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x030000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x0300000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000 -FP0($$Device:GD32F407VK$Flash\GD32F4xx_3MB.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:GD32F407VK$Device\Include\gd32f4xx.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:GD32F407VK$SVD\GD32F4xx.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputName>rtthread-gd32f4xx</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>0</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -REMAP -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x300000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x300000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\gd32_rom.ld</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.1" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.1"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="rt-thread_gd32f4xx"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayDesc></LayDesc>
|
||||
<LayUrl></LayUrl>
|
||||
<LayKeys></LayKeys>
|
||||
<LayCat></LayCat>
|
||||
<LayLic></LayLic>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
/*!
|
||||
\file gd32f4xx.h
|
||||
\brief general definitions for GD32F4xx
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_H
|
||||
#define GD32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* define GD32F4xx */
|
||||
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407)
|
||||
/* #define GD32F450 */
|
||||
/* #define GD32F405 */
|
||||
/* #define GD32F407 */
|
||||
#endif /* define GD32F4xx */
|
||||
|
||||
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407)
|
||||
#error "Please select the target GD32F4xx device in gd32f4xx.h file"
|
||||
#endif /* undefine GD32F4xx tip */
|
||||
|
||||
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
||||
#if !defined (HXTAL_VALUE)
|
||||
#define HXTAL_VALUE ((uint32_t)25000000)
|
||||
#endif /* high speed crystal oscillator value */
|
||||
|
||||
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
||||
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
||||
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
|
||||
#endif /* high speed crystal oscillator startup timeout */
|
||||
|
||||
/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */
|
||||
#if !defined (IRC16M_VALUE)
|
||||
#define IRC16M_VALUE ((uint32_t)16000000)
|
||||
#endif /* internal 16MHz RC oscillator value */
|
||||
|
||||
/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */
|
||||
#if !defined (IRC16M_STARTUP_TIMEOUT)
|
||||
#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
||||
#endif /* internal 16MHz RC oscillator startup timeout */
|
||||
|
||||
/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
|
||||
#if !defined (IRC32K_VALUE)
|
||||
#define IRC32K_VALUE ((uint32_t)32000)
|
||||
#endif /* internal 32KHz RC oscillator value */
|
||||
|
||||
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
||||
#if !defined (LXTAL_VALUE)
|
||||
#define LXTAL_VALUE ((uint32_t)32768)
|
||||
#endif /* low speed crystal oscillator value */
|
||||
|
||||
/* I2S external clock in selection */
|
||||
//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U
|
||||
|
||||
/* GD32F4xx firmware library version number V1.0 */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\
|
||||
|(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\
|
||||
|(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\
|
||||
|(__GD32F4xx_STDPERIPH_VERSION_RC))
|
||||
|
||||
/* configuration of the cortex-M4 processor and core peripherals */
|
||||
#define __CM4_REV 0x0001 /*!< core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
/* define interrupt number */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* cortex-M4 processor exceptions numbers */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */
|
||||
/* interruput numbers */
|
||||
WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
|
||||
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||
TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */
|
||||
RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */
|
||||
FMC_IRQn = 4, /*!< FMC interrupt */
|
||||
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
|
||||
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
|
||||
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
|
||||
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
|
||||
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
|
||||
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
|
||||
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */
|
||||
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */
|
||||
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
|
||||
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
|
||||
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
|
||||
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
|
||||
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
|
||||
ADC_IRQn = 18, /*!< ADC interrupt */
|
||||
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
|
||||
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
|
||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
|
||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
|
||||
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
|
||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
|
||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
|
||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
|
||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||
DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */
|
||||
|
||||
#if defined (GD32F450)
|
||||
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
||||
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
|
||||
ENET_IRQn = 61, /*!< ENET interrupt */
|
||||
ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBFS_IRQn = 67, /*!< USBFS interrupt */
|
||||
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
|
||||
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
|
||||
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
|
||||
USART5_IRQn = 71, /*!< USART5 interrupt */
|
||||
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
|
||||
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
|
||||
USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
|
||||
USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
|
||||
USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
|
||||
USBHS_IRQn = 77, /*!< USBHS interrupt */
|
||||
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||
UART6_IRQn = 82, /*!< UART6 interrupt */
|
||||
UART7_IRQn = 83, /*!< UART7 interrupt */
|
||||
SPI3_IRQn = 84, /*!< SPI3 interrupt */
|
||||
SPI4_IRQn = 85, /*!< SPI4 interrupt */
|
||||
SPI5_IRQn = 86, /*!< SPI5 interrupt */
|
||||
TLI_IRQn = 88, /*!< TLI interrupt */
|
||||
TLI_ER_IRQn = 89, /*!< TLI error interrupt */
|
||||
IPA_IRQn = 90, /*!< IPA interrupt */
|
||||
#endif /* GD32F450 */
|
||||
|
||||
#if defined (GD32F405)
|
||||
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBFS_IRQn = 67, /*!< USBFS interrupt */
|
||||
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
|
||||
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
|
||||
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
|
||||
USART5_IRQn = 71, /*!< USART5 interrupt */
|
||||
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
|
||||
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
|
||||
USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */
|
||||
USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
|
||||
USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
|
||||
USBHS_IRQn = 77, /*!< USBHS interrupt */
|
||||
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||
#endif /* GD32F405 */
|
||||
|
||||
#if defined (GD32F407)
|
||||
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
||||
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
|
||||
ENET_IRQn = 61, /*!< ENET interrupt */
|
||||
ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBFS_IRQn = 67, /*!< USBFS interrupt */
|
||||
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
|
||||
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
|
||||
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
|
||||
USART5_IRQn = 71, /*!< USART5 interrupt */
|
||||
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
|
||||
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
|
||||
USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
|
||||
USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
|
||||
USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
|
||||
USBHS_IRQn = 77, /*!< USBHS interrupt */
|
||||
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||
#endif /* GD32F407 */
|
||||
|
||||
} IRQn_Type;
|
||||
|
||||
/* includes */
|
||||
#include "core_cm4.h"
|
||||
#include "system_gd32f4xx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
/* enum definitions */
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||
|
||||
/* bit operations */
|
||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||
|
||||
/* main flash and SRAM memory map */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||
#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */
|
||||
#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
||||
|
||||
/* peripheral memory map */
|
||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
|
||||
#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */
|
||||
|
||||
/* EXMC memory map */
|
||||
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
||||
|
||||
/* advanced peripheral bus 1 memory map */
|
||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||
#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */
|
||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
||||
#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */
|
||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||||
#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */
|
||||
|
||||
/* advanced peripheral bus 2 memory map */
|
||||
#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */
|
||||
#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */
|
||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */
|
||||
#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */
|
||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */
|
||||
/* advanced high performance bus 1 memory map */
|
||||
#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
|
||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */
|
||||
#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */
|
||||
#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */
|
||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */
|
||||
#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
|
||||
#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */
|
||||
#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
|
||||
|
||||
/* advanced high performance bus 2 memory map */
|
||||
#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */
|
||||
#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */
|
||||
#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */
|
||||
/* option byte and debug memory map */
|
||||
#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */
|
||||
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||||
|
||||
/* define marco USE_STDPERIPH_DRIVER */
|
||||
#if !defined USE_STDPERIPH_DRIVER
|
||||
#define USE_STDPERIPH_DRIVER
|
||||
#endif
|
||||
#ifdef USE_STDPERIPH_DRIVER
|
||||
#include "gd32f4xx_libopt.h"
|
||||
#endif /* USE_STDPERIPH_DRIVER */
|
||||
|
||||
#ifdef cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*!
|
||||
\file system_gd32f4xx.h
|
||||
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
|
||||
GD32F4xx Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32F4XX_H
|
||||
#define SYSTEM_GD32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit (void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32F4XX_H */
|
||||
|
|
@ -0,0 +1,427 @@
|
|||
;/*!
|
||||
; \file startup_gd32f4xx.s
|
||||
; \brief start up file
|
||||
;*/
|
||||
|
||||
;/*
|
||||
; Copyright (C) 2016 GigaDevice
|
||||
|
||||
; 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
;*/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC_IRQHandler ; 34:ADC
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
DCD TIMER0_CC_IRQHandler ; 43:TIMER0 Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
DCD TIMER7_CC_IRQHandler ; 62:TIMER7 Capture Compare
|
||||
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||
DCD USART5_IRQHandler ; 87:USART5
|
||||
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||
DCD USBHS_IRQHandler ; 93:USBHS
|
||||
DCD DCI_IRQHandler ; 94:DCI
|
||||
DCD 0 ; 95:Reserved
|
||||
DCD TRNG_IRQHandler ; 96:TRNG
|
||||
DCD FPU_IRQHandler ; 97:FPU
|
||||
DCD UART6_IRQHandler ; 98:UART6
|
||||
DCD UART7_IRQHandler ; 98:UART7
|
||||
DCD SPI3_IRQHandler ; 100:SPI3
|
||||
DCD SPI4_IRQHandler ; 101:SPI4
|
||||
DCD SPI5_IRQHandler ; 102:SPI5
|
||||
DCD TLI_IRQHandler ; 104:TLI
|
||||
DCD TLI_ER_IRQHandler ; 105:TLI Error
|
||||
DCD IPA_IRQHandler ; 106:IPA
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_CC_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||
EXPORT USBFS_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT USART5_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT USBHS_IRQHandler [WEAK]
|
||||
EXPORT DCI_IRQHandler [WEAK]
|
||||
EXPORT TRNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT UART6_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT TLI_IRQHandler [WEAK]
|
||||
EXPORT TLI_ER_IRQHandler [WEAK]
|
||||
EXPORT IPA_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN0_TX_IRQHandler
|
||||
CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_CC_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBFS_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_CC_IRQHandler
|
||||
DMA0_Channel7_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_DAC_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
ENET_IRQHandler
|
||||
ENET_WKUP_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_EWMC_IRQHandler
|
||||
USBFS_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
USART5_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
USBHS_EP1_Out_IRQHandler
|
||||
USBHS_EP1_In_IRQHandler
|
||||
USBHS_WKUP_IRQHandler
|
||||
USBHS_IRQHandler
|
||||
DCI_IRQHandler
|
||||
TRNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
UART6_IRQHandler
|
||||
UART7_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
TLI_IRQHandler
|
||||
TLI_ER_IRQHandler
|
||||
IPA_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,315 @@
|
|||
;/*
|
||||
; * Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2018-05-22 tanek first implementation
|
||||
; */
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack // Top of Stack
|
||||
.word Reset_Handler // Reset Handler
|
||||
.word NMI_Handler // NMI Handler
|
||||
.word HardFault_Handler // Hard Fault Handler
|
||||
.word MemManage_Handler // MPU Fault Handler
|
||||
.word BusFault_Handler // Bus Fault Handler
|
||||
.word UsageFault_Handler // Usage Fault Handler
|
||||
.word 0 // Reserved
|
||||
.word 0 // Reserved
|
||||
.word 0 // Reserved
|
||||
.word 0 // Reserved
|
||||
.word SVC_Handler // SVCall Handler
|
||||
.word DebugMon_Handler // Debug Monitor Handler
|
||||
.word 0 // Reserved
|
||||
.word PendSV_Handler // PendSV Handler
|
||||
.word SysTick_Handler // SysTick Handler
|
||||
|
||||
// external interrupts handler
|
||||
.word WWDGT_IRQHandler // 16:Window Watchdog Timer
|
||||
.word LVD_IRQHandler // 17:LVD through EXTI Line detect
|
||||
.word TAMPER_STAMP_IRQHandler // 18:Tamper and TimeStamp through EXTI Line detect
|
||||
.word RTC_WKUP_IRQHandler // 19:RTC Wakeup through EXTI Line
|
||||
.word FMC_IRQHandler // 20:FMC
|
||||
.word RCU_CTC_IRQHandler // 21:RCU and CTC
|
||||
.word EXTI0_IRQHandler // 22:EXTI Line 0
|
||||
.word EXTI1_IRQHandler // 23:EXTI Line 1
|
||||
.word EXTI2_IRQHandler // 24:EXTI Line 2
|
||||
.word EXTI3_IRQHandler // 25:EXTI Line 3
|
||||
.word EXTI4_IRQHandler // 26:EXTI Line 4
|
||||
.word DMA0_Channel0_IRQHandler // 27:DMA0 Channel0
|
||||
.word DMA0_Channel1_IRQHandler // 28:DMA0 Channel1
|
||||
.word DMA0_Channel2_IRQHandler // 29:DMA0 Channel2
|
||||
.word DMA0_Channel3_IRQHandler // 30:DMA0 Channel3
|
||||
.word DMA0_Channel4_IRQHandler // 31:DMA0 Channel4
|
||||
.word DMA0_Channel5_IRQHandler // 32:DMA0 Channel5
|
||||
.word DMA0_Channel6_IRQHandler // 33:DMA0 Channel6
|
||||
.word ADC_IRQHandler // 34:ADC
|
||||
.word CAN0_TX_IRQHandler // 35:CAN0 TX
|
||||
.word CAN0_RX0_IRQHandler // 36:CAN0 RX0
|
||||
.word CAN0_RX1_IRQHandler // 37:CAN0 RX1
|
||||
.word CAN0_EWMC_IRQHandler // 38:CAN0 EWMC
|
||||
.word EXTI5_9_IRQHandler // 39:EXTI5 to EXTI9
|
||||
.word TIMER0_BRK_TIMER8_IRQHandler // 40:TIMER0 Break and TIMER8
|
||||
.word TIMER0_UP_TIMER9_IRQHandler // 41:TIMER0 Update and TIMER9
|
||||
.word TIMER0_TRG_CMT_TIMER10_IRQHandler // 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
.word TIMER0_CC_IRQHandler // 43:TIMER0 Capture Compare
|
||||
.word TIMER1_IRQHandler // 44:TIMER1
|
||||
.word TIMER2_IRQHandler // 45:TIMER2
|
||||
.word TIMER3_IRQHandler // 46:TIMER3
|
||||
.word I2C0_EV_IRQHandler // 47:I2C0 Event
|
||||
.word I2C0_ER_IRQHandler // 48:I2C0 Error
|
||||
.word I2C1_EV_IRQHandler // 49:I2C1 Event
|
||||
.word I2C1_ER_IRQHandler // 50:I2C1 Error
|
||||
.word SPI0_IRQHandler // 51:SPI0
|
||||
.word SPI1_IRQHandler // 52:SPI1
|
||||
.word USART0_IRQHandler // 53:USART0
|
||||
.word USART1_IRQHandler // 54:USART1
|
||||
.word USART2_IRQHandler // 55:USART2
|
||||
.word EXTI10_15_IRQHandler // 56:EXTI10 to EXTI15
|
||||
.word RTC_Alarm_IRQHandler // 57:RTC Alarm
|
||||
.word USBFS_WKUP_IRQHandler // 58:USBFS Wakeup
|
||||
.word TIMER7_BRK_TIMER11_IRQHandler // 59:TIMER7 Break and TIMER11
|
||||
.word TIMER7_UP_TIMER12_IRQHandler // 60:TIMER7 Update and TIMER12
|
||||
.word TIMER7_TRG_CMT_TIMER13_IRQHandler // 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
.word TIMER7_CC_IRQHandler // 62:TIMER7 Capture Compare
|
||||
.word DMA0_Channel7_IRQHandler // 63:DMA0 Channel7
|
||||
.word EXMC_IRQHandler // 64:EXMC
|
||||
.word SDIO_IRQHandler // 65:SDIO
|
||||
.word TIMER4_IRQHandler // 66:TIMER4
|
||||
.word SPI2_IRQHandler // 67:SPI2
|
||||
.word UART3_IRQHandler // 68:UART3
|
||||
.word UART4_IRQHandler // 69:UART4
|
||||
.word TIMER5_DAC_IRQHandler // 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||
.word TIMER6_IRQHandler // 71:TIMER6
|
||||
.word DMA1_Channel0_IRQHandler // 72:DMA1 Channel0
|
||||
.word DMA1_Channel1_IRQHandler // 73:DMA1 Channel1
|
||||
.word DMA1_Channel2_IRQHandler // 74:DMA1 Channel2
|
||||
.word DMA1_Channel3_IRQHandler // 75:DMA1 Channel3
|
||||
.word DMA1_Channel4_IRQHandler // 76:DMA1 Channel4
|
||||
.word ENET_IRQHandler // 77:Ethernet
|
||||
.word ENET_WKUP_IRQHandler // 78:Ethernet Wakeup through EXTI Line
|
||||
.word CAN1_TX_IRQHandler // 79:CAN1 TX
|
||||
.word CAN1_RX0_IRQHandler // 80:CAN1 RX0
|
||||
.word CAN1_RX1_IRQHandler // 81:CAN1 RX1
|
||||
.word USBFS_IRQHandler // 83:USBFS
|
||||
.word DMA1_Channel5_IRQHandler // 84:DMA1 Channel5
|
||||
.word DMA1_Channel6_IRQHandler // 85:DMA1 Channel6
|
||||
.word DMA1_Channel7_IRQHandler // 86:DMA1 Channel7
|
||||
.word USART5_IRQHandler // 87:USART5
|
||||
.word I2C2_EV_IRQHandler // 88:I2C2 Event
|
||||
.word I2C2_ER_IRQHandler // 89:I2C2 Error
|
||||
.word USBHS_EP1_Out_IRQHandler // 90:USBHS Endpoint 1 Out
|
||||
.word USBHS_EP1_In_IRQHandler // 91:USBHS Endpoint 1 in
|
||||
.word USBHS_WKUP_IRQHandler // 92:USBHS Wakeup through EXTI Line
|
||||
.word USBHS_IRQHandler // 93:USBHS
|
||||
.word DCI_IRQHandler // 94:DCI
|
||||
.word 0 // 95:Reserved
|
||||
.word TRNG_IRQHandler // 96:TRNG
|
||||
.word FPU_IRQHandler // 97:FPU
|
||||
.word UART6_IRQHandler // 98:UART6
|
||||
.word UART7_IRQHandler // 98:UART7
|
||||
.word SPI3_IRQHandler // 100:SPI3
|
||||
.word SPI4_IRQHandler // 101:SPI4
|
||||
.word SPI5_IRQHandler // 102:SPI5
|
||||
.word TLI_IRQHandler // 104:TLI
|
||||
.word TLI_ER_IRQHandler // 105:TLI Error
|
||||
.word IPA_IRQHandler // 106:IPA
|
||||
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r1, =_sidata
|
||||
ldr r2, =_sdata
|
||||
ldr r3, =_edata
|
||||
|
||||
subs r3, r2
|
||||
ble fill_bss_start
|
||||
|
||||
loop_copy_data:
|
||||
subs r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt loop_copy_data
|
||||
|
||||
fill_bss_start:
|
||||
ldr r1, =__bss_start
|
||||
ldr r2, =__bss_end
|
||||
movs r0, 0
|
||||
subs r2, r1
|
||||
ble startup_enter
|
||||
|
||||
loop_fill_bss:
|
||||
subs r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt loop_fill_bss
|
||||
|
||||
startup_enter:
|
||||
bl SystemInit
|
||||
bl entry
|
||||
|
||||
/* Exception Handlers */
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.type MemManage_Handler, %function
|
||||
MemManage_Handler:
|
||||
b .
|
||||
.size MemManage_Handler, . - MemManage_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
/* IQR Handler */
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ WWDGT_IRQHandler
|
||||
IRQ LVD_IRQHandler
|
||||
IRQ TAMPER_STAMP_IRQHandler
|
||||
IRQ RTC_WKUP_IRQHandler
|
||||
IRQ FMC_IRQHandler
|
||||
IRQ RCU_CTC_IRQHandler
|
||||
IRQ EXTI0_IRQHandler
|
||||
IRQ EXTI1_IRQHandler
|
||||
IRQ EXTI2_IRQHandler
|
||||
IRQ EXTI3_IRQHandler
|
||||
IRQ EXTI4_IRQHandler
|
||||
IRQ DMA0_Channel0_IRQHandler
|
||||
IRQ DMA0_Channel1_IRQHandler
|
||||
IRQ DMA0_Channel2_IRQHandler
|
||||
IRQ DMA0_Channel3_IRQHandler
|
||||
IRQ DMA0_Channel4_IRQHandler
|
||||
IRQ DMA0_Channel5_IRQHandler
|
||||
IRQ DMA0_Channel6_IRQHandler
|
||||
IRQ ADC_IRQHandler
|
||||
IRQ CAN0_TX_IRQHandler
|
||||
IRQ CAN0_RX0_IRQHandler
|
||||
IRQ CAN0_RX1_IRQHandler
|
||||
IRQ CAN0_EWMC_IRQHandler
|
||||
IRQ EXTI5_9_IRQHandler
|
||||
IRQ TIMER0_BRK_TIMER8_IRQHandler
|
||||
IRQ TIMER0_UP_TIMER9_IRQHandler
|
||||
IRQ TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
IRQ TIMER0_CC_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ TIMER3_IRQHandler
|
||||
IRQ I2C0_EV_IRQHandler
|
||||
IRQ I2C0_ER_IRQHandler
|
||||
IRQ I2C1_EV_IRQHandler
|
||||
IRQ I2C1_ER_IRQHandler
|
||||
IRQ SPI0_IRQHandler
|
||||
IRQ SPI1_IRQHandler
|
||||
IRQ USART0_IRQHandler
|
||||
IRQ USART1_IRQHandler
|
||||
IRQ USART2_IRQHandler
|
||||
IRQ EXTI10_15_IRQHandler
|
||||
IRQ RTC_Alarm_IRQHandler
|
||||
IRQ USBFS_WKUP_IRQHandler
|
||||
IRQ TIMER7_BRK_TIMER11_IRQHandler
|
||||
IRQ TIMER7_UP_TIMER12_IRQHandler
|
||||
IRQ TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
IRQ TIMER7_CC_IRQHandler
|
||||
IRQ DMA0_Channel7_IRQHandler
|
||||
IRQ EXMC_IRQHandler
|
||||
IRQ SDIO_IRQHandler
|
||||
IRQ TIMER4_IRQHandler
|
||||
IRQ SPI2_IRQHandler
|
||||
IRQ UART3_IRQHandler
|
||||
IRQ UART4_IRQHandler
|
||||
IRQ TIMER5_DAC_IRQHandler
|
||||
IRQ TIMER6_IRQHandler
|
||||
IRQ DMA1_Channel0_IRQHandler
|
||||
IRQ DMA1_Channel1_IRQHandler
|
||||
IRQ DMA1_Channel2_IRQHandler
|
||||
IRQ DMA1_Channel3_IRQHandler
|
||||
IRQ DMA1_Channel4_IRQHandler
|
||||
IRQ ENET_IRQHandler
|
||||
IRQ ENET_WKUP_IRQHandler
|
||||
IRQ CAN1_TX_IRQHandler
|
||||
IRQ CAN1_RX0_IRQHandler
|
||||
IRQ CAN1_RX1_IRQHandler
|
||||
IRQ CAN1_EWMC_IRQHandler
|
||||
IRQ USBFS_IRQHandler
|
||||
IRQ DMA1_Channel5_IRQHandler
|
||||
IRQ DMA1_Channel6_IRQHandler
|
||||
IRQ DMA1_Channel7_IRQHandler
|
||||
IRQ USART5_IRQHandler
|
||||
IRQ I2C2_EV_IRQHandler
|
||||
IRQ I2C2_ER_IRQHandler
|
||||
IRQ USBHS_EP1_Out_IRQHandler
|
||||
IRQ USBHS_EP1_In_IRQHandler
|
||||
IRQ USBHS_WKUP_IRQHandler
|
||||
IRQ USBHS_IRQHandler
|
||||
IRQ DCI_IRQHandler
|
||||
IRQ TRNG_IRQHandler
|
||||
IRQ FPU_IRQHandler
|
||||
IRQ UART6_IRQHandler
|
||||
IRQ UART7_IRQHandler
|
||||
IRQ SPI3_IRQHandler
|
||||
IRQ SPI4_IRQHandler
|
||||
IRQ SPI5_IRQHandler
|
||||
IRQ TLI_IRQHandler
|
||||
IRQ TLI_ER_IRQHandler
|
||||
IRQ IPA_IRQHandler
|
||||
|
|
@ -0,0 +1,640 @@
|
|||
;/*!
|
||||
; \file startup_gd32f4xx.s
|
||||
; \brief start up file
|
||||
;*/
|
||||
|
||||
;/*
|
||||
; Copyright (C) 2016 GigaDevice
|
||||
|
||||
; 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
|
||||
;*/
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||
|
||||
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC_IRQHandler ; 34:ADC
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||
DCD TIMER0_CC_IRQHandler ; 43:TIMER0 Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||
DCD TIMER7_CC_IRQHandler ; 62:TIMER7 Capture Compare
|
||||
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||
DCD USART5_IRQHandler ; 87:USART5
|
||||
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||
DCD USBHS_IRQHandler ; 93:USBHS
|
||||
DCD DCI_IRQHandler ; 94:DCI
|
||||
DCD 0 ; 95:Reserved
|
||||
DCD TRNG_IRQHandler ; 96:TRNG
|
||||
DCD FPU_IRQHandler ; 97:FPU
|
||||
DCD UART6_IRQHandler ; 98:UART6
|
||||
DCD UART7_IRQHandler ; 98:UART7
|
||||
DCD SPI3_IRQHandler ; 100:SPI3
|
||||
DCD SPI4_IRQHandler ; 101:SPI4
|
||||
DCD SPI5_IRQHandler ; 102:SPI5
|
||||
DCD TLI_IRQHandler ; 104:TLI
|
||||
DCD TLI_ER_IRQHandler ; 105:TLI Error
|
||||
DCD IPA_IRQHandler ; 106:IPA
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMPER_STAMP_IRQHandler
|
||||
B TAMPER_STAMP_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_CTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_CTC_IRQHandler
|
||||
B RCU_CTC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel0_IRQHandler
|
||||
B DMA0_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel1_IRQHandler
|
||||
B DMA0_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel2_IRQHandler
|
||||
B DMA0_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel3_IRQHandler
|
||||
B DMA0_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel4_IRQHandler
|
||||
B DMA0_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel5_IRQHandler
|
||||
B DMA0_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel6_IRQHandler
|
||||
B DMA0_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_TX_IRQHandler
|
||||
B CAN0_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX0_IRQHandler
|
||||
B CAN0_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX1_IRQHandler
|
||||
B CAN0_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_EWMC_IRQHandler
|
||||
B CAN0_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_9_IRQHandler
|
||||
B EXTI5_9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
B TIMER0_BRK_TIMER8_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
B TIMER0_UP_TIMER9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_CC_IRQHandler
|
||||
B TIMER0_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_15_IRQHandler
|
||||
B EXTI10_15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_WKUP_IRQHandler
|
||||
B USBFS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
B TIMER7_BRK_TIMER11_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
B TIMER7_UP_TIMER12_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_CC_IRQHandler
|
||||
B TIMER7_CC_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel7_IRQHandler
|
||||
B DMA0_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK EXMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXMC_IRQHandler
|
||||
B EXMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER4_IRQHandler
|
||||
B TIMER4_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_DAC_IRQHandler
|
||||
B TIMER5_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIMER6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER6_IRQHandler
|
||||
B TIMER6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel0_IRQHandler
|
||||
B DMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK ENET_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_IRQHandler
|
||||
B ENET_IRQHandler
|
||||
|
||||
PUBWEAK ENET_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_WKUP_IRQHandler
|
||||
B ENET_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_EWMC_IRQHandler
|
||||
B CAN1_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_IRQHandler
|
||||
B USBFS_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK USART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART5_IRQHandler
|
||||
B USART5_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_EP1_Out_IRQHandler
|
||||
B USBHS_EP1_Out_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_EP1_In_IRQHandler
|
||||
B USBHS_EP1_In_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_WKUP_IRQHandler
|
||||
B USBHS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_IRQHandler
|
||||
B USBHS_IRQHandler
|
||||
|
||||
PUBWEAK DCI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCI_IRQHandler
|
||||
B DCI_IRQHandler
|
||||
|
||||
PUBWEAK TRNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TRNG_IRQHandler
|
||||
B TRNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK UART6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART6_IRQHandler
|
||||
B UART6_IRQHandler
|
||||
|
||||
PUBWEAK UART7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART7_IRQHandler
|
||||
B UART7_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK SPI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI4_IRQHandler
|
||||
B SPI4_IRQHandler
|
||||
|
||||
PUBWEAK SPI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI5_IRQHandler
|
||||
B SPI5_IRQHandler
|
||||
|
||||
PUBWEAK TLI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TLI_IRQHandler
|
||||
B TLI_IRQHandler
|
||||
|
||||
PUBWEAK TLI_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TLI_ER_IRQHandler
|
||||
B TLI_ER_IRQHandler
|
||||
|
||||
PUBWEAK IPA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPA_IRQHandler
|
||||
B IPA_IRQHandler
|
||||
END
|
||||
|
|
@ -0,0 +1,916 @@
|
|||
/*!
|
||||
\file system_gd32f4xx.c
|
||||
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
|
||||
GD32F4xx Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* system frequency define */
|
||||
#define __IRC16M (IRC16M_VALUE) /* internal 16 MHz RC oscillator frequency */
|
||||
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
|
||||
#define __SYS_OSC_CLK (__IRC16M) /* main oscillator frequency */
|
||||
|
||||
/* select a system clock by uncommenting the following line */
|
||||
//#define __SYSTEM_CLOCK_IRC16M (uint32_t)(__IRC16M)
|
||||
//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
|
||||
//#define __SYSTEM_CLOCK_120M_PLL_IRC16M (uint32_t)(120000000)
|
||||
//#define __SYSTEM_CLOCK_120M_PLL_8M_HXTAL (uint32_t)(120000000)
|
||||
//#define __SYSTEM_CLOCK_120M_PLL_25M_HXTAL (uint32_t)(120000000)
|
||||
//#define __SYSTEM_CLOCK_168M_PLL_IRC16M (uint32_t)(168000000)
|
||||
//#define __SYSTEM_CLOCK_168M_PLL_8M_HXTAL (uint32_t)(168000000)
|
||||
//#define __SYSTEM_CLOCK_168M_PLL_25M_HXTAL (uint32_t)(168000000)
|
||||
//#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000)
|
||||
//#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000)
|
||||
#define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000)
|
||||
|
||||
#define SEL_IRC16M 0x00U
|
||||
#define SEL_HXTAL 0x01U
|
||||
#define SEL_PLLP 0x02U
|
||||
#define RCU_MODIFY {volatile uint32_t i; \
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
|
||||
for(i=0;i<50000;i++);}
|
||||
|
||||
/* set the system clock frequency and declare the system clock configuration function */
|
||||
#ifdef __SYSTEM_CLOCK_IRC16M
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC16M;
|
||||
static void system_clock_16m_irc16m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
|
||||
static void system_clock_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC16M;
|
||||
static void system_clock_120m_irc16m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_8M_HXTAL;
|
||||
static void system_clock_120m_8m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_25M_HXTAL;
|
||||
static void system_clock_120m_25m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_IRC16M;
|
||||
static void system_clock_168m_irc16m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_8M_HXTAL;
|
||||
static void system_clock_168m_8m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_25M_HXTAL;
|
||||
static void system_clock_168m_25m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_IRC16M;
|
||||
static void system_clock_200m_irc16m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_8M_HXTAL;
|
||||
static void system_clock_200m_8m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL;
|
||||
static void system_clock_200m_25m_hxtal(void);
|
||||
|
||||
#endif /* __SYSTEM_CLOCK_IRC16M */
|
||||
|
||||
/* configure the system clock */
|
||||
static void system_clock_config(void);
|
||||
|
||||
/*!
|
||||
\brief setup the microcontroller system, initialize the system
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCU clock configuration to the default reset state ------------*/
|
||||
/* Set IRC16MEN bit */
|
||||
RCU_CTL |= RCU_CTL_IRC16MEN;
|
||||
|
||||
RCU_MODIFY
|
||||
|
||||
/* Reset CFG0 register */
|
||||
RCU_CFG0 = 0x00000000U;
|
||||
|
||||
/* Reset HXTALEN, CKMEN and PLLEN bits */
|
||||
RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCU_PLL = 0x24003010U;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCU_INT = 0x00000000U;
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
system_clock_config();
|
||||
}
|
||||
/*!
|
||||
\brief configure the system clock
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_config(void)
|
||||
{
|
||||
#ifdef __SYSTEM_CLOCK_IRC16M
|
||||
system_clock_16m_irc16m();
|
||||
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
||||
system_clock_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M)
|
||||
system_clock_120m_irc16m();
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL)
|
||||
system_clock_120m_8m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL)
|
||||
system_clock_120m_25m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M)
|
||||
system_clock_168m_irc16m();
|
||||
#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL)
|
||||
system_clock_168m_8m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL)
|
||||
system_clock_168m_25m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M)
|
||||
system_clock_200m_irc16m();
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL)
|
||||
system_clock_200m_8m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
|
||||
system_clock_200m_25m_hxtal();
|
||||
#endif /* __SYSTEM_CLOCK_IRC16M */
|
||||
}
|
||||
|
||||
#ifdef __SYSTEM_CLOCK_IRC16M
|
||||
/*!
|
||||
\brief configure the system clock to 16M by IRC16M
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_16m_irc16m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC16M */
|
||||
RCU_CTL |= RCU_CTL_IRC16MEN;
|
||||
|
||||
/* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
|
||||
}while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
/* select IRC16M as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_IRC16M;
|
||||
|
||||
/* wait until IRC16M is selected as system clock */
|
||||
while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to HXTAL
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
/* select HXTAL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
|
||||
|
||||
/* wait until HXTAL is selected as system clock */
|
||||
while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M)
|
||||
/*!
|
||||
\brief configure the system clock to 120M by PLL which selects IRC16M as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_120m_irc16m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC16M */
|
||||
RCU_CTL |= RCU_CTL_IRC16MEN;
|
||||
|
||||
/* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
|
||||
}while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* IRC16M is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||
/* APB1 = AHB/4 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||
|
||||
/* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
|
||||
RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||
(RCU_PLLSRC_IRC16M) | (5U << 24U));
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* Enable the high-drive to extend the clock frequency to 120 Mhz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_120m_8m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||
/* APB1 = AHB/4 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||
|
||||
/* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
|
||||
RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||
(RCU_PLLSRC_HXTAL) | (5U << 24U));
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* Enable the high-drive to extend the clock frequency to 120 Mhz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_120m_25m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||
/* APB1 = AHB/4 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||
|
||||
/* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
|
||||
RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||
(RCU_PLLSRC_HXTAL) | (5U << 24U));
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* Enable the high-drive to extend the clock frequency to 120 Mhz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M)
|
||||
/*!
|
||||
\brief configure the system clock to 168M by PLL which selects IRC16M as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_168m_irc16m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC16M */
|
||||
RCU_CTL |= RCU_CTL_IRC16MEN;
|
||||
|
||||
/* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
|
||||
}while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* IRC16M is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||
/* APB1 = AHB/4 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||
|
||||
/* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
|
||||
RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||
(RCU_PLLSRC_IRC16M) | (7U << 24U));
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* Enable the high-drive to extend the clock frequency to 168 Mhz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 168M by PLL which selects HXTAL(8M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_168m_8m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
while((0U == (RCU_CTL & RCU_CTL_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++)){
|
||||
}
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||
/* APB1 = AHB/4 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||
|
||||
/* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
|
||||
RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) |
|
||||
(RCU_PLLSRC_HXTAL) | (7 << 24U));
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* Enable the high-drive to extend the clock frequency to 168 Mhz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 168M by PLL which selects HXTAL(25M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_168m_25m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||
|
||||
/* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
|
||||
RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||
(RCU_PLLSRC_HXTAL) | (7U << 24U));
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* Enable the high-drive to extend the clock frequency to 168 Mhz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M)
|
||||
/*!
|
||||
\brief configure the system clock to 200M by PLL which selects IRC16M as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_200m_irc16m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC16M */
|
||||
RCU_CTL |= RCU_CTL_IRC16MEN;
|
||||
|
||||
/* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
|
||||
}while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* IRC16M is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||
/* APB1 = AHB/4 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||
|
||||
/* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
|
||||
RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||
(RCU_PLLSRC_IRC16M) | (9U << 24U));
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* Enable the high-drive to extend the clock frequency to 200 Mhz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 200M by PLL which selects HXTAL(8M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_200m_8m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||
/* APB1 = AHB/4 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||
|
||||
/* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
|
||||
RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||
(RCU_PLLSRC_HXTAL) | (9U << 24U));
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* Enable the high-drive to extend the clock frequency to 200 Mhz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 200M by PLL which selects HXTAL(25M) as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_200m_25m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||
PMU_CTL |= PMU_CTL_LDOVS;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB/2 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||
/* APB1 = AHB/4 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||
|
||||
/* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
|
||||
RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||
(RCU_PLLSRC_HXTAL) | (9U << 24U));
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||
}
|
||||
|
||||
/* Enable the high-drive to extend the clock frequency to 200 Mhz */
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||
}
|
||||
|
||||
/* select the high-drive mode */
|
||||
PMU_CTL |= PMU_CTL_HDS;
|
||||
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||
}
|
||||
|
||||
/* select PLL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __SYSTEM_CLOCK_IRC16M */
|
||||
/*!
|
||||
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t sws;
|
||||
uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp;
|
||||
|
||||
/* exponent of AHB, APB1 and APB2 clock divider */
|
||||
const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
sws = GET_BITS(RCU_CFG0, 2, 3);
|
||||
switch(sws){
|
||||
/* IRC16M is selected as CK_SYS */
|
||||
case SEL_IRC16M:
|
||||
SystemCoreClock = IRC16M_VALUE;
|
||||
break;
|
||||
/* HXTAL is selected as CK_SYS */
|
||||
case SEL_HXTAL:
|
||||
SystemCoreClock = HXTAL_VALUE;
|
||||
break;
|
||||
/* PLLP is selected as CK_SYS */
|
||||
case SEL_PLLP:
|
||||
/* get the value of PLLPSC[5:0] */
|
||||
pllpsc = GET_BITS(RCU_PLL, 0U, 5U);
|
||||
plln = GET_BITS(RCU_PLL, 6U, 14U);
|
||||
pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U;
|
||||
/* PLL clock source selection, HXTAL or IRC8M/2 */
|
||||
pllsel = (RCU_PLL & RCU_PLL_PLLSEL);
|
||||
if (RCU_PLLSRC_HXTAL == pllsel) {
|
||||
ck_src = HXTAL_VALUE;
|
||||
} else {
|
||||
ck_src = IRC16M_VALUE;
|
||||
}
|
||||
SystemCoreClock = ((ck_src / pllpsc) * plln)/pllp;
|
||||
break;
|
||||
/* IRC16M is selected as CK_SYS */
|
||||
default:
|
||||
SystemCoreClock = IRC16M_VALUE;
|
||||
break;
|
||||
}
|
||||
/* calculate AHB clock frequency */
|
||||
idx = GET_BITS(RCU_CFG0, 4, 7);
|
||||
clk_exp = ahb_exp[idx];
|
||||
SystemCoreClock = SystemCoreClock >> clk_exp;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,697 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm4_simd.h
|
||||
* @brief CMSIS Cortex-M4 SIMD Header File
|
||||
* @version V3.30
|
||||
* @date 17. February 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM4_SIMD_H
|
||||
#define __CORE_CM4_SIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32) ) >> 32))
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SSAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/* not yet supported */
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM4_SIMD_H */
|
||||
|
|
@ -0,0 +1,664 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.10
|
||||
* @date 18. March 2015
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority with condition
|
||||
|
||||
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority with condition
|
||||
|
||||
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
__ASM volatile ("");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
|
||||
__ASM volatile ("");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
@ -0,0 +1,916 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.10
|
||||
* @date 18. March 2015
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0)
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0)
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0)
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
|
||||
|
||||
result = value; // r will be reversed bits of v; first get LSB of v
|
||||
for (value >>= 1; value; value >>= 1)
|
||||
{
|
||||
result <<= 1;
|
||||
result |= value & 1;
|
||||
s--;
|
||||
}
|
||||
result <<= s; // shift when v's highest bits are zero
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/* Define macros for porting to both thumb1 and thumb2.
|
||||
* For thumb1, use low register (r0-r7), specified by constrant "l"
|
||||
* Otherwise, use general registers, specified by constrant "r" */
|
||||
#if defined (__thumb__) && !defined (__thumb2__)
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||||
#else
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||||
#endif
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||
return __builtin_bswap32(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
return (short)__builtin_bswap16(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << (32 - op2));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
#else
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
|
||||
|
||||
result = value; // r will be reversed bits of v; first get LSB of v
|
||||
for (value >>= 1; value; value >>= 1)
|
||||
{
|
||||
result <<= 1;
|
||||
result |= value & 1;
|
||||
s--;
|
||||
}
|
||||
result <<= s; // shift when v's highest bits are zero
|
||||
#endif
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __builtin_clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex" ::: "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
|
|
@ -0,0 +1,515 @@
|
|||
/*!
|
||||
\file gd32f4xx_adc.h
|
||||
\brief definitions for the ADC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_ADC_H
|
||||
#define GD32F4XX_ADC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* ADC definitions */
|
||||
#define ADC0 ADC_BASE
|
||||
#define ADC1 (ADC_BASE + 0x100U)
|
||||
#define ADC2 (ADC_BASE + 0x200U)
|
||||
|
||||
/* registers definitions */
|
||||
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
|
||||
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
|
||||
#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
|
||||
#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
|
||||
#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
|
||||
#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
||||
#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
||||
#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
||||
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
|
||||
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
|
||||
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
|
||||
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
|
||||
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
|
||||
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
|
||||
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
|
||||
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
|
||||
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
|
||||
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
|
||||
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
|
||||
#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */
|
||||
#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */
|
||||
#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */
|
||||
#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization regular data register */
|
||||
|
||||
/* bits definitions */
|
||||
/* ADC_STAT */
|
||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
|
||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
|
||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
||||
#define ADC_STAT_ROVF BIT(5) /*!< regular data register overflow */
|
||||
|
||||
/* ADC_CTL0 */
|
||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
||||
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||
#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */
|
||||
|
||||
/* ADC_CTL1 */
|
||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||
#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */
|
||||
#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */
|
||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||
#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted group */
|
||||
#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */
|
||||
#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */
|
||||
#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for regular group */
|
||||
#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for regular channels */
|
||||
#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of regular channels */
|
||||
|
||||
/* ADC_SAMPTx x=0..1 */
|
||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */
|
||||
|
||||
/* ADC_IOFFx x=0..3 */
|
||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||
|
||||
/* ADC_WDHT */
|
||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||
|
||||
/* ADC_WDLT */
|
||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||
|
||||
/* ADC_RSQx */
|
||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */
|
||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
||||
|
||||
/* ADC_ISQ */
|
||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */
|
||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||
|
||||
/* ADC_IDATAx x=0..3*/
|
||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */
|
||||
|
||||
/* ADC_RDATA */
|
||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
|
||||
|
||||
/* ADC_OVSAMPCTL */
|
||||
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
||||
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
|
||||
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
|
||||
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
|
||||
|
||||
/* ADC_SSTAT */
|
||||
#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */
|
||||
#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */
|
||||
#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */
|
||||
#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */
|
||||
#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */
|
||||
#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */
|
||||
#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */
|
||||
#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */
|
||||
#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */
|
||||
#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */
|
||||
#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */
|
||||
#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */
|
||||
#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */
|
||||
#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */
|
||||
#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */
|
||||
#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */
|
||||
#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */
|
||||
#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */
|
||||
|
||||
/* ADC_SYNCCTL */
|
||||
#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */
|
||||
#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */
|
||||
#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */
|
||||
#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */
|
||||
#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */
|
||||
#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */
|
||||
#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */
|
||||
|
||||
/* ADC_SYNCDATA */
|
||||
#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< regular data1 in ADC synchronization mode */
|
||||
#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< regular data2 in ADC synchronization mode */
|
||||
|
||||
/* constants definitions */
|
||||
/* ADC status flag */
|
||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
|
||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
|
||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
|
||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
|
||||
#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */
|
||||
|
||||
/* adc_ctl0 register value */
|
||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
|
||||
|
||||
/* ADC special function definitions */
|
||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||
|
||||
/* temperature sensor channel, internal reference voltage channel, VBAT channel */
|
||||
#define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */
|
||||
#define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */
|
||||
|
||||
/* ADC synchronization mode */
|
||||
#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */
|
||||
#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */
|
||||
#define ADC_DAUL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */
|
||||
#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */
|
||||
#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined regular parallel & inserted parallel mode */
|
||||
#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined regular parallel & trigger rotation mode */
|
||||
#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */
|
||||
#define ADC_ALL_REGULAL_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in regular parallel mode */
|
||||
#define ADC_ALL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */
|
||||
#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */
|
||||
|
||||
/* ADC data alignment */
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
|
||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
|
||||
|
||||
/* external trigger mode for regular and inserted channel */
|
||||
#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */
|
||||
#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */
|
||||
#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */
|
||||
#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */
|
||||
|
||||
/* ADC external trigger select for regular channel */
|
||||
#define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */
|
||||
#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */
|
||||
|
||||
/* ADC external trigger select for inserted channel */
|
||||
#define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
||||
#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */
|
||||
#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */
|
||||
#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */
|
||||
#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */
|
||||
#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */
|
||||
#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */
|
||||
#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */
|
||||
#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */
|
||||
#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */
|
||||
#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */
|
||||
#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */
|
||||
#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */
|
||||
#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */
|
||||
#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */
|
||||
#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */
|
||||
#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */
|
||||
|
||||
/* ADC channel sample time */
|
||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
|
||||
#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */
|
||||
#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */
|
||||
#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */
|
||||
#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */
|
||||
#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */
|
||||
#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */
|
||||
#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */
|
||||
#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */
|
||||
|
||||
/* adc_ioffx register value */
|
||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
|
||||
|
||||
/* adc_wdht register value */
|
||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
|
||||
|
||||
/* adc_wdlt register value */
|
||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
|
||||
|
||||
/* adc_rsqx register value */
|
||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
|
||||
|
||||
/* adc_isq register value */
|
||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
|
||||
|
||||
/* adc_ovsampctl register value */
|
||||
/* ADC resolution */
|
||||
#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */
|
||||
#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
|
||||
|
||||
/* oversampling shift */
|
||||
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */
|
||||
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
|
||||
|
||||
/* oversampling ratio */
|
||||
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
||||
|
||||
/* triggered Oversampling */
|
||||
#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||
#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */
|
||||
|
||||
/* ADC channel group definitions */
|
||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
|
||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */
|
||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
||||
|
||||
/* ADC inserted channel definitions */
|
||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
|
||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
|
||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
|
||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
|
||||
|
||||
/* ADC channel definitions */
|
||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
|
||||
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
|
||||
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
|
||||
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
|
||||
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
|
||||
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
|
||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||
#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of group conversion interrupt */
|
||||
#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted group conversion interrupt */
|
||||
#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< regular data register overflow */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
||||
#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */
|
||||
|
||||
/* configure the ADC clock for all the ADCs */
|
||||
#define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
|
||||
#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */
|
||||
#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */
|
||||
#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */
|
||||
#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */
|
||||
#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */
|
||||
#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */
|
||||
#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */
|
||||
#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */
|
||||
|
||||
/* ADC synchronization delay */
|
||||
#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */
|
||||
|
||||
/* ADC synchronization DMA mode selection */
|
||||
#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */
|
||||
#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */
|
||||
#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */
|
||||
|
||||
/* end of conversion mode */
|
||||
#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of regular conversions, the EOC bit is set */
|
||||
#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each regular conversion, the EOC bit is set */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization config */
|
||||
/* reset ADC */
|
||||
void adc_deinit(void);
|
||||
/* configure the ADC clock for all the ADCs */
|
||||
void adc_clock_config(uint32_t prescaler);
|
||||
/* enable or disable ADC special function */
|
||||
void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue);
|
||||
/* configure ADC data alignment */
|
||||
void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment);
|
||||
/* enable ADC interface */
|
||||
void adc_enable(uint32_t adc_periph);
|
||||
/* disable ADC interface */
|
||||
void adc_disable(uint32_t adc_periph);
|
||||
/* ADC calibration and reset calibration */
|
||||
void adc_calibration_enable(uint32_t adc_periph);
|
||||
/* configure temperature sensor and internal reference voltage channel or VBAT channel function */
|
||||
void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue);
|
||||
/* configure ADC resolution */
|
||||
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
|
||||
/* configure ADC oversample mode */
|
||||
void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio);
|
||||
/* enable ADC oversample mode */
|
||||
void adc_oversample_mode_enable(uint32_t adc_periph);
|
||||
/* disable ADC oversample mode */
|
||||
void adc_oversample_mode_disable(uint32_t adc_periph);
|
||||
|
||||
/* DMA config */
|
||||
/* enable DMA request */
|
||||
void adc_dma_mode_enable(uint32_t adc_periph);
|
||||
/* disable DMA request */
|
||||
void adc_dma_mode_disable(uint32_t adc_periph);
|
||||
/* when DMA=1, the DMA engine issues a request at end of each regular conversion */
|
||||
void adc_dma_request_after_last_enable(uint32_t adc_periph);
|
||||
/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */
|
||||
void adc_dma_request_after_last_disable(uint32_t adc_periph);
|
||||
|
||||
/* regular group and inserted group config */
|
||||
/* configure ADC discontinuous mode */
|
||||
void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length);
|
||||
/* configure the length of regular channel group or inserted channel group */
|
||||
void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length);
|
||||
/* configure ADC regular channel */
|
||||
void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||
/* configure ADC inserted channel */
|
||||
void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||
/* configure ADC inserted channel offset */
|
||||
void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset);
|
||||
/* configure ADC external trigger source */
|
||||
void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source);
|
||||
/* enable ADC external trigger */
|
||||
void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode);
|
||||
/* enable ADC software trigger */
|
||||
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group);
|
||||
/* configure end of conversion mode */
|
||||
void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection);
|
||||
|
||||
/* get channel data */
|
||||
/* read ADC regular group data register */
|
||||
uint16_t adc_regular_data_read(uint32_t adc_periph);
|
||||
/* read ADC inserted group data register */
|
||||
uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
|
||||
|
||||
/* watchdog config */
|
||||
/* disable ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_disable(uint32_t adc_periph );
|
||||
/* enable ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel);
|
||||
/* configure ADC analog watchdog group channel */
|
||||
void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group);
|
||||
/* disable ADC analog watchdog */
|
||||
void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group);
|
||||
/* configure ADC analog watchdog threshold */
|
||||
void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get the ADC flag bits */
|
||||
FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag);
|
||||
/* clear the ADC flag bits */
|
||||
void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag);
|
||||
/* get the bit state of ADCx software start conversion */
|
||||
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
|
||||
/* get the bit state of ADCx software inserted channel start conversion */
|
||||
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
|
||||
/* get the ADC interrupt bits */
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
/* clear the ADC flag */
|
||||
void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
/* enable ADC interrupt */
|
||||
void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
/* disable ADC interrupt */
|
||||
void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
|
||||
/* ADC synchronization */
|
||||
/* configure the ADC sync mode */
|
||||
void adc_sync_mode_config(uint32_t sync_mode);
|
||||
/* configure the delay between 2 sampling phases in ADC sync modes */
|
||||
void adc_sync_delay_config(uint32_t sample_delay);
|
||||
/* configure ADC sync DMA mode selection */
|
||||
void adc_sync_dma_config(uint32_t dma_mode );
|
||||
/* configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected */
|
||||
void adc_sync_dma_request_after_last_enable(void);
|
||||
/* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */
|
||||
void adc_sync_dma_request_after_last_disable(void);
|
||||
/* read ADC sync regular data register */
|
||||
uint32_t adc_sync_regular_data_read(void);
|
||||
|
||||
#endif /* GD32F4XX_ADC_H */
|
||||
|
|
@ -0,0 +1,753 @@
|
|||
/*!
|
||||
\file gd32f4xx_can.h
|
||||
\brief definitions for the CAN
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2019-11-27, V2.0.1, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_CAN_H
|
||||
#define GD32F4XX_CAN_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* CAN definitions */
|
||||
#define CAN0 CAN_BASE /*!< CAN0 base address */
|
||||
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */
|
||||
#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */
|
||||
#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/
|
||||
#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */
|
||||
#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */
|
||||
#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */
|
||||
#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */
|
||||
#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */
|
||||
#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */
|
||||
#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */
|
||||
#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */
|
||||
#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */
|
||||
#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */
|
||||
#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */
|
||||
#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */
|
||||
#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */
|
||||
#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */
|
||||
#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */
|
||||
#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */
|
||||
#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */
|
||||
#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */
|
||||
#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */
|
||||
#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */
|
||||
#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */
|
||||
#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */
|
||||
#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */
|
||||
#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */
|
||||
#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */
|
||||
#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */
|
||||
#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */
|
||||
#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */
|
||||
#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */
|
||||
#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */
|
||||
#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */
|
||||
#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */
|
||||
#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */
|
||||
#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */
|
||||
#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */
|
||||
#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */
|
||||
#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */
|
||||
#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */
|
||||
#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */
|
||||
#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */
|
||||
#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */
|
||||
#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */
|
||||
#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */
|
||||
#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */
|
||||
#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */
|
||||
#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */
|
||||
#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */
|
||||
#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */
|
||||
#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */
|
||||
#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */
|
||||
#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */
|
||||
#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */
|
||||
#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */
|
||||
#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */
|
||||
#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */
|
||||
#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */
|
||||
#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */
|
||||
#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */
|
||||
#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */
|
||||
#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */
|
||||
#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */
|
||||
#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */
|
||||
#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */
|
||||
#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */
|
||||
#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */
|
||||
#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */
|
||||
#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */
|
||||
#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */
|
||||
#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */
|
||||
#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */
|
||||
#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */
|
||||
#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */
|
||||
#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */
|
||||
#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */
|
||||
#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */
|
||||
#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */
|
||||
#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */
|
||||
#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */
|
||||
#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */
|
||||
#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */
|
||||
#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */
|
||||
#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */
|
||||
#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */
|
||||
#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */
|
||||
#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */
|
||||
#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */
|
||||
|
||||
/* CAN transmit mailbox bank */
|
||||
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
|
||||
#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */
|
||||
#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */
|
||||
#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */
|
||||
|
||||
/* CAN filter bank */
|
||||
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
|
||||
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
|
||||
|
||||
/* CAN receive fifo mailbox bank */
|
||||
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
|
||||
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
|
||||
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
|
||||
#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CAN_CTL */
|
||||
#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */
|
||||
#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */
|
||||
#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */
|
||||
#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */
|
||||
#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */
|
||||
#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */
|
||||
#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */
|
||||
#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */
|
||||
#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */
|
||||
#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */
|
||||
|
||||
/* CAN_STAT */
|
||||
#define CAN_STAT_IWS BIT(0) /*!< initial working state */
|
||||
#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */
|
||||
#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/
|
||||
#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */
|
||||
#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */
|
||||
#define CAN_STAT_TS BIT(8) /*!< transmitting state */
|
||||
#define CAN_STAT_RS BIT(9) /*!< receiving state */
|
||||
#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */
|
||||
#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */
|
||||
|
||||
/* CAN_TSTAT */
|
||||
#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */
|
||||
#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */
|
||||
#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */
|
||||
#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */
|
||||
#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */
|
||||
#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */
|
||||
#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */
|
||||
#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */
|
||||
#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */
|
||||
#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */
|
||||
#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */
|
||||
#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */
|
||||
#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */
|
||||
#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */
|
||||
#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */
|
||||
#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */
|
||||
#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */
|
||||
#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */
|
||||
#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */
|
||||
#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */
|
||||
#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */
|
||||
#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */
|
||||
|
||||
/* CAN_RFIFO0 */
|
||||
#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */
|
||||
#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */
|
||||
#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */
|
||||
#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */
|
||||
|
||||
/* CAN_RFIFO1 */
|
||||
#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */
|
||||
#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */
|
||||
#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */
|
||||
#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */
|
||||
|
||||
/* CAN_INTEN */
|
||||
#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */
|
||||
#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */
|
||||
#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */
|
||||
#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */
|
||||
#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */
|
||||
#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */
|
||||
#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */
|
||||
#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */
|
||||
#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */
|
||||
#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */
|
||||
#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */
|
||||
#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */
|
||||
#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */
|
||||
#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */
|
||||
|
||||
/* CAN_ERR */
|
||||
#define CAN_ERR_WERR BIT(0) /*!< warning error */
|
||||
#define CAN_ERR_PERR BIT(1) /*!< passive error */
|
||||
#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */
|
||||
#define CAN_ERR_ERRN BITS(4,6) /*!< error number */
|
||||
#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */
|
||||
#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */
|
||||
|
||||
/* CAN_BT */
|
||||
#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */
|
||||
#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */
|
||||
#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */
|
||||
#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */
|
||||
#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */
|
||||
#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */
|
||||
|
||||
/* CAN_TMIx */
|
||||
#define CAN_TMI_TEN BIT(0) /*!< transmit enable */
|
||||
#define CAN_TMI_FT BIT(1) /*!< frame type */
|
||||
#define CAN_TMI_FF BIT(2) /*!< frame format */
|
||||
#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */
|
||||
#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */
|
||||
|
||||
/* CAN_TMPx */
|
||||
#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */
|
||||
#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */
|
||||
#define CAN_TMP_TS BITS(16,31) /*!< time stamp */
|
||||
|
||||
/* CAN_TMDATA0x */
|
||||
#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */
|
||||
#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */
|
||||
#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */
|
||||
#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */
|
||||
|
||||
/* CAN_TMDATA1x */
|
||||
#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */
|
||||
#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */
|
||||
#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */
|
||||
#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */
|
||||
|
||||
/* CAN_RFIFOMIx */
|
||||
#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */
|
||||
#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */
|
||||
#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */
|
||||
#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */
|
||||
|
||||
/* CAN_RFIFOMPx */
|
||||
#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */
|
||||
#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */
|
||||
#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */
|
||||
|
||||
/* CAN_RFIFOMDATA0x */
|
||||
#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */
|
||||
#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */
|
||||
#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */
|
||||
#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */
|
||||
|
||||
/* CAN_RFIFOMDATA1x */
|
||||
#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */
|
||||
#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */
|
||||
#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */
|
||||
#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */
|
||||
|
||||
/* CAN_FCTL */
|
||||
#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */
|
||||
#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */
|
||||
|
||||
/* CAN_FMCFG */
|
||||
#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/
|
||||
|
||||
/* CAN_FSCFG */
|
||||
#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/
|
||||
|
||||
/* CAN_FAFIFO */
|
||||
#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */
|
||||
|
||||
/* CAN_FW */
|
||||
#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */
|
||||
|
||||
/* CAN_FxDATAy */
|
||||
#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */
|
||||
|
||||
/* consts definitions */
|
||||
/* define the CAN bit position and its register index offset */
|
||||
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
|
||||
#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
|
||||
#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
|
||||
#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
|
||||
#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register offset */
|
||||
#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */
|
||||
#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */
|
||||
#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */
|
||||
#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */
|
||||
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
|
||||
|
||||
/* CAN flags */
|
||||
typedef enum
|
||||
{
|
||||
/* flags in STAT register */
|
||||
CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */
|
||||
CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */
|
||||
CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */
|
||||
CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */
|
||||
CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */
|
||||
CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */
|
||||
CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */
|
||||
CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */
|
||||
CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */
|
||||
/* flags in TSTAT register */
|
||||
CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */
|
||||
CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */
|
||||
CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */
|
||||
CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */
|
||||
CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */
|
||||
CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */
|
||||
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
|
||||
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
|
||||
CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */
|
||||
CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */
|
||||
CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */
|
||||
CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */
|
||||
CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */
|
||||
CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */
|
||||
CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */
|
||||
CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */
|
||||
CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */
|
||||
CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */
|
||||
/* flags in RFIFO0 register */
|
||||
CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */
|
||||
CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */
|
||||
/* flags in RFIFO1 register */
|
||||
CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */
|
||||
CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */
|
||||
/* flags in ERR register */
|
||||
CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
|
||||
CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
|
||||
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
|
||||
}can_flag_enum;
|
||||
|
||||
/* CAN interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt flags in STAT register */
|
||||
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
|
||||
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
|
||||
CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */
|
||||
/* interrupt flags in TSTAT register */
|
||||
CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */
|
||||
CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */
|
||||
CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */
|
||||
/* interrupt flags in RFIFO0 register */
|
||||
CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */
|
||||
CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */
|
||||
CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */
|
||||
/* interrupt flags in RFIFO0 register */
|
||||
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
|
||||
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
|
||||
CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */
|
||||
/* interrupt flags in ERR register */
|
||||
CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */
|
||||
CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */
|
||||
CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */
|
||||
CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */
|
||||
}can_interrupt_flag_enum;
|
||||
|
||||
/* CAN initiliaze parameters struct */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t working_mode; /*!< CAN working mode */
|
||||
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
|
||||
uint8_t time_segment_1; /*!< time segment 1 */
|
||||
uint8_t time_segment_2; /*!< time segment 2 */
|
||||
ControlStatus time_triggered; /*!< time triggered communication mode */
|
||||
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
|
||||
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
|
||||
ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */
|
||||
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
|
||||
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
|
||||
uint16_t prescaler; /*!< baudrate prescaler */
|
||||
}can_parameter_struct;
|
||||
|
||||
/* CAN transmit message struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t tx_sfid; /*!< standard format frame identifier */
|
||||
uint32_t tx_efid; /*!< extended format frame identifier */
|
||||
uint8_t tx_ff; /*!< format of frame, standard or extended format */
|
||||
uint8_t tx_ft; /*!< type of frame, data or remote */
|
||||
uint8_t tx_dlen; /*!< data length */
|
||||
uint8_t tx_data[8]; /*!< transmit data */
|
||||
}can_trasnmit_message_struct;
|
||||
|
||||
/* CAN receive message struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t rx_sfid; /*!< standard format frame identifier */
|
||||
uint32_t rx_efid; /*!< extended format frame identifier */
|
||||
uint8_t rx_ff; /*!< format of frame, standard or extended format */
|
||||
uint8_t rx_ft; /*!< type of frame, data or remote */
|
||||
uint8_t rx_dlen; /*!< data length */
|
||||
uint8_t rx_data[8]; /*!< receive data */
|
||||
uint8_t rx_fi; /*!< filtering index */
|
||||
} can_receive_message_struct;
|
||||
|
||||
/* CAN filter parameters struct */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t filter_list_high; /*!< filter list number high bits*/
|
||||
uint16_t filter_list_low; /*!< filter list number low bits */
|
||||
uint16_t filter_mask_high; /*!< filter mask number high bits */
|
||||
uint16_t filter_mask_low; /*!< filter mask number low bits */
|
||||
uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */
|
||||
uint16_t filter_number; /*!< filter number */
|
||||
uint16_t filter_mode; /*!< filter mode, list or mask */
|
||||
uint16_t filter_bits; /*!< filter scale */
|
||||
ControlStatus filter_enable; /*!< filter work or not */
|
||||
}can_filter_parameter_struct;
|
||||
|
||||
/* CAN errors */
|
||||
typedef enum
|
||||
{
|
||||
CAN_ERROR_NONE = 0, /*!< no error */
|
||||
CAN_ERROR_FILL, /*!< fill error */
|
||||
CAN_ERROR_FORMATE, /*!< format error */
|
||||
CAN_ERROR_ACK, /*!< ACK error */
|
||||
CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
|
||||
CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
|
||||
CAN_ERROR_CRC, /*!< CRC error */
|
||||
CAN_ERROR_SOFTWARECFG, /*!< software configure */
|
||||
}can_error_enum;
|
||||
|
||||
/* transmit states */
|
||||
typedef enum
|
||||
{
|
||||
CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */
|
||||
CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */
|
||||
CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */
|
||||
CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */
|
||||
}can_transmit_state_enum;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */
|
||||
CAN_FILTER_STRUCT, /* CAN filter parameters struct */
|
||||
CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
|
||||
CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */
|
||||
}can_struct_type_enum;
|
||||
|
||||
/* CAN baudrate prescaler*/
|
||||
#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* CAN bit segment 1*/
|
||||
#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* CAN bit segment 2*/
|
||||
#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* CAN resynchronization jump width*/
|
||||
#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
|
||||
|
||||
/* CAN communication mode*/
|
||||
#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
|
||||
|
||||
/* CAN FDATA high 16 bits */
|
||||
#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* CAN FDATA low 16 bits */
|
||||
#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* CAN1 filter start bank_number*/
|
||||
#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
|
||||
|
||||
/* CAN transmit mailbox extended identifier*/
|
||||
#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
|
||||
|
||||
/* CAN transmit mailbox standard identifier*/
|
||||
#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
|
||||
|
||||
/* transmit data byte 0 */
|
||||
#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* transmit data byte 1 */
|
||||
#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
||||
|
||||
/* transmit data byte 2 */
|
||||
#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* transmit data byte 3 */
|
||||
#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
||||
|
||||
/* transmit data byte 4 */
|
||||
#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* transmit data byte 5 */
|
||||
#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
||||
|
||||
/* transmit data byte 6 */
|
||||
#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* transmit data byte 7 */
|
||||
#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
||||
|
||||
/* receive mailbox extended identifier*/
|
||||
#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U)
|
||||
|
||||
/* receive mailbox standrad identifier*/
|
||||
#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U)
|
||||
|
||||
/* receive data length */
|
||||
#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U)
|
||||
|
||||
/* the index of the filter by which the frame is passed */
|
||||
#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||
|
||||
/* receive data byte 0 */
|
||||
#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
||||
|
||||
/* receive data byte 1 */
|
||||
#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||
|
||||
/* receive data byte 2 */
|
||||
#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||
|
||||
/* receive data byte 3 */
|
||||
#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||
|
||||
/* receive data byte 4 */
|
||||
#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
||||
|
||||
/* receive data byte 5 */
|
||||
#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||
|
||||
/* receive data byte 6 */
|
||||
#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||
|
||||
/* receive data byte 7 */
|
||||
#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||
|
||||
/* error number */
|
||||
#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U)
|
||||
|
||||
/* transmit error count */
|
||||
#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||
|
||||
/* receive error count */
|
||||
#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||
|
||||
/* CAN errors */
|
||||
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
||||
#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */
|
||||
#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */
|
||||
#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */
|
||||
#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */
|
||||
#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */
|
||||
#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */
|
||||
#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */
|
||||
#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */
|
||||
|
||||
#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */
|
||||
|
||||
/* CAN communication mode */
|
||||
#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */
|
||||
#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */
|
||||
#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */
|
||||
#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */
|
||||
|
||||
/* CAN resynchronisation jump width */
|
||||
#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||
#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||
#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||
#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||
|
||||
/* CAN time segment 1 */
|
||||
#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||
#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||
#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||
#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||
#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
||||
#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
||||
#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
||||
#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
||||
#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */
|
||||
#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */
|
||||
#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */
|
||||
#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */
|
||||
#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */
|
||||
#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */
|
||||
#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */
|
||||
#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */
|
||||
|
||||
/* CAN time segment 2 */
|
||||
#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||
#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||
#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||
#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||
#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
||||
#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
||||
#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
||||
#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
||||
|
||||
/* CAN mailbox number */
|
||||
#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */
|
||||
#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */
|
||||
#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */
|
||||
#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */
|
||||
|
||||
/* CAN frame format */
|
||||
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
|
||||
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
|
||||
|
||||
/* CAN receive fifo */
|
||||
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
|
||||
|
||||
/* frame number of receive fifo */
|
||||
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */
|
||||
|
||||
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
|
||||
#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */
|
||||
|
||||
/* CAN working mode */
|
||||
#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
|
||||
#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
|
||||
#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */
|
||||
|
||||
/* filter bits */
|
||||
#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */
|
||||
#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */
|
||||
|
||||
/* filter mode */
|
||||
#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */
|
||||
#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */
|
||||
|
||||
/* filter 16 bits mask */
|
||||
#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */
|
||||
|
||||
/* frame type */
|
||||
#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */
|
||||
#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */
|
||||
|
||||
/* CAN timeout */
|
||||
#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */
|
||||
|
||||
/* interrupt enable bits */
|
||||
#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */
|
||||
#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */
|
||||
#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */
|
||||
#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */
|
||||
#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */
|
||||
#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */
|
||||
#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */
|
||||
#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */
|
||||
#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */
|
||||
#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */
|
||||
#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */
|
||||
#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */
|
||||
#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */
|
||||
#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize CAN */
|
||||
void can_deinit(uint32_t can_periph);
|
||||
/* initialize CAN struct */
|
||||
void can_struct_para_init(can_struct_type_enum type, void* p_struct);
|
||||
/* initialize CAN */
|
||||
ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init);
|
||||
/* CAN filter init */
|
||||
void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init);
|
||||
/* set can1 fliter start bank number */
|
||||
void can1_filter_start_bank(uint8_t start_bank);
|
||||
/* enable functions */
|
||||
/* CAN debug freeze enable */
|
||||
void can_debug_freeze_enable(uint32_t can_periph);
|
||||
/* CAN debug freeze disable */
|
||||
void can_debug_freeze_disable(uint32_t can_periph);
|
||||
/* CAN time trigger mode enable */
|
||||
void can_time_trigger_mode_enable(uint32_t can_periph);
|
||||
/* CAN time trigger mode disable */
|
||||
void can_time_trigger_mode_disable(uint32_t can_periph);
|
||||
|
||||
/* transmit functions */
|
||||
/* transmit CAN message */
|
||||
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message);
|
||||
/* get CAN transmit state */
|
||||
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
|
||||
/* stop CAN transmission */
|
||||
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
|
||||
/* CAN receive message */
|
||||
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message);
|
||||
/* CAN release fifo */
|
||||
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
|
||||
/* CAN receive message length */
|
||||
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
|
||||
/* CAN working mode */
|
||||
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
|
||||
/* CAN wakeup from sleep mode */
|
||||
ErrStatus can_wakeup(uint32_t can_periph);
|
||||
|
||||
/* CAN get error */
|
||||
can_error_enum can_error_get(uint32_t can_periph);
|
||||
/* get CAN receive error number */
|
||||
uint8_t can_receive_error_number_get(uint32_t can_periph);
|
||||
/* get CAN transmit error number */
|
||||
uint8_t can_transmit_error_number_get(uint32_t can_periph);
|
||||
|
||||
/* CAN interrupt enable */
|
||||
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
|
||||
/* CAN interrupt disable */
|
||||
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
|
||||
/* CAN get flag state */
|
||||
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
|
||||
/* CAN clear flag state */
|
||||
void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
|
||||
/* CAN get interrupt flag state */
|
||||
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
|
||||
/* CAN clear interrupt flag state */
|
||||
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
|
||||
|
||||
#endif /* GD32F4XX_CAN_H */
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/*!
|
||||
\file gd32f4xx_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_CRC_H
|
||||
#define GD32F4XX_CRC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
|
||||
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the value of the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the value of the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write data to the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* calculate the CRC value of a 32-bit data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata);
|
||||
/* calculate the CRC value of an array of 32-bit values */
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
|
||||
|
||||
#endif /* GD32F4XX_CRC_H */
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
/*!
|
||||
\file gd32f4xx_ctc.h
|
||||
\brief definitions for the CTC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_CTC_H
|
||||
#define GD32F4XX_CTC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* CTC definitions */
|
||||
#define CTC CTC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
|
||||
#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
|
||||
#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
|
||||
#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CTC_CTL0 */
|
||||
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
|
||||
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
|
||||
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
|
||||
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
|
||||
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
|
||||
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
|
||||
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
|
||||
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
|
||||
|
||||
/* CTC_CTL1 */
|
||||
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
|
||||
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
|
||||
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
|
||||
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
|
||||
#define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */
|
||||
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
|
||||
|
||||
/* CTC_STAT */
|
||||
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
|
||||
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
|
||||
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
|
||||
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
|
||||
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
|
||||
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
|
||||
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
|
||||
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
|
||||
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
|
||||
|
||||
/* CTC_INTC */
|
||||
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
|
||||
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
|
||||
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
|
||||
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
|
||||
|
||||
/* constants definitions */
|
||||
/* hardware automatically trim mode definitions */
|
||||
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
|
||||
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
|
||||
|
||||
/* reference signal source polarity definitions */
|
||||
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
|
||||
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
|
||||
|
||||
/* USBFS or USBHS SOF signal selection definitions */
|
||||
#define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/
|
||||
#define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/
|
||||
|
||||
/* reference signal source selection definitions */
|
||||
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
|
||||
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */
|
||||
#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */
|
||||
|
||||
/* reference signal source prescaler definitions */
|
||||
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
||||
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
|
||||
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
|
||||
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
|
||||
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
|
||||
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
|
||||
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
|
||||
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
|
||||
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
|
||||
|
||||
/* CTC interrupt enable definitions */
|
||||
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
|
||||
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
|
||||
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
|
||||
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
|
||||
|
||||
/* CTC interrupt source definitions */
|
||||
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
|
||||
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
|
||||
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
|
||||
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
|
||||
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
|
||||
|
||||
/* CTC flag definitions */
|
||||
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
|
||||
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
|
||||
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
|
||||
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
|
||||
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
|
||||
|
||||
/* function declarations */
|
||||
/* reset ctc clock trim controller */
|
||||
void ctc_deinit(void);
|
||||
/* enable CTC trim counter */
|
||||
void ctc_counter_enable(void);
|
||||
/* disable CTC trim counter */
|
||||
void ctc_counter_disable(void);
|
||||
|
||||
/* configure the IRC48M trim value */
|
||||
void ctc_irc48m_trim_value_config(uint8_t trim_value);
|
||||
/* generate software reference source sync pulse */
|
||||
void ctc_software_refsource_pulse_generate(void);
|
||||
/* configure hardware automatically trim mode */
|
||||
void ctc_hardware_trim_mode_config(uint32_t hardmode);
|
||||
|
||||
/* configure reference signal source polarity */
|
||||
void ctc_refsource_polarity_config(uint32_t polarity);
|
||||
/* select USBFS or USBHS SOF signal */
|
||||
void ctc_usbsof_signal_select(uint32_t usbsof);
|
||||
/* select reference signal source */
|
||||
void ctc_refsource_signal_select(uint32_t refs);
|
||||
/* configure reference signal source prescaler */
|
||||
void ctc_refsource_prescaler_config(uint32_t prescaler);
|
||||
/* configure clock trim base limit value */
|
||||
void ctc_clock_limit_value_config(uint8_t limit_value);
|
||||
/* configure CTC counter reload value */
|
||||
void ctc_counter_reload_value_config(uint16_t reload_value);
|
||||
|
||||
/* read CTC counter capture value when reference sync pulse occurred */
|
||||
uint16_t ctc_counter_capture_value_read(void);
|
||||
/* read CTC trim counter direction when reference sync pulse occurred */
|
||||
FlagStatus ctc_counter_direction_read(void);
|
||||
/* read CTC counter reload value */
|
||||
uint16_t ctc_counter_reload_value_read(void);
|
||||
/* read the IRC48M trim value */
|
||||
uint8_t ctc_irc48m_trim_value_read(void);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* enable the CTC interrupt */
|
||||
void ctc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable the CTC interrupt */
|
||||
void ctc_interrupt_disable(uint32_t interrupt);
|
||||
/* get CTC interrupt flag */
|
||||
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear CTC interrupt flag */
|
||||
void ctc_interrupt_flag_clear(uint32_t int_flag);
|
||||
/* get CTC flag */
|
||||
FlagStatus ctc_flag_get(uint32_t flag);
|
||||
/* clear CTC flag */
|
||||
void ctc_flag_clear(uint32_t flag);
|
||||
|
||||
#endif /* GD32F4XX_CTC_H */
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/*!
|
||||
\file gd32f4xx_dac.h
|
||||
\brief definitions for the DAC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_DAC_H
|
||||
#define GD32F4XX_DAC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* DACx(x=0,1) definitions */
|
||||
#define DAC DAC_BASE
|
||||
#define DAC0 0U
|
||||
#define DAC1 1U
|
||||
|
||||
/* registers definitions */
|
||||
#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */
|
||||
#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */
|
||||
#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */
|
||||
#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */
|
||||
#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */
|
||||
#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */
|
||||
#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */
|
||||
#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */
|
||||
#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
|
||||
#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
|
||||
#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
|
||||
#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */
|
||||
#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */
|
||||
#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DAC_CTL */
|
||||
#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */
|
||||
#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */
|
||||
#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */
|
||||
#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */
|
||||
#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */
|
||||
#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */
|
||||
#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */
|
||||
#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */
|
||||
#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */
|
||||
#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */
|
||||
#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */
|
||||
#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */
|
||||
#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */
|
||||
#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */
|
||||
#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */
|
||||
#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */
|
||||
|
||||
/* DAC_SWT */
|
||||
#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */
|
||||
#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */
|
||||
|
||||
/* DAC0_R12DH */
|
||||
#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */
|
||||
|
||||
/* DAC0_L12DH */
|
||||
#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */
|
||||
|
||||
/* DAC0_R8DH */
|
||||
#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */
|
||||
|
||||
/* DAC1_R12DH */
|
||||
#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */
|
||||
|
||||
/* DAC1_L12DH */
|
||||
#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */
|
||||
|
||||
/* DAC1_R8DH */
|
||||
#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */
|
||||
|
||||
/* DACC_R12DH */
|
||||
#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
|
||||
#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
|
||||
|
||||
/* DACC_L12DH */
|
||||
#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
|
||||
#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
|
||||
|
||||
/* DACC_R8DH */
|
||||
#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
|
||||
#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
|
||||
|
||||
/* DAC0_DO */
|
||||
#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */
|
||||
|
||||
/* DAC1_DO */
|
||||
#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */
|
||||
|
||||
/* DAC_STAT */
|
||||
#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */
|
||||
#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */
|
||||
|
||||
/* constants definitions */
|
||||
/* DAC trigger source */
|
||||
#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
|
||||
#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */
|
||||
#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */
|
||||
#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */
|
||||
#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */
|
||||
#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */
|
||||
#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */
|
||||
#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
|
||||
|
||||
/* DAC noise wave mode */
|
||||
#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */
|
||||
#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
|
||||
#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
|
||||
|
||||
/* DAC noise wave bit width */
|
||||
#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
|
||||
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
|
||||
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
|
||||
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
|
||||
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
|
||||
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
|
||||
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
|
||||
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
|
||||
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
|
||||
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
|
||||
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
|
||||
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
|
||||
|
||||
/* unmask LFSR bits in DAC LFSR noise mode */
|
||||
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
|
||||
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
|
||||
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
|
||||
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
|
||||
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
|
||||
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
|
||||
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
|
||||
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
|
||||
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
|
||||
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
|
||||
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
|
||||
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
|
||||
|
||||
/* DAC data alignment */
|
||||
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */
|
||||
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */
|
||||
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */
|
||||
|
||||
/* triangle amplitude in DAC triangle noise mode */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* deinitialize DAC */
|
||||
void dac_deinit(void);
|
||||
/* enable DAC */
|
||||
void dac_enable(uint32_t dac_periph);
|
||||
/* disable DAC */
|
||||
void dac_disable(uint32_t dac_periph);
|
||||
/* enable DAC DMA */
|
||||
void dac_dma_enable(uint32_t dac_periph);
|
||||
/* disable DAC DMA */
|
||||
void dac_dma_disable(uint32_t dac_periph);
|
||||
/* enable DAC output buffer */
|
||||
void dac_output_buffer_enable(uint32_t dac_periph);
|
||||
/* disable DAC output buffer */
|
||||
void dac_output_buffer_disable(uint32_t dac_periph);
|
||||
/* get the last data output value */
|
||||
uint16_t dac_output_value_get(uint32_t dac_periph);
|
||||
/* set DAC data holding register value */
|
||||
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
|
||||
|
||||
/* DAC trigger configuration */
|
||||
/* enable DAC trigger */
|
||||
void dac_trigger_enable(uint32_t dac_periph);
|
||||
/* disable DAC trigger */
|
||||
void dac_trigger_disable(uint32_t dac_periph);
|
||||
/* configure DAC trigger source */
|
||||
void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
|
||||
/* enable DAC software trigger */
|
||||
void dac_software_trigger_enable(uint32_t dac_periph);
|
||||
/* disable DAC software trigger */
|
||||
void dac_software_trigger_disable(uint32_t dac_periph);
|
||||
|
||||
/* DAC wave mode configuration */
|
||||
/* configure DAC wave mode */
|
||||
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
|
||||
/* configure DAC wave bit width */
|
||||
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
|
||||
/* configure DAC LFSR noise mode */
|
||||
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
|
||||
/* configure DAC triangle noise mode */
|
||||
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
|
||||
|
||||
/* DAC concurrent mode configuration */
|
||||
/* enable DAC concurrent mode */
|
||||
void dac_concurrent_enable(void);
|
||||
/* disable DAC concurrent mode */
|
||||
void dac_concurrent_disable(void);
|
||||
/* enable DAC concurrent software trigger */
|
||||
void dac_concurrent_software_trigger_enable(void);
|
||||
/* disable DAC concurrent software trigger */
|
||||
void dac_concurrent_software_trigger_disable(void);
|
||||
/* enable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_enable(void);
|
||||
/* disable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_disable(void);
|
||||
/* set DAC concurrent mode data holding register value */
|
||||
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1);
|
||||
/* enable DAC concurrent interrupt */
|
||||
void dac_concurrent_interrupt_enable(void);
|
||||
/* disable DAC concurrent interrupt */
|
||||
void dac_concurrent_interrupt_disable(void);
|
||||
|
||||
/* DAC interrupt configuration */
|
||||
/* enable DAC interrupt(DAC DMA underrun interrupt) */
|
||||
void dac_interrupt_enable(uint32_t dac_periph);
|
||||
/* disable DAC interrupt(DAC DMA underrun interrupt) */
|
||||
void dac_interrupt_disable(uint32_t dac_periph);
|
||||
/* get the specified DAC flag(DAC DMA underrun flag) */
|
||||
FlagStatus dac_flag_get(uint32_t dac_periph);
|
||||
/* clear the specified DAC flag(DAC DMA underrun flag) */
|
||||
void dac_flag_clear(uint32_t dac_periph);
|
||||
/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
||||
FlagStatus dac_interrupt_flag_get(uint32_t dac_periph);
|
||||
/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
||||
void dac_interrupt_flag_clear(uint32_t dac_periph);
|
||||
|
||||
#endif /* GD32F4XX_DAC_H */
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/*!
|
||||
\file gd32f4xx_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_DBG_H
|
||||
#define GD32F4XX_DBG_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
|
||||
#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
|
||||
#define DBG_CTL2 REG32(DBG + 0x0CU) /*!< DBG control register 2 */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL0 */
|
||||
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
|
||||
#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
|
||||
|
||||
/* DBG_CTL1 */
|
||||
#define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER2_HOLD BIT(1) /*!< hold TIMER2 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER3_HOLD BIT(2) /*!< hold TIMER3 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER4_HOLD BIT(3) /*!< hold TIMER4 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER5_HOLD BIT(4) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER6_HOLD BIT(5) /*!< hold TIMER6 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER11_HOLD BIT(6) /*!< hold TIMER11 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER12_HOLD BIT(7) /*!< hold TIMER12 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER13_HOLD BIT(8) /*!< hold TIMER13 counter when core is halted */
|
||||
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||
#define DBG_CTL1_WWDGT_HOLD BIT(11) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL1_FWDGT_HOLD BIT(12) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL1_I2C0_HOLD BIT(21) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL1_I2C1_HOLD BIT(22) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL1_I2C2_HOLD BIT(23) /*!< hold I2C2 smbus when core is halted */
|
||||
#define DBG_CTL1_CAN0_HOLD BIT(25) /*!< debug CAN0 kept when core is halted */
|
||||
#define DBG_CTL1_CAN1_HOLD BIT(26) /*!< debug CAN1 kept when core is halted */
|
||||
|
||||
/* DBG_CTL2 */
|
||||
#define DBG_CTL2_TIMER0_HOLD BIT(0) /*!< hold TIMER0 counter when core is halted */
|
||||
#define DBG_CTL2_TIMER7_HOLD BIT(1) /*!< hold TIMER7 counter when core is halted */
|
||||
#define DBG_CTL2_TIMER8_HOLD BIT(16) /*!< hold TIMER8 counter when core is halted */
|
||||
#define DBG_CTL2_TIMER9_HOLD BIT(17) /*!< hold TIMER9 counter when core is halted */
|
||||
#define DBG_CTL2_TIMER10_HOLD BIT(18) /*!< hold TIMER10 counter when core is halted */
|
||||
|
||||
/* constants definitions */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* define the peripheral debug hold bit position and its register index offset */
|
||||
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
|
||||
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
|
||||
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register index */
|
||||
enum dbg_reg_idx
|
||||
{
|
||||
DBG_IDX_CTL0 = 0x04U,
|
||||
DBG_IDX_CTL1 = 0x08U,
|
||||
DBG_IDX_CTL2 = 0x0CU
|
||||
};
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */
|
||||
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */
|
||||
DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */
|
||||
DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */
|
||||
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */
|
||||
DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */
|
||||
DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */
|
||||
DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */
|
||||
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */
|
||||
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */
|
||||
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */
|
||||
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */
|
||||
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */
|
||||
DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */
|
||||
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */
|
||||
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */
|
||||
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */
|
||||
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */
|
||||
DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */
|
||||
DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */
|
||||
DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */
|
||||
}dbg_periph_enum;
|
||||
|
||||
#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6))
|
||||
#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the DBG */
|
||||
void dbg_deinit(void);
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
/* enable trace pin assignment */
|
||||
void dbg_trace_pin_enable(void);
|
||||
/* disable trace pin assignment */
|
||||
void dbg_trace_pin_disable(void);
|
||||
/* set trace pin mode */
|
||||
void dbg_trace_pin_mode_set(uint32_t trace_mode);
|
||||
|
||||
#endif /* GD32F4XX_DBG_H */
|
||||
|
|
@ -0,0 +1,238 @@
|
|||
/*!
|
||||
\file gd32f4xx_dci.h
|
||||
\brief definitions for the DCI
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_DCI_H
|
||||
#define GD32F4XX_DCI_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* DCI definitions */
|
||||
#define DCI DCI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */
|
||||
#define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */
|
||||
#define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */
|
||||
#define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */
|
||||
#define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */
|
||||
#define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */
|
||||
#define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */
|
||||
#define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */
|
||||
#define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position register */
|
||||
#define DCI_CWSZ REG32(DCI + 0x24U) /*!< DCI cropping window size register */
|
||||
#define DCI_DATA REG32(DCI + 0x28U) /*!< DCI data register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DCI_CTL */
|
||||
#define DCI_CTL_CAP BIT(0) /*!< capture enable */
|
||||
#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */
|
||||
#define DCI_CTL_WDEN BIT(2) /*!< window enable */
|
||||
#define DCI_CTL_JM BIT(3) /*!< JPEG mode */
|
||||
#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */
|
||||
#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */
|
||||
#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */
|
||||
#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */
|
||||
#define DCI_CTL_FR BITS(8,9) /*!< frame rate */
|
||||
#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */
|
||||
#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */
|
||||
|
||||
/* DCI_STAT0 */
|
||||
#define DCI_STAT0_HS BIT(0) /*!< HS line status */
|
||||
#define DCI_STAT0_VS BIT(1) /*!< VS line status */
|
||||
#define DCI_STAT0_FV BIT(2) /*!< FIFO valid */
|
||||
|
||||
/* DCI_STAT1 */
|
||||
#define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */
|
||||
#define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */
|
||||
#define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */
|
||||
#define DCI_STAT1_VSF BIT(3) /*!< vsync flag */
|
||||
#define DCI_STAT1_ELF BIT(4) /*!< end of line flag */
|
||||
|
||||
/* DCI_INTEN */
|
||||
#define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */
|
||||
#define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */
|
||||
#define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */
|
||||
#define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */
|
||||
#define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */
|
||||
|
||||
/* DCI_INTF */
|
||||
#define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */
|
||||
#define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */
|
||||
#define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */
|
||||
#define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */
|
||||
#define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */
|
||||
|
||||
/* DCI_INTC */
|
||||
#define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */
|
||||
#define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */
|
||||
#define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */
|
||||
#define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */
|
||||
#define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */
|
||||
|
||||
/* DCI_SC */
|
||||
#define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */
|
||||
#define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */
|
||||
#define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */
|
||||
#define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */
|
||||
|
||||
/* DCI_SCUNMSK */
|
||||
#define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */
|
||||
#define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */
|
||||
#define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */
|
||||
#define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */
|
||||
|
||||
/* DCI_CWSPOS */
|
||||
#define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */
|
||||
#define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */
|
||||
|
||||
/* DCI_CWSZ */
|
||||
#define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */
|
||||
#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */
|
||||
|
||||
/* constants definitions */
|
||||
/* DCI parameter structure definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */
|
||||
uint32_t clock_polarity; /*!< clock polarity selection */
|
||||
uint32_t hsync_polarity; /*!< horizontal polarity selection */
|
||||
uint32_t vsync_polarity; /*!< vertical polarity selection */
|
||||
uint32_t frame_rate; /*!< frame capture rate */
|
||||
uint32_t interface_format; /*!< digital camera interface format */
|
||||
}dci_parameter_struct;
|
||||
|
||||
#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */
|
||||
#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */
|
||||
|
||||
#define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */
|
||||
#define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */
|
||||
|
||||
#define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
|
||||
#define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */
|
||||
|
||||
#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
|
||||
#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/
|
||||
|
||||
#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U))
|
||||
#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */
|
||||
#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */
|
||||
#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */
|
||||
|
||||
#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U))
|
||||
#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */
|
||||
#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */
|
||||
#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */
|
||||
#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */
|
||||
|
||||
/* DCI interrupt constants definitions */
|
||||
#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */
|
||||
#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */
|
||||
#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */
|
||||
#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */
|
||||
#define DCI_INT_EL BIT(4) /*!< end of line interrupt */
|
||||
|
||||
/* DCI interrupt flag definitions */
|
||||
#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */
|
||||
#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */
|
||||
#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */
|
||||
#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */
|
||||
#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */
|
||||
|
||||
/* DCI flag definitions */
|
||||
#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */
|
||||
#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */
|
||||
#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */
|
||||
#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */
|
||||
#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */
|
||||
#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */
|
||||
#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */
|
||||
#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* DCI deinit */
|
||||
void dci_deinit(void);
|
||||
/* initialize DCI registers */
|
||||
void dci_init(dci_parameter_struct* dci_struct);
|
||||
|
||||
/* enable DCI function */
|
||||
void dci_enable(void);
|
||||
/* disable DCI function */
|
||||
void dci_disable(void);
|
||||
/* enable DCI capture */
|
||||
void dci_capture_enable(void);
|
||||
/* disable DCI capture */
|
||||
void dci_capture_disable(void);
|
||||
/* enable DCI jpeg mode */
|
||||
void dci_jpeg_enable(void);
|
||||
/* disable DCI jpeg mode */
|
||||
void dci_jpeg_disable(void);
|
||||
|
||||
/* function configuration */
|
||||
/* enable cropping window function */
|
||||
void dci_crop_window_enable(void);
|
||||
/* disable cropping window function */
|
||||
void dci_crop_window_disable(void);
|
||||
/* configure DCI cropping window */
|
||||
void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height);
|
||||
|
||||
/* enable embedded synchronous mode */
|
||||
void dci_embedded_sync_enable(void);
|
||||
/* disable embedded synchronous mode */
|
||||
void dci_embedded_sync_disable(void);
|
||||
/* configure synchronous codes in embedded synchronous mode */
|
||||
void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
|
||||
/* configure synchronous codes unmask in embedded synchronous mode */
|
||||
void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
|
||||
|
||||
/* read DCI data register */
|
||||
uint32_t dci_data_read(void);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get specified flag */
|
||||
FlagStatus dci_flag_get(uint32_t flag);
|
||||
/* enable specified DCI interrupt */
|
||||
void dci_interrupt_enable(uint32_t interrupt);
|
||||
/* disable specified DCI interrupt */
|
||||
void dci_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
|
||||
/* get specified interrupt flag */
|
||||
FlagStatus dci_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear specified interrupt flag */
|
||||
void dci_interrupt_flag_clear(uint32_t int_flag);
|
||||
|
||||
#endif /* GD32F4XX_DCI_H */
|
||||
|
|
@ -0,0 +1,428 @@
|
|||
/*!
|
||||
\file gd32f4xx_dma.c
|
||||
\brief definitions for the DMA
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_DMA_H
|
||||
#define GD32F4XX_DMA_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* DMA definitions */
|
||||
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
|
||||
#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DMA_INTF0(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register 0 */
|
||||
#define DMA_INTF1(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag register 1 */
|
||||
#define DMA_INTC0(dmax) REG32((dmax) + 0x08U) /*!< DMA interrupt flag clear register 0 */
|
||||
#define DMA_INTC1(dmax) REG32((dmax) + 0x0CU) /*!< DMA interrupt flag clear register 1 */
|
||||
|
||||
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 control register */
|
||||
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 counter register */
|
||||
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x18U) /*!< DMA channel 0 peripheral base address register */
|
||||
#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 0 memory 0 base address register */
|
||||
#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 0 memory 1 base address register */
|
||||
#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 0 FIFO control register */
|
||||
|
||||
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 control register */
|
||||
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x2CU) /*!< DMA channel 1 counter register */
|
||||
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 1 peripheral base address register */
|
||||
#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 1 memory 0 base address register */
|
||||
#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 1 memory 1 base address register */
|
||||
#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 1 FIFO control register */
|
||||
|
||||
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x40U) /*!< DMA channel 2 control register */
|
||||
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 2 counter register */
|
||||
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 2 peripheral base address register */
|
||||
#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 2 memory 0 base address register */
|
||||
#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 2 memory 1 base address register */
|
||||
#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x54U) /*!< DMA channel 2 FIFO control register */
|
||||
|
||||
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 3 control register */
|
||||
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 3 counter register */
|
||||
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 3 peripheral base address register */
|
||||
#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 3 memory 0 base address register */
|
||||
#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x68U) /*!< DMA channel 3 memory 1 base address register */
|
||||
#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 3 FIFO control register */
|
||||
|
||||
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 4 control register */
|
||||
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 4 counter register */
|
||||
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 4 peripheral base address register */
|
||||
#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x7CU) /*!< DMA channel 4 memory 0 base address register */
|
||||
#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 4 memory 1 base address register */
|
||||
#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 4 FIFO control register */
|
||||
|
||||
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 5 control register */
|
||||
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 5 counter register */
|
||||
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x90U) /*!< DMA channel 5 peripheral base address register */
|
||||
#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x94U) /*!< DMA channel 5 memory 0 base address register */
|
||||
#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x98U) /*!< DMA channel 5 memory 1 base address register */
|
||||
#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x9CU) /*!< DMA channel 5 FIFO control register */
|
||||
|
||||
#define DMA_CH6CTL(dmax) REG32((dmax) + 0xA0U) /*!< DMA channel 6 control register */
|
||||
#define DMA_CH6CNT(dmax) REG32((dmax) + 0xA4U) /*!< DMA channel 6 counter register */
|
||||
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0xA8U) /*!< DMA channel 6 peripheral base address register */
|
||||
#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0xACU) /*!< DMA channel 6 memory 0 base address register */
|
||||
#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0xB0U) /*!< DMA channel 6 memory 1 base address register */
|
||||
#define DMA_CH6FCTL(dmax) REG32((dmax) + 0xB4U) /*!< DMA channel 6 FIFO control register */
|
||||
|
||||
#define DMA_CH7CTL(dmax) REG32((dmax) + 0xB8U) /*!< DMA channel 7 control register */
|
||||
#define DMA_CH7CNT(dmax) REG32((dmax) + 0xBCU) /*!< DMA channel 7 counter register */
|
||||
#define DMA_CH7PADDR(dmax) REG32((dmax) + 0xC0U) /*!< DMA channel 7 peripheral base address register */
|
||||
#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0xC4U) /*!< DMA channel 7 memory 0 base address register */
|
||||
#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0xC8U) /*!< DMA channel 7 memory 1 base address register */
|
||||
#define DMA_CH7FCTL(dmax) REG32((dmax) + 0xCCU) /*!< DMA channel 7 FIFO control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DMA_INTF */
|
||||
#define DMA_INTF_FEEIF BIT(0) /*!< FIFO error and exception flag */
|
||||
#define DMA_INTF_SDEIF BIT(2) /*!< single data mode exception flag */
|
||||
#define DMA_INTF_TAEIF BIT(3) /*!< transfer access error flag */
|
||||
#define DMA_INTF_HTFIF BIT(4) /*!< half transfer finish flag */
|
||||
#define DMA_INTF_FTFIF BIT(5) /*!< full transger finish flag */
|
||||
|
||||
/* DMA_INTC */
|
||||
#define DMA_INTC_FEEIFC BIT(0) /*!< clear FIFO error and exception flag */
|
||||
#define DMA_INTC_SDEIFC BIT(2) /*!< clear single data mode exception flag */
|
||||
#define DMA_INTC_TAEIFC BIT(3) /*!< clear single data mode exception flag */
|
||||
#define DMA_INTC_HTFIFC BIT(4) /*!< clear half transfer finish flag */
|
||||
#define DMA_INTC_FTFIFC BIT(5) /*!< clear full transger finish flag */
|
||||
|
||||
/* DMA_CHxCTL,x=0..7 */
|
||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */
|
||||
#define DMA_CHXCTL_SDEIE BIT(1) /*!< enable bit for channel x single data mode exception interrupt */
|
||||
#define DMA_CHXCTL_TAEIE BIT(2) /*!< enable bit for channel x tranfer access error interrupt */
|
||||
#define DMA_CHXCTL_HTFIE BIT(3) /*!< enable bit for channel x half transfer finish interrupt */
|
||||
#define DMA_CHXCTL_FTFIE BIT(4) /*!< enable bit for channel x full transfer finish interrupt */
|
||||
#define DMA_CHXCTL_TFCS BIT(5) /*!< transfer flow controller select */
|
||||
#define DMA_CHXCTL_TM BITS(6,7) /*!< transfer mode */
|
||||
#define DMA_CHXCTL_CMEN BIT(8) /*!< circulation mode */
|
||||
#define DMA_CHXCTL_PNAGA BIT(9) /*!< next address generation algorithm of peripheral */
|
||||
#define DMA_CHXCTL_MNAGA BIT(10) /*!< next address generation algorithm of memory */
|
||||
#define DMA_CHXCTL_PWIDTH BITS(11,12) /*!< transfer width of peipheral */
|
||||
#define DMA_CHXCTL_MWIDTH BITS(13,14) /*!< transfer width of memory */
|
||||
#define DMA_CHXCTL_PAIF BIT(15) /*!< peripheral address increment fixed */
|
||||
#define DMA_CHXCTL_PRIO BITS(16,17) /*!< priority level */
|
||||
#define DMA_CHXCTL_SBMEN BIT(18) /*!< switch-buffer mode enable */
|
||||
#define DMA_CHXCTL_MBS BIT(19) /*!< memory buffer select */
|
||||
#define DMA_CHXCTL_PBURST BITS(21,22) /*!< transfer burst type of peripheral */
|
||||
#define DMA_CHXCTL_MBURST BITS(23,24) /*!< transfer burst type of memory */
|
||||
#define DMA_CHXCTL_PERIEN BITS(25,27) /*!< peripheral enable */
|
||||
|
||||
/* DMA_CHxCNT,x=0..7 */
|
||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||
|
||||
/* DMA_CHxPADDR,x=0..7 */
|
||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||
|
||||
/* DMA_CHxM0ADDR,x=0..7 */
|
||||
#define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */
|
||||
|
||||
/* DMA_CHxM1ADDR,x=0..7 */
|
||||
#define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */
|
||||
|
||||
/* DMA_CHxFCTL,x=0..7 */
|
||||
#define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */
|
||||
#define DMA_CHXFCTL_MDMEN BIT(2) /*!< multi-data mode enable */
|
||||
#define DMA_CHXFCTL_FCNT BITS(3,5) /*!< FIFO counter */
|
||||
#define DMA_CHXFCTL_FEEIE BIT(7) /*!< FIFO exception interrupt enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA channel select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_CH0 = 0, /*!< DMA Channel 0 */
|
||||
DMA_CH1, /*!< DMA Channel 1 */
|
||||
DMA_CH2, /*!< DMA Channel 2 */
|
||||
DMA_CH3, /*!< DMA Channel 3 */
|
||||
DMA_CH4, /*!< DMA Channel 4 */
|
||||
DMA_CH5, /*!< DMA Channel 5 */
|
||||
DMA_CH6, /*!< DMA Channel 6 */
|
||||
DMA_CH7 /*!< DMA Channel 7 */
|
||||
} dma_channel_enum;
|
||||
|
||||
/* DMA peripheral select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */
|
||||
DMA_SUBPERI1, /*!< DMA Peripheral 1 */
|
||||
DMA_SUBPERI2, /*!< DMA Peripheral 2 */
|
||||
DMA_SUBPERI3, /*!< DMA Peripheral 3 */
|
||||
DMA_SUBPERI4, /*!< DMA Peripheral 4 */
|
||||
DMA_SUBPERI5, /*!< DMA Peripheral 5 */
|
||||
DMA_SUBPERI6, /*!< DMA Peripheral 6 */
|
||||
DMA_SUBPERI7 /*!< DMA Peripheral 7 */
|
||||
} dma_subperipheral_enum;
|
||||
|
||||
/* DMA multidata mode initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||
uint32_t periph_inc; /*!< peripheral increasing mode */
|
||||
|
||||
uint32_t memory0_addr; /*!< memory 0 base address */
|
||||
uint32_t memory_width; /*!< transfer data size of memory */
|
||||
uint32_t memory_inc; /*!< memory increasing mode */
|
||||
|
||||
uint32_t memory_burst_width; /*!< multi data mode enable */
|
||||
uint32_t periph_burst_width; /*!< multi data mode enable */
|
||||
uint32_t critical_value; /*!< FIFO critical */
|
||||
|
||||
uint32_t circular_mode; /*!< DMA circular mode */
|
||||
uint32_t direction; /*!< channel data transfer direction */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
}dma_multi_data_parameter_struct;
|
||||
|
||||
/* DMA singledata mode initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_inc; /*!< peripheral increasing mode */
|
||||
|
||||
uint32_t memory0_addr; /*!< memory 0 base address */
|
||||
uint32_t memory_inc; /*!< memory increasing mode */
|
||||
|
||||
uint32_t periph_memory_width; /*!< transfer data size of peripheral */
|
||||
|
||||
uint32_t circular_mode; /*!< DMA circular mode */
|
||||
uint32_t direction; /*!< channel data transfer direction */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
} dma_single_data_parameter_struct;
|
||||
|
||||
#define DMA_FLAG_ADD(flag,channel) ((uint32_t)((flag)<<((((uint32_t)(channel)*6U))+((uint32_t)(((uint32_t)(channel)) >> 1U)&0x01U)*4U))) /*!< DMA channel flag shift */
|
||||
|
||||
/* DMA_register address */
|
||||
#define DMA_CHCTL(dma,channel) REG32(((dma) + 0x10U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT(dma,channel) REG32(((dma) + 0x14U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR(dma,channel) REG32(((dma) + 0x18U) + 0x18U*(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHM0ADDR(dma,channel) REG32(((dma) + 0x1CU) + 0x18U*(channel)) /*!< the address of DMA channel CHXM0ADDR register */
|
||||
#define DMA_CHM1ADDR(dma,channel) REG32(((dma) + 0x20U) + 0x18U*(channel)) /*!< the address of DMA channel CHXM1ADDR register */
|
||||
#define DMA_CHFCTL(dma,channel) REG32(((dma) + 0x24U) + 0x18U*(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||
|
||||
/* peripheral select */
|
||||
#define CHCTL_PERIEN(regval) (BITS(25,27) & ((uint32_t)(regval) << 25))
|
||||
#define DMA_PERIPH_0_SELECT CHCTL_PERIEN(0) /*!< peripheral 0 select */
|
||||
#define DMA_PERIPH_1_SELECT CHCTL_PERIEN(1) /*!< peripheral 1 select */
|
||||
#define DMA_PERIPH_2_SELECT CHCTL_PERIEN(2) /*!< peripheral 2 select */
|
||||
#define DMA_PERIPH_3_SELECT CHCTL_PERIEN(3) /*!< peripheral 3 select */
|
||||
#define DMA_PERIPH_4_SELECT CHCTL_PERIEN(4) /*!< peripheral 4 select */
|
||||
#define DMA_PERIPH_5_SELECT CHCTL_PERIEN(5) /*!< peripheral 5 select */
|
||||
#define DMA_PERIPH_6_SELECT CHCTL_PERIEN(6) /*!< peripheral 6 select */
|
||||
#define DMA_PERIPH_7_SELECT CHCTL_PERIEN(7) /*!< peripheral 7 select */
|
||||
|
||||
/* burst type of memory */
|
||||
#define CHCTL_MBURST(regval) (BITS(23,24) & ((uint32_t)(regval) << 23))
|
||||
#define DMA_MEMORY_BURST_SINGLE CHCTL_MBURST(0) /*!< single burst */
|
||||
#define DMA_MEMORY_BURST_4_BEAT CHCTL_MBURST(1) /*!< 4-beat burst */
|
||||
#define DMA_MEMORY_BURST_8_BEAT CHCTL_MBURST(2) /*!< 8-beat burst */
|
||||
#define DMA_MEMORY_BURST_16_BEAT CHCTL_MBURST(3) /*!< 16-beat burst */
|
||||
|
||||
/* burst type of peripheral */
|
||||
#define CHCTL_PBURST(regval) (BITS(21,22) & ((uint32_t)(regval) << 21))
|
||||
#define DMA_PERIPH_BURST_SINGLE CHCTL_PBURST(0) /*!< single burst */
|
||||
#define DMA_PERIPH_BURST_4_BEAT CHCTL_PBURST(1) /*!< 4-beat burst */
|
||||
#define DMA_PERIPH_BURST_8_BEAT CHCTL_PBURST(2) /*!< 8-beat burst */
|
||||
#define DMA_PERIPH_BURST_16_BEAT CHCTL_PBURST(3) /*!< 16-beat burst */
|
||||
|
||||
/* channel priority level */
|
||||
#define CHCTL_PRIO(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */
|
||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */
|
||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */
|
||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */
|
||||
|
||||
/* transfer data width of memory */
|
||||
#define CHCTL_MWIDTH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13))
|
||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data width of memory is 8-bit */
|
||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data width of memory is 16-bit */
|
||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data width of memory is 32-bit */
|
||||
|
||||
/* transfer data width of peripheral */
|
||||
#define CHCTL_PWIDTH(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
|
||||
#define DMA_PERIPH_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data width of peripheral is 8-bit */
|
||||
#define DMA_PERIPH_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data width of peripheral is 16-bit */
|
||||
#define DMA_PERIPH_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data width of peripheral is 32-bit */
|
||||
|
||||
/* channel transfer mode */
|
||||
#define CHCTL_TM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define DMA_PERIPH_TO_MEMORY CHCTL_TM(0) /*!< read from peripheral and write to memory */
|
||||
#define DMA_MEMORY_TO_PERIPH CHCTL_TM(1) /*!< read from memory and write to peripheral */
|
||||
#define DMA_MEMORY_TO_MEMORY CHCTL_TM(2) /*!< read from memory and write to memory */
|
||||
|
||||
/* FIFO counter critical value */
|
||||
#define CHFCTL_FCCV(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define DMA_FIFO_1_WORD CHFCTL_FCCV(0) /*!< critical value 1 word */
|
||||
#define DMA_FIFO_2_WORD CHFCTL_FCCV(1) /*!< critical value 2 word */
|
||||
#define DMA_FIFO_3_WORD CHFCTL_FCCV(2) /*!< critical value 3 word */
|
||||
#define DMA_FIFO_4_WORD CHFCTL_FCCV(3) /*!< critical value 4 word */
|
||||
|
||||
/* memory select */
|
||||
#define DMA_MEMORY_0 ((uint32_t)0x00000000U) /*!< select memory 0 */
|
||||
#define DMA_MEMORY_1 ((uint32_t)0x00000001U) /*!< select memory 1 */
|
||||
|
||||
/* DMA circular mode */
|
||||
#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000000U) /*!< circular mode enable */
|
||||
#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000001U) /*!< circular mode disable */
|
||||
|
||||
/* DMA flow controller select */
|
||||
#define DMA_FLOW_CONTROLLER_DMA ((uint32_t)0x00000000U) /*!< DMA is the flow controler */
|
||||
#define DMA_FLOW_CONTROLLER_PERI ((uint32_t)0x00000001U) /*!< peripheral is the flow controler */
|
||||
|
||||
/* peripheral increasing mode */
|
||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is increasing address mode */
|
||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is fixed address mode */
|
||||
#define DMA_PERIPH_INCREASE_FIX ((uint32_t)0x00000002U) /*!< next address of peripheral is increasing fixed */
|
||||
|
||||
/* memory increasing mode */
|
||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of memory is increasing address mode */
|
||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of memory is fixed address mode */
|
||||
|
||||
/* FIFO status */
|
||||
#define DMA_FIFO_STATUS_NODATA ((uint32_t)0x00000000U) /*!< the data in the FIFO less than 1 word */
|
||||
#define DMA_FIFO_STATUS_1_WORD ((uint32_t)0x00000001U) /*!< the data in the FIFO more than 1 word, less than 2 words */
|
||||
#define DMA_FIFO_STATUS_2_WORD ((uint32_t)0x00000002U) /*!< the data in the FIFO more than 2 word, less than 3 words */
|
||||
#define DMA_FIFO_STATUS_3_WORD ((uint32_t)0x00000003U) /*!< the data in the FIFO more than 3 word, less than 4 words */
|
||||
#define DMA_FIFO_STATUS_EMPTY ((uint32_t)0x00000004U) /*!< the data in the FIFO is empty */
|
||||
#define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */
|
||||
|
||||
/* DMA reset value */
|
||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||
#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */
|
||||
#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */
|
||||
|
||||
/* DMA_INTF register */
|
||||
/* interrupt flag bits */
|
||||
#define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */
|
||||
#define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */
|
||||
#define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */
|
||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */
|
||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */
|
||||
|
||||
/* flag bits */
|
||||
#define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */
|
||||
#define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */
|
||||
#define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */
|
||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */
|
||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */
|
||||
|
||||
|
||||
/* function declarations */
|
||||
/* DMA deinitialization and initialization functions */
|
||||
/* deinitialize DMA a channel registers */
|
||||
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* initialize the DMA single data mode parameters struct with the default values */
|
||||
void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct);
|
||||
/* initialize the DMA multi data mode parameters struct with the default values */
|
||||
void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct);
|
||||
/* DMA single data mode initialize */
|
||||
void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct);
|
||||
/* DMA multi data mode initialize */
|
||||
void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct);
|
||||
|
||||
/* DMA configuration functions */
|
||||
/* set DMA peripheral base address */
|
||||
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
||||
/* set DMA Memory base address */
|
||||
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address);
|
||||
|
||||
/* set the number of remaining data to be transferred by the DMA */
|
||||
void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number);
|
||||
/* get the number of remaining data to be transferred by the DMA */
|
||||
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* configure priority level of DMA channel */
|
||||
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
|
||||
|
||||
/* configure transfer burst beats of memory */
|
||||
void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat);
|
||||
/* configure transfer burst beats of peripheral */
|
||||
void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat);
|
||||
/* configure transfer data size of memory */
|
||||
void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize);
|
||||
/* configure transfer data size of peripheral */
|
||||
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize);
|
||||
|
||||
/* configure next address increasement algorithm of memory */
|
||||
void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm);
|
||||
/* configure next address increasement algorithm of peripheral */
|
||||
void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm);
|
||||
|
||||
/* enable DMA circulation mode */
|
||||
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA circulation mode */
|
||||
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable DMA channel */
|
||||
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA channel */
|
||||
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* configure the direction of data transfer on the channel */
|
||||
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction);
|
||||
|
||||
/* DMA switch buffer mode config */
|
||||
void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select);
|
||||
/* DMA using memory get */
|
||||
uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* DMA channel peripheral select */
|
||||
void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph);
|
||||
/* DMA flow controller configure */
|
||||
void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller);
|
||||
/* DMA flow controller enable */
|
||||
void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue);
|
||||
/* DMA FIFO status get */
|
||||
uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
||||
/* enable DMA interrupt */
|
||||
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
/* disable DMA interrupt */
|
||||
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
|
||||
#endif /* GD32F4XX_DMA_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,809 @@
|
|||
/*!
|
||||
\file gd32f4xx_exmc.h
|
||||
\brief definitions for the EXMC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_EXMC_H
|
||||
#define GD32F4XX_EXMC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* EXMC definitions */
|
||||
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
|
||||
#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */
|
||||
#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */
|
||||
#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */
|
||||
#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */
|
||||
|
||||
/* registers definitions */
|
||||
/* NOR/PSRAM */
|
||||
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register for region0 */
|
||||
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */
|
||||
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */
|
||||
|
||||
#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register for region1 */
|
||||
#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */
|
||||
#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */
|
||||
|
||||
#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register for region2 */
|
||||
#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */
|
||||
#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */
|
||||
|
||||
#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register for region3 */
|
||||
#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */
|
||||
#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */
|
||||
|
||||
/* NAND/PC card */
|
||||
#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register for bank1 */
|
||||
#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register for bank1 */
|
||||
#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register for bank1 */
|
||||
#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank1 */
|
||||
#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */
|
||||
|
||||
#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register for bank2 */
|
||||
#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register for bank2 */
|
||||
#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register for bank2 */
|
||||
#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank2 */
|
||||
#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */
|
||||
|
||||
#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register for bank3 */
|
||||
#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register for bank3 */
|
||||
#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register for bank3 */
|
||||
#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank3 */
|
||||
#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register for bank3 */
|
||||
|
||||
/* SDRAM */
|
||||
#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register for device0 */
|
||||
#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register for device0 */
|
||||
|
||||
#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register for device1 */
|
||||
#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register for device1 */
|
||||
|
||||
#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */
|
||||
#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */
|
||||
#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */
|
||||
#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */
|
||||
|
||||
/* SQPI PSRAM */
|
||||
#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */
|
||||
#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */
|
||||
#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */
|
||||
#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */
|
||||
#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXMC_SNCTLx,x=0..3 */
|
||||
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
|
||||
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */
|
||||
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
|
||||
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
|
||||
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
|
||||
#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */
|
||||
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
||||
#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
|
||||
#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
|
||||
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
|
||||
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
||||
#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
|
||||
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */
|
||||
#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */
|
||||
#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */
|
||||
#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock config */
|
||||
|
||||
/* EXMC_SNTCFGx,x=0..3 */
|
||||
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */
|
||||
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */
|
||||
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */
|
||||
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
|
||||
#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
|
||||
#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */
|
||||
#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||
|
||||
/* EXMC_SNWTCFGx,x=0..3 */
|
||||
#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */
|
||||
#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */
|
||||
#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */
|
||||
#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */
|
||||
#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||
|
||||
/* EXMC_NPCTLx,x=1..3 */
|
||||
#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */
|
||||
#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */
|
||||
#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */
|
||||
#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */
|
||||
#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */
|
||||
#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */
|
||||
#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */
|
||||
#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */
|
||||
|
||||
/* EXMC_NPINTENx,x=1..3 */
|
||||
#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */
|
||||
#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */
|
||||
#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */
|
||||
#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */
|
||||
#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */
|
||||
#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */
|
||||
#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */
|
||||
|
||||
/* EXMC_NPCTCFGx,x=1..3 */
|
||||
#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */
|
||||
#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */
|
||||
#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */
|
||||
#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */
|
||||
|
||||
/* EXMC_NPATCFGx,x=1..3 */
|
||||
#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */
|
||||
#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */
|
||||
#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */
|
||||
#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */
|
||||
|
||||
/* EXMC_PIOTCFG3 */
|
||||
#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */
|
||||
#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */
|
||||
#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */
|
||||
#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */
|
||||
|
||||
/* EXMC_NECCx,x=1..2 */
|
||||
#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */
|
||||
|
||||
/* EXMC_SDCTLx,x=0..1 */
|
||||
#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */
|
||||
#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */
|
||||
#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */
|
||||
#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */
|
||||
#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */
|
||||
#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */
|
||||
#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */
|
||||
#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable */
|
||||
#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */
|
||||
|
||||
/* EXMC_SDTCFGx,x=0..1 */
|
||||
#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */
|
||||
#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */
|
||||
#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */
|
||||
#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */
|
||||
#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */
|
||||
#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */
|
||||
#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */
|
||||
|
||||
/* EXMC_SDCMD */
|
||||
#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */
|
||||
#define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */
|
||||
#define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */
|
||||
#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */
|
||||
#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */
|
||||
|
||||
/* EXMC_SDARI */
|
||||
#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */
|
||||
#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */
|
||||
#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */
|
||||
|
||||
/* EXMC_SDSTAT */
|
||||
#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */
|
||||
#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */
|
||||
#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */
|
||||
#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */
|
||||
|
||||
/* EXMC_SDRSCTL */
|
||||
#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */
|
||||
#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */
|
||||
#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */
|
||||
|
||||
/* EXMC_SINIT */
|
||||
#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */
|
||||
#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */
|
||||
#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */
|
||||
#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */
|
||||
|
||||
/* EXMC_SRCMD */
|
||||
#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */
|
||||
#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */
|
||||
#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */
|
||||
#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */
|
||||
|
||||
/* EXMC_SWCMD */
|
||||
#define EXMC_SWCMD_WCMD BITS(0,15) /*!< SPI write command for AHB write transfer */
|
||||
#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI write wait cycle number after address phase */
|
||||
#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI PSRAM write command mode */
|
||||
#define EXMC_SWCMD_SC BIT(31) /*!< send SPI special command */
|
||||
|
||||
/* EXMC_SIDL */
|
||||
#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */
|
||||
|
||||
/* EXMC_SIDH */
|
||||
#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXMC NOR/SRAM timing initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t asyn_access_mode; /*!< asynchronous access mode */
|
||||
uint32_t syn_data_latency; /*!< configure the data latency */
|
||||
uint32_t syn_clk_division; /*!< configure the clock divide ratio */
|
||||
uint32_t bus_latency; /*!< configure the bus latency */
|
||||
uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */
|
||||
uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */
|
||||
uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */
|
||||
}exmc_norsram_timing_parameter_struct;
|
||||
|
||||
/* EXMC NOR/SRAM initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
|
||||
uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
|
||||
uint32_t extended_mode; /*!< enable or disable the extended mode */
|
||||
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
|
||||
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */
|
||||
uint32_t memory_write; /*!< enable or disable the write operation */
|
||||
uint32_t nwait_config; /*!< NWAIT signal configuration */
|
||||
uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */
|
||||
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
|
||||
uint32_t burst_mode; /*!< enable or disable the burst mode */
|
||||
uint32_t databus_width; /*!< specifies the databus width of external memory */
|
||||
uint32_t memory_type; /*!< specifies the type of external memory */
|
||||
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
|
||||
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing
|
||||
parameters for read if the extendedmode is used. */
|
||||
exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */
|
||||
}exmc_norsram_parameter_struct;
|
||||
|
||||
/* EXMC NAND/PC card timing initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
|
||||
uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
|
||||
uint32_t waittime; /*!< configure the minimum wait time */
|
||||
uint32_t setuptime; /*!< configure the address setup time */
|
||||
}exmc_nand_pccard_timing_parameter_struct;
|
||||
|
||||
/* EXMC NAND initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nand_bank; /*!< select the bank of NAND */
|
||||
uint32_t ecc_size; /*!< the page size for the ECC calculation */
|
||||
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||
uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
|
||||
uint32_t databus_width; /*!< the NAND flash databus width */
|
||||
uint32_t wait_feature; /*!< enable or disable the wait feature */
|
||||
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
|
||||
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
|
||||
}exmc_nand_parameter_struct;
|
||||
|
||||
/* EXMC PC card initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||
uint32_t wait_feature; /*!< enable or disable the wait feature */
|
||||
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */
|
||||
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */
|
||||
exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */
|
||||
}exmc_pccard_parameter_struct;
|
||||
|
||||
/* EXMC SDRAM timing initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t row_to_column_delay; /*!< configure the row to column delay */
|
||||
uint32_t row_precharge_delay; /*!< configure the row precharge delay */
|
||||
uint32_t write_recovery_delay; /*!< configure the write recovery delay */
|
||||
uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */
|
||||
uint32_t row_address_select_delay; /*!< configure the row address select delay */
|
||||
uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */
|
||||
uint32_t load_mode_register_delay; /*!< configure the load mode register delay */
|
||||
}exmc_sdram_timing_parameter_struct;
|
||||
|
||||
/* EXMC SDRAM initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t sdram_device; /*!< device of SDRAM */
|
||||
uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */
|
||||
uint32_t brust_read_switch; /*!< enable or disable the burst read */
|
||||
uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */
|
||||
uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */
|
||||
uint32_t cas_latency; /*!< configure the SDRAM CAS latency */
|
||||
uint32_t internal_bank_number; /*!< the number of internal bank */
|
||||
uint32_t data_width; /*!< the databus width of SDRAM memory */
|
||||
uint32_t row_address_width; /*!< the bit width of a row address */
|
||||
uint32_t column_address_width; /*!< the bit width of a column address */
|
||||
exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */
|
||||
}exmc_sdram_parameter_struct;
|
||||
|
||||
/* EXMC SDRAM command initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t mode_register_content; /*!< the SDRAM mode register content */
|
||||
uint32_t auto_refresh_number; /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */
|
||||
uint32_t bank_select; /*!< the bank which command will be sent to */
|
||||
uint32_t command; /*!< the commands that will be sent to SDRAM */
|
||||
}exmc_sdram_command_parameter_struct;
|
||||
|
||||
/* EXMC SQPISRAM initialize struct */
|
||||
typedef struct{
|
||||
uint32_t sample_polarity; /*!< read data sample polarity */
|
||||
uint32_t id_length; /*!< SPI PSRAM ID length */
|
||||
uint32_t address_bits; /*!< bit number of SPI PSRAM address phase */
|
||||
uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */
|
||||
}exmc_sqpipsram_parameter_struct;
|
||||
|
||||
/* EXMC_register address */
|
||||
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */
|
||||
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */
|
||||
#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */
|
||||
|
||||
#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */
|
||||
#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */
|
||||
#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */
|
||||
#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */
|
||||
#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND ECC registers, bank = 1,2 */
|
||||
|
||||
#define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */
|
||||
#define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */
|
||||
|
||||
/* CRAM page size */
|
||||
#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
|
||||
#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */
|
||||
#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */
|
||||
#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */
|
||||
#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */
|
||||
#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */
|
||||
|
||||
/* NOR bank memory data bus width */
|
||||
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */
|
||||
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */
|
||||
|
||||
/* NOR bank memory type */
|
||||
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
|
||||
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
|
||||
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
|
||||
|
||||
/* asynchronous access mode */
|
||||
#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */
|
||||
#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */
|
||||
#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */
|
||||
#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */
|
||||
|
||||
/* data latency for NOR flash */
|
||||
#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||
#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */
|
||||
#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */
|
||||
#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */
|
||||
#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */
|
||||
#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */
|
||||
#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */
|
||||
#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */
|
||||
#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */
|
||||
#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */
|
||||
#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */
|
||||
#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */
|
||||
#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */
|
||||
#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */
|
||||
#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */
|
||||
#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */
|
||||
#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */
|
||||
|
||||
/* synchronous clock divide ratio */
|
||||
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */
|
||||
|
||||
/* ECC size */
|
||||
#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
|
||||
#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */
|
||||
#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */
|
||||
#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */
|
||||
#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */
|
||||
#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */
|
||||
#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */
|
||||
|
||||
/* ALE to RE delay */
|
||||
#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
|
||||
#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
|
||||
|
||||
/* CLE to RE delay */
|
||||
#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
|
||||
#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
|
||||
|
||||
/* NAND bank memory data bus width */
|
||||
#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */
|
||||
#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */
|
||||
|
||||
/* SDRAM pipeline delay */
|
||||
#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13))
|
||||
#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */
|
||||
#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */
|
||||
#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */
|
||||
|
||||
/* SDRAM clock configuration */
|
||||
#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10))
|
||||
#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */
|
||||
#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */
|
||||
#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */
|
||||
|
||||
/* CAS latency */
|
||||
#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7))
|
||||
#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */
|
||||
#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */
|
||||
#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */
|
||||
|
||||
/* SDRAM data bus width */
|
||||
#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */
|
||||
#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */
|
||||
#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */
|
||||
|
||||
/* SDRAM row address bit width */
|
||||
#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */
|
||||
#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */
|
||||
#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */
|
||||
|
||||
/* SDRAM column address bit width */
|
||||
#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */
|
||||
#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */
|
||||
#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */
|
||||
#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */
|
||||
|
||||
/* SDRAM number of successive auto-refresh */
|
||||
#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */
|
||||
|
||||
/* SDRAM command select */
|
||||
#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */
|
||||
#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */
|
||||
#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */
|
||||
#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */
|
||||
#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */
|
||||
#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */
|
||||
#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */
|
||||
|
||||
/* SDRAM the delayed sample clock of read data */
|
||||
#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */
|
||||
#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */
|
||||
#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */
|
||||
#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */
|
||||
#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */
|
||||
#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */
|
||||
#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */
|
||||
#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */
|
||||
#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */
|
||||
#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */
|
||||
#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */
|
||||
#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */
|
||||
#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */
|
||||
#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */
|
||||
#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */
|
||||
#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */
|
||||
|
||||
/* SPI PSRAM ID length */
|
||||
#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29))
|
||||
#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */
|
||||
#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */
|
||||
#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */
|
||||
#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */
|
||||
|
||||
/* SPI PSRAM bit number of address phase */
|
||||
#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24))
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */
|
||||
|
||||
/* SPI PSRAM bit number of command phase */
|
||||
#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||
#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */
|
||||
#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */
|
||||
#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */
|
||||
|
||||
/* SPI PSRAM read command mode */
|
||||
#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||
#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */
|
||||
#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */
|
||||
#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */
|
||||
#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */
|
||||
|
||||
/* SPI PSRAM write command mode */
|
||||
#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||
#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */
|
||||
#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */
|
||||
#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */
|
||||
#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */
|
||||
|
||||
/* EXMC NOR/SRAM bank region definition */
|
||||
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */
|
||||
|
||||
/* EXMC consecutive clock */
|
||||
#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */
|
||||
#define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */
|
||||
|
||||
/* EXMC NOR/SRAM write mode */
|
||||
#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */
|
||||
#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */
|
||||
|
||||
/* EXMC NWAIT signal configuration */
|
||||
#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */
|
||||
#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */
|
||||
|
||||
/* EXMC NWAIT signal polarity configuration */
|
||||
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
|
||||
#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */
|
||||
|
||||
/* EXMC NAND/PC card bank definition */
|
||||
#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< NAND flash bank1 */
|
||||
#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */
|
||||
#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< PC card bank3 */
|
||||
|
||||
/* EXMC SDRAM bank definition */
|
||||
#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */
|
||||
#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */
|
||||
|
||||
/* EXMC SDRAM internal banks */
|
||||
#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */
|
||||
#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */
|
||||
|
||||
/* SDRAM device0 select */
|
||||
#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device0 unselect */
|
||||
#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< SDRAM device0 select */
|
||||
|
||||
/* SDRAM device1 select */
|
||||
#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device1 unselect */
|
||||
#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< SDRAM device1 select */
|
||||
|
||||
/* SDRAM device status */
|
||||
#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */
|
||||
#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */
|
||||
#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */
|
||||
|
||||
/* sample cycle of read data */
|
||||
#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */
|
||||
#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK EXMC_SDRSCTL_SSCR /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */
|
||||
|
||||
/* read data sample polarity */
|
||||
#define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */
|
||||
#define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE EXMC_SINIT_POL /*!< sample data at falling edge */
|
||||
|
||||
/* SQPI SRAM command flag */
|
||||
#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */
|
||||
#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */
|
||||
|
||||
/* EXMC flag bits */
|
||||
#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */
|
||||
#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */
|
||||
#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */
|
||||
|
||||
/* EXMC interrupt flag bits */
|
||||
#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */
|
||||
#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */
|
||||
#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */
|
||||
#define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt and flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* NOR/SRAM */
|
||||
/* deinitialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_deinit(uint32_t exmc_norsram_region);
|
||||
/* initialize exmc_norsram_parameter_struct with the default values */
|
||||
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* initialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* enable EXMC NOR/SRAM region */
|
||||
void exmc_norsram_enable(uint32_t exmc_norsram_region);
|
||||
/* disable EXMC NOR/SRAM region */
|
||||
void exmc_norsram_disable(uint32_t exmc_norsram_region);
|
||||
/* NAND */
|
||||
/* deinitialize EXMC NAND bank */
|
||||
void exmc_nand_deinit(uint32_t exmc_nand_bank);
|
||||
/* initialize exmc_norsram_parameter_struct with the default values */
|
||||
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||
/* initialize EXMC NAND bank */
|
||||
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||
/* enable EXMC NAND bank */
|
||||
void exmc_nand_enable(uint32_t exmc_nand_bank);
|
||||
/* disable EXMC NAND bank */
|
||||
void exmc_nand_disable(uint32_t exmc_nand_bank);
|
||||
/* PC card */
|
||||
/* deinitialize EXMC PC card bank */
|
||||
void exmc_pccard_deinit(void);
|
||||
/* initialize exmc_pccard_parameter_struct with the default values */
|
||||
void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||
/* initialize EXMC PC card bank */
|
||||
void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||
/* enable EXMC PC card bank */
|
||||
void exmc_pccard_enable(void);
|
||||
/* disable EXMC PC card bank */
|
||||
void exmc_pccard_disable(void);
|
||||
/* SDRAM */
|
||||
/* deinitialize EXMC SDRAM device */
|
||||
void exmc_sdram_deinit(uint32_t exmc_sdram_device);
|
||||
/* initialize exmc_sdram_parameter_struct with the default values */
|
||||
void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
||||
/* initialize EXMC SDRAM device */
|
||||
void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
||||
/* SQPIPSRAM */
|
||||
/* deinitialize EXMC SQPIPSRAM */
|
||||
void exmc_sqpipsram_deinit(void);
|
||||
/* initialize exmc_sqpipsram_parameter_struct with the default values */
|
||||
void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct);
|
||||
/* initialize EXMC SQPIPSRAM */
|
||||
void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct);
|
||||
|
||||
/* function configuration */
|
||||
/* NOR/SRAM */
|
||||
/* configure consecutive clock */
|
||||
void exmc_norsram_consecutive_clock_config(uint32_t clock_mode);
|
||||
/* configure CRAM page size */
|
||||
void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size);
|
||||
/* NAND */
|
||||
/* enable or disable the EXMC NAND ECC function */
|
||||
void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue);
|
||||
/* get the EXMC ECC value */
|
||||
uint32_t exmc_ecc_get(uint32_t exmc_nand_bank);
|
||||
/* SDRAM */
|
||||
/* enable or disable read sample */
|
||||
void exmc_sdram_readsample_enable(ControlStatus newvalue);
|
||||
/* configure the delayed sample clock of read data */
|
||||
void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk);
|
||||
/* configure the SDRAM memory command */
|
||||
void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct);
|
||||
/* set auto-refresh interval */
|
||||
void exmc_sdram_refresh_count_set(uint32_t exmc_count);
|
||||
/* set the number of successive auto-refresh command */
|
||||
void exmc_sdram_autorefresh_number_set(uint32_t exmc_number);
|
||||
/* config the write protection function */
|
||||
void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue);
|
||||
/* get the status of SDRAM device0 or device1 */
|
||||
uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device);
|
||||
/* SQPIPSRAM */
|
||||
/* set the read command */
|
||||
void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code);
|
||||
/* set the write command */
|
||||
void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle,uint32_t write_command_code);
|
||||
/* send SPI read ID command */
|
||||
void exmc_sqpipsram_read_id_command_send(void);
|
||||
/* send SPI special command which does not have address and data phase */
|
||||
void exmc_sqpipsram_write_cmd_send(void);
|
||||
/* get the EXMC SPI ID low data */
|
||||
uint32_t exmc_sqpipsram_low_id_get(void);
|
||||
/* get the EXMC SPI ID high data */
|
||||
uint32_t exmc_sqpipsram_high_id_get(void);
|
||||
/* get the bit value of EXMC send write command bit or read ID command */
|
||||
FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* enable EXMC interrupt */
|
||||
void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt);
|
||||
/* disable EXMC interrupt */
|
||||
void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt);
|
||||
/* get EXMC flag status */
|
||||
FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag);
|
||||
/* clear EXMC flag status */
|
||||
void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag);
|
||||
/* get EXMC interrupt flag */
|
||||
FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt);
|
||||
/* clear EXMC interrupt flag */
|
||||
void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt);
|
||||
|
||||
#endif /* GD32F4XX_EXMC_H */
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
/*!
|
||||
\file gd32f4xx_exti.h
|
||||
\brief definitions for the EXTI
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.1, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_EXTI_H
|
||||
#define GD32F4XX_EXTI_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* EXTI definitions */
|
||||
#define EXTI EXTI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */
|
||||
#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */
|
||||
#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */
|
||||
#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */
|
||||
#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */
|
||||
#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXTI_INTEN */
|
||||
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
||||
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
||||
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
||||
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
||||
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
||||
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
||||
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
||||
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
||||
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
||||
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
||||
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
||||
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
||||
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
||||
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
||||
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
||||
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
||||
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
||||
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
||||
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
||||
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
|
||||
#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */
|
||||
#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */
|
||||
#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */
|
||||
|
||||
/* EXTI_EVEN */
|
||||
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
||||
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
||||
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
||||
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
||||
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
||||
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
||||
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
||||
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
||||
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
||||
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
||||
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
||||
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
||||
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
||||
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
||||
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
||||
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
||||
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
||||
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
||||
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
||||
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
|
||||
#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */
|
||||
#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */
|
||||
#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */
|
||||
|
||||
/* EXTI_RTEN */
|
||||
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
||||
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
||||
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
||||
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
||||
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
||||
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
||||
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
||||
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
||||
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
||||
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
||||
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
||||
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
||||
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
||||
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
||||
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
||||
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
||||
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
||||
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
||||
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
|
||||
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
|
||||
#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */
|
||||
#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */
|
||||
#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */
|
||||
|
||||
/* EXTI_FTEN */
|
||||
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
||||
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
||||
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
||||
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
||||
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
||||
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
||||
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
||||
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
||||
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
||||
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
||||
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
||||
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
||||
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
||||
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
||||
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
||||
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
||||
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
||||
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
||||
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
|
||||
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
|
||||
#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */
|
||||
#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */
|
||||
#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */
|
||||
|
||||
/* EXTI_SWIEV */
|
||||
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
||||
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
||||
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
||||
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
||||
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
||||
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
||||
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
||||
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
||||
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
||||
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
||||
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
||||
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
||||
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
||||
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
||||
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
||||
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
||||
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
||||
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
||||
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
|
||||
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
|
||||
#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */
|
||||
#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
|
||||
#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */
|
||||
|
||||
/* EXTI_PD */
|
||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */
|
||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */
|
||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */
|
||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */
|
||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */
|
||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */
|
||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */
|
||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */
|
||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */
|
||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */
|
||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */
|
||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */
|
||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */
|
||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */
|
||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */
|
||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */
|
||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */
|
||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
|
||||
#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */
|
||||
#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */
|
||||
#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */
|
||||
#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */
|
||||
#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXTI line number */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
||||
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
||||
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
||||
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
||||
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
||||
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
||||
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
||||
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
||||
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
||||
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
||||
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
||||
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
||||
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
||||
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
||||
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
||||
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
||||
EXTI_19 = BIT(19), /*!< EXTI line 19 */
|
||||
EXTI_20 = BIT(20), /*!< EXTI line 20 */
|
||||
EXTI_21 = BIT(21), /*!< EXTI line 21 */
|
||||
EXTI_22 = BIT(22), /*!< EXTI line 22 */
|
||||
}exti_line_enum;
|
||||
|
||||
/* external interrupt and event */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||
EXTI_EVENT /*!< EXTI event mode */
|
||||
}exti_mode_enum;
|
||||
|
||||
/* interrupt trigger mode */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
|
||||
EXTI_TRIG_NONE /*!< none EXTI edge trigger */
|
||||
}exti_trig_type_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the EXTI */
|
||||
void exti_deinit(void);
|
||||
/* enable the configuration of EXTI initialize */
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||
/* enable the interrupts from EXTI line x */
|
||||
void exti_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the interrupts from EXTI line x */
|
||||
void exti_interrupt_disable(exti_line_enum linex);
|
||||
/* enable the events from EXTI line x */
|
||||
void exti_event_enable(exti_line_enum linex);
|
||||
/* disable the events from EXTI line x */
|
||||
void exti_event_disable(exti_line_enum linex);
|
||||
/* EXTI software interrupt event enable */
|
||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||
/* EXTI software interrupt event disable */
|
||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get EXTI lines pending flag */
|
||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI lines pending flag */
|
||||
void exti_flag_clear(exti_line_enum linex);
|
||||
/* get EXTI lines flag when the interrupt flag is set */
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI lines pending flag */
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||
|
||||
#endif /* GD32F4XX_EXTI_H */
|
||||
|
|
@ -0,0 +1,383 @@
|
|||
/*!
|
||||
\file gd32f4xx_fmc.h
|
||||
\brief definitions for the FMC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F4XX_FMC_H
|
||||
#define GD32F4XX_FMC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* FMC and option byte definition */
|
||||
#define FMC FMC_BASE /*!< FMC register base address */
|
||||
#define OB OB_BASE /*!< option byte base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FMC_WS REG32((FMC) + 0x0000U) /*!< FMC wait state register */
|
||||
#define FMC_KEY REG32((FMC) + 0x0004U) /*!< FMC unlock key register */
|
||||
#define FMC_OBKEY REG32((FMC) + 0x0008U) /*!< FMC option byte unlock key register */
|
||||
#define FMC_STAT REG32((FMC) + 0x000CU) /*!< FMC status register */
|
||||
#define FMC_CTL REG32((FMC) + 0x0010U) /*!< FMC control register */
|
||||
#define FMC_OBCTL0 REG32((FMC) + 0x0014U) /*!< FMC option byte control register 0 */
|
||||
#define FMC_OBCTL1 REG32((FMC) + 0x0018U) /*!< FMC option byte control register 1 */
|
||||
#define FMC_WSEN REG32((FMC) + 0x00FCU) /*!< FMC wait state enable register */
|
||||
#define FMC_PID REG32((FMC) + 0x0100U) /*!< FMC product ID register */
|
||||
|
||||
#define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */
|
||||
#define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/
|
||||
#define OB_SPC REG32((OB) + 0x00010001U) /*!< option byte security protection value */
|
||||
#define OB_WP0 REG32((OB) + 0x00010008U) /*!< option byte write protection 0 */
|
||||
|
||||
/* bits definitions */
|
||||
/* FMC_WS */
|
||||
#define FMC_WC_WSCNT BITS(0,3) /*!< wait state counter */
|
||||
|
||||
/* FMC_KEY */
|
||||
#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash key bits */
|
||||
|
||||
/* FMC_OBKEY */
|
||||
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option byte key bits */
|
||||
|
||||
/* FMC_STAT */
|
||||
#define FMC_STAT_END BIT(0) /*!< end of operation flag bit */
|
||||
#define FMC_STAT_OPERR BIT(1) /*!< flash operation error flag bit */
|
||||
#define FMC_STAT_WPERR BIT(4) /*!< erase/Program protection error flag bit */
|
||||
#define FMC_STAT_PGMERR BIT(6) /*!< program size not match error flag bit */
|
||||
#define FMC_STAT_PGSERR BIT(7) /*!< program sequence error flag bit */
|
||||
#define FMC_STAT_RDDERR BIT(8) /*!< read D-bus protection error flag bit */
|
||||
#define FMC_STAT_BUSY BIT(16) /*!< flash busy flag bit */
|
||||
|
||||
/* FMC_CTL */
|
||||
#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
|
||||
#define FMC_CTL_SER BIT(1) /*!< main flash sector erase command bit */
|
||||
#define FMC_CTL_MER0 BIT(2) /*!< main flash mass erase for bank0 command bit */
|
||||
#define FMC_CTL_SN BITS(3,7) /*!< select which sector number to be erased */
|
||||
#define FMC_CTL_PSZ BITS(8,9) /*!< program size bit */
|
||||
#define FMC_CTL_MER1 BIT(15) /*!< main flash mass erase for bank1 command bit */
|
||||
#define FMC_CTL_START BIT(16) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL_ENDIE BIT(24) /*!< end of operation interrupt enable bit */
|
||||
#define FMC_CTL_ERRIE BIT(25) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL_LK BIT(31) /*!< FMC_CTL lock bit */
|
||||
|
||||
/* FMC_OBCTL0 */
|
||||
#define FMC_OBCTL0_OB_LK BIT(0) /*!< FMC_OBCTL0 lock bit */
|
||||
#define FMC_OBCTL0_OB_START BIT(1) /*!< send option byte change command to FMC bit */
|
||||
#define FMC_OBCTL0_BOR_TH BITS(2,3) /*!< option byte BOR threshold value */
|
||||
#define FMC_OBCTL0_BB BIT(4) /*!< option byte boot bank value */
|
||||
#define FMC_OBCTL0_NWDG_HW BIT(5) /*!< option byte watchdog value */
|
||||
#define FMC_OBCTL0_NRST_DPSLP BIT(6) /*!< option byte deepsleep reset value */
|
||||
#define FMC_OBCTL0_NRST_STDBY BIT(7) /*!< option byte standby reset value */
|
||||
#define FMC_OBCTL0_SPC BITS(8,15) /*!< option byte Security Protection code */
|
||||
#define FMC_OBCTL0_WP0 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */
|
||||
#define FMC_OBCTL0_DBS BIT(30) /*!< double banks or single bank selection when flash size is 1M bytes */
|
||||
#define FMC_OBCTL0_DRP BIT(31) /*!< D-bus read protection bit */
|
||||
|
||||
/* FMC_OBCTL1 */
|
||||
#define FMC_OBCTL1_WP1 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */
|
||||
|
||||
/* FMC_WSEN */
|
||||
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
|
||||
|
||||
/* FMC_PID */
|
||||
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* fmc state */
|
||||
typedef enum
|
||||
{
|
||||
FMC_READY, /*!< the operation has been completed */
|
||||
FMC_BUSY, /*!< the operation is in progress */
|
||||
FMC_RDDERR, /*!< read D-bus protection error */
|
||||
FMC_PGSERR, /*!< program sequence error */
|
||||
FMC_PGMERR, /*!< program size not match error */
|
||||
FMC_WPERR, /*!< erase/program protection error */
|
||||
FMC_OPERR, /*!< operation error */
|
||||
FMC_PGERR, /*!< program error */
|
||||
}fmc_state_enum;
|
||||
|
||||
/* unlock key */
|
||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||
|
||||
#define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */
|
||||
#define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */
|
||||
|
||||
/* option byte write protection */
|
||||
#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
|
||||
#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
|
||||
|
||||
/* FMC wait state counter */
|
||||
#define WC_WSCNT(regval) (BITS(0,3) & ((uint32_t)(regval)))
|
||||
#define WS_WSCNT_0 WC_WSCNT(0) /*!< FMC 0 wait */
|
||||
#define WS_WSCNT_1 WC_WSCNT(1) /*!< FMC 1 wait */
|
||||
#define WS_WSCNT_2 WC_WSCNT(2) /*!< FMC 2 wait */
|
||||
#define WS_WSCNT_3 WC_WSCNT(3) /*!< FMC 3 wait */
|
||||
#define WS_WSCNT_4 WC_WSCNT(4) /*!< FMC 4 wait */
|
||||
#define WS_WSCNT_5 WC_WSCNT(5) /*!< FMC 5 wait */
|
||||
#define WS_WSCNT_6 WC_WSCNT(6) /*!< FMC 6 wait */
|
||||
#define WS_WSCNT_7 WC_WSCNT(7) /*!< FMC 7 wait */
|
||||
#define WS_WSCNT_8 WC_WSCNT(8) /*!< FMC 8 wait */
|
||||
#define WS_WSCNT_9 WC_WSCNT(9) /*!< FMC 9 wait */
|
||||
#define WS_WSCNT_10 WC_WSCNT(10) /*!< FMC 10 wait */
|
||||
#define WS_WSCNT_11 WC_WSCNT(11) /*!< FMC 11 wait */
|
||||
#define WS_WSCNT_12 WC_WSCNT(12) /*!< FMC 12 wait */
|
||||
#define WS_WSCNT_13 WC_WSCNT(13) /*!< FMC 13 wait */
|
||||
#define WS_WSCNT_14 WC_WSCNT(14) /*!< FMC 14 wait */
|
||||
#define WS_WSCNT_15 WC_WSCNT(15) /*!< FMC 15 wait */
|
||||
|
||||
/* option byte BOR threshold value */
|
||||
#define OBCTL0_BOR_TH(regval) (BITS(2,3) & ((uint32_t)(regval))<< 2)
|
||||
#define OB_BOR_TH_VALUE3 OBCTL0_BOR_TH(0) /*!< BOR threshold value 3 */
|
||||
#define OB_BOR_TH_VALUE2 OBCTL0_BOR_TH(1) /*!< BOR threshold value 2 */
|
||||
#define OB_BOR_TH_VALUE1 OBCTL0_BOR_TH(2) /*!< BOR threshold value 1 */
|
||||
#define OB_BOR_TH_OFF OBCTL0_BOR_TH(3) /*!< no BOR function */
|
||||
|
||||
/* option byte boot bank value */
|
||||
#define OBCTL0_BB(regval) (BIT(4) & ((uint32_t)(regval)<<4))
|
||||
#define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */
|
||||
#define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */
|
||||
|
||||
/* option byte software/hardware free watch dog timer */
|
||||
#define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5)
|
||||
#define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */
|
||||
#define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */
|
||||
|
||||
/* option byte reset or not entering deep sleep mode */
|
||||
#define OBCTL0_NRST_DPSLP(regval) (BIT(6) & ((uint32_t)(regval))<< 6)
|
||||
#define OB_DEEPSLEEP_NRST OBCTL0_NRST_DPSLP(1) /*!< no reset when entering deepsleep mode */
|
||||
#define OB_DEEPSLEEP_RST OBCTL0_NRST_DPSLP(0) /*!< generate a reset instead of entering deepsleep mode */
|
||||
|
||||
/* option byte reset or not entering standby mode */
|
||||
#define OBCTL0_NRST_STDBY(regval) (BIT(7) & ((uint32_t)(regval))<< 7)
|
||||
#define OB_STDBY_NRST OBCTL0_NRST_STDBY(1) /*!< no reset when entering deepsleep mode */
|
||||
#define OB_STDBY_RST OBCTL0_NRST_STDBY(0) /*!< generate a reset instead of entering standby mode */
|
||||
|
||||
/* read protect configure */
|
||||
#define FMC_NSPC ((uint8_t)0xAAU) /*!< no security protection */
|
||||
#define FMC_LSPC ((uint8_t)0xABU) /*!< low security protection */
|
||||
#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */
|
||||
|
||||
/* option bytes write protection */
|
||||
#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */
|
||||
#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */
|
||||
#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */
|
||||
#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */
|
||||
#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */
|
||||
#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */
|
||||
#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */
|
||||
#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */
|
||||
#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */
|
||||
#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
|
||||
#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
|
||||
#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
|
||||
#define OB_WP_12 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 12 */
|
||||
#define OB_WP_13 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 13 */
|
||||
#define OB_WP_14 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 14 */
|
||||
#define OB_WP_15 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 15 */
|
||||
#define OB_WP_16 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 16 */
|
||||
#define OB_WP_17 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 17 */
|
||||
#define OB_WP_18 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 18 */
|
||||
#define OB_WP_19 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 19 */
|
||||
#define OB_WP_20 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 20 */
|
||||
#define OB_WP_21 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 21 */
|
||||
#define OB_WP_22 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 22 */
|
||||
#define OB_WP_23_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 23~27 */
|
||||
#define OB_WP_ALL ((uint32_t)0x0FFF0FFFU) /*!< erase/program protection of all sectors */
|
||||
|
||||
/* option bytes D-bus read protection */
|
||||
#define OB_DRP_0 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 0 */
|
||||
#define OB_DRP_1 ((uint32_t)0x00000002U) /*!< D-bus read protection protection of sector 1 */
|
||||
#define OB_DRP_2 ((uint32_t)0x00000004U) /*!< D-bus read protection protection of sector 2 */
|
||||
#define OB_DRP_3 ((uint32_t)0x00000008U) /*!< D-bus read protection protection of sector 3 */
|
||||
#define OB_DRP_4 ((uint32_t)0x00000010U) /*!< D-bus read protection protection of sector 4 */
|
||||
#define OB_DRP_5 ((uint32_t)0x00000020U) /*!< D-bus read protection protection of sector 5 */
|
||||
#define OB_DRP_6 ((uint32_t)0x00000040U) /*!< D-bus read protection protection of sector 6 */
|
||||
#define OB_DRP_7 ((uint32_t)0x00000080U) /*!< D-bus read protection protection of sector 7 */
|
||||
#define OB_DRP_8 ((uint32_t)0x00000100U) /*!< D-bus read protection protection of sector 8 */
|
||||
#define OB_DRP_9 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 9 */
|
||||
#define OB_DRP_10 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 10 */
|
||||
#define OB_DRP_11 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 11 */
|
||||
#define OB_DRP_12 ((uint32_t)0x00010000U) /*!< D-bus read protection protection of sector 12 */
|
||||
#define OB_DRP_13 ((uint32_t)0x00020000U) /*!< D-bus read protection protection of sector 13 */
|
||||
#define OB_DRP_14 ((uint32_t)0x00040000U) /*!< D-bus read protection protection of sector 14 */
|
||||
#define OB_DRP_15 ((uint32_t)0x00080000U) /*!< D-bus read protection protection of sector 15 */
|
||||
#define OB_DRP_16 ((uint32_t)0x00100000U) /*!< D-bus read protection protection of sector 16 */
|
||||
#define OB_DRP_17 ((uint32_t)0x00200000U) /*!< D-bus read protection protection of sector 17 */
|
||||
#define OB_DRP_18 ((uint32_t)0x00400000U) /*!< D-bus read protection protection of sector 18 */
|
||||
#define OB_DRP_19 ((uint32_t)0x00800000U) /*!< D-bus read protection protection of sector 19 */
|
||||
#define OB_DRP_20 ((uint32_t)0x01000000U) /*!< D-bus read protection protection of sector 20 */
|
||||
#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */
|
||||
#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */
|
||||
#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */
|
||||
|
||||
/* double banks or single bank selection when flash size is 1M bytes */
|
||||
#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval)<<30))
|
||||
#define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */
|
||||
#define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */
|
||||
|
||||
/* option bytes D-bus read protection mode */
|
||||
#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval)<<31))
|
||||
#define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */
|
||||
#define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */
|
||||
|
||||
/* FMC sectors */
|
||||
#define CTL_SN(regval) (BITS(3,7) & ((uint32_t)(regval))<< 3)
|
||||
#define CTL_SECTOR_NUMBER_0 CTL_SN(0) /*!< sector 0 */
|
||||
#define CTL_SECTOR_NUMBER_1 CTL_SN(1) /*!< sector 1 */
|
||||
#define CTL_SECTOR_NUMBER_2 CTL_SN(2) /*!< sector 2 */
|
||||
#define CTL_SECTOR_NUMBER_3 CTL_SN(3) /*!< sector 3 */
|
||||
#define CTL_SECTOR_NUMBER_4 CTL_SN(4) /*!< sector 4 */
|
||||
#define CTL_SECTOR_NUMBER_5 CTL_SN(5) /*!< sector 5 */
|
||||
#define CTL_SECTOR_NUMBER_6 CTL_SN(6) /*!< sector 6 */
|
||||
#define CTL_SECTOR_NUMBER_7 CTL_SN(7) /*!< sector 7 */
|
||||
#define CTL_SECTOR_NUMBER_8 CTL_SN(8) /*!< sector 8 */
|
||||
#define CTL_SECTOR_NUMBER_9 CTL_SN(9) /*!< sector 9 */
|
||||
#define CTL_SECTOR_NUMBER_10 CTL_SN(10) /*!< sector 10 */
|
||||
#define CTL_SECTOR_NUMBER_11 CTL_SN(11) /*!< sector 11 */
|
||||
#define CTL_SECTOR_NUMBER_24 CTL_SN(12) /*!< sector 24 */
|
||||
#define CTL_SECTOR_NUMBER_25 CTL_SN(13) /*!< sector 25 */
|
||||
#define CTL_SECTOR_NUMBER_26 CTL_SN(14) /*!< sector 26 */
|
||||
#define CTL_SECTOR_NUMBER_27 CTL_SN(15) /*!< sector 27 */
|
||||
#define CTL_SECTOR_NUMBER_12 CTL_SN(16) /*!< sector 12 */
|
||||
#define CTL_SECTOR_NUMBER_13 CTL_SN(17) /*!< sector 13 */
|
||||
#define CTL_SECTOR_NUMBER_14 CTL_SN(18) /*!< sector 14 */
|
||||
#define CTL_SECTOR_NUMBER_15 CTL_SN(19) /*!< sector 15 */
|
||||
#define CTL_SECTOR_NUMBER_16 CTL_SN(20) /*!< sector 16 */
|
||||
#define CTL_SECTOR_NUMBER_17 CTL_SN(21) /*!< sector 17 */
|
||||
#define CTL_SECTOR_NUMBER_18 CTL_SN(22) /*!< sector 18 */
|
||||
#define CTL_SECTOR_NUMBER_19 CTL_SN(23) /*!< sector 19 */
|
||||
#define CTL_SECTOR_NUMBER_20 CTL_SN(24) /*!< sector 20 */
|
||||
#define CTL_SECTOR_NUMBER_21 CTL_SN(25) /*!< sector 21 */
|
||||
#define CTL_SECTOR_NUMBER_22 CTL_SN(26) /*!< sector 22 */
|
||||
#define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */
|
||||
|
||||
|
||||
/* FMC program size */
|
||||
#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8)
|
||||
#define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */
|
||||
#define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */
|
||||
#define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */
|
||||
|
||||
/* FMC interrupt enable */
|
||||
#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */
|
||||
#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */
|
||||
|
||||
/* FMC flags */
|
||||
#define FMC_FLAG_END ((uint32_t)0x00000001U) /*!< FMC end of operation flag bit */
|
||||
#define FMC_FLAG_OPERR ((uint32_t)0x00000002U) /*!< FMC operation error flag bit */
|
||||
#define FMC_FLAG_WPERR ((uint32_t)0x00000010U) /*!< FMC erase/program protection error flag bit */
|
||||
#define FMC_FLAG_PGMERR ((uint32_t)0x00000040U) /*!< FMC program size not match error flag bit */
|
||||
#define FMC_FLAG_PGSERR ((uint32_t)0x00000080U) /*!< FMC program sequence error flag bit */
|
||||
#define FMC_FLAG_RDDERR ((uint32_t)0x00000100U) /*!< FMC read D-bus protection error flag bit */
|
||||
#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */
|
||||
|
||||
/* function declarations */
|
||||
/* FMC main memory programming functions */
|
||||
/* set the FMC wait state counter */
|
||||
void fmc_wscnt_set(uint32_t wscnt);
|
||||
/* unlock the main FMC operation */
|
||||
void fmc_unlock(void);
|
||||
/* lock the main FMC operation */
|
||||
void fmc_lock(void);
|
||||
/* FMC erase sector */
|
||||
fmc_state_enum fmc_sector_erase(uint32_t fmc_sector);
|
||||
/* FMC erase whole chip */
|
||||
fmc_state_enum fmc_mass_erase(void);
|
||||
/* FMC erase whole bank0 */
|
||||
fmc_state_enum fmc_bank0_erase(void);
|
||||
/* FMC erase whole bank1 */
|
||||
fmc_state_enum fmc_bank1_erase(void);
|
||||
/* FMC program a word at the corresponding address */
|
||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
||||
/* FMC program a half word at the corresponding address */
|
||||
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
|
||||
/* FMC program a byte at the corresponding address */
|
||||
fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data);
|
||||
|
||||
/* FMC option bytes programming functions */
|
||||
/* unlock the option byte operation */
|
||||
void ob_unlock(void);
|
||||
/* lock the option byte operation */
|
||||
void ob_lock(void);
|
||||
/* send option byte change command */
|
||||
void ob_start(void);
|
||||
/* erase option byte */
|
||||
void ob_erase(void);
|
||||
/* enable write protect */
|
||||
void ob_write_protection_enable(uint32_t ob_wp);
|
||||
/* disable write protect */
|
||||
void ob_write_protection_disable(uint32_t ob_wp);
|
||||
/* enable erase/program protection and D-bus read protection */
|
||||
void ob_drp_enable(uint32_t ob_drp);
|
||||
/* disable erase/program protection and D-bus read protection */
|
||||
void ob_drp_disable(uint32_t ob_drp);
|
||||
/* set the option byte security protection level */
|
||||
void ob_security_protection_config(uint8_t ob_spc);
|
||||
/* write the FMC option byte user */
|
||||
void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby);
|
||||
/* option byte BOR threshold value */
|
||||
void ob_user_bor_threshold(uint32_t ob_bor_th);
|
||||
/* configure the boot mode */
|
||||
void ob_boot_mode_config(uint32_t boot_mode);
|
||||
/* get the FMC option byte user */
|
||||
uint8_t ob_user_get(void);
|
||||
/* get the FMC option byte write protection */
|
||||
uint16_t ob_write_protection0_get(void);
|
||||
/* get the FMC option byte write protection */
|
||||
uint16_t ob_write_protection1_get(void);
|
||||
/* get the FMC erase/program protection and D-bus read protection option bytes value */
|
||||
uint16_t ob_drp0_get(void);
|
||||
/* get the FMC erase/program protection and D-bus read protection option bytes value */
|
||||
uint16_t ob_drp1_get(void);
|
||||
/* get option byte security protection code value */
|
||||
FlagStatus ob_spc_get(void);
|
||||
/* get the FMC threshold value */
|
||||
uint8_t ob_user_bor_threshold_get(void);
|
||||
|
||||
/* FMC interrupts and flags management functions */
|
||||
/* enable FMC interrupt */
|
||||
void fmc_interrupt_enable(uint32_t fmc_int);
|
||||
/* disable FMC interrupt */
|
||||
void fmc_interrupt_disable(uint32_t fmc_int);
|
||||
/* get flag set or reset */
|
||||
FlagStatus fmc_flag_get(uint32_t fmc_flag);
|
||||
/* clear the FMC pending flag */
|
||||
void fmc_flag_clear(uint32_t fmc_flag);
|
||||
/* return the FMC state */
|
||||
fmc_state_enum fmc_state_get(void);
|
||||
/* check FMC ready or not */
|
||||
fmc_state_enum fmc_ready_wait(void);
|
||||
|
||||
#endif /* GD32F4XX_FMC_H */
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
/*!
|
||||
\file gd32f4xx_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_FWDGT_H
|
||||
#define GD32F4XX_FWDGT_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
|
||||
/* constants definitions */
|
||||
/* psc register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32F4XX_FWDGT_H */
|
||||
|
|
@ -0,0 +1,408 @@
|
|||
/*!
|
||||
\file gd32f4xx_gpio.h
|
||||
\brief definitions for the GPIO
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_GPIO_H
|
||||
#define GD32F4XX_GPIO_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* GPIOx(x=A,B,C,D,E,F,G,H,I) definitions */
|
||||
#define GPIOA (GPIO_BASE + 0x00000000U)
|
||||
#define GPIOB (GPIO_BASE + 0x00000400U)
|
||||
#define GPIOC (GPIO_BASE + 0x00000800U)
|
||||
#define GPIOD (GPIO_BASE + 0x00000C00U)
|
||||
#define GPIOE (GPIO_BASE + 0x00001000U)
|
||||
#define GPIOF (GPIO_BASE + 0x00001400U)
|
||||
#define GPIOG (GPIO_BASE + 0x00001800U)
|
||||
#define GPIOH (GPIO_BASE + 0x00001C00U)
|
||||
#define GPIOI (GPIO_BASE + 0x00002000U)
|
||||
|
||||
/* registers definitions */
|
||||
#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */
|
||||
#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */
|
||||
#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */
|
||||
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */
|
||||
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */
|
||||
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */
|
||||
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */
|
||||
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */
|
||||
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */
|
||||
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */
|
||||
#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */
|
||||
#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */
|
||||
|
||||
/* bits definitions */
|
||||
/* GPIO_CTL */
|
||||
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
|
||||
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
|
||||
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
|
||||
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
|
||||
#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */
|
||||
#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */
|
||||
#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */
|
||||
#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */
|
||||
#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */
|
||||
#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */
|
||||
#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */
|
||||
#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */
|
||||
#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */
|
||||
#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */
|
||||
#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */
|
||||
#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
|
||||
|
||||
/* GPIO_OMODE */
|
||||
#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */
|
||||
#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */
|
||||
#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */
|
||||
#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */
|
||||
#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */
|
||||
#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */
|
||||
#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */
|
||||
#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */
|
||||
#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */
|
||||
#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */
|
||||
#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */
|
||||
#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */
|
||||
#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */
|
||||
#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */
|
||||
#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */
|
||||
#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */
|
||||
|
||||
/* GPIO_OSPD */
|
||||
#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */
|
||||
|
||||
/* GPIO_PUD */
|
||||
#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */
|
||||
|
||||
/* GPIO_ISTAT */
|
||||
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
|
||||
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
|
||||
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
|
||||
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
|
||||
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
|
||||
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
|
||||
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
|
||||
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
|
||||
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
|
||||
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
|
||||
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
|
||||
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
|
||||
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
|
||||
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
|
||||
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
|
||||
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
||||
|
||||
/* GPIO_OCTL */
|
||||
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
|
||||
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
|
||||
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
|
||||
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
|
||||
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
|
||||
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
|
||||
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
|
||||
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
|
||||
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
|
||||
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
|
||||
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
|
||||
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
|
||||
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
|
||||
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
|
||||
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
|
||||
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
|
||||
|
||||
/* GPIO_BOP */
|
||||
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
||||
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
|
||||
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
|
||||
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
|
||||
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
|
||||
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
|
||||
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
|
||||
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
|
||||
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
|
||||
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
|
||||
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
|
||||
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
|
||||
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
|
||||
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
|
||||
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
|
||||
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
|
||||
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
|
||||
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
|
||||
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
|
||||
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
|
||||
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
|
||||
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
|
||||
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
|
||||
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
|
||||
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
|
||||
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
|
||||
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
|
||||
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
|
||||
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
|
||||
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
|
||||
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
|
||||
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_LOCK */
|
||||
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
|
||||
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
|
||||
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
|
||||
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
|
||||
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
|
||||
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
|
||||
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
|
||||
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
|
||||
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
|
||||
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
|
||||
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
|
||||
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
|
||||
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
|
||||
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
||||
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
||||
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
||||
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
|
||||
|
||||
/* GPIO_AFSEL0 */
|
||||
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
|
||||
|
||||
/* GPIO_AFSEL1 */
|
||||
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */
|
||||
|
||||
/* GPIO_BC */
|
||||
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
|
||||
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
|
||||
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
|
||||
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
|
||||
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
|
||||
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
|
||||
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
|
||||
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
|
||||
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
|
||||
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
|
||||
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
|
||||
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
|
||||
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
|
||||
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
|
||||
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
|
||||
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_TG */
|
||||
#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */
|
||||
#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */
|
||||
#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */
|
||||
#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */
|
||||
#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */
|
||||
#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */
|
||||
#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */
|
||||
#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */
|
||||
#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */
|
||||
#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */
|
||||
#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */
|
||||
#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */
|
||||
#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */
|
||||
#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */
|
||||
#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */
|
||||
#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */
|
||||
|
||||
/* constants definitions */
|
||||
typedef FlagStatus bit_status;
|
||||
|
||||
/* output mode definitions */
|
||||
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
|
||||
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
|
||||
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
|
||||
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
|
||||
|
||||
/* pull-up/ pull-down definitions */
|
||||
#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */
|
||||
#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */
|
||||
#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */
|
||||
|
||||
/* GPIO pin definitions */
|
||||
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
|
||||
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
|
||||
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
|
||||
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
|
||||
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
|
||||
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
|
||||
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
|
||||
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
|
||||
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
|
||||
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
|
||||
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
|
||||
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
|
||||
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
|
||||
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
|
||||
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
|
||||
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
|
||||
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
|
||||
|
||||
/* GPIO mode configuration values */
|
||||
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
|
||||
#define GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO pull-up/ pull-down values */
|
||||
#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
|
||||
#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO output speed values */
|
||||
#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
|
||||
#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO output type */
|
||||
#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */
|
||||
#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */
|
||||
|
||||
/* GPIO output max speed level */
|
||||
#define OSPD_OSPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_OSPEED_LEVEL0 OSPD_OSPD(0) /*!< output max speed level 0 */
|
||||
#define GPIO_OSPEED_LEVEL1 OSPD_OSPD(1) /*!< output max speed level 1 */
|
||||
#define GPIO_OSPEED_LEVEL2 OSPD_OSPD(2) /*!< output max speed level 2 */
|
||||
#define GPIO_OSPEED_LEVEL3 OSPD_OSPD(3) /*!< output max speed level 3 */
|
||||
|
||||
/* GPIO output max speed value */
|
||||
#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */
|
||||
#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */
|
||||
#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */
|
||||
#define GPIO_OSPEED_200MHZ GPIO_OSPEED_LEVEL3 /*!< output max speed 200MHz */
|
||||
|
||||
/* GPIO alternate function values */
|
||||
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
|
||||
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
|
||||
|
||||
/* GPIO alternate function */
|
||||
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
|
||||
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
|
||||
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */
|
||||
#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */
|
||||
#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */
|
||||
#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */
|
||||
#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */
|
||||
#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */
|
||||
#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */
|
||||
#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */
|
||||
#define GPIO_AF_10 AF(10) /*!< alternate function 10 selected */
|
||||
#define GPIO_AF_11 AF(11) /*!< alternate function 11 selected */
|
||||
#define GPIO_AF_12 AF(12) /*!< alternate function 12 selected */
|
||||
#define GPIO_AF_13 AF(13) /*!< alternate function 13 selected */
|
||||
#define GPIO_AF_14 AF(14) /*!< alternate function 14 selected */
|
||||
#define GPIO_AF_15 AF(15) /*!< alternate function 15 selected */
|
||||
|
||||
/* function declarations */
|
||||
/* reset GPIO port */
|
||||
void gpio_deinit(uint32_t gpio_periph);
|
||||
/* set GPIO mode */
|
||||
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
|
||||
/* set GPIO output type and speed */
|
||||
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
|
||||
|
||||
/* set GPIO pin bit */
|
||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
|
||||
/* reset GPIO pin bit */
|
||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
|
||||
/* write data to the specified GPIO pin */
|
||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
|
||||
/* write data to the specified GPIO port */
|
||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
|
||||
|
||||
/* get GPIO pin input status */
|
||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port input status */
|
||||
uint16_t gpio_input_port_get(uint32_t gpio_periph);
|
||||
/* get GPIO pin output status */
|
||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port output status */
|
||||
uint16_t gpio_output_port_get(uint32_t gpio_periph);
|
||||
|
||||
/* set GPIO alternate function */
|
||||
void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin);
|
||||
/* lock GPIO pin bit */
|
||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
|
||||
|
||||
/* toggle GPIO pin status */
|
||||
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
|
||||
/* toggle GPIO port status */
|
||||
void gpio_port_toggle(uint32_t gpio_periph);
|
||||
|
||||
#endif /* GD32F4XX_GPIO_H */
|
||||
|
|
@ -0,0 +1,422 @@
|
|||
/*!
|
||||
\file gd32f4xx_i2c.h
|
||||
\brief definitions for the I2C
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2019-04-16, V2.0.1, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F4XX_I2C_H
|
||||
#define GD32F4XX_I2C_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* I2Cx(x=0,1,2) definitions */
|
||||
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
||||
#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */
|
||||
#define I2C2 (I2C_BASE+0x800U) /*!< I2C2 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */
|
||||
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */
|
||||
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0 */
|
||||
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register 1 */
|
||||
#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */
|
||||
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */
|
||||
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */
|
||||
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */
|
||||
#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */
|
||||
#define I2C_FCTL(i2cx) REG32((i2cx) + 0x24U) /*!< I2C filter control register */
|
||||
#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* I2Cx_CTL0 */
|
||||
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
|
||||
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
|
||||
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
|
||||
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
|
||||
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
|
||||
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
|
||||
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
|
||||
#define I2C_CTL0_START BIT(8) /*!< start generation */
|
||||
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
|
||||
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
|
||||
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
|
||||
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
|
||||
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
|
||||
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
|
||||
|
||||
/* I2Cx_CTL1 */
|
||||
#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
|
||||
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
|
||||
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
|
||||
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
|
||||
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
|
||||
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
|
||||
|
||||
/* I2Cx_SADDR0 */
|
||||
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
|
||||
|
||||
/* I2Cx_SADDR1 */
|
||||
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
|
||||
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
|
||||
|
||||
/* I2Cx_DATA */
|
||||
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
|
||||
|
||||
/* I2Cx_STAT0 */
|
||||
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
|
||||
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
|
||||
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
|
||||
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
|
||||
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
|
||||
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
|
||||
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
|
||||
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
|
||||
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
|
||||
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
|
||||
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
|
||||
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
|
||||
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
|
||||
|
||||
/* I2Cx_STAT1 */
|
||||
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
|
||||
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
|
||||
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
|
||||
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
|
||||
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
|
||||
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
|
||||
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
|
||||
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
|
||||
|
||||
/* I2Cx_CKCFG */
|
||||
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */
|
||||
#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */
|
||||
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
|
||||
|
||||
/* I2Cx_RT */
|
||||
#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */
|
||||
|
||||
/* I2Cx_FCTL */
|
||||
#define I2C_FCTL_DF BITS(0,3) /*!< digital noise filter */
|
||||
#define I2C_FCTL_AFD BIT(4) /*!< analog noise filter disable */
|
||||
|
||||
/* I2Cx_SAMCS */
|
||||
#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */
|
||||
#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */
|
||||
#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */
|
||||
#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */
|
||||
#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */
|
||||
#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
|
||||
#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
|
||||
#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
|
||||
#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag, cleared by software write 0 */
|
||||
#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag, cleared by software write 0 */
|
||||
#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */
|
||||
#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */
|
||||
|
||||
/* constants definitions */
|
||||
|
||||
/* the digital noise filter can filter spikes's length */
|
||||
typedef enum {
|
||||
I2C_DF_DISABLE, /*!< disable digital noise filter */
|
||||
I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */
|
||||
I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */
|
||||
I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */
|
||||
I2C_DF_4PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 */
|
||||
I2C_DF_5PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 */
|
||||
I2C_DF_6PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 */
|
||||
I2C_DF_7PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 */
|
||||
I2C_DF_8PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 */
|
||||
I2C_DF_9PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 */
|
||||
I2C_DF_10PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 */
|
||||
I2C_DF_11PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 */
|
||||
I2C_DF_12PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 */
|
||||
I2C_DF_13PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 */
|
||||
I2C_DF_14PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 */
|
||||
I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */
|
||||
}i2c_digital_filter_enum;
|
||||
|
||||
/* constants definitions */
|
||||
/* define the I2C bit position and its register index offset */
|
||||
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
|
||||
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
||||
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */
|
||||
#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */
|
||||
#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */
|
||||
#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */
|
||||
|
||||
/* I2C flags */
|
||||
typedef enum
|
||||
{
|
||||
/* flags in STAT0 register */
|
||||
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
||||
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
||||
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
||||
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
||||
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */
|
||||
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
||||
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
||||
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
||||
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
||||
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
||||
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
||||
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
||||
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
||||
/* flags in STAT1 register */
|
||||
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
||||
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
||||
I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
||||
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
||||
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
||||
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
||||
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
||||
/* flags in SAMCS register */
|
||||
I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */
|
||||
I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */
|
||||
I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */
|
||||
I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */
|
||||
}i2c_flag_enum;
|
||||
|
||||
/* I2C interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt flags in CTL1 register */
|
||||
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
||||
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
||||
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
||||
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
||||
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
||||
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
||||
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
||||
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
||||
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
||||
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
|
||||
/* interrupt flags in SAMCS register */
|
||||
I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */
|
||||
I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */
|
||||
I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */
|
||||
I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */
|
||||
}i2c_interrupt_flag_enum;
|
||||
|
||||
/* I2C interrupt enable or disable */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt in CTL1 register */
|
||||
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
|
||||
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
|
||||
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
|
||||
/* interrupt in SAMCS register */
|
||||
I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */
|
||||
I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */
|
||||
I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */
|
||||
I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */
|
||||
}i2c_interrupt_enum;
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
||||
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
|
||||
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
|
||||
|
||||
/* I2C transfer direction */
|
||||
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
|
||||
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
|
||||
|
||||
/* whether or not to send an ACK */
|
||||
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
||||
#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */
|
||||
|
||||
/* I2C POAP position*/
|
||||
#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
||||
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
||||
|
||||
/* I2C dual-address mode switch */
|
||||
#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */
|
||||
#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */
|
||||
|
||||
/* whether or not to stretch SCL low */
|
||||
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */
|
||||
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */
|
||||
|
||||
/* whether or not to response to a general call */
|
||||
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
||||
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
||||
|
||||
/* software reset I2C */
|
||||
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
||||
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
||||
|
||||
/* I2C DMA mode configure */
|
||||
/* DMA mode switch */
|
||||
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
|
||||
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
|
||||
|
||||
/* flag indicating DMA last transfer */
|
||||
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
||||
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
||||
|
||||
/* I2C PEC configure */
|
||||
/* PEC enable */
|
||||
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
||||
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
||||
|
||||
/* PEC transfer */
|
||||
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
|
||||
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
||||
|
||||
/* I2C SMBus configure */
|
||||
/* issue or not alert through SMBA pin */
|
||||
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
||||
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
||||
|
||||
/* ARP protocol in SMBus switch */
|
||||
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */
|
||||
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */
|
||||
|
||||
/* transmit I2C data */
|
||||
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* receive I2C data */
|
||||
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
||||
|
||||
/* I2C duty cycle in fast mode */
|
||||
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */
|
||||
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
||||
|
||||
/* address mode for the I2C slave */
|
||||
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
|
||||
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */
|
||||
|
||||
/* function declarations */
|
||||
/* reset I2C */
|
||||
void i2c_deinit(uint32_t i2c_periph);
|
||||
/* configure I2C clock */
|
||||
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
||||
/* configure I2C address */
|
||||
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
|
||||
/* SMBus type selection */
|
||||
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
||||
/* whether or not to send an ACK */
|
||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
||||
/* configure I2C POAP position */
|
||||
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
|
||||
/* master sends slave address */
|
||||
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
|
||||
/* enable dual-address mode */
|
||||
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
|
||||
/* disable dual-address mode */
|
||||
void i2c_dualaddr_disable(uint32_t i2c_periph);
|
||||
/* enable I2C */
|
||||
void i2c_enable(uint32_t i2c_periph);
|
||||
/* disable I2C */
|
||||
void i2c_disable(uint32_t i2c_periph);
|
||||
|
||||
/* generate a START condition on I2C bus */
|
||||
void i2c_start_on_bus(uint32_t i2c_periph);
|
||||
/* generate a STOP condition on I2C bus */
|
||||
void i2c_stop_on_bus(uint32_t i2c_periph);
|
||||
/* I2C transmit data function */
|
||||
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
||||
/* I2C receive data function */
|
||||
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
||||
/* enable I2C DMA mode */
|
||||
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
|
||||
/* configure whether next DMA EOT is DMA last transfer or not */
|
||||
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
||||
/* whether to stretch SCL low when data is not ready in slave mode */
|
||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
||||
/* whether or not to response to a general call */
|
||||
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
||||
/* software reset I2C */
|
||||
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
||||
|
||||
/* I2C PEC calculation on or off */
|
||||
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
|
||||
/* I2C whether to transfer PEC value */
|
||||
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
|
||||
/* packet error checking value */
|
||||
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
||||
/* I2C issue alert through SMBA pin */
|
||||
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
|
||||
/* I2C ARP protocol in SMBus switch */
|
||||
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
|
||||
|
||||
/* I2C analog noise filter disable */
|
||||
void i2c_analog_noise_filter_disable(uint32_t i2c_periph);
|
||||
/* I2C analog noise filter enable */
|
||||
void i2c_analog_noise_filter_enable(uint32_t i2c_periph);
|
||||
/* digital noise filter */
|
||||
void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara);
|
||||
|
||||
/* enable SAM_V interface */
|
||||
void i2c_sam_enable(uint32_t i2c_periph);
|
||||
/* disable SAM_V interface */
|
||||
void i2c_sam_disable(uint32_t i2c_periph);
|
||||
/* enable SAM_V interface timeout detect */
|
||||
void i2c_sam_timeout_enable(uint32_t i2c_periph);
|
||||
/* disable SAM_V interface timeout detect */
|
||||
void i2c_sam_timeout_disable(uint32_t i2c_periph);
|
||||
|
||||
/* check I2C flag is set or not */
|
||||
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* clear I2C flag */
|
||||
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* enable I2C interrupt */
|
||||
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* disable I2C interrupt */
|
||||
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* check I2C interrupt flag */
|
||||
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
/* clear I2C interrupt flag */
|
||||
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
|
||||
#endif /* GD32F4XX_I2C_H */
|
||||
|
|
@ -0,0 +1,384 @@
|
|||
/*!
|
||||
\file gd32f4xx_ipa.h
|
||||
\brief definitions for the IPA
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_IPA_H
|
||||
#define GD32F4XX_IPA_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* TLI definitions */
|
||||
#define IPA IPA_BASE /*!< IPA base address */
|
||||
|
||||
/* bits definitions */
|
||||
/* registers definitions */
|
||||
#define IPA_CTL REG32(IPA + 0x00U) /*!< IPA control register */
|
||||
#define IPA_INTF REG32(IPA + 0x04U) /*!< IPA interrupt flag register */
|
||||
#define IPA_INTC REG32(IPA + 0x08U) /*!< IPA interrupt flag clear register */
|
||||
#define IPA_FMADDR REG32(IPA + 0x0CU) /*!< IPA foreground memory base address register */
|
||||
#define IPA_FLOFF REG32(IPA + 0x10U) /*!< IPA foreground line offset register */
|
||||
#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */
|
||||
#define IPA_BLOFF REG32(IPA + 0x18U) /*!< IPA background line offset register */
|
||||
#define IPA_FPCTL REG32(IPA + 0x1CU) /*!< IPA foreground pixel control register */
|
||||
#define IPA_FPV REG32(IPA + 0x20U) /*!< IPA foreground pixel value register */
|
||||
#define IPA_BPCTL REG32(IPA + 0x24U) /*!< IPA background pixel control register */
|
||||
#define IPA_BPV REG32(IPA + 0x28U) /*!< IPA background pixel value register */
|
||||
#define IPA_FLMADDR REG32(IPA + 0x2CU) /*!< IPA foreground LUT memory base address register */
|
||||
#define IPA_BLMADDR REG32(IPA + 0x30U) /*!< IPA background LUT memory base address register */
|
||||
#define IPA_DPCTL REG32(IPA + 0x34U) /*!< IPA destination pixel control register */
|
||||
#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */
|
||||
#define IPA_DMADDR REG32(IPA + 0x3CU) /*!< IPA destination memory base address register */
|
||||
#define IPA_DLOFF REG32(IPA + 0x40U) /*!< IPA destination line offset register */
|
||||
#define IPA_IMS REG32(IPA + 0x44U) /*!< IPA image size register */
|
||||
#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */
|
||||
#define IPA_ITCTL REG32(IPA + 0x4CU) /*!< IPA inter-timer control register */
|
||||
|
||||
/* IPA_CTL */
|
||||
#define IPA_CTL_TEN BIT(0) /*!< transfer enable */
|
||||
#define IPA_CTL_THU BIT(1) /*!< transfer hang up */
|
||||
#define IPA_CTL_TST BIT(2) /*!< transfer stop */
|
||||
#define IPA_CTL_TAEIE BIT(8) /*!< enable bit for transfer access error interrupt */
|
||||
#define IPA_CTL_FTFIE BIT(9) /*!< enable bit for full transfer finish interrup */
|
||||
#define IPA_CTL_TLMIE BIT(10) /*!< enable bit for transfer line mark interrupt */
|
||||
#define IPA_CTL_LACIE BIT(11) /*!< enable bit for LUT access conflict interrupt */
|
||||
#define IPA_CTL_LLFIE BIT(12) /*!< enable bit for LUT loading finish interrupt */
|
||||
#define IPA_CTL_WCFIE BIT(13) /*!< enable bit for wrong configuration interrupt */
|
||||
#define IPA_CTL_PFCM BITS(16,17) /*!< pixel format convert mode */
|
||||
|
||||
/* IPA_INTF */
|
||||
#define IPA_INTF_TAEIF BIT(0) /*!< transfer access error interrupt flag */
|
||||
#define IPA_INTF_FTFIF BIT(1) /*!< full transfer finish interrupt flag */
|
||||
#define IPA_INTF_TLMIF BIT(2) /*!< transfer line mark interrupt flag */
|
||||
#define IPA_INTF_LACIF BIT(3) /*!< LUT access conflict interrupt flag */
|
||||
#define IPA_INTF_LLFIF BIT(4) /*!< LUT loading finish interrupt flag */
|
||||
#define IPA_INTF_WCFIF BIT(5) /*!< wrong configuration interrupt flag */
|
||||
|
||||
/* IPA_INTC */
|
||||
#define IPA_INTC_TAEIFC BIT(0) /*!< clear bit for transfer access error interrupt flag */
|
||||
#define IPA_INTC_FTFIFC BIT(1) /*!< clear bit for full transfer finish interrupt flag */
|
||||
#define IPA_INTC_TLMIFC BIT(2) /*!< clear bit for transfer line mark interrupt flag */
|
||||
#define IPA_INTC_LACIFC BIT(3) /*!< clear bit for LUT access conflict interrupt flag */
|
||||
#define IPA_INTC_LLFIFC BIT(4) /*!< clear bit for LUT loading finish interrupt flag */
|
||||
#define IPA_INTC_WCFIFC BIT(5) /*!< clear bit for wrong configuration interrupt flag */
|
||||
|
||||
/* IPA_FMADDR */
|
||||
#define IPA_FMADDR_FMADDR BITS(0,31) /*!< foreground memory base address */
|
||||
|
||||
/* IPA_FLOFF */
|
||||
#define IPA_FLOFF_FLOFF BITS(0,13) /*!< foreground line offset */
|
||||
|
||||
/* IPA_BMADDR */
|
||||
#define IPA_BMADDR_BMADDR BITS(0,31) /*!< background memory base address */
|
||||
|
||||
/* IPA_BLOFF */
|
||||
#define IPA_BLOFF_BLOFF BITS(0,13) /*!< background line offset */
|
||||
|
||||
/* IPA_FPCTL */
|
||||
#define IPA_FPCTL_FPF BITS(0,3) /*!< foreground pixel format */
|
||||
#define IPA_FPCTL_FLPF BIT(4) /*!< foreground LUT pixel format */
|
||||
#define IPA_FPCTL_FLLEN BIT(5) /*!< foreground LUT loading enable */
|
||||
#define IPA_FPCTL_FCNP BITS(8,15) /*!< foreground LUT number of pixel */
|
||||
#define IPA_FPCTL_FAVCA BITS(16,17) /*!< foreground alpha value calculation algorithm */
|
||||
#define IPA_FPCTL_FPDAV BITS(24,31) /*!< foreground pre- defined alpha value */
|
||||
|
||||
/* IPA_FPV */
|
||||
#define IPA_FPV_FPDBV BITS(0,7) /*!< foreground pre-defined red value */
|
||||
#define IPA_FPV_FPDGV BITS(8,15) /*!< foreground pre-defined green value */
|
||||
#define IPA_FPV_FPDRV BITS(16,23) /*!< foreground pre-defined red value */
|
||||
|
||||
/* IPA_BPCTL */
|
||||
#define IPA_BPCTL_BPF BITS(0,3) /*!< background pixel format */
|
||||
#define IPA_BPCTL_BLPF BIT(4) /*!< background LUT pixel format */
|
||||
#define IPA_BPCTL_BLLEN BIT(5) /*!< background LUT loading enable */
|
||||
#define IPA_BPCTL_BCNP BITS(8,15) /*!< background LUT number of pixel */
|
||||
#define IPA_BPCTL_BAVCA BITS(16,17) /*!< background alpha value calculation algorithm */
|
||||
#define IPA_BPCTL_BPDAV BITS(24,31) /*!< background pre- defined alpha value */
|
||||
|
||||
/* IPA_BPV */
|
||||
#define IPA_BPV_BPDBV BITS(0,7) /*!< background pre-defined blue value */
|
||||
#define IPA_BPV_BPDGV BITS(8,15) /*!< background pre-defined green value */
|
||||
#define IPA_BPV_BPDRV BITS(16,23) /*!< background pre-defined red value */
|
||||
|
||||
/* IPA_FLMADDR */
|
||||
#define IPA_FLMADDR_FLMADDR BITS(0,31) /*!< foreground LUT memory base address */
|
||||
|
||||
/* IPA_BLMADDR */
|
||||
#define IPA_BLMADDR_BLMADDR BITS(0,31) /*!< background LUT memory base address */
|
||||
|
||||
/* IPA_DPCTL */
|
||||
#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */
|
||||
|
||||
/* IPA_DPV */
|
||||
/* destination pixel format ARGB8888 */
|
||||
#define IPA_DPV_DPDBV_0 BITS(0,7) /*!< destination pre-defined blue value */
|
||||
#define IPA_DPV_DPDGV_0 BITS(8,15) /*!< destination pre-defined green value */
|
||||
#define IPA_DPV_DPDRV_0 BITS(16,23) /*!< destination pre-defined red value */
|
||||
#define IPA_DPV_DPDAV_0 BITS(24,31) /*!< destination pre-defined alpha value */
|
||||
|
||||
/* destination pixel format RGB8888 */
|
||||
#define IPA_DPV_DPDBV_1 BITS(0,7) /*!< destination pre-defined blue value */
|
||||
#define IPA_DPV_DPDGV_1 BITS(8,15) /*!< destination pre-defined green value */
|
||||
#define IPA_DPV_DPDRV_1 BITS(16,23) /*!< destination pre-defined red value */
|
||||
|
||||
/* destination pixel format RGB565 */
|
||||
#define IPA_DPV_DPDBV_2 BITS(0,4) /*!< destination pre-defined blue value */
|
||||
#define IPA_DPV_DPDGV_2 BITS(5,10) /*!< destination pre-defined green value */
|
||||
#define IPA_DPV_DPDRV_2 BITS(11,15) /*!< destination pre-defined red value */
|
||||
|
||||
/* destination pixel format ARGB1555 */
|
||||
#define IPA_DPV_DPDBV_3 BITS(0,4) /*!< destination pre-defined blue value */
|
||||
#define IPA_DPV_DPDGV_3 BITS(5,9) /*!< destination pre-defined green value */
|
||||
#define IPA_DPV_DPDRV_3 BITS(10,14) /*!< destination pre-defined red value */
|
||||
#define IPA_DPV_DPDAV_3 BIT(15) /*!< destination pre-defined alpha value */
|
||||
|
||||
/* destination pixel format ARGB4444 */
|
||||
#define IPA_DPV_DPDBV_4 BITS(0,3) /*!< destination pre-defined blue value */
|
||||
#define IPA_DPV_DPDGV_4 BITS(4,7) /*!< destination pre-defined green value */
|
||||
#define IPA_DPV_DPDRV_4 BITS(8,11) /*!< destination pre-defined red value */
|
||||
#define IPA_DPV_DPDAV_4 BITS(12,15) /*!< destination pre-defined alpha value */
|
||||
|
||||
/* IPA_DMADDR */
|
||||
#define IPA_DMADDR_DMADDR BITS(0,31) /*!< destination memory base address */
|
||||
|
||||
/* IPA_DLOFF */
|
||||
#define IPA_DLOFF_DLOFF BITS(0,13) /*!< destination line offset */
|
||||
|
||||
/* IPA_IMS */
|
||||
#define IPA_IMS_HEIGHT BITS(0,15) /*!< height of the image to be processed */
|
||||
#define IPA_IMS_WIDTH BITS(16,29) /*!< width of the image to be processed */
|
||||
|
||||
/* IPA_LM */
|
||||
#define IPA_LM_LM BITS(0,15) /*!< line mark */
|
||||
|
||||
/* IPA_ITCTL */
|
||||
#define IPA_ITCTL_ITEN BIT(0) /*!< inter-timer enable */
|
||||
#define IPA_ITCTL_NCCI BITS(8,15) /*!< number of clock cycles interval */
|
||||
|
||||
|
||||
/* constants definitions */
|
||||
/* IPA foreground parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t foreground_memaddr; /*!< foreground memory base address */
|
||||
uint32_t foreground_lineoff; /*!< foreground line offset */
|
||||
uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */
|
||||
uint32_t foreground_alpha_algorithm; /*!< foreground alpha value calculation algorithm */
|
||||
uint32_t foreground_pf; /*!< foreground pixel format */
|
||||
uint32_t foreground_prered; /*!< foreground pre-defined red value */
|
||||
uint32_t foreground_pregreen; /*!< foreground pre-defined green value */
|
||||
uint32_t foreground_preblue; /*!< foreground pre-defined blue value */
|
||||
}ipa_foreground_parameter_struct;
|
||||
|
||||
/* IPA background parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t background_memaddr; /*!< background memory base address */
|
||||
uint32_t background_lineoff; /*!< background line offset */
|
||||
uint32_t background_prealpha; /*!< background pre-defined alpha value */
|
||||
uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */
|
||||
uint32_t background_pf; /*!< background pixel format */
|
||||
uint32_t background_prered; /*!< background pre-defined red value */
|
||||
uint32_t background_pregreen; /*!< background pre-defined green value */
|
||||
uint32_t background_preblue; /*!< background pre-defined blue value */
|
||||
}ipa_background_parameter_struct;
|
||||
|
||||
/* IPA destination parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t destination_memaddr; /*!< destination memory base address */
|
||||
uint32_t destination_lineoff; /*!< destination line offset */
|
||||
uint32_t destination_prealpha; /*!< destination pre-defined alpha value */
|
||||
uint32_t destination_pf; /*!< destination pixel format */
|
||||
uint32_t destination_prered; /*!< destination pre-defined red value */
|
||||
uint32_t destination_pregreen; /*!< destination pre-defined green value */
|
||||
uint32_t destination_preblue; /*!< destination pre-defined blue value */
|
||||
uint32_t image_width; /*!< width of the image to be processed */
|
||||
uint32_t image_height; /*!< height of the image to be processed */
|
||||
}ipa_destination_parameter_struct;
|
||||
|
||||
/* destination pixel format */
|
||||
typedef enum
|
||||
{
|
||||
IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */
|
||||
IPA_DPF_RGB888, /*!< destination pixel format RGB888 */
|
||||
IPA_DPF_RGB565, /*!< destination pixel format RGB565 */
|
||||
IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */
|
||||
IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */
|
||||
} ipa_dpf_enum;
|
||||
|
||||
/* LUT pixel format */
|
||||
#define IPA_LUT_PF_ARGB8888 ((uint8_t)0x00U) /*!< LUT pixel format ARGB8888 */
|
||||
#define IPA_LUT_PF_RGB888 ((uint8_t)0x01U) /*!< LUT pixel format RGB888 */
|
||||
|
||||
/* Inter-timer */
|
||||
#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< inter-timer disable */
|
||||
#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< inter-timer enable */
|
||||
|
||||
/* IPA pixel format convert mode */
|
||||
#define CTL_PFCM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||
#define IPA_FGTODE CTL_PFCM(0) /*!< foreground memory to destination memory without pixel format convert */
|
||||
#define IPA_FGTODE_PF_CONVERT CTL_PFCM(1) /*!< foreground memory to destination memory with pixel format convert */
|
||||
#define IPA_FGBGTODE CTL_PFCM(2) /*!< blending foreground and background memory to destination memory */
|
||||
#define IPA_FILL_UP_DE CTL_PFCM(3) /*!< fill up destination memory with specific color */
|
||||
|
||||
/* foreground alpha value calculation algorithm */
|
||||
#define FPCTL_FAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||
#define IPA_FG_ALPHA_MODE_0 FPCTL_FAVCA(0) /*!< no effect */
|
||||
#define IPA_FG_ALPHA_MODE_1 FPCTL_FAVCA(1) /*!< FPDAV[7:0] is selected as the foreground alpha value */
|
||||
#define IPA_FG_ALPHA_MODE_2 FPCTL_FAVCA(2) /*!< FPDAV[7:0] multiplied by read alpha value */
|
||||
|
||||
/* background alpha value calculation algorithm */
|
||||
#define BPCTL_BAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||
#define IPA_BG_ALPHA_MODE_0 BPCTL_BAVCA(0) /*!< no effect */
|
||||
#define IPA_BG_ALPHA_MODE_1 BPCTL_BAVCA(1) /*!< BPDAV[7:0] is selected as the background alpha value */
|
||||
#define IPA_BG_ALPHA_MODE_2 BPCTL_BAVCA(2) /*!< BPDAV[7:0] multiplied by read alpha value */
|
||||
|
||||
/* foreground pixel format */
|
||||
#define FPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval)))
|
||||
#define FOREGROUND_PPF_ARGB8888 FPCTL_PPF(0) /*!< foreground pixel format ARGB8888 */
|
||||
#define FOREGROUND_PPF_RGB888 FPCTL_PPF(1) /*!< foreground pixel format RGB888 */
|
||||
#define FOREGROUND_PPF_RGB565 FPCTL_PPF(2) /*!< foreground pixel format RGB565 */
|
||||
#define FOREGROUND_PPF_ARG1555 FPCTL_PPF(3) /*!< foreground pixel format ARGB1555 */
|
||||
#define FOREGROUND_PPF_ARGB4444 FPCTL_PPF(4) /*!< foreground pixel format ARGB4444 */
|
||||
#define FOREGROUND_PPF_L8 FPCTL_PPF(5) /*!< foreground pixel format L8 */
|
||||
#define FOREGROUND_PPF_AL44 FPCTL_PPF(6) /*!< foreground pixel format AL44 */
|
||||
#define FOREGROUND_PPF_AL88 FPCTL_PPF(7) /*!< foreground pixel format AL88 */
|
||||
#define FOREGROUND_PPF_L4 FPCTL_PPF(8) /*!< foreground pixel format L4 */
|
||||
#define FOREGROUND_PPF_A8 FPCTL_PPF(9) /*!< foreground pixel format A8 */
|
||||
#define FOREGROUND_PPF_A4 FPCTL_PPF(10) /*!< foreground pixel format A4 */
|
||||
|
||||
/* background pixel format */
|
||||
#define BPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval)))
|
||||
#define BACKGROUND_PPF_ARGB8888 BPCTL_PPF(0) /*!< background pixel format ARGB8888 */
|
||||
#define BACKGROUND_PPF_RGB888 BPCTL_PPF(1) /*!< background pixel format RGB888 */
|
||||
#define BACKGROUND_PPF_RGB565 BPCTL_PPF(2) /*!< background pixel format RGB565 */
|
||||
#define BACKGROUND_PPF_ARG1555 BPCTL_PPF(3) /*!< background pixel format ARGB1555 */
|
||||
#define BACKGROUND_PPF_ARGB4444 BPCTL_PPF(4) /*!< background pixel format ARGB4444 */
|
||||
#define BACKGROUND_PPF_L8 BPCTL_PPF(5) /*!< background pixel format L8 */
|
||||
#define BACKGROUND_PPF_AL44 BPCTL_PPF(6) /*!< background pixel format AL44 */
|
||||
#define BACKGROUND_PPF_AL88 BPCTL_PPF(7) /*!< background pixel format AL88 */
|
||||
#define BACKGROUND_PPF_L4 BPCTL_PPF(8) /*!< background pixel format L4 */
|
||||
#define BACKGROUND_PPF_A8 BPCTL_PPF(9) /*!< background pixel format A8 */
|
||||
#define BACKGROUND_PPF_A4 BPCTL_PPF(10) /*!< background pixel format A4 */
|
||||
|
||||
/* IPA flags */
|
||||
#define IPA_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */
|
||||
#define IPA_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */
|
||||
#define IPA_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */
|
||||
#define IPA_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */
|
||||
#define IPA_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */
|
||||
#define IPA_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */
|
||||
|
||||
/* IPA interrupt enable or disable */
|
||||
#define IPA_INT_TAE IPA_CTL_TAEIE /*!< transfer access error interrupt */
|
||||
#define IPA_INT_FTF IPA_CTL_FTFIE /*!< full transfer finish interrupt */
|
||||
#define IPA_INT_TLM IPA_CTL_TLMIE /*!< transfer line mark interrupt */
|
||||
#define IPA_INT_LAC IPA_CTL_LACIE /*!< LUT access conflict interrupt */
|
||||
#define IPA_INT_LLF IPA_CTL_LLFIE /*!< LUT loading finish interrupt */
|
||||
#define IPA_INT_WCF IPA_CTL_WCFIE /*!< wrong configuration interrupt */
|
||||
|
||||
/* IPA interrupt flags */
|
||||
#define IPA_INT_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */
|
||||
#define IPA_INT_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */
|
||||
#define IPA_INT_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */
|
||||
#define IPA_INT_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */
|
||||
#define IPA_INT_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */
|
||||
#define IPA_INT_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */
|
||||
|
||||
/* function declarations */
|
||||
/* functions enable or disable, pixel format convert mode set */
|
||||
/* deinitialize IPA */
|
||||
void ipa_deinit(void);
|
||||
/* enable IPA transfer */
|
||||
void ipa_transfer_enable(void);
|
||||
/* enable IPA transfer hang up */
|
||||
void ipa_transfer_hangup_enable(void);
|
||||
/* disable IPA transfer hang up */
|
||||
void ipa_transfer_hangup_disable(void);
|
||||
/* enable IPA transfer stop */
|
||||
void ipa_transfer_stop_enable(void);
|
||||
/* disable IPA transfer stop */
|
||||
void ipa_transfer_stop_disable(void);
|
||||
/* enable IPA foreground LUT loading */
|
||||
void ipa_foreground_lut_loading_enable(void);
|
||||
/* enable IPA background LUT loading */
|
||||
void ipa_background_lut_loading_enable(void);
|
||||
/* set pixel format convert mode, the function is invalid when the IPA transfer is enabled */
|
||||
void ipa_pixel_format_convert_mode_set(uint32_t pfcm);
|
||||
|
||||
/* structure initialization, foreground, background, destination and LUT initialization */
|
||||
/* initialize the structure of IPA foreground parameter struct with the default values, it is
|
||||
suggested that call this function after an ipa_foreground_parameter_struct structure is defined */
|
||||
void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct);
|
||||
/* initialize foreground parameters */
|
||||
void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct);
|
||||
/* initialize the structure of IPA background parameter struct with the default values, it is
|
||||
suggested that call this function after an ipa_background_parameter_struct structure is defined */
|
||||
void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct);
|
||||
/* initialize background parameters */
|
||||
void ipa_background_init(ipa_background_parameter_struct* background_struct);
|
||||
/* initialize the structure of IPA destination parameter struct with the default values, it is
|
||||
suggested that call this function after an ipa_destination_parameter_struct structure is defined */
|
||||
void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct);
|
||||
/* initialize destination parameters */
|
||||
void ipa_destination_init(ipa_destination_parameter_struct* destination_struct);
|
||||
/* initialize IPA foreground LUT parameters */
|
||||
void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr);
|
||||
/* initialize IPA background LUT parameters */
|
||||
void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr);
|
||||
|
||||
/* configuration functions */
|
||||
/* configure IPA line mark */
|
||||
void ipa_line_mark_config(uint16_t line_num);
|
||||
/* inter-timer enable or disable */
|
||||
void ipa_inter_timer_config(uint8_t timer_cfg);
|
||||
/* configure the number of clock cycles interval */
|
||||
void ipa_interval_clock_num_config(uint8_t clk_num);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* get IPA flag status in IPA_INTF register */
|
||||
FlagStatus ipa_flag_get(uint32_t flag);
|
||||
/* clear IPA flag in IPA_INTF register */
|
||||
void ipa_flag_clear(uint32_t flag);
|
||||
/* enable IPA interrupt */
|
||||
void ipa_interrupt_enable(uint32_t int_flag);
|
||||
/* disable IPA interrupt */
|
||||
void ipa_interrupt_disable(uint32_t int_flag);
|
||||
/* get IPA interrupt flag */
|
||||
FlagStatus ipa_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear IPA interrupt flag */
|
||||
void ipa_interrupt_flag_clear(uint32_t int_flag);
|
||||
|
||||
#endif /* GD32F4XX_IPA_H */
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
/*!
|
||||
\file gd32f4xx_iref.h
|
||||
\brief definitions for the IREF
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_IREF_H
|
||||
#define GD32F4XX_IREF_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* IREF definitions */
|
||||
#define IREF IREF_BASE /*!< IREF base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define IREF_CTL REG32(IREF + 0x300U) /*!< IREF control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* IREF_CTL */
|
||||
#define IREF_CTL_CSDT BITS(0,5) /*!< current step data */
|
||||
#define IREF_CTL_SCMOD BIT(7) /*!< sink current mode */
|
||||
#define IREF_CTL_CPT BITS(8,12) /*!< current precision trim */
|
||||
#define IREF_CTL_SSEL BIT(14) /*!< step selection */
|
||||
#define IREF_CTL_CREN BIT(15) /*!< current reference enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* IREF current precision trim */
|
||||
#define CTL_CPT(regval) (BITS(8,12) & ((uint32_t)(regval) << 8))
|
||||
#define IREF_CUR_PRECISION_TRIM_0 CTL_CPT(0) /*!< IREF current precision trim 0 */
|
||||
#define IREF_CUR_PRECISION_TRIM_1 CTL_CPT(1) /*!< IREF current precision trim 1 */
|
||||
#define IREF_CUR_PRECISION_TRIM_2 CTL_CPT(2) /*!< IREF current precision trim 2 */
|
||||
#define IREF_CUR_PRECISION_TRIM_3 CTL_CPT(3) /*!< IREF current precision trim 3 */
|
||||
#define IREF_CUR_PRECISION_TRIM_4 CTL_CPT(4) /*!< IREF current precision trim 4 */
|
||||
#define IREF_CUR_PRECISION_TRIM_5 CTL_CPT(5) /*!< IREF current precision trim 5 */
|
||||
#define IREF_CUR_PRECISION_TRIM_6 CTL_CPT(6) /*!< IREF current precision trim 6 */
|
||||
#define IREF_CUR_PRECISION_TRIM_7 CTL_CPT(7) /*!< IREF current precision trim 7 */
|
||||
#define IREF_CUR_PRECISION_TRIM_8 CTL_CPT(8) /*!< IREF current precision trim 8 */
|
||||
#define IREF_CUR_PRECISION_TRIM_9 CTL_CPT(9) /*!< IREF current precision trim 9 */
|
||||
#define IREF_CUR_PRECISION_TRIM_10 CTL_CPT(10) /*!< IREF current precision trim 10 */
|
||||
#define IREF_CUR_PRECISION_TRIM_11 CTL_CPT(11) /*!< IREF current precision trim 11 */
|
||||
#define IREF_CUR_PRECISION_TRIM_12 CTL_CPT(12) /*!< IREF current precision trim 12 */
|
||||
#define IREF_CUR_PRECISION_TRIM_13 CTL_CPT(13) /*!< IREF current precision trim 13 */
|
||||
#define IREF_CUR_PRECISION_TRIM_14 CTL_CPT(14) /*!< IREF current precision trim 14 */
|
||||
#define IREF_CUR_PRECISION_TRIM_15 CTL_CPT(15) /*!< IREF current precision trim 15 */
|
||||
#define IREF_CUR_PRECISION_TRIM_16 CTL_CPT(16) /*!< IREF current precision trim 16 */
|
||||
#define IREF_CUR_PRECISION_TRIM_17 CTL_CPT(17) /*!< IREF current precision trim 17 */
|
||||
#define IREF_CUR_PRECISION_TRIM_18 CTL_CPT(18) /*!< IREF current precision trim 18 */
|
||||
#define IREF_CUR_PRECISION_TRIM_19 CTL_CPT(19) /*!< IREF current precision trim 19 */
|
||||
#define IREF_CUR_PRECISION_TRIM_20 CTL_CPT(20) /*!< IREF current precision trim 20 */
|
||||
#define IREF_CUR_PRECISION_TRIM_21 CTL_CPT(21) /*!< IREF current precision trim 21 */
|
||||
#define IREF_CUR_PRECISION_TRIM_22 CTL_CPT(22) /*!< IREF current precision trim 22 */
|
||||
#define IREF_CUR_PRECISION_TRIM_23 CTL_CPT(23) /*!< IREF current precision trim 23 */
|
||||
#define IREF_CUR_PRECISION_TRIM_24 CTL_CPT(24) /*!< IREF current precision trim 24 */
|
||||
#define IREF_CUR_PRECISION_TRIM_25 CTL_CPT(25) /*!< IREF current precision trim 25 */
|
||||
#define IREF_CUR_PRECISION_TRIM_26 CTL_CPT(26) /*!< IREF current precision trim 26 */
|
||||
#define IREF_CUR_PRECISION_TRIM_27 CTL_CPT(27) /*!< IREF current precision trim 27 */
|
||||
#define IREF_CUR_PRECISION_TRIM_28 CTL_CPT(28) /*!< IREF current precision trim 28 */
|
||||
#define IREF_CUR_PRECISION_TRIM_29 CTL_CPT(29) /*!< IREF current precision trim 29 */
|
||||
#define IREF_CUR_PRECISION_TRIM_30 CTL_CPT(30) /*!< IREF current precision trim 30 */
|
||||
#define IREF_CUR_PRECISION_TRIM_31 CTL_CPT(31) /*!< IREF current precision trim 31 */
|
||||
|
||||
/* IREF current step */
|
||||
#define CTL_CSDT(regval) (BITS(0,5) & ((uint32_t)(regval) << 0))
|
||||
#define IREF_CUR_STEP_DATA_0 CTL_CSDT(0) /*!< IREF current step data 0 */
|
||||
#define IREF_CUR_STEP_DATA_1 CTL_CSDT(1) /*!< IREF current step data 1 */
|
||||
#define IREF_CUR_STEP_DATA_2 CTL_CSDT(2) /*!< IREF current step data 2 */
|
||||
#define IREF_CUR_STEP_DATA_3 CTL_CSDT(3) /*!< IREF current step data 3 */
|
||||
#define IREF_CUR_STEP_DATA_4 CTL_CSDT(4) /*!< IREF current step data 4 */
|
||||
#define IREF_CUR_STEP_DATA_5 CTL_CSDT(5) /*!< IREF current step data 5 */
|
||||
#define IREF_CUR_STEP_DATA_6 CTL_CSDT(6) /*!< IREF current step data 6 */
|
||||
#define IREF_CUR_STEP_DATA_7 CTL_CSDT(7) /*!< IREF current step data 7 */
|
||||
#define IREF_CUR_STEP_DATA_8 CTL_CSDT(8) /*!< IREF current step data 8 */
|
||||
#define IREF_CUR_STEP_DATA_9 CTL_CSDT(9) /*!< IREF current step data 9 */
|
||||
#define IREF_CUR_STEP_DATA_10 CTL_CSDT(10) /*!< IREF current step data 10 */
|
||||
#define IREF_CUR_STEP_DATA_11 CTL_CSDT(11) /*!< IREF current step data 11 */
|
||||
#define IREF_CUR_STEP_DATA_12 CTL_CSDT(12) /*!< IREF current step data 12 */
|
||||
#define IREF_CUR_STEP_DATA_13 CTL_CSDT(13) /*!< IREF current step data 13 */
|
||||
#define IREF_CUR_STEP_DATA_14 CTL_CSDT(14) /*!< IREF current step data 14 */
|
||||
#define IREF_CUR_STEP_DATA_15 CTL_CSDT(15) /*!< IREF current step data 15 */
|
||||
#define IREF_CUR_STEP_DATA_16 CTL_CSDT(16) /*!< IREF current step data 16 */
|
||||
#define IREF_CUR_STEP_DATA_17 CTL_CSDT(17) /*!< IREF current step data 17 */
|
||||
#define IREF_CUR_STEP_DATA_18 CTL_CSDT(18) /*!< IREF current step data 18 */
|
||||
#define IREF_CUR_STEP_DATA_19 CTL_CSDT(19) /*!< IREF current step data 19 */
|
||||
#define IREF_CUR_STEP_DATA_20 CTL_CSDT(20) /*!< IREF current step data 20 */
|
||||
#define IREF_CUR_STEP_DATA_21 CTL_CSDT(21) /*!< IREF current step data 21 */
|
||||
#define IREF_CUR_STEP_DATA_22 CTL_CSDT(22) /*!< IREF current step data 22 */
|
||||
#define IREF_CUR_STEP_DATA_23 CTL_CSDT(23) /*!< IREF current step data 23 */
|
||||
#define IREF_CUR_STEP_DATA_24 CTL_CSDT(24) /*!< IREF current step data 24 */
|
||||
#define IREF_CUR_STEP_DATA_25 CTL_CSDT(25) /*!< IREF current step data 25 */
|
||||
#define IREF_CUR_STEP_DATA_26 CTL_CSDT(26) /*!< IREF current step data 26 */
|
||||
#define IREF_CUR_STEP_DATA_27 CTL_CSDT(27) /*!< IREF current step data 27 */
|
||||
#define IREF_CUR_STEP_DATA_28 CTL_CSDT(28) /*!< IREF current step data 28 */
|
||||
#define IREF_CUR_STEP_DATA_29 CTL_CSDT(29) /*!< IREF current step data 29 */
|
||||
#define IREF_CUR_STEP_DATA_30 CTL_CSDT(30) /*!< IREF current step data 30 */
|
||||
#define IREF_CUR_STEP_DATA_31 CTL_CSDT(31) /*!< IREF current step data 31 */
|
||||
#define IREF_CUR_STEP_DATA_32 CTL_CSDT(32) /*!< IREF current step data 32 */
|
||||
#define IREF_CUR_STEP_DATA_33 CTL_CSDT(33) /*!< IREF current step data 33 */
|
||||
#define IREF_CUR_STEP_DATA_34 CTL_CSDT(34) /*!< IREF current step data 34 */
|
||||
#define IREF_CUR_STEP_DATA_35 CTL_CSDT(35) /*!< IREF current step data 35 */
|
||||
#define IREF_CUR_STEP_DATA_36 CTL_CSDT(36) /*!< IREF current step data 36 */
|
||||
#define IREF_CUR_STEP_DATA_37 CTL_CSDT(37) /*!< IREF current step data 37 */
|
||||
#define IREF_CUR_STEP_DATA_38 CTL_CSDT(38) /*!< IREF current step data 38 */
|
||||
#define IREF_CUR_STEP_DATA_39 CTL_CSDT(39) /*!< IREF current step data 39 */
|
||||
#define IREF_CUR_STEP_DATA_40 CTL_CSDT(40) /*!< IREF current step data 40 */
|
||||
#define IREF_CUR_STEP_DATA_41 CTL_CSDT(41) /*!< IREF current step data 41 */
|
||||
#define IREF_CUR_STEP_DATA_42 CTL_CSDT(42) /*!< IREF current step data 42 */
|
||||
#define IREF_CUR_STEP_DATA_43 CTL_CSDT(43) /*!< IREF current step data 43 */
|
||||
#define IREF_CUR_STEP_DATA_44 CTL_CSDT(44) /*!< IREF current step data 44 */
|
||||
#define IREF_CUR_STEP_DATA_45 CTL_CSDT(45) /*!< IREF current step data 45 */
|
||||
#define IREF_CUR_STEP_DATA_46 CTL_CSDT(46) /*!< IREF current step data 46 */
|
||||
#define IREF_CUR_STEP_DATA_47 CTL_CSDT(47) /*!< IREF current step data 47 */
|
||||
#define IREF_CUR_STEP_DATA_48 CTL_CSDT(48) /*!< IREF current step data 48 */
|
||||
#define IREF_CUR_STEP_DATA_49 CTL_CSDT(49) /*!< IREF current step data 49 */
|
||||
#define IREF_CUR_STEP_DATA_50 CTL_CSDT(50) /*!< IREF current step data 50 */
|
||||
#define IREF_CUR_STEP_DATA_51 CTL_CSDT(51) /*!< IREF current step data 51 */
|
||||
#define IREF_CUR_STEP_DATA_52 CTL_CSDT(52) /*!< IREF current step data 52 */
|
||||
#define IREF_CUR_STEP_DATA_53 CTL_CSDT(53) /*!< IREF current step data 53 */
|
||||
#define IREF_CUR_STEP_DATA_54 CTL_CSDT(54) /*!< IREF current step data 54 */
|
||||
#define IREF_CUR_STEP_DATA_55 CTL_CSDT(55) /*!< IREF current step data 54 */
|
||||
#define IREF_CUR_STEP_DATA_56 CTL_CSDT(56) /*!< IREF current step data 54 */
|
||||
#define IREF_CUR_STEP_DATA_57 CTL_CSDT(57) /*!< IREF current step data 57 */
|
||||
#define IREF_CUR_STEP_DATA_58 CTL_CSDT(58) /*!< IREF current step data 58 */
|
||||
#define IREF_CUR_STEP_DATA_59 CTL_CSDT(59) /*!< IREF current step data 59 */
|
||||
#define IREF_CUR_STEP_DATA_60 CTL_CSDT(60) /*!< IREF current step data 60 */
|
||||
#define IREF_CUR_STEP_DATA_61 CTL_CSDT(61) /*!< IREF current step data 61 */
|
||||
#define IREF_CUR_STEP_DATA_62 CTL_CSDT(62) /*!< IREF current step data 62 */
|
||||
#define IREF_CUR_STEP_DATA_63 CTL_CSDT(63) /*!< IREF current step data 63 */
|
||||
|
||||
/* IREF mode selection */
|
||||
#define IREF_STEP(regval) (BIT(14) & ((uint32_t)(regval) << 14))
|
||||
#define IREF_MODE_LOW_POWER IREF_STEP(0) /*!< low power, 1uA step */
|
||||
#define IREF_MODE_HIGH_CURRENT IREF_STEP(1) /*!< high current, 8uA step */
|
||||
|
||||
/* IREF sink current mode*/
|
||||
#define IREF_CURRENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
|
||||
#define IREF_SOURCE_CURRENT IREF_CURRENT(0) /*!< IREF source current */
|
||||
#define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit IREF */
|
||||
void iref_deinit(void);
|
||||
/* enable IREF */
|
||||
void iref_enable(void);
|
||||
/* disable IREF */
|
||||
void iref_disable(void);
|
||||
|
||||
/* set IREF mode*/
|
||||
void iref_mode_set(uint32_t step);
|
||||
/* set IREF sink current mode*/
|
||||
void iref_sink_set(uint32_t sinkmode);
|
||||
/* set IREF current precision trim value */
|
||||
void iref_precision_trim_value_set(uint32_t precisiontrim);
|
||||
/* set IREF step data*/
|
||||
void iref_step_data_config(uint32_t stepdata);
|
||||
|
||||
#endif /* GD32F4XX_IREF_H */
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/*!
|
||||
\file gd32f4xx_misc.h
|
||||
\brief definitions for the MISC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_MISC_H
|
||||
#define GD32F4XX_MISC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* constants definitions */
|
||||
/* set the RAM and FLASH base address */
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */
|
||||
|
||||
/* set the NVIC vector table offset mask */
|
||||
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)
|
||||
|
||||
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
|
||||
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
|
||||
/* priority group - define the pre-emption priority and the subpriority */
|
||||
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
|
||||
|
||||
/* choose the method to enter or exit the lowpower mode */
|
||||
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
|
||||
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
|
||||
|
||||
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
|
||||
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
|
||||
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
|
||||
|
||||
/* choose the systick clock source */
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
|
||||
|
||||
/* function declarations */
|
||||
/* set the priority group */
|
||||
void nvic_priority_group_set(uint32_t nvic_prigroup);
|
||||
|
||||
/* enable NVIC request */
|
||||
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
|
||||
/* disable NVIC request */
|
||||
void nvic_irq_disable(uint8_t nvic_irq);
|
||||
|
||||
/* set the NVIC vector table base address */
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
|
||||
|
||||
/* set the state of the low power mode */
|
||||
void system_lowpower_set(uint8_t lowpower_mode);
|
||||
/* reset the state of the low power mode */
|
||||
void system_lowpower_reset(uint8_t lowpower_mode);
|
||||
|
||||
/* set the systick clock source */
|
||||
void systick_clksource_set(uint32_t systick_clksource);
|
||||
|
||||
#endif /* GD32F4XX_MISC_H */
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
/*!
|
||||
\file gd32f4xx_pmu.h
|
||||
\brief definitions for the PMU
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F4XX_PMU_H
|
||||
#define GD32F4XX_PMU_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* PMU definitions */
|
||||
#define PMU PMU_BASE /*!< PMU base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
|
||||
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* PMU_CTL */
|
||||
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||
#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */
|
||||
#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */
|
||||
#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
|
||||
#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */
|
||||
#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */
|
||||
#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */
|
||||
|
||||
/* PMU_CS */
|
||||
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||
#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */
|
||||
#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
|
||||
#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */
|
||||
#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */
|
||||
#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */
|
||||
#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */
|
||||
#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */
|
||||
|
||||
/* constants definitions */
|
||||
/* PMU low voltage detector threshold definitions */
|
||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
|
||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
|
||||
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */
|
||||
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */
|
||||
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */
|
||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
|
||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
|
||||
|
||||
/* PMU LDO output voltage select definitions */
|
||||
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
|
||||
#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */
|
||||
#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */
|
||||
#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */
|
||||
|
||||
/* PMU low-driver mode enable in deep-sleep mode */
|
||||
#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
||||
#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */
|
||||
#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */
|
||||
|
||||
/* PMU high-driver mode switch */
|
||||
#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17))
|
||||
#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */
|
||||
#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */
|
||||
|
||||
/* PMU low-driver mode when use low power LDO */
|
||||
#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10))
|
||||
#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */
|
||||
#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */
|
||||
|
||||
/* PMU low-driver mode when use normal power LDO */
|
||||
#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11))
|
||||
#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */
|
||||
#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
|
||||
|
||||
/* PMU low power mode ready flag definitions */
|
||||
#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
||||
#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */
|
||||
#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */
|
||||
|
||||
/* PMU backup SRAM LDO on or off */
|
||||
#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9))
|
||||
#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */
|
||||
#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */
|
||||
|
||||
/* PMU flag definitions */
|
||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
|
||||
#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */
|
||||
#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */
|
||||
#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */
|
||||
#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */
|
||||
#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */
|
||||
|
||||
/* PMU ldo definitions */
|
||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
|
||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
||||
|
||||
/* PMU flag reset definitions */
|
||||
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
|
||||
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
|
||||
|
||||
/* PMU command constants definitions */
|
||||
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||
|
||||
/* function declarations */
|
||||
/* reset PMU register */
|
||||
void pmu_deinit(void);
|
||||
|
||||
/* select low voltage detector threshold */
|
||||
void pmu_lvd_select(uint32_t lvdt_n);
|
||||
/* LDO output voltage select */
|
||||
void pmu_ldo_output_select(uint32_t ldo_output);
|
||||
/* PMU lvd disable */
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
/* functions of low-driver mode and high-driver mode in deep-sleep mode */
|
||||
/* high-driver mode switch */
|
||||
void pmu_highdriver_switch_select(uint32_t highdr_switch);
|
||||
/* high-driver mode enable */
|
||||
void pmu_highdriver_mode_enable(void);
|
||||
/* high-driver mode disable */
|
||||
void pmu_highdriver_mode_disable(void);
|
||||
/* low-driver mode enable in deep-sleep mode */
|
||||
void pmu_low_driver_mode_enable(uint32_t lowdr_mode);
|
||||
/* in deep-sleep mode, low-driver mode when use low power LDO */
|
||||
void pmu_lowdriver_lowpower_config(uint32_t mode);
|
||||
/* in deep-sleep mode, low-driver mode when use normal power LDO */
|
||||
void pmu_lowdriver_normalpower_config(uint32_t mode);
|
||||
|
||||
/* set PMU mode */
|
||||
/* PMU work at sleep mode */
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||
/* PMU work at deepsleep mode */
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
||||
/* PMU work at standby mode */
|
||||
void pmu_to_standbymode(uint8_t standbymodecmd);
|
||||
/* PMU wakeup pin enable */
|
||||
void pmu_wakeup_pin_enable(void);
|
||||
/* PMU wakeup pin disable */
|
||||
void pmu_wakeup_pin_disable(void);
|
||||
|
||||
/* backup related functions */
|
||||
/* backup SRAM LDO on */
|
||||
void pmu_backup_ldo_config(uint32_t bkp_ldo);
|
||||
/* backup domain write enable */
|
||||
void pmu_backup_write_enable(void);
|
||||
/* backup domain write disable */
|
||||
void pmu_backup_write_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* reset flag bit */
|
||||
void pmu_flag_reset(uint32_t flag_reset);
|
||||
/* get flag status */
|
||||
FlagStatus pmu_flag_get(uint32_t pmu_flag);
|
||||
|
||||
#endif /* GD32F4XX_PMU_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,640 @@
|
|||
/*!
|
||||
\file gd32f4xx_rtc.c
|
||||
\brief definitions for the RTC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F4XX_RTC_H
|
||||
#define GD32F4XX_RTC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* RTC definitions */
|
||||
#define RTC RTC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define RTC_TIME REG32((RTC) + 0x00U) /*!< RTC time of day register */
|
||||
#define RTC_DATE REG32((RTC) + 0x04U) /*!< RTC date register */
|
||||
#define RTC_CTL REG32((RTC) + 0x08U) /*!< RTC control register */
|
||||
#define RTC_STAT REG32((RTC) + 0x0CU) /*!< RTC status register */
|
||||
#define RTC_PSC REG32((RTC) + 0x10U) /*!< RTC time prescaler register */
|
||||
#define RTC_WUT REG32((RTC) + 0x14U) /*!< RTC wakeup timer regiser */
|
||||
#define RTC_COSC REG32((RTC) + 0x18U) /*!< RTC coarse calibration register */
|
||||
#define RTC_ALRM0TD REG32((RTC) + 0x1CU) /*!< RTC alarm 0 time and date register */
|
||||
#define RTC_ALRM1TD REG32((RTC) + 0x20U) /*!< RTC alarm 1 time and date register */
|
||||
#define RTC_WPK REG32((RTC) + 0x24U) /*!< RTC write protection key register */
|
||||
#define RTC_SS REG32((RTC) + 0x28U) /*!< RTC sub second register */
|
||||
#define RTC_SHIFTCTL REG32((RTC) + 0x2CU) /*!< RTC shift function control register */
|
||||
#define RTC_TTS REG32((RTC) + 0x30U) /*!< RTC time of timestamp register */
|
||||
#define RTC_DTS REG32((RTC) + 0x34U) /*!< RTC date of timestamp register */
|
||||
#define RTC_SSTS REG32((RTC) + 0x38U) /*!< RTC sub second of timestamp register */
|
||||
#define RTC_HRFC REG32((RTC) + 0x3CU) /*!< RTC high resolution frequency compensation registor */
|
||||
#define RTC_TAMP REG32((RTC) + 0x40U) /*!< RTC tamper register */
|
||||
#define RTC_ALRM0SS REG32((RTC) + 0x44U) /*!< RTC alarm 0 sub second register */
|
||||
#define RTC_ALRM1SS REG32((RTC) + 0x48U) /*!< RTC alarm 1 sub second register */
|
||||
#define RTC_BKP0 REG32((RTC) + 0x50U) /*!< RTC backup register */
|
||||
#define RTC_BKP1 REG32((RTC) + 0x54U) /*!< RTC backup register */
|
||||
#define RTC_BKP2 REG32((RTC) + 0x58U) /*!< RTC backup register */
|
||||
#define RTC_BKP3 REG32((RTC) + 0x5CU) /*!< RTC backup register */
|
||||
#define RTC_BKP4 REG32((RTC) + 0x60U) /*!< RTC backup register */
|
||||
#define RTC_BKP5 REG32((RTC) + 0x64U) /*!< RTC backup register */
|
||||
#define RTC_BKP6 REG32((RTC) + 0x68U) /*!< RTC backup register */
|
||||
#define RTC_BKP7 REG32((RTC) + 0x6CU) /*!< RTC backup register */
|
||||
#define RTC_BKP8 REG32((RTC) + 0x70U) /*!< RTC backup register */
|
||||
#define RTC_BKP9 REG32((RTC) + 0x74U) /*!< RTC backup register */
|
||||
#define RTC_BKP10 REG32((RTC) + 0x78U) /*!< RTC backup register */
|
||||
#define RTC_BKP11 REG32((RTC) + 0x7CU) /*!< RTC backup register */
|
||||
#define RTC_BKP12 REG32((RTC) + 0x80U) /*!< RTC backup register */
|
||||
#define RTC_BKP13 REG32((RTC) + 0x84U) /*!< RTC backup register */
|
||||
#define RTC_BKP14 REG32((RTC) + 0x88U) /*!< RTC backup register */
|
||||
#define RTC_BKP15 REG32((RTC) + 0x8CU) /*!< RTC backup register */
|
||||
#define RTC_BKP16 REG32((RTC) + 0x90U) /*!< RTC backup register */
|
||||
#define RTC_BKP17 REG32((RTC) + 0x94U) /*!< RTC backup register */
|
||||
#define RTC_BKP18 REG32((RTC) + 0x98U) /*!< RTC backup register */
|
||||
#define RTC_BKP19 REG32((RTC) + 0x9CU) /*!< RTC backup register */
|
||||
|
||||
/* bits definitions */
|
||||
/* RTC_TIME */
|
||||
#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */
|
||||
#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */
|
||||
#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */
|
||||
#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */
|
||||
#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */
|
||||
#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */
|
||||
#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */
|
||||
|
||||
/* RTC_DATE */
|
||||
#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */
|
||||
#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */
|
||||
#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */
|
||||
#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */
|
||||
#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */
|
||||
#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */
|
||||
#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */
|
||||
|
||||
/* RTC_CTL */
|
||||
#define RTC_CTL_WTCS BITS(0,2) /*!< auto wakeup timer clock selection */
|
||||
#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */
|
||||
#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */
|
||||
#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */
|
||||
#define RTC_CTL_CS BIT(6) /*!< display format of clock system */
|
||||
#define RTC_CTL_CCEN BIT(7) /*!< coarse calibration function enable */
|
||||
#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm0 function enable */
|
||||
#define RTC_CTL_ALRM1EN BIT(9) /*!< alarm1 function enable */
|
||||
#define RTC_CTL_WTEN BIT(10) /*!< auto wakeup timer function enable */
|
||||
#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */
|
||||
#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm0 interrupt enable */
|
||||
#define RTC_CTL_ALRM1IE BIT(13) /*!< RTC alarm1 interrupt enable */
|
||||
#define RTC_CTL_WTIE BIT(14) /*!< auto wakeup timer interrupt enable */
|
||||
#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */
|
||||
#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */
|
||||
#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */
|
||||
#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */
|
||||
#define RTC_CTL_COS BIT(19) /*!< calibration output selection */
|
||||
#define RTC_CTL_OPOL BIT(20) /*!< output polarity */
|
||||
#define RTC_CTL_OS BITS(21,22) /*!< output selection */
|
||||
#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */
|
||||
|
||||
/* RTC_STAT */
|
||||
#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm0 configuration can be write flag */
|
||||
#define RTC_STAT_ALRM1WF BIT(1) /*!< alarm1 configuration can be write flag */
|
||||
#define RTC_STAT_WTWF BIT(2) /*!< wakeup timer can be write flag */
|
||||
#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */
|
||||
#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */
|
||||
#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */
|
||||
#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */
|
||||
#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */
|
||||
#define RTC_STAT_ALRM0F BIT(8) /*!< alarm0 occurs flag */
|
||||
#define RTC_STAT_ALRM1F BIT(9) /*!< alarm1 occurs flag */
|
||||
#define RTC_STAT_WTF BIT(10) /*!< wakeup timer occurs flag */
|
||||
#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */
|
||||
#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */
|
||||
#define RTC_STAT_TP0F BIT(13) /*!< RTC tamper 0 detected flag */
|
||||
#define RTC_STAT_TP1F BIT(14) /*!< RTC tamper 1 detected flag */
|
||||
#define RTC_STAT_SCPF BIT(16) /*!< smooth calibration pending flag */
|
||||
|
||||
/* RTC_PSC */
|
||||
#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */
|
||||
#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */
|
||||
|
||||
/* RTC_WUT */
|
||||
#define RTC_WUT_WTRV BITS(0,15) /*!< auto wakeup timer reloads value */
|
||||
|
||||
/* RTC_COSC */
|
||||
#define RTC_COSC_COSS BITS(0,4) /*!< coarse calibration step */
|
||||
#define RTC_COSC_COSD BIT(7) /*!< coarse calibration direction */
|
||||
|
||||
/* RTC_ALRMxTD */
|
||||
#define RTC_ALRMXTD_SCU BITS(0,3) /*!< second units in BCD code */
|
||||
#define RTC_ALRMXTD_SCT BITS(4,6) /*!< second tens in BCD code */
|
||||
#define RTC_ALRMXTD_MSKS BIT(7) /*!< alarm second mask bit */
|
||||
#define RTC_ALRMXTD_MNU BITS(8,11) /*!< minutes units in BCD code */
|
||||
#define RTC_ALRMXTD_MNT BITS(12,14) /*!< minutes tens in BCD code */
|
||||
#define RTC_ALRMXTD_MSKM BIT(15) /*!< alarm minutes mask bit */
|
||||
#define RTC_ALRMXTD_HRU BITS(16,19) /*!< hour units in BCD code */
|
||||
#define RTC_ALRMXTD_HRT BITS(20,21) /*!< hour units in BCD code */
|
||||
#define RTC_ALRMXTD_PM BIT(22) /*!< AM/PM flag */
|
||||
#define RTC_ALRMXTD_MSKH BIT(23) /*!< alarm hour mask bit */
|
||||
#define RTC_ALRMXTD_DAYU BITS(24,27) /*!< date units or week day in BCD code */
|
||||
#define RTC_ALRMXTD_DAYT BITS(28,29) /*!< date tens in BCD code */
|
||||
#define RTC_ALRMXTD_DOWS BIT(30) /*!< day of week selection */
|
||||
#define RTC_ALRMXTD_MSKD BIT(31) /*!< alarm date mask bit */
|
||||
|
||||
/* RTC_WPK */
|
||||
#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */
|
||||
|
||||
/* RTC_SS */
|
||||
#define RTC_SS_SSC BITS(0,15) /*!< sub second value */
|
||||
|
||||
/* RTC_SHIFTCTL */
|
||||
#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */
|
||||
#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */
|
||||
|
||||
/* RTC_TTS */
|
||||
#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */
|
||||
#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */
|
||||
#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */
|
||||
#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */
|
||||
#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */
|
||||
#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */
|
||||
#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */
|
||||
|
||||
/* RTC_DTS */
|
||||
#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */
|
||||
#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */
|
||||
#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */
|
||||
#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */
|
||||
#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */
|
||||
|
||||
/* RTC_SSTS */
|
||||
#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */
|
||||
|
||||
/* RTC_HRFC */
|
||||
#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */
|
||||
#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */
|
||||
#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */
|
||||
#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */
|
||||
|
||||
/* RTC_TAMP */
|
||||
#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */
|
||||
#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */
|
||||
#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */
|
||||
#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */
|
||||
#define RTC_TAMP_TP1EG BIT(4) /*!< Tamper 1 event trigger edge for RTC tamp 1 input */
|
||||
#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */
|
||||
#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */
|
||||
#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */
|
||||
#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */
|
||||
#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */
|
||||
#define RTC_TAMP_TP0SEL BIT(16) /*!< Tamper 0 function input mapping selection */
|
||||
#define RTC_TAMP_TSSEL BIT(17) /*!< Timestamp input mapping selection */
|
||||
#define RTC_TAMP_AOT BIT(18) /*!< RTC_ALARM output Type */
|
||||
|
||||
/* RTC_ALRM0SS */
|
||||
#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm0 sub second value */
|
||||
#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */
|
||||
|
||||
/* RTC_ALRM1SS */
|
||||
#define RTC_ALRM1SS_SSC BITS(0,14) /*!< alarm1 sub second value */
|
||||
#define RTC_ALRM1SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */
|
||||
|
||||
/* constants definitions */
|
||||
/* structure for initialization of the RTC */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t year; /*!< RTC year value: 0x0 - 0x99(BCD format) */
|
||||
uint8_t month; /*!< RTC month value */
|
||||
uint8_t date; /*!< RTC date value: 0x1 - 0x31(BCD format) */
|
||||
uint8_t day_of_week; /*!< RTC weekday value */
|
||||
uint8_t hour; /*!< RTC hour value */
|
||||
uint8_t minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */
|
||||
uint8_t second; /*!< RTC second value: 0x0 - 0x59(BCD format) */
|
||||
uint16_t factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */
|
||||
uint16_t factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */
|
||||
uint32_t am_pm; /*!< RTC AM/PM value */
|
||||
uint32_t display_format; /*!< RTC time notation */
|
||||
}rtc_parameter_struct;
|
||||
|
||||
/* structure for RTC alarm configuration */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t alarm_mask; /*!< RTC alarm mask */
|
||||
uint32_t weekday_or_date; /*!< specify RTC alarm is on date or weekday */
|
||||
uint8_t alarm_day; /*!< RTC alarm date or weekday value*/
|
||||
uint8_t alarm_hour; /*!< RTC alarm hour value */
|
||||
uint8_t alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */
|
||||
uint8_t alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */
|
||||
uint32_t am_pm; /*!< RTC alarm AM/PM value */
|
||||
}rtc_alarm_struct;
|
||||
|
||||
/* structure for RTC time-stamp configuration */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t timestamp_month; /*!< RTC time-stamp month value */
|
||||
uint8_t timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */
|
||||
uint8_t timestamp_day; /*!< RTC time-stamp weekday value */
|
||||
uint8_t timestamp_hour; /*!< RTC time-stamp hour value */
|
||||
uint8_t timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */
|
||||
uint8_t timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */
|
||||
uint32_t am_pm; /*!< RTC time-stamp AM/PM value */
|
||||
}rtc_timestamp_struct;
|
||||
|
||||
/* structure for RTC tamper configuration */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t tamper_source; /*!< RTC tamper source */
|
||||
uint32_t tamper_trigger; /*!< RTC tamper trigger */
|
||||
uint32_t tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */
|
||||
uint32_t tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */
|
||||
ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */
|
||||
uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */
|
||||
ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */
|
||||
}rtc_tamper_struct;
|
||||
|
||||
/* time register value */
|
||||
#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */
|
||||
#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */
|
||||
|
||||
#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TIME_MN bit field */
|
||||
#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */
|
||||
|
||||
#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TIME_HR bit field */
|
||||
#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */
|
||||
|
||||
#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */
|
||||
#define RTC_PM RTC_TIME_PM /*!< PM format */
|
||||
|
||||
/* date register value */
|
||||
#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DATE_DAY bit field */
|
||||
#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */
|
||||
|
||||
#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DATE_MON bit field */
|
||||
#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */
|
||||
#define RTC_JAN ((uint8_t)0x01U) /*!< janurary */
|
||||
#define RTC_FEB ((uint8_t)0x02U) /*!< february */
|
||||
#define RTC_MAR ((uint8_t)0x03U) /*!< march */
|
||||
#define RTC_APR ((uint8_t)0x04U) /*!< april */
|
||||
#define RTC_MAY ((uint8_t)0x05U) /*!< may */
|
||||
#define RTC_JUN ((uint8_t)0x06U) /*!< june */
|
||||
#define RTC_JUL ((uint8_t)0x07U) /*!< july */
|
||||
#define RTC_AUG ((uint8_t)0x08U) /*!< august */
|
||||
#define RTC_SEP ((uint8_t)0x09U) /*!< september */
|
||||
#define RTC_OCT ((uint8_t)0x10U) /*!< october */
|
||||
#define RTC_NOV ((uint8_t)0x11U) /*!< november */
|
||||
#define RTC_DEC ((uint8_t)0x12U) /*!< december */
|
||||
|
||||
#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DATE_DOW bit field */
|
||||
#define GET_DATE_DOW(regval) GET_BITS((uint32_t)(regval),13,15) /*!< get value of RTC_DATE_DOW bit field */
|
||||
#define RTC_MONDAY ((uint8_t)0x01) /*!< monday */
|
||||
#define RTC_TUESDAY ((uint8_t)0x02) /*!< tuesday */
|
||||
#define RTC_WEDSDAY ((uint8_t)0x03) /*!< wednesday */
|
||||
#define RTC_THURSDAY ((uint8_t)0x04) /*!< thursday */
|
||||
#define RTC_FRIDAY ((uint8_t)0x05) /*!< friday */
|
||||
#define RTC_SATURDAY ((uint8_t)0x06) /*!< saturday */
|
||||
#define RTC_SUNDAY ((uint8_t)0x07) /*!< sunday */
|
||||
|
||||
#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_DATE_YR bit field */
|
||||
#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */
|
||||
|
||||
/* ctl register value */
|
||||
#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) /*!< write value to RTC_CTL_OS bit field */
|
||||
#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */
|
||||
#define RTC_OS_ALARM0 CTL_OS(1) /*!< enable alarm0 flag output */
|
||||
#define RTC_OS_ALARM1 CTL_OS(2) /*!< enable alarm1 flag output */
|
||||
#define RTC_OS_WAKEUP CTL_OS(3) /*!< enable wakeup flag output */
|
||||
|
||||
#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */
|
||||
#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */
|
||||
#define RTC_ALARM0_HIGH RTC_OS_ALARM0 /*!< enable alarm0 flag output with high level */
|
||||
#define RTC_ALARM0_LOW (RTC_OS_ALARM0 | RTC_CTL_OPOL) /*!< enable alarm0 flag output with low level*/
|
||||
#define RTC_ALARM1_HIGH RTC_OS_ALARM1 /*!< enable alarm1 flag output with high level */
|
||||
#define RTC_ALARM1_LOW (RTC_OS_ALARM1 | RTC_CTL_OPOL) /*!< enable alarm1 flag output with low level*/
|
||||
#define RTC_WAKEUP_HIGH RTC_OS_WAKEUP /*!< enable wakeup flag output with high level */
|
||||
#define RTC_WAKEUP_LOW (RTC_OS_WAKEUP | RTC_CTL_OPOL) /*!< enable wakeup flag output with low level*/
|
||||
|
||||
#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */
|
||||
#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */
|
||||
|
||||
#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */
|
||||
#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */
|
||||
|
||||
/* psc register value */
|
||||
#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_PSC_FACTOR_S bit field */
|
||||
#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */
|
||||
|
||||
#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_PSC_FACTOR_A bit field */
|
||||
#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */
|
||||
|
||||
/* alrmtd register value */
|
||||
#define ALRMTD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMTD_SC bit field */
|
||||
#define GET_ALRMTD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRMTD_SC bit field */
|
||||
|
||||
#define ALRMTD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_ALRMTD_MN bit field */
|
||||
#define GET_ALRMTD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRMTD_MN bit field */
|
||||
|
||||
#define ALRMTD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_ALRMTD_HR bit field */
|
||||
#define GET_ALRMTD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRMTD_HR bit field */
|
||||
|
||||
#define ALRMTD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMTD_DAY bit field */
|
||||
#define GET_ALRMTD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRMTD_DAY bit field */
|
||||
|
||||
#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */
|
||||
#define RTC_ALARM_DATE_MASK RTC_ALRMXTD_MSKD /*!< alarm date mask */
|
||||
#define RTC_ALARM_HOUR_MASK RTC_ALRMXTD_MSKH /*!< alarm hour mask */
|
||||
#define RTC_ALARM_MINUTE_MASK RTC_ALRMXTD_MSKM /*!< alarm minute mask */
|
||||
#define RTC_ALARM_SECOND_MASK RTC_ALRMXTD_MSKS /*!< alarm second mask */
|
||||
#define RTC_ALARM_ALL_MASK (RTC_ALRMXTD_MSKD|RTC_ALRMXTD_MSKH|RTC_ALRMXTD_MSKM|RTC_ALRMXTD_MSKS) /*!< alarm all mask */
|
||||
|
||||
#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */
|
||||
#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRMXTD_DOWS /*!< alarm weekday format selected */
|
||||
|
||||
/* wpk register value */
|
||||
#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_WPK_WPK bit field */
|
||||
|
||||
/* ss register value */
|
||||
#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SS_SSC bit field */
|
||||
|
||||
/* shiftctl register value */
|
||||
#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SHIFTCTL_SFS bit field */
|
||||
|
||||
#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */
|
||||
#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */
|
||||
|
||||
/* tts register value */
|
||||
#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TTS_SC bit field */
|
||||
#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */
|
||||
|
||||
#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TTS_MN bit field */
|
||||
#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */
|
||||
|
||||
#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TTS_HR bit field */
|
||||
#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */
|
||||
|
||||
/* dts register value */
|
||||
#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DTS_DAY bit field */
|
||||
#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */
|
||||
|
||||
#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DTS_MON bit field */
|
||||
#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */
|
||||
|
||||
#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DTS_DOW bit field */
|
||||
#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */
|
||||
|
||||
/* ssts register value */
|
||||
#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SSTS_SSC bit field */
|
||||
|
||||
/* hrfc register value */
|
||||
#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_HRFC_CMSK bit field */
|
||||
|
||||
#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */
|
||||
#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */
|
||||
#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */
|
||||
|
||||
#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */
|
||||
#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */
|
||||
|
||||
/* tamp register value */
|
||||
#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TAMP_FREQ bit field */
|
||||
#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */
|
||||
|
||||
#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< write value to RTC_TAMP_FLT bit field */
|
||||
#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */
|
||||
#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */
|
||||
#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */
|
||||
#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */
|
||||
|
||||
#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_TAMP_PRCH bit field */
|
||||
#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */
|
||||
#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */
|
||||
#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */
|
||||
#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */
|
||||
|
||||
#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */
|
||||
#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */
|
||||
|
||||
#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */
|
||||
#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */
|
||||
#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */
|
||||
#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */
|
||||
|
||||
#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */
|
||||
|
||||
#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */
|
||||
#define RTC_ALARM_OUTPUT_PP RTC_TAMP_AOT /*!< RTC alarm output push-pull mode */
|
||||
|
||||
/* ALRMXSS register value */
|
||||
#define ALRMXSS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMXSS_SSC bit field */
|
||||
|
||||
#define ALRMXSS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMXSS_MASKSSC bit field */
|
||||
#define RTC_MASKSSC_0_14 ALRMXSS_MASKSSC(0) /*!< mask alarm subsecond configuration */
|
||||
#define RTC_MASKSSC_1_14 ALRMXSS_MASKSSC(1) /*!< mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared */
|
||||
#define RTC_MASKSSC_2_14 ALRMXSS_MASKSSC(2) /*!< mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared */
|
||||
#define RTC_MASKSSC_3_14 ALRMXSS_MASKSSC(3) /*!< mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared */
|
||||
#define RTC_MASKSSC_4_14 ALRMXSS_MASKSSC(4) /*!< mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared */
|
||||
#define RTC_MASKSSC_5_14 ALRMXSS_MASKSSC(5) /*!< mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared */
|
||||
#define RTC_MASKSSC_6_14 ALRMXSS_MASKSSC(6) /*!< mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared */
|
||||
#define RTC_MASKSSC_7_14 ALRMXSS_MASKSSC(7) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */
|
||||
#define RTC_MASKSSC_8_14 ALRMXSS_MASKSSC(8) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */
|
||||
#define RTC_MASKSSC_9_14 ALRMXSS_MASKSSC(9) /*!< mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared */
|
||||
#define RTC_MASKSSC_10_14 ALRMXSS_MASKSSC(10) /*!< mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared */
|
||||
#define RTC_MASKSSC_11_14 ALRMXSS_MASKSSC(11) /*!< mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared */
|
||||
#define RTC_MASKSSC_12_14 ALRMXSS_MASKSSC(12) /*!< mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared */
|
||||
#define RTC_MASKSSC_13_14 ALRMXSS_MASKSSC(13) /*!< mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared */
|
||||
#define RTC_MASKSSC_14 ALRMXSS_MASKSSC(14) /*!< mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared */
|
||||
#define RTC_MASKSSC_NONE ALRMXSS_MASKSSC(15) /*!< mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared */
|
||||
|
||||
/* RTC interrupt source */
|
||||
#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */
|
||||
#define RTC_INT_ALARM0 RTC_CTL_ALRM0IE /*!< RTC alarm0 interrupt enable */
|
||||
#define RTC_INT_ALARM1 RTC_CTL_ALRM1IE /*!< RTC alarm1 interrupt enable */
|
||||
#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */
|
||||
#define RTC_INT_WAKEUP RTC_CTL_WTIE /*!< RTC wakeup timer interrupt enable */
|
||||
|
||||
/* write protect key */
|
||||
#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */
|
||||
#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */
|
||||
#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */
|
||||
|
||||
/* registers reset value */
|
||||
#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */
|
||||
#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */
|
||||
#define RTC_STAT_RESET ((uint32_t)0x00000000U) /*!< RTC_STAT register reset value */
|
||||
#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */
|
||||
#define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */
|
||||
|
||||
/* RTC alarm */
|
||||
#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */
|
||||
#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */
|
||||
|
||||
/* RTC coarse calibration direction */
|
||||
#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */
|
||||
#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */
|
||||
|
||||
/* RTC wakeup timer clock */
|
||||
#define CTL_WTCS(regval) (BITS(0,2) & ((regval)<< 0))
|
||||
#define WAKEUP_RTCCK_DIV16 CTL_WTCS(0) /*!< wakeup timer clock is RTC clock divided by 16 */
|
||||
#define WAKEUP_RTCCK_DIV8 CTL_WTCS(1) /*!< wakeup timer clock is RTC clock divided by 8 */
|
||||
#define WAKEUP_RTCCK_DIV4 CTL_WTCS(2) /*!< wakeup timer clock is RTC clock divided by 4 */
|
||||
#define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */
|
||||
#define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */
|
||||
#define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */
|
||||
|
||||
/* RTC_AF pin */
|
||||
#define RTC_AF0_TIMESTAMP ((uint32_t)0x00000000) /*!< RTC_AF0 use for timestamp */
|
||||
#define RTC_AF1_TIMESTAMP RTC_TAMP_TSSEL /*!< RTC_AF1 use for timestamp */
|
||||
#define RTC_AF0_TAMPER0 ((uint32_t)0x00000000) /*!< RTC_AF0 use for tamper0 */
|
||||
#define RTC_AF1_TAMPER0 RTC_TAMP_TP0SEL /*!< RTC_AF1 use for tamper0 */
|
||||
|
||||
/* RTC flags */
|
||||
#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */
|
||||
#define RTC_FLAG_ALRM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */
|
||||
#define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */
|
||||
#define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */
|
||||
#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year configuration mark status flag */
|
||||
#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< register synchronization flag */
|
||||
#define RTC_FLAG_INIT RTC_STAT_INITF /*!< initialization state flag */
|
||||
#define RTC_FLAG_ALRM0 RTC_STAT_ALRM0F /*!< alarm0 occurs flag */
|
||||
#define RTC_FLAG_ALRM1 RTC_STAT_ALRM1F /*!< alarm1 occurs flag */
|
||||
#define RTC_FLAG_WT RTC_STAT_WTF /*!< wakeup timer occurs flag */
|
||||
#define RTC_FLAG_TS RTC_STAT_TSF /*!< time-stamp flag */
|
||||
#define RTC_FLAG_TSOVR RTC_STAT_TSOVRF /*!< time-stamp overflow flag */
|
||||
#define RTC_FLAG_TP0 RTC_STAT_TP0F /*!< RTC tamper 0 detected flag */
|
||||
#define RTC_FLAG_TP1 RTC_STAT_TP1F /*!< RTC tamper 1 detected flag */
|
||||
#define RTC_STAT_SCP RTC_STAT_SCPF /*!< smooth calibration pending flag */
|
||||
|
||||
/* function declarations */
|
||||
/* reset most of the RTC registers */
|
||||
ErrStatus rtc_deinit(void);
|
||||
/* initialize RTC registers */
|
||||
ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct);
|
||||
/* enter RTC init mode */
|
||||
ErrStatus rtc_init_mode_enter(void);
|
||||
/* exit RTC init mode */
|
||||
void rtc_init_mode_exit(void);
|
||||
/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */
|
||||
ErrStatus rtc_register_sync_wait(void);
|
||||
|
||||
/* get current time and date */
|
||||
void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct);
|
||||
/* get current subsecond value */
|
||||
uint32_t rtc_subsecond_get(void);
|
||||
|
||||
/* configure RTC alarm */
|
||||
void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time);
|
||||
/* configure subsecond of RTC alarm */
|
||||
void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond);
|
||||
/* get RTC alarm */
|
||||
void rtc_alarm_get(uint8_t rtc_alarm,rtc_alarm_struct* rtc_alarm_time);
|
||||
/* get RTC alarm subsecond */
|
||||
uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm);
|
||||
/* enable RTC alarm */
|
||||
void rtc_alarm_enable(uint8_t rtc_alarm);
|
||||
/* disable RTC alarm */
|
||||
ErrStatus rtc_alarm_disable(uint8_t rtc_alarm);
|
||||
|
||||
/* enable RTC time-stamp */
|
||||
void rtc_timestamp_enable(uint32_t edge);
|
||||
/* disable RTC time-stamp */
|
||||
void rtc_timestamp_disable(void);
|
||||
/* get RTC timestamp time and date */
|
||||
void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp);
|
||||
/* get RTC time-stamp subsecond */
|
||||
uint32_t rtc_timestamp_subsecond_get(void);
|
||||
/* RTC time-stamp pin map */
|
||||
void rtc_timestamp_pin_map(uint32_t rtc_af);
|
||||
|
||||
/* enable RTC tamper */
|
||||
void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper);
|
||||
/* disable RTC tamper */
|
||||
void rtc_tamper_disable(uint32_t source);
|
||||
/* RTC tamper0 pin map */
|
||||
void rtc_tamper0_pin_map(uint32_t rtc_af);
|
||||
|
||||
/* enable specified RTC interrupt */
|
||||
void rtc_interrupt_enable(uint32_t interrupt);
|
||||
/* disble specified RTC interrupt */
|
||||
void rtc_interrupt_disable(uint32_t interrupt);
|
||||
/* check specified flag */
|
||||
FlagStatus rtc_flag_get(uint32_t flag);
|
||||
/* clear specified flag */
|
||||
void rtc_flag_clear(uint32_t flag);
|
||||
|
||||
/* configure RTC alarm output source */
|
||||
void rtc_alarm_output_config(uint32_t source, uint32_t mode);
|
||||
/* configure RTC calibration output source */
|
||||
void rtc_calibration_output_config(uint32_t source);
|
||||
|
||||
/* adjust the daylight saving time by adding or substracting one hour from the current time */
|
||||
void rtc_hour_adjust(uint32_t operation);
|
||||
/* adjust RTC second or subsecond value of current time */
|
||||
ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus);
|
||||
|
||||
/* enable RTC bypass shadow registers function */
|
||||
void rtc_bypass_shadow_enable(void);
|
||||
/* disable RTC bypass shadow registers function */
|
||||
void rtc_bypass_shadow_disable(void);
|
||||
|
||||
/* enable RTC reference clock detection function */
|
||||
ErrStatus rtc_refclock_detection_enable(void);
|
||||
/* disable RTC reference clock detection function */
|
||||
ErrStatus rtc_refclock_detection_disable(void);
|
||||
|
||||
/* enable RTC wakeup timer */
|
||||
void rtc_wakeup_enable(void);
|
||||
/* disable RTC wakeup timer */
|
||||
ErrStatus rtc_wakeup_disable(void);
|
||||
/* set auto wakeup timer clock */
|
||||
ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock);
|
||||
/* set auto wakeup timer value */
|
||||
ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer);
|
||||
/* get auto wakeup timer value */
|
||||
uint16_t rtc_wakeup_timer_get(void);
|
||||
|
||||
/* configure RTC smooth calibration */
|
||||
ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus);
|
||||
/* enable RTC coarse calibration */
|
||||
ErrStatus rtc_coarse_calibration_enable(void);
|
||||
/* disable RTC coarse calibration */
|
||||
ErrStatus rtc_coarse_calibration_disable(void);
|
||||
/* configure RTC coarse calibration direction and step */
|
||||
ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step);
|
||||
|
||||
#endif /* GD32F4XX_RTC_H */
|
||||
|
|
@ -0,0 +1,433 @@
|
|||
/*!
|
||||
\file gd32f4xx_sdio.h
|
||||
\brief definitions for the SDIO
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_SDIO_H
|
||||
#define GD32F4XX_SDIO_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* SDIO definitions */
|
||||
#define SDIO SDIO_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */
|
||||
#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */
|
||||
#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */
|
||||
#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */
|
||||
#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */
|
||||
#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */
|
||||
#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */
|
||||
#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */
|
||||
#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */
|
||||
#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */
|
||||
#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */
|
||||
#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */
|
||||
#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */
|
||||
#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */
|
||||
#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */
|
||||
#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */
|
||||
#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */
|
||||
#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */
|
||||
|
||||
/* bits definitions */
|
||||
/* SDIO_PWRCTL */
|
||||
#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */
|
||||
|
||||
/* SDIO_CLKCTL */
|
||||
#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */
|
||||
#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */
|
||||
#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */
|
||||
#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */
|
||||
#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */
|
||||
#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */
|
||||
#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */
|
||||
#define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */
|
||||
|
||||
/* SDIO_CMDAGMT */
|
||||
#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */
|
||||
|
||||
/* SDIO_CMDCTL */
|
||||
#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */
|
||||
#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */
|
||||
#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */
|
||||
#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */
|
||||
#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */
|
||||
#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */
|
||||
#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */
|
||||
#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */
|
||||
#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */
|
||||
|
||||
/* SDIO_DATATO */
|
||||
#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */
|
||||
|
||||
/* SDIO_DATALEN */
|
||||
#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */
|
||||
|
||||
/* SDIO_DATACTL */
|
||||
#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */
|
||||
#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */
|
||||
#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */
|
||||
#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */
|
||||
#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */
|
||||
#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */
|
||||
#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */
|
||||
#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */
|
||||
#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */
|
||||
|
||||
/* SDIO_STAT */
|
||||
#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */
|
||||
#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */
|
||||
#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */
|
||||
#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */
|
||||
#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */
|
||||
#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */
|
||||
#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */
|
||||
#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */
|
||||
#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */
|
||||
#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */
|
||||
#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */
|
||||
#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */
|
||||
#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */
|
||||
#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */
|
||||
#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */
|
||||
#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */
|
||||
#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */
|
||||
#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */
|
||||
#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */
|
||||
#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */
|
||||
#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */
|
||||
#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */
|
||||
#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */
|
||||
#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */
|
||||
|
||||
/* SDIO_INTC */
|
||||
#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */
|
||||
#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */
|
||||
#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */
|
||||
#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */
|
||||
#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */
|
||||
#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */
|
||||
#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */
|
||||
#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */
|
||||
#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */
|
||||
#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */
|
||||
#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */
|
||||
#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */
|
||||
#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */
|
||||
|
||||
/* SDIO_INTEN */
|
||||
#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */
|
||||
#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */
|
||||
#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */
|
||||
#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */
|
||||
#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */
|
||||
#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */
|
||||
#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */
|
||||
#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */
|
||||
#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */
|
||||
#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */
|
||||
#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */
|
||||
#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */
|
||||
#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */
|
||||
#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */
|
||||
#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */
|
||||
#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */
|
||||
#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */
|
||||
#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */
|
||||
#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */
|
||||
#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */
|
||||
#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */
|
||||
#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */
|
||||
#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */
|
||||
#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */
|
||||
|
||||
/* SDIO_FIFO */
|
||||
#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */
|
||||
|
||||
/* constants definitions */
|
||||
/* SDIO flags */
|
||||
#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */
|
||||
#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */
|
||||
#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */
|
||||
#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */
|
||||
#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */
|
||||
#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */
|
||||
#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */
|
||||
#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */
|
||||
#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */
|
||||
#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */
|
||||
#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */
|
||||
#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */
|
||||
#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */
|
||||
#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */
|
||||
#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */
|
||||
#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */
|
||||
#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */
|
||||
#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */
|
||||
#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */
|
||||
#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */
|
||||
#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */
|
||||
#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */
|
||||
#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */
|
||||
#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */
|
||||
|
||||
/* SDIO interrupt enable or disable */
|
||||
#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */
|
||||
#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */
|
||||
#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */
|
||||
#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */
|
||||
#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */
|
||||
#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */
|
||||
#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */
|
||||
#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */
|
||||
#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */
|
||||
#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */
|
||||
#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */
|
||||
#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */
|
||||
#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */
|
||||
#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */
|
||||
#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */
|
||||
#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */
|
||||
#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */
|
||||
#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */
|
||||
#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */
|
||||
#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */
|
||||
#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */
|
||||
#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */
|
||||
#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */
|
||||
#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */
|
||||
|
||||
/* SDIO interrupt flags */
|
||||
#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */
|
||||
#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */
|
||||
#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */
|
||||
#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */
|
||||
#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */
|
||||
#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */
|
||||
#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */
|
||||
#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */
|
||||
#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */
|
||||
#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */
|
||||
#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */
|
||||
#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */
|
||||
#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */
|
||||
#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */
|
||||
#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */
|
||||
#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */
|
||||
#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */
|
||||
#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */
|
||||
#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */
|
||||
#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */
|
||||
#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */
|
||||
#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */
|
||||
#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */
|
||||
#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */
|
||||
|
||||
/* SDIO power control */
|
||||
#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */
|
||||
#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */
|
||||
|
||||
/* SDIO card bus mode control */
|
||||
#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
|
||||
#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */
|
||||
#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */
|
||||
#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */
|
||||
|
||||
/* SDIO_CLK clock edge selection */
|
||||
#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */
|
||||
#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */
|
||||
|
||||
/* clock bypass enable or disable */
|
||||
#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U /*!< no bypass */
|
||||
#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */
|
||||
|
||||
/* SDIO_CLK clock dynamic switch on/off for power saving */
|
||||
#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */
|
||||
#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */
|
||||
|
||||
/* SDIO command response type */
|
||||
#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */
|
||||
#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */
|
||||
#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */
|
||||
|
||||
/* command state machine wait type */
|
||||
#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */
|
||||
#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */
|
||||
#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */
|
||||
|
||||
#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */
|
||||
#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */
|
||||
#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */
|
||||
#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */
|
||||
|
||||
/* SDIO data block size */
|
||||
#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||
#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */
|
||||
#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */
|
||||
|
||||
/* SDIO data transfer mode */
|
||||
#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U /*!< block transfer */
|
||||
#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */
|
||||
|
||||
/* SDIO data transfer direction */
|
||||
#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */
|
||||
#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */
|
||||
|
||||
/* SDIO read wait type */
|
||||
#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */
|
||||
#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */
|
||||
|
||||
/* function declarations */
|
||||
/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */
|
||||
/* deinitialize the SDIO */
|
||||
void sdio_deinit(void);
|
||||
/* configure the SDIO clock */
|
||||
void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division);
|
||||
/* enable hardware clock control */
|
||||
void sdio_hardware_clock_enable(void);
|
||||
/* disable hardware clock control */
|
||||
void sdio_hardware_clock_disable(void);
|
||||
/* set different SDIO card bus mode */
|
||||
void sdio_bus_mode_set(uint32_t bus_mode);
|
||||
/* set the SDIO power state */
|
||||
void sdio_power_state_set(uint32_t power_state);
|
||||
/* get the SDIO power state */
|
||||
uint32_t sdio_power_state_get(void);
|
||||
/* enable SDIO_CLK clock output */
|
||||
void sdio_clock_enable(void);
|
||||
/* disable SDIO_CLK clock output */
|
||||
void sdio_clock_disable(void);
|
||||
|
||||
/* configure the command index, argument, response type, wait type and CSM to send command functions */
|
||||
/* configure the command and response */
|
||||
void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
|
||||
/* set the command state machine wait type */
|
||||
void sdio_wait_type_set(uint32_t wait_type);
|
||||
/* enable the CSM(command state machine) */
|
||||
void sdio_csm_enable(void);
|
||||
/* disable the CSM(command state machine) */
|
||||
void sdio_csm_disable(void);
|
||||
/* get the last response command index */
|
||||
uint8_t sdio_command_index_get(void);
|
||||
/* get the response for the last received command */
|
||||
uint32_t sdio_response_get(uint32_t sdio_responsex);
|
||||
|
||||
/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */
|
||||
/* configure the data timeout, data length and data block size */
|
||||
void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
|
||||
/* configure the data transfer mode and direction */
|
||||
void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction);
|
||||
/* enable the DSM(data state machine) for data transfer */
|
||||
void sdio_dsm_enable(void);
|
||||
/* disable the DSM(data state machine) */
|
||||
void sdio_dsm_disable(void);
|
||||
/* write data(one word) to the transmit FIFO */
|
||||
void sdio_data_write(uint32_t data);
|
||||
/* read data(one word) from the receive FIFO */
|
||||
uint32_t sdio_data_read(void);
|
||||
/* get the number of remaining data bytes to be transferred to card */
|
||||
uint32_t sdio_data_counter_get(void);
|
||||
/* get the number of words remaining to be written or read from FIFO */
|
||||
uint32_t sdio_fifo_counter_get(void);
|
||||
/* enable the DMA request for SDIO */
|
||||
void sdio_dma_enable(void);
|
||||
/* disable the DMA request for SDIO */
|
||||
void sdio_dma_disable(void);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* get the flags state of SDIO */
|
||||
FlagStatus sdio_flag_get(uint32_t flag);
|
||||
/* clear the pending flags of SDIO */
|
||||
void sdio_flag_clear(uint32_t flag);
|
||||
/* enable the SDIO interrupt */
|
||||
void sdio_interrupt_enable(uint32_t int_flag);
|
||||
/* disable the SDIO interrupt */
|
||||
void sdio_interrupt_disable(uint32_t int_flag);
|
||||
/* get the interrupt flags state of SDIO */
|
||||
FlagStatus sdio_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear the interrupt pending flags of SDIO */
|
||||
void sdio_interrupt_flag_clear(uint32_t int_flag);
|
||||
|
||||
/* SD I/O card functions */
|
||||
/* enable the read wait mode(SD I/O only) */
|
||||
void sdio_readwait_enable(void);
|
||||
/* disable the read wait mode(SD I/O only) */
|
||||
void sdio_readwait_disable(void);
|
||||
/* enable the function that stop the read wait process(SD I/O only) */
|
||||
void sdio_stop_readwait_enable(void);
|
||||
/* disable the function that stop the read wait process(SD I/O only) */
|
||||
void sdio_stop_readwait_disable(void);
|
||||
/* set the read wait type(SD I/O only) */
|
||||
void sdio_readwait_type_set(uint32_t readwait_type);
|
||||
/* enable the SD I/O mode specific operation(SD I/O only) */
|
||||
void sdio_operation_enable(void);
|
||||
/* disable the SD I/O mode specific operation(SD I/O only) */
|
||||
void sdio_operation_disable(void);
|
||||
/* enable the SD I/O suspend operation(SD I/O only) */
|
||||
void sdio_suspend_enable(void);
|
||||
/* disable the SD I/O suspend operation(SD I/O only) */
|
||||
void sdio_suspend_disable(void);
|
||||
|
||||
/* CE-ATA functions */
|
||||
/* enable the CE-ATA command(CE-ATA only) */
|
||||
void sdio_ceata_command_enable(void);
|
||||
/* disable the CE-ATA command(CE-ATA only) */
|
||||
void sdio_ceata_command_disable(void);
|
||||
/* enable the CE-ATA interrupt(CE-ATA only) */
|
||||
void sdio_ceata_interrupt_enable(void);
|
||||
/* disable the CE-ATA interrupt(CE-ATA only) */
|
||||
void sdio_ceata_interrupt_disable(void);
|
||||
/* enable the CE-ATA command completion signal(CE-ATA only) */
|
||||
void sdio_ceata_command_completion_enable(void);
|
||||
/* disable the CE-ATA command completion signal(CE-ATA only) */
|
||||
void sdio_ceata_command_completion_disable(void);
|
||||
|
||||
#endif /* GD32F4XX_SDIO_H */
|
||||
|
|
@ -0,0 +1,379 @@
|
|||
/*!
|
||||
\file gd32f4xx_spi.h
|
||||
\brief definitions for the SPI
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F4XX_SPI_H
|
||||
#define GD32F4XX_SPI_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* SPIx(x=0,1,2,3,4,5) definitions */
|
||||
#define SPI0 (SPI_BASE + 0x0000F800U)
|
||||
#define SPI1 SPI_BASE
|
||||
#define SPI2 (SPI_BASE + 0x00000400U)
|
||||
#define SPI3 (SPI_BASE + 0x0000FC00U)
|
||||
#define SPI4 (SPI_BASE + 0x00011800U)
|
||||
#define SPI5 (SPI_BASE + 0x00011C00U)
|
||||
|
||||
/* I2Sx_ADD(x=1,2) definitions */
|
||||
#define I2S1_ADD I2S_ADD_BASE
|
||||
#define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U)
|
||||
|
||||
/* SPI registers definitions */
|
||||
#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */
|
||||
#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/
|
||||
#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */
|
||||
#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */
|
||||
#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */
|
||||
#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */
|
||||
#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */
|
||||
#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */
|
||||
#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */
|
||||
#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register */
|
||||
|
||||
/* I2S_ADD registers definitions */
|
||||
#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00U) /*!< I2S_ADD control register 0 */
|
||||
#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x04U) /*!< I2S_ADD control register 1*/
|
||||
#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x08U) /*!< I2S_ADD status register */
|
||||
#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0CU) /*!< I2S_ADD data register */
|
||||
#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x10U) /*!< I2S_ADD CRC polynomial register */
|
||||
#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x14U) /*!< I2S_ADD receive CRC register */
|
||||
#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x18U) /*!< I2S_ADD transmit CRC register */
|
||||
#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x1CU) /*!< I2S_ADD I2S control register */
|
||||
#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */
|
||||
|
||||
/* bits definitions */
|
||||
/* SPI_CTL0 */
|
||||
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/
|
||||
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
|
||||
#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
|
||||
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
|
||||
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
|
||||
#define SPI_CTL0_LF BIT(7) /*!< lsb first mode */
|
||||
#define SPI_CTL0_SWNSS BIT(8) /*!< nss pin selection in nss software mode */
|
||||
#define SPI_CTL0_SWNSSEN BIT(9) /*!< nss software mode selection */
|
||||
#define SPI_CTL0_RO BIT(10) /*!< receive only */
|
||||
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
|
||||
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
|
||||
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
|
||||
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
|
||||
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
|
||||
|
||||
/* SPI_CTL1 */
|
||||
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */
|
||||
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */
|
||||
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive nss output */
|
||||
#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */
|
||||
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
|
||||
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
|
||||
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
|
||||
|
||||
/* SPI_STAT */
|
||||
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
|
||||
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
|
||||
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
|
||||
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
|
||||
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
|
||||
#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
|
||||
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
|
||||
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
|
||||
#define SPI_STAT_FERR BIT(8) /*!< format error bit */
|
||||
|
||||
/* SPI_DATA */
|
||||
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
|
||||
|
||||
/* SPI_CRCPOLY */
|
||||
#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */
|
||||
|
||||
/* SPI_RCRC */
|
||||
#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */
|
||||
|
||||
/* SPI_TCRC */
|
||||
#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */
|
||||
|
||||
/* SPI_I2SCTL */
|
||||
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
|
||||
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
|
||||
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
|
||||
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
|
||||
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
|
||||
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
|
||||
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
|
||||
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
|
||||
|
||||
/* SPI_I2S_PSC */
|
||||
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
|
||||
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
|
||||
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
|
||||
|
||||
/* SPI_SPI_QCTL(only SPI5) */
|
||||
#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
|
||||
#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
|
||||
#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* SPI and I2S parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t device_mode; /*!< SPI master or slave */
|
||||
uint32_t trans_mode; /*!< SPI transtype */
|
||||
uint32_t frame_size; /*!< SPI frame size */
|
||||
uint32_t nss; /*!< SPI nss control by handware or software */
|
||||
uint32_t endian; /*!< SPI big endian or little endian */
|
||||
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
|
||||
uint32_t prescale; /*!< SPI prescale factor */
|
||||
}spi_parameter_struct;
|
||||
|
||||
/* SPI mode definitions */
|
||||
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
|
||||
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
|
||||
|
||||
/* SPI bidirectional transfer direction */
|
||||
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
|
||||
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
|
||||
|
||||
/* SPI transmit type */
|
||||
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
|
||||
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
|
||||
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
|
||||
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
|
||||
|
||||
/* SPI frame size */
|
||||
#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */
|
||||
#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */
|
||||
|
||||
/* SPI NSS control mode */
|
||||
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI nss control by sofrware */
|
||||
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI nss control by hardware */
|
||||
|
||||
/* SPI transmit way */
|
||||
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
|
||||
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
|
||||
|
||||
/* SPI clock polarity and phase */
|
||||
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
|
||||
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
|
||||
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
|
||||
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL|SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
|
||||
|
||||
/* SPI clock prescale factor */
|
||||
#define CTL0_PSC(regval) (BITS(3,5)&((uint32_t)(regval)<<3))
|
||||
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */
|
||||
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */
|
||||
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */
|
||||
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */
|
||||
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */
|
||||
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */
|
||||
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */
|
||||
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */
|
||||
|
||||
/* I2S audio sample rate */
|
||||
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
|
||||
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
|
||||
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
|
||||
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
|
||||
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
|
||||
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
|
||||
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
|
||||
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
|
||||
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
|
||||
|
||||
/* I2S frame format */
|
||||
#define I2SCTL_DTLEN(regval) (BITS(1,2)&((uint32_t)(regval)<<1))
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
|
||||
|
||||
/* I2S master clock output */
|
||||
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
|
||||
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
|
||||
|
||||
/* I2S operation mode */
|
||||
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9)&((uint32_t)(regval)<<8))
|
||||
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
|
||||
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
|
||||
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
|
||||
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
|
||||
|
||||
/* I2S standard */
|
||||
#define I2SCTL_I2SSTD(regval) (BITS(4,5)&((uint32_t)(regval)<<4))
|
||||
#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */
|
||||
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
|
||||
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
|
||||
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
|
||||
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
|
||||
|
||||
/* I2S clock polarity */
|
||||
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
|
||||
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
|
||||
|
||||
/* SPI DMA constants definitions */
|
||||
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
|
||||
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
|
||||
|
||||
/* SPI CRC constants definitions */
|
||||
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
|
||||
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
|
||||
|
||||
/* SPI/I2S interrupt enable/disable constants definitions */
|
||||
#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */
|
||||
#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */
|
||||
#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */
|
||||
|
||||
/* SPI/I2S interrupt flag constants definitions */
|
||||
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
|
||||
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
|
||||
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
|
||||
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */
|
||||
|
||||
/* SPI/I2S flag definitions */
|
||||
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
|
||||
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
|
||||
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
|
||||
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
|
||||
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* deinitialize SPI and I2S */
|
||||
void spi_i2s_deinit(uint32_t spi_periph);
|
||||
/* initialize the parameters of SPI struct with the default values */
|
||||
void spi_struct_para_init(spi_parameter_struct* spi_struct);
|
||||
/* initialize SPI parameter */
|
||||
void spi_init(uint32_t spi_periph,spi_parameter_struct* spi_struct);
|
||||
/* enable SPI */
|
||||
void spi_enable(uint32_t spi_periph);
|
||||
/* disable SPI */
|
||||
void spi_disable(uint32_t spi_periph);
|
||||
|
||||
/* initialize I2S parameter */
|
||||
void i2s_init(uint32_t spi_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl);
|
||||
/* configure I2S prescale */
|
||||
void i2s_psc_config(uint32_t spi_periph,uint32_t i2s_audiosample,uint32_t i2s_frameformat,uint32_t i2s_mckout);
|
||||
/* enable I2S */
|
||||
void i2s_enable(uint32_t spi_periph);
|
||||
/* disable I2S */
|
||||
void i2s_disable(uint32_t spi_periph);
|
||||
|
||||
/* NSS functions */
|
||||
/* enable SPI nss output */
|
||||
void spi_nss_output_enable(uint32_t spi_periph);
|
||||
/* disable SPI nss output */
|
||||
void spi_nss_output_disable(uint32_t spi_periph);
|
||||
/* SPI nss pin high level in software mode */
|
||||
void spi_nss_internal_high(uint32_t spi_periph);
|
||||
/* SPI nss pin low level in software mode */
|
||||
void spi_nss_internal_low(uint32_t spi_periph);
|
||||
|
||||
/* SPI DMA functions */
|
||||
/* enable SPI DMA */
|
||||
void spi_dma_enable(uint32_t spi_periph,uint8_t spi_dma);
|
||||
/* disable SPI DMA */
|
||||
void spi_dma_disable(uint32_t spi_periph,uint8_t spi_dma);
|
||||
|
||||
/* SPI/I2S transfer configure functions */
|
||||
/* configure SPI/I2S data frame format */
|
||||
void spi_i2s_data_frame_format_config(uint32_t spi_periph,uint16_t frame_format);
|
||||
/* SPI transmit data */
|
||||
void spi_i2s_data_transmit(uint32_t spi_periph,uint16_t data);
|
||||
/* SPI receive data */
|
||||
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||
/* configure SPI bidirectional transfer direction */
|
||||
void spi_bidirectional_transfer_config(uint32_t spi_periph,uint32_t transfer_direction);
|
||||
|
||||
/* SPI CRC functions */
|
||||
/* set SPI CRC polynomial */
|
||||
void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly);
|
||||
/* get SPI CRC polynomial */
|
||||
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
|
||||
/* turn on SPI CRC function */
|
||||
void spi_crc_on(uint32_t spi_periph);
|
||||
/* turn off SPI CRC function */
|
||||
void spi_crc_off(uint32_t spi_periph);
|
||||
/* SPI next data is CRC value */
|
||||
void spi_crc_next(uint32_t spi_periph);
|
||||
/* get SPI CRC send value or receive value */
|
||||
uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc);
|
||||
|
||||
/* SPI TI mode functions */
|
||||
/* enable SPI TI mode */
|
||||
void spi_ti_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI TI mode */
|
||||
void spi_ti_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* configure i2s full duplex mode */
|
||||
void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat);
|
||||
|
||||
/* quad wire SPI functions */
|
||||
/* enable quad wire SPI */
|
||||
void qspi_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI */
|
||||
void qspi_disable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI write */
|
||||
void qspi_write_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI read */
|
||||
void qspi_read_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void qspi_io23_output_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void qspi_io23_output_disable(uint32_t spi_periph);
|
||||
|
||||
/* flag & interrupt functions */
|
||||
/* enable SPI interrupt */
|
||||
void spi_i2s_interrupt_enable(uint32_t spi_periph,uint8_t spi_i2s_int);
|
||||
/* disable SPI interrupt */
|
||||
void spi_i2s_interrupt_disable(uint32_t spi_periph,uint8_t spi_i2s_int);
|
||||
/* get SPI and I2S interrupt status*/
|
||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph,uint8_t spi_i2s_int);
|
||||
/* get SPI and I2S flag status */
|
||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t spi_i2s_flag);
|
||||
/* clear SPI CRC error flag status */
|
||||
void spi_crc_error_clear(uint32_t spi_periph);
|
||||
|
||||
#endif /* GD32F4XX_SPI_H */
|
||||
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Reference in New Issue