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1. 更新 apm32\libraries\APM32F10x_Library 为 Geehy 官网 APM32F10x_SDK_V1.6。 

2. 增加 apm32\libraries\APM32F4xx_Library 为 Geehy 官网 APM32F4xx_SDK_V1.2。
3. 更新 apm32\libraries\Drivers。
4. 增加 apm32f407ig-minibroard 支持。
This commit is contained in:
Aligagago 2022-07-22 15:05:14 +08:00 committed by guo
parent a79b34ef8a
commit 1b55a1dedd
781 changed files with 315031 additions and 5850 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

336
bsp/apm32/apm32f103xe-minibroard/.config
View File

@ -21,17 +21,20 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_PRINTF_LONGLONG is not set
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
@ -77,8 +80,8 @@ CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40100
CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
CONFIG_RT_VER_NUM=0x40101
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
@ -108,7 +111,17 @@ CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
# CONFIG_RT_USING_DFS is not set
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
@ -210,19 +223,19 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LWIP is not set
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_MQTTCLIENT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
@ -242,12 +255,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
@ -256,13 +267,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
@ -270,105 +278,40 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
#
# JSON: JavaScript Object Notation, a lightweight data-interchange format
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
#
# XML: Extensible Markup Language
#
# CONFIG_PKG_USING_SIMPLE_XML is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
#
# tools packages
@ -377,115 +320,36 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# POSIX extension functions
#
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_RTDUINO is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_CHERRYUSB is not set
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
#
# peripheral libraries and drivers
@ -494,22 +358,19 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
@ -523,71 +384,26 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# project laboratory
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
@ -596,50 +412,15 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_HEATSHRINK is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_CONTROLLER is not set
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
# CONFIG_PKG_USING_MFBD is not set
CONFIG_SOC_FAMILY_APM32=y
CONFIG_SOC_SERIES_APM32F1=y
@ -654,6 +435,7 @@ CONFIG_SOC_APM32F103ZE=y
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set

42
bsp/apm32/apm32f103xe-minibroard/.gitignore vendored
View File

@ -1,42 +0,0 @@
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

20
bsp/apm32/apm32f103xe-minibroard/README.md
View File

@ -27,7 +27,7 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
- 外部 FLASH：无
- 常用外设
- LED：2个，（黄色，PE5/PE6）
- 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13）
- 按键：2个，K1（PA1），K2（PA0）
- 常用接口：RS232转串口、USB SLAVE
- 调试接口：标准 JTAG/SWD
@ -37,20 +37,20 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :------------------------------------ |
| RS232转串口 | 支持 | 使用 UART1/ UART2(通过跳线选择) |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA0, PA1... PG15 ---> PIN: 0, 1...143 |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA0, PA1... PG15 ---> PIN: 0, 1...108 |
| UART | 支持 | UART1/2 |
| ADC | 支持 | ADC1/2/3 |
| DAC | 支持 | DAC1 |
| RTC | 支持 | |
| TMR | 支持 | TMR1/2/3/4/5/6/7/8 |
| PWM | 支持 | TMR3 ->CH1/2 |
| I2C | 支持 | 软件I2C |
| SPI | 支持 | SPI1/2/3 |
| WDT | 支持 | IWDT |
| RTC | 支持 | 支持外部晶振和内部低速时钟 |
| TMR | 支持 | TMR1/2/3/4/5/6/7/8 |
| PWM | 支持 | TMR3 ->CH1/2/3/4 |
| I2C | 支持 | 软件I2C |
| SPI | 支持 | SPI1/2/3 |
| WDT | 支持 | IWDT |
## 使用说明

2
bsp/apm32/apm32f103xe-minibroard/SConstruct
View File

@ -26,7 +26,7 @@ env = Environment(tools = ['mingw'],
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')

6
bsp/apm32/apm32f103xe-minibroard/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -17,8 +17,12 @@
int main(void)
{
uint32_t sysclock = 0;
/* set LED2 pin mode to output */
rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
/* Print system clock */
sysclock = RCM_ReadSYSCLKFreq();
rt_kprintf("Read: Sec = %d, Usec = 0x%08X\n", sysclock, sysclock);
while (1)
{

4
bsp/apm32/apm32f103xe-minibroard/board/Kconfig
View File

@ -22,7 +22,9 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_UART2
bool "Enable UART2"
default n
endif
menuconfig BSP_USING_ADC

6
bsp/apm32/apm32f103xe-minibroard/board/SConscript
View File

@ -15,13 +15,13 @@ path = [cwd]
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['armcc', 'armclang']:
if rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s']
if rtconfig.PLATFORM in ['iccarm']:
if rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s']
if rtconfig.PLATFORM in ['gcc']:
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s']
# You can select chips from the list above

169
bsp/apm32/apm32f103xe-minibroard/project.ewp
View File

@ -48,16 +48,16 @@
<option>
<name>GRuntimeLibSelect</name>
<version>0</version>
<state>1</state>
<state>2</state>
</option>
<option>
<name>GRuntimeLibSelectSlave</name>
<version>0</version>
<state>1</state>
<state>2</state>
</option>
<option>
<name>RTDescription</name>
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
<state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
</option>
<option>
<name>OGProductVersion</name>
@ -111,7 +111,7 @@
</option>
<option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>
</option>
<option>
<name>GBECoreSlave</name>
@ -220,7 +220,11 @@
<option>
<name>CCDefines</name>
<state />
<state>CLOCKS_PER_SEC=RT_TICK_PER_SECOND</state>
<state>RT_USING_DLIBC</state>
<state>RT_USING_LIBC</state>
<state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
<state>_DLIB_FILE_DESCRIPTOR</state>
<state>APM32F10X_HD</state>
<state>__RTTHREAD__</state>
<state>USE_STDPERIPH_DRIVER</state>
@ -349,10 +353,12 @@
<option>
<name>CCIncludePath2</name>
<state />
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3</state>
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
<state>$PROJ_DIR$\..\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\stdio</state>
<state>$PROJ_DIR$\..\libraries\Drivers</state>
<state>$PROJ_DIR$\..\libraries\Drivers\config</state>
@ -361,9 +367,9 @@
<state>$PROJ_DIR$\..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include</state>
<state>$PROJ_DIR$\applications</state>
<state>$PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc</state>
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common</state>
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
<state>$PROJ_DIR$\..\libraries\APM32F10x_Library\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\include</state>
<state>$PROJ_DIR$\board</state>
@ -674,7 +680,7 @@
</option>
<option>
<name>OOCOutputFile</name>
<state>../../../rtthread.bin</state>
<state>../../rtthread.bin</state>
</option>
<option>
<name>OOCCommandLineProducer</name>
@ -1297,7 +1303,11 @@
<option>
<name>CCDefines</name>
<state>NDEBUG</state>
<state>CLOCKS_PER_SEC=RT_TICK_PER_SECOND</state>
<state>RT_USING_DLIBC</state>
<state>RT_USING_LIBC</state>
<state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
<state>_DLIB_FILE_DESCRIPTOR</state>
<state>APM32F10X_HD</state>
<state>__RTTHREAD__</state>
<state>USE_STDPERIPH_DRIVER</state>
@ -1426,10 +1436,12 @@
<option>
<name>CCIncludePath2</name>
<state />
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3</state>
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
<state>$PROJ_DIR$\..\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\stdio</state>
<state>$PROJ_DIR$\..\libraries\Drivers</state>
<state>$PROJ_DIR$\..\libraries\Drivers\config</state>
@ -1438,9 +1450,9 @@
<state>$PROJ_DIR$\..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include</state>
<state>$PROJ_DIR$\applications</state>
<state>$PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc</state>
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common</state>
<state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
<state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
<state>$PROJ_DIR$\..\libraries\APM32F10x_Library\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\include</state>
<state>$PROJ_DIR$\board</state>
@ -2163,44 +2175,53 @@
<group>
<name>Compiler</name>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c</name>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\stdlib.c</name>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdio.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c</name>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c</name>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c</name>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c</name>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
</file>
</group>
<group>
<name>CPU</name>
<file>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c</name>
</file>
@ -2208,35 +2229,38 @@
<name>$PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\cpuport.c</name>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\context_iar.S</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\cpuport.c</name>
</file>
</group>
<group>
<name>DeviceDrivers</name>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
</file>
@ -2252,14 +2276,29 @@
<file>
<name>$PROJ_DIR$\..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\iar\startup_apm32f10x_hd.s</name>
</file>
<file>
<name>$PROJ_DIR$\..\libraries\Drivers\drv_common.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\libraries\Drivers\drv_gpio.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\libraries\Drivers\drv_usart.c</name>
</file>
</group>
<group>
<name>Filesystem</name>
<file>
<name>$PROJ_DIR$\..\libraries\Drivers\drv_common.c</name>
<name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c</name>
</file>
</group>
<group>
@ -2270,50 +2309,56 @@
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\msh_parse.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\msh_file.c</name>
</file>
</group>
<group>
<name>Kernel</name>
<file>
<name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\idle.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\mem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\object.c</name>
<name>$PROJ_DIR$\..\..\..\src\clock.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\components.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\thread.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\clock.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\timer.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\device.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\idle.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\irq.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
<name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\mem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\object.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\thread.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\timer.c</name>
</file>
</group>
<group>

267
bsp/apm32/apm32f103xe-minibroard/project.uvprojx
View File

@ -333,9 +333,9 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls />
<Define>USE_STDPERIPH_DRIVER, APM32F10X_HD, __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Define>__STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARM_LIBC, APM32F10X_HD</Define>
<Undefine />
<IncludePath>applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\extension;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
<IncludePath>applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -404,21 +404,56 @@
</Files>
<Files>
<File>
<FileName>time.c</FileName>
<FileName>cctype.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\time.c</FilePath>
<FilePath>..\..\..\components\libc\compilers\common\cctype.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stdlib.c</FileName>
<FileName>cstdio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\stdlib.c</FilePath>
<FilePath>..\..\..\components\libc\compilers\common\cstdio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cstdlib.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cstring.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstring.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ctime.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cwchar.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cwchar.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>div0.c</FileName>
@ -435,9 +470,9 @@
</Files>
<Files>
<File>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath>
</File>
</Files>
<Files>
@ -447,16 +482,30 @@
<FilePath>..\..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ringblk_buf.c</FileName>
@ -471,20 +520,6 @@
<FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>waitqueue.c</FileName>
@ -492,13 +527,6 @@
<FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>workqueue.c</FileName>
@ -523,6 +551,13 @@
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>startup_apm32f10x_hd.s</FileName>
@ -532,9 +567,9 @@
</Files>
<Files>
<File>
<FileName>board.c</FileName>
<FileName>drv_common.c</FileName>
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
<FilePath>..\libraries\Drivers\drv_common.c</FilePath>
</File>
</Files>
<Files>
@ -551,11 +586,35 @@
<FilePath>..\libraries\Drivers\drv_usart.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Filesystem</GroupName>
<Files>
<File>
<FileName>drv_common.c</FileName>
<FileName>dfs_posix.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_common.c</FilePath>
<FilePath>..\..\..\components\dfs\src\dfs_posix.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs_fs.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs_fs.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs_file.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs_file.c</FilePath>
</File>
</Files>
</Group>
@ -575,6 +634,13 @@
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_parse.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmd.c</FileName>
@ -582,23 +648,16 @@
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_file.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>clock.c</FileName>
@ -606,27 +665,6 @@
<FilePath>..\..\..\src\clock.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\thread.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\irq.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\scheduler.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>components.c</FileName>
@ -634,13 +672,6 @@
<FilePath>..\..\..\src\components.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\timer.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>device.c</FileName>
@ -648,20 +679,6 @@
<FilePath>..\..\..\src\device.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\kservice.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mempool.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>idle.c</FileName>
@ -669,6 +686,27 @@
<FilePath>..\..\..\src\idle.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\irq.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\kservice.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mem.c</FileName>
@ -676,6 +714,41 @@
<FilePath>..\..\..\src\mem.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mempool.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\scheduler.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\thread.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\timer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Libraries</GroupName>

49
bsp/apm32/apm32f103xe-minibroard/rtconfig.h
View File

@ -17,11 +17,14 @@
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
@ -43,8 +46,8 @@
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40100
#define RT_CONSOLE_DEVICE_NAME "uart"
#define RT_VER_NUM 0x40101
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
@ -69,6 +72,12 @@
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
/* Device Drivers */
@ -125,58 +134,24 @@
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* POSIX extension functions */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* AI packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
#define SOC_FAMILY_APM32
#define SOC_SERIES_APM32F1

40
bsp/apm32/apm32f103xe-minibroard/rtconfig.py
View File

@ -23,7 +23,7 @@ elif CROSS_TOOL == 'keil':
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
EXEC_PATH = r'E:\IAR'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@ -46,7 +46,7 @@ if PLATFORM == 'gcc':
DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
@ -73,7 +73,7 @@ elif PLATFORM == 'armcc':
DEVICE = ' --cpu Cortex-M3 '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
@ -93,6 +93,40 @@ elif PLATFORM == 'armcc':
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'armclang':
# toolchains
CC = 'armclang'
CXX = 'armclang'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M1.fp '
CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m0 '
CFLAGS += ' -mcpu=cortex-m0 '
CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
CFLAGS += ' -gdwarf-3 -ffunction-sections '
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
LFLAGS += ' --list rt-thread.map '
LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
EXEC_PATH += '/ARM/ARMCLANG/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O1' # armclang recommend
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iccarm':
# toolchains
CC = 'iccarm'

10
bsp/apm32/apm32f103xe-minibroard/template.ewp
View File

@ -49,16 +49,16 @@
<option>
<name>GRuntimeLibSelect</name>
<version>0</version>
<state>1</state>
<state>2</state>
</option>
<option>
<name>GRuntimeLibSelectSlave</name>
<version>0</version>
<state>1</state>
<state>2</state>
</option>
<option>
<name>RTDescription</name>
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
<state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
</option>
<option>
<name>OGProductVersion</name>
@ -112,7 +112,7 @@
</option>
<option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
<state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>
</option>
<option>
<name>GBECoreSlave</name>
@ -653,7 +653,7 @@
</option>
<option>
<name>OOCOutputFile</name>
<state>../../../rtthread.bin</state>
<state>../../rtthread.bin</state>
</option>
<option>
<name>OOCCommandLineProducer</name>

447
bsp/apm32/apm32f407ig-minibroard/.config Normal file
View File

@ -0,0 +1,447 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
CONFIG_RT_VER_NUM=0x40101
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# C/C++ and POSIX layer
#
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_MQTTCLIENT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
CONFIG_SOC_FAMILY_APM32=y
CONFIG_SOC_SERIES_APM32F4=y
#
# Hardware Drivers Config
#
CONFIG_SOC_APM32F407IG=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_WDT is not set

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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "board/Kconfig"

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# APM32F103ZE MINI BOARD BSP 说明
## 简介
本文档为 APM32F407IG MINI 开发板（MINI BOARD）的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
## 开发板介绍
APM32F407IG MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO。开发板外观如下图所示：
![board](figures/APM32F407IG.png)
- 有关开发板和芯片的详情可至极海官网查阅。[官网开发板链接 ](https://www.geehy.com/support/apm32?id=192)
该开发板常用 **板载资源** 如下：
- MCU：APM32F407IGT6，主频 168MHz，1MKB FLASH ，192+4KB RAM
- 外部 RAM：无
- 外部 FLASH：无
- 常用外设
- LED：2个，（黄色，PE5/PE6）
- 按键：2个，K1（PA1），K2（PA0）
- 常用接口：RS232转串口、USB SLAVE
- 调试接口：标准 JTAG/SWD
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :------------------------------------ |
| RS232转串口 | 支持 | 使用 UART1/ UART2(通过跳线选择) |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA0, PA1... PI11 ---> PIN: 0, 1...134 |
| UART | 支持 | UART1/2 |
| ADC | 支持 | ADC1/2/3 |
| DAC | 支持 | DAC1 |
| RTC | 支持 | 支持外部晶振和内部低速时钟 |
| TMR | 支持 | TMR1/2/3/4/5/6/7/8/9/10/11/12/13/14 |
| PWM | 支持 | TMR3 ->CH1/2/3/4 |
| I2C | 支持 | 软件I2C |
| SPI | 支持 | SPI1/2/3 |
| WDT | 支持 | IWDT |
## 使用说明
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
### 快速上手
本 BSP 为开发者提供MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
- 方式一：MDK
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
- 方式二：J-Flash下载
通过ENV工具的scons指令或MDK编译出bin文件后，再使用J-Flash工具将bin文件下载至开发板即可，大致步骤如下：
##### 1、建立J-Flash工程
![board](figures/JFlash_Leader_01.png)
##### 2、连接开发板
![board](figures/JFlash_Leader_02.png)
##### 3、将bin文件拖至工程，起始地址设为0x8000000
![board](figures/JFlash_Leader_03.png)
##### 4、点击下载
![board](figures/JFlash_Leader_04.png)
#### 运行结果
下载程序成功之后，系统会自动运行，LED 闪烁
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.1.0 build Aug 20 2021
2006 - 2021 Copyright by rt-thread team
msh >
```
## 注意事项
- 可在极海官方网站进行所需资料下载，如pack安装包和MINI开发板原理图等（www.geehy.com）;
## 联系人信息
-[abbbcc ](https://gitee.com/abbbcc)
-[Aligagago ](https://github.com/Aligagago)

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
apm32_library = 'APM32F4xx_Library'
rtconfig.BSP_LIBRARY_TYPE = apm32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, apm32_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-20 Abbcc first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
/* defined the LED2 pin: PE6 */
#define LED2_PIN GET_PIN(E, 6)
int main(void)
{
uint32_t sysclock = 0;
/* set LED2 pin mode to output */
rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
/* Print system clock */
sysclock = RCM_ReadSYSCLKFreq();
rt_kprintf("Read: Sec = %d, Usec = 0x%08X\n", sysclock, sysclock);
while (1)
{
rt_pin_write(LED2_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED2_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}

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menu "Hardware Drivers Config"
config SOC_APM32F407IG
bool
select SOC_SERIES_APM32F4
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_UART2
bool "Enable UART2"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
config BSP_USING_ADC2
bool "Enable ADC2"
default n
config BSP_USING_ADC3
bool "Enable ADC3"
default n
endif
menuconfig BSP_USING_DAC
bool "Enable DAC"
default n
select RT_USING_DAC
if BSP_USING_DAC
config BSP_USING_DAC1
bool "Enable DAC1"
default n
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_ONCHIP_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 0 63
default 22
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0 63
default 23
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1"
default n
config BSP_USING_SPI2
bool "Enable SPI2"
default n
config BSP_USING_SPI3
bool "Enable SPI3"
default n
endif
menuconfig BSP_USING_TMR
bool "Enable Timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TMR
config BSP_USING_TMR1
bool "Enable TMR1"
default n
config BSP_USING_TMR2
bool "Enable TMR2"
default n
config BSP_USING_TMR3
bool "Enable TMR3"
default n
config BSP_USING_TMR4
bool "Enable TMR4"
default n
config BSP_USING_TMR5
bool "Enable TMR5"
default n
config BSP_USING_TMR6
bool "Enable TMR6"
default n
config BSP_USING_TMR7
bool "Enable TMR7"
default n
config BSP_USING_TMR8
bool "Enable TMR8"
default n
config BSP_USING_TMR9
bool "Enable TMR9"
default n
config BSP_USING_TMR10
bool "Enable TMR10"
default n
config BSP_USING_TMR11
bool "Enable TMR11"
default n
config BSP_USING_TMR12
bool "Enable TMR12"
default n
config BSP_USING_TMR13
bool "Enable TMR13"
default n
config BSP_USING_TMR14
bool "Enable TMR14"
default n
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
menuconfig BSP_USING_PWM3
bool "Enable timer3 output PWM"
default n
if BSP_USING_PWM3
config BSP_USING_PWM3_CH1
bool "Enable PWM3 channel1"
default n
config BSP_USING_PWM3_CH2
bool "Enable PWM3 channel2"
default n
config BSP_USING_PWM3_CH3
bool "Enable PWM3 channel3"
default n
config BSP_USING_PWM3_CH4
bool "Enable PWM3 channel4"
default n
endif
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
endmenu
endmenu

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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
''')
path = [cwd]
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/APM32F4xx_Library/Device/Geehy/APM32F4xx/Source/arm/startup_apm32f40x.s']
if rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/APM32F4xx_Library/Device/Geehy/APM32F4xx/Source/iar/startup_apm32f40x.s']
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/APM32F4xx_Library/Device/Geehy/APM32F4xx/Source/gcc/startup_apm32f40x.s']
# You can select chips from the list above
CPPDEFINES = ['APM32F40X']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-20 Abbcc first version
*/
#include "board.h"
void apm32_usart_init(void)
{
GPIO_Config_T GPIO_ConfigStruct;
#ifdef BSP_USING_UART1
RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOA);
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_USART1);
GPIO_ConfigStruct.mode = GPIO_MODE_AF;
GPIO_ConfigStruct.pin = GPIO_PIN_9;
GPIO_ConfigStruct.otype = GPIO_OTYPE_PP;
GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
GPIO_ConfigPinAF(GPIOA,GPIO_PIN_SOURCE_9,GPIO_AF_USART1);
GPIO_ConfigStruct.mode = GPIO_MODE_IN;
GPIO_ConfigStruct.pin = GPIO_PIN_10;
GPIO_ConfigStruct.pupd = GPIO_PUPD_UP;
GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
GPIO_ConfigPinAF(GPIOA,GPIO_PIN_SOURCE_10,GPIO_AF_USART1);
#endif
#ifdef BSP_USING_UART2
RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOA);
RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2);
GPIO_ConfigStruct.mode = GPIO_MODE_AF;
GPIO_ConfigStruct.pin = GPIO_PIN_2;
GPIO_ConfigStruct.otype = GPIO_OTYPE_PP;
GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
GPIO_ConfigPinAF(GPIOA,GPIO_PIN_SOURCE_2,GPIO_AF_USART2);
GPIO_ConfigStruct.mode = GPIO_MODE_IN;
GPIO_ConfigStruct.pin = GPIO_PIN_3;
GPIO_ConfigStruct.pupd = GPIO_PUPD_UP;
GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
GPIO_ConfigPinAF(GPIOA,GPIO_PIN_SOURCE_3,GPIO_AF_USART2);
#endif
}

81
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-03-28 Abbcc first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include <apm32f4xx.h>
#include "apm32f4xx_gpio.h"
#include "apm32f4xx_rcm.h"
#include "apm32f4xx_misc.h"
#include "apm32f4xx_rcm.h"
#include "apm32f4xx_eint.h"
#include "apm32f4xx_usart.h"
#if defined(RT_USING_ADC)
#include "apm32f4xx_adc.h"
#endif
#if defined(RT_USING_DAC)
#include "apm32f4xx_dac.h"
#endif
#if defined(RT_USING_RTC)
#include "apm32f4xx_rtc.h"
#include "apm32f4xx_pmu.h"
#endif
#if defined(RT_USING_SPI)
#include "apm32f4xx_spi.h"
#endif
#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM)
#include "apm32f4xx_tmr.h"
#endif
#if defined(RT_USING_WDT)
#include "apm32f4xx_iwdt.h"
#include "apm32f4xx_wwdt.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define APM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define APM32_FLASH_SIZE (1024 * 1024)
#define APM32_FLASH_END_ADDRESS ((uint32_t)(APM32_FLASH_START_ADRESS + APM32_FLASH_SIZE))
/* Internal SRAM memory size[Kbytes] <6-128>, Default: 128 */
#define APM32_SRAM_SIZE 128
#define APM32_SRAM_END (0x20000000 + APM32_SRAM_SIZE * 1024)
#if defined(__ARMCC_VERSION)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END APM32_SRAM_END
void SystemClock_Config(void);
void apm32_usart_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H__ */

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0400;
define symbol __ICFEDIT_size_heap__ = 0x0000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK};

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/*
* linker script for APM32F10x with GNU ld
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
} > CODE = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
.stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >DATA
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

17
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00020000 { ; RW data
.ANY (+RW +ZI)
}
}

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\project.ewp</path>
</project>
<batchBuild/>
</workspace>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\keil\List\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0APM32F4xx_1024 -FL080000 -FS08000000 -FP0($$Device:APM32F407IG$Flash\APM32F4xx_1024.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59401308 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0APM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:APM32F407IG$Flash\APM32F4xx_1024.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Group 1</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
</ProjectOpt>

806
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>APM32F407IG</Device>
<Vendor>Geehy</Vendor>
<PackID>Geehy.APM32F4xx_DFP.1.0.1</PackID>
<PackURL>https://www.geehy.com/uploads/tool/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec />
<StartupFile />
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F4xx_1024 -FS08000000 -FL080000 -FP0($$Device:APM32F407IG$Flash\APM32F4xx_1024.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile />
<MemoryEnv />
<Cmp />
<Asm />
<Linker />
<OHString />
<InfinionOptionDll />
<SLE66CMisc />
<SLE66AMisc />
<SLE66LinkerMisc />
<SFDFile>$$Device:APM32F407IG$SVD\APM32F40x.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath />
<IncludePath />
<LibPath />
<RegisterFilePath />
<DBRegisterFilePath />
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name />
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString />
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument />
<IncludeLibraryModules />
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3 />
<Flash4 />
<pFcarmOut />
<pFcarmGrp />
<pFcArmRoot />
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName />
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>4</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x100000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x100000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector />
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls />
<Define>__STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, APM32F40X, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARM_LIBC</Define>
<Undefine />
<IncludePath>applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc;..\libraries\APM32F4xx_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls />
<Define />
<Undefine />
<IncludePath />
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase />
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs />
<IncludeLibsPath />
<Misc />
<LinkerInputFile />
<DisabledWarnings />
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Applications</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>applications\main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Compiler</GroupName>
<Files>
<File>
<FileName>syscall_mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>syscalls.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cctype.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cctype.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cstdio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstdio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cstdlib.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cstring.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstring.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ctime.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cwchar.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cwchar.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>div0.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cpuport.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ringblk_buf.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>startup_apm32f40x.s</FileName>
<FileType>2</FileType>
<FilePath>..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Source\arm\startup_apm32f40x.s</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>drv_common.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_common.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>drv_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_usart.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Filesystem</GroupName>
<Files>
<File>
<FileName>dfs_posix.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs_posix.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs_fs.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs_fs.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs_file.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs_file.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_parse.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_file.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\clock.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\components.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\device.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\idle.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\irq.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\kservice.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mem.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mempool.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\scheduler.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\thread.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\timer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Libraries</GroupName>
<Files>
<File>
<FileName>apm32f4xx_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_usart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f4xx_rcm.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_rcm.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f4xx_eint.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_eint.c</FilePath>
</File>
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<Files>
<File>
<FileName>apm32f4xx_misc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_misc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f4xx_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>system_apm32f4xx.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Source\system_apm32f4xx.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis />
<components />
<files />
</RTE>
</Project>

168
bsp/apm32/apm32f407ig-minibroard/rtconfig.h Normal file
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@ -0,0 +1,168 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart"
#define RT_VER_NUM 0x40101
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* samples: kernel and components samples */
#define SOC_FAMILY_APM32
#define SOC_SERIES_APM32F4
/* Hardware Drivers Config */
#define SOC_APM32F407IG
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
#endif

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import os
# toolchains options
ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='gcc'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
EXEC_PATH = r'E:\IAR'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M4.fp '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'armclang':
# toolchains
CC = 'armclang'
CXX = 'armclang'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M4.fp '
CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 '
CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 '
CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
CFLAGS += ' -gdwarf-3 -ffunction-sections '
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
LFLAGS += ' --list rt-thread.map '
LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
EXEC_PATH += '/ARM/ARMCLANG/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O1' # armclang recommend
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iccarm':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' -e'
CFLAGS += ' --fpu=VFPv4_sp'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu VFPv4_sp'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\keil\List\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0APM32F4xx_1024 -FL080000 -FS08000000 -FP0($$Device:APM32F407IG$Flash\APM32F4xx_1024.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59401308 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0APM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:APM32F407IG$Flash\APM32F4xx_1024.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Group 1</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
</ProjectOpt>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>APM32F407IG</Device>
<Vendor>Geehy</Vendor>
<PackID>Geehy.APM32F4xx_DFP.1.0.1</PackID>
<PackURL>https://www.geehy.com/uploads/tool/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F4xx_1024 -FS08000000 -FL080000 -FP0($$Device:APM32F407IG$Flash\APM32F4xx_1024.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:APM32F407IG$SVD\APM32F40x.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>4</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x100000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x100000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>

100
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_ADC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -71,7 +71,7 @@ typedef enum
ADC_EXT_TRIG_CONV_TMR2_CC2 = ((uint32_t)0x00060000),
ADC_EXT_TRIG_CONV_TMR3_TRGO = ((uint32_t)0x00080000),
ADC_EXT_TRIG_CONV_TMR4_CC4 = ((uint32_t)0x000A0000),
ADC_EXT_TRIG_CONV_EINT9_T8_TRGO = ((uint32_t)0x000C0000),
ADC_EXT_TRIG_CONV_EINT11_T8_TRGO = ((uint32_t)0x000C0000),
ADC_EXT_TRIG_CONV_TMR1_CC3 = ((uint32_t)0x00040000),
ADC_EXT_TRIG_CONV_None = ((uint32_t)0x000E0000),
@ -260,80 +260,80 @@ typedef struct
*/
/** ADC reset and common configuration */
void ADC_Reset(ADC_T *adc);
void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig);
void ADC_ConfigStructInit(ADC_Config_T *adcConfig);
void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
void ADC_Enable(ADC_T *adc);
void ADC_Disable(ADC_T *adc);
void ADC_Reset(ADC_T* adc);
void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig);
void ADC_ConfigStructInit(ADC_Config_T* adcConfig);
void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime);
void ADC_Enable(ADC_T* adc);
void ADC_Disable(ADC_T* adc);
/** ADC for DMA */
void ADC_EnableDMA(ADC_T *adc);
void ADC_DisableDMA(ADC_T *adc);
void ADC_EnableDMA(ADC_T* adc);
void ADC_DisableDMA(ADC_T* adc);
/** ADC Calibration */
void ADC_ResetCalibration(ADC_T *adc);
uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc);
void ADC_StartCalibration(ADC_T *adc);
uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc);
void ADC_ResetCalibration(ADC_T* adc);
uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc);
void ADC_StartCalibration(ADC_T* adc);
uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc);
/** ADC software start conversion */
void ADC_EnableSoftwareStartConv(ADC_T *adc);
void ADC_DisableSoftwareStartConv(ADC_T *adc);
uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc);
void ADC_EnableSoftwareStartConv(ADC_T* adc);
void ADC_DisableSoftwareStartConv(ADC_T* adc);
uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc);
/** ADC Discontinuous mode */
void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number);
void ADC_EnableDiscMode(ADC_T *adc);
void ADC_DisableDiscMode(ADC_T *adc);
void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number);
void ADC_EnableDiscMode(ADC_T* adc);
void ADC_DisableDiscMode(ADC_T* adc);
/** ADC External trigger conversion */
void ADC_EnableExternalTrigConv(ADC_T *adc);
void ADC_DisableExternalTrigConv(ADC_T *adc);
void ADC_EnableExternalTrigConv(ADC_T* adc);
void ADC_DisableExternalTrigConv(ADC_T* adc);
/** ADC Conversion result */
uint16_t ADC_ReadConversionValue(ADC_T *adc);
uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc);
uint16_t ADC_ReadConversionValue(ADC_T* adc);
uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc);
/** ADC Automatic injected group */
void ADC_EnableAutoInjectedConv(ADC_T *adc);
void ADC_DisableAutoInjectedConv(ADC_T *adc);
void ADC_EnableInjectedDiscMode(ADC_T *adc);
void ADC_DisableInjectedDiscMode(ADC_T *adc);
void ADC_EnableAutoInjectedConv(ADC_T* adc);
void ADC_DisableAutoInjectedConv(ADC_T* adc);
void ADC_EnableInjectedDiscMode(ADC_T* adc);
void ADC_DisableInjectedDiscMode(ADC_T* adc);
/** ADC External trigger for injected channels conversion */
void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
void ADC_EnableExternalTrigInjectedConv(ADC_T *adc);
void ADC_DisableExternalTrigInjectedConv(ADC_T *adc);
void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
void ADC_EnableExternalTrigInjectedConv(ADC_T* adc);
void ADC_DisableExternalTrigInjectedConv(ADC_T* adc);
/** ADC Start of the injected channels conversion */
void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc);
void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc);
uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc);
void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc);
void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc);
uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc);
/** ADC injected channel */
void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length);
void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel);
void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length);
void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel);
/** ADC analog watchdog */
void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog);
void ADC_DisableAnalogWatchdog(ADC_T *adc);
void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold);
void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel);
void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog);
void ADC_DisableAnalogWatchdog(ADC_T* adc);
void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold);
void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel);
/** ADC temperature sensor */
void ADC_EnableTempSensorVrefint(ADC_T *adc);
void ADC_DisableTempSensorVrefint(ADC_T *adc);
void ADC_EnableTempSensorVrefint(ADC_T* adc);
void ADC_DisableTempSensorVrefint(ADC_T* adc);
/** Interrupt and flag */
void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt);
void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt);
uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag);
void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag);
uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag);
void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag);
void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt);
void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt);
uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag);
void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag);
uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag);
void ADC_ClearIntFlag(ADC_T* adc, uint16_t flag);
/**@} end of group ADC_Fuctions*/
/**@} end of group ADC_Driver*/

2
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_BAKPR_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"

52
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_CAN_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -302,41 +302,41 @@ typedef struct
*/
/** CAN reset and configuration */
void CAN_Reset(CAN_T *can);
uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig);
void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig);
void CAN_ConfigStructInit(CAN_Config_T *canConfig);
void CAN_EnableDBGFreeze(CAN_T *can);
void CAN_DisableDBGFreeze(CAN_T *can);
void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum);
void CAN_Reset(CAN_T* can);
uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig);
void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig);
void CAN_ConfigStructInit(CAN_Config_T* canConfig);
void CAN_EnableDBGFreeze(CAN_T* can);
void CAN_DisableDBGFreeze(CAN_T* can);
void CAN_SlaveStartBank(CAN_T* can, uint8_t bankNum);
/** CAN frames transmit */
uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage);
uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox);
void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox);
uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage);
uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
/** CAN frames receive */
void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage);
void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber);
uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber);
void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage);
void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
/** CAN operation modes */
uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode);
uint8_t CAN_SleepMode(CAN_T *can);
uint8_t CAN_WakeUpMode(CAN_T *can);
uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode);
uint8_t CAN_SleepMode(CAN_T* can);
uint8_t CAN_WakeUpMode(CAN_T* can);
/** CAN bus error management */
uint8_t CAN_ReadLastErrorCode(CAN_T *can);
uint8_t CAN_ReadRxErrorCounter(CAN_T *can);
uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can);
uint8_t CAN_ReadLastErrorCode(CAN_T* can);
uint8_t CAN_ReadRxErrorCounter(CAN_T* can);
uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can);
/** CAN interrupt and flag */
void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupt);
void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupt);
uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag);
void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag);
uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag);
void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag);
void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt);
void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt);
uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag);
void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag);
uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag);
void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag);
/**@} end of group CAN_Fuctions*/
/**@} end of group CAN_Driver*/

2
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_CRC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"

20
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_DAC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -51,7 +51,7 @@ typedef enum
{
DAC_CHANNEL_1 = 0x00000000,
DAC_CHANNEL_2 = 0x00000010
} DAC_CHANNEL_T;
}DAC_CHANNEL_T;
/**
* @brief DAC trigger selection
@ -67,7 +67,7 @@ typedef enum
DAC_TRIGGER_TMR4_TRGO = 0x0000002C,
DAC_TRIGGER_EINT9 = 0x00000034,
DAC_TRIGGER_SOFT = 0x0000003C
} DAC_TRIGGER_T;
}DAC_TRIGGER_T;
/**
* @brief DAC wave generation
@ -77,7 +77,7 @@ typedef enum
DAC_WAVE_GENERATION_NONE = 0x00000000,
DAC_WAVE_GENERATION_NOISE = 0x00000040,
DAC_WAVE_GENERATION_TRIANGLE = 0x00000080
} DAC_WAVE_GENERATION_T;
}DAC_WAVE_GENERATION_T;
/**
* @brief DAC channelx mask/amplitude selector
@ -109,7 +109,7 @@ typedef enum
DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, //!< Triangle amplitude equal to 1023
DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, //!< Triangle amplitude equal to 2047
DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00 //!< Triangle amplitude equal to 4095
} DAC_MASK_AMPLITUDE_SEL_T;
}DAC_MASK_AMPLITUDE_SEL_T;
/**
* @brief DAC output buffer
@ -118,7 +118,7 @@ typedef enum
{
DAC_OUTPUT_BUFFER_ENBALE = 0x00000000,
DAC_OUTPUT_BUFFER_DISABLE = 0x00000002
} DAC_OUTPUT_BUFFER_T;
}DAC_OUTPUT_BUFFER_T;
/**
* @brief DAC data align
@ -128,7 +128,7 @@ typedef enum
DAC_ALIGN_12BIT_R = 0x00000000,
DAC_ALIGN_12BIT_L = 0x00000004,
DAC_ALIGN_8BIT_R = 0x00000008
} DAC_ALIGN_T;
}DAC_ALIGN_T;
/**@} end of group DAC_Enumerations*/
@ -146,7 +146,7 @@ typedef struct
DAC_OUTPUT_BUFFER_T outputBuffer;
DAC_WAVE_GENERATION_T waveGeneration;
DAC_MASK_AMPLITUDE_SEL_T maskAmplitudeSelect;
} DAC_Config_T;
}DAC_Config_T;
/**@} end of group DAC_Structure*/
@ -157,8 +157,8 @@ typedef struct
/** DAC Reset and Configuration */
void DAC_Reset(void);
void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig);
void DAC_ConfigStructInit(DAC_Config_T *dacConfig);
void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig);
void DAC_ConfigStructInit(DAC_Config_T* dacConfig);
void DAC_Enable(DAC_CHANNEL_T channel);
void DAC_Disable(DAC_CHANNEL_T channel);

2
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_DBGMCU_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"

6
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_DMA_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -276,8 +276,8 @@ typedef struct
/** Reset and configuration */
void DMA_Reset(DMA_Channel_T *channel);
void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig);
void DMA_ConfigStructInit(DMA_Config_T *dmaConfig);
void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
void DMA_ConfigStructInit( DMA_Config_T* dmaConfig);
void DMA_Enable(DMA_Channel_T *channel);
void DMA_Disable(DMA_Channel_T *channel);

48
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_DMC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -52,7 +52,7 @@ typedef enum
{
DMC_BANK_WIDTH_1,
DMC_BANK_WIDTH_2
} DMC_BANK_WIDTH_T;
}DMC_BANK_WIDTH_T;
/**
* @brief Row Address Width
@ -65,7 +65,7 @@ typedef enum
DMC_ROW_WIDTH_14,
DMC_ROW_WIDTH_15,
DMC_ROW_WIDTH_16
} DMC_ROW_WIDTH_T;
}DMC_ROW_WIDTH_T;
/**
* @brief Column Address Width
@ -80,7 +80,7 @@ typedef enum
DMC_COL_WIDTH_13,
DMC_COL_WIDTH_14,
DMC_COL_WIDTH_15
} DMC_COL_WIDTH_T;
}DMC_COL_WIDTH_T;
/**
* @brief CAS Latency Select
@ -91,7 +91,7 @@ typedef enum
DMC_CAS_LATENCY_2,
DMC_CAS_LATENCY_3,
DMC_CAS_LATENCY_4
} DMC_CAS_LATENCY_T;
}DMC_CAS_LATENCY_T;
/**
* @brief RAS Minimun Time Select
@ -114,7 +114,7 @@ typedef enum
DMC_RAS_MINIMUM_14,
DMC_RAS_MINIMUM_15,
DMC_RAS_MINIMUM_16
} DMC_RAS_MINIMUM_T;
}DMC_RAS_MINIMUM_T;
/**
* @brief RAS To CAS Delay Time Select
@ -129,7 +129,7 @@ typedef enum
DMC_DELAY_TIME_6,
DMC_DELAY_TIME_7,
DMC_DELAY_TIME_8
} DMC_DELAY_TIME_T;
}DMC_DELAY_TIME_T;
/**
* @brief Precharge Period Select
@ -144,7 +144,7 @@ typedef enum
DMC_PRECHARGE_6,
DMC_PRECHARGE_7,
DMC_PRECHARGE_8
} DMC_PRECHARGE_T;
}DMC_PRECHARGE_T;
/**
* @brief Last Data Next Precharge For Write Time Select
@ -155,7 +155,7 @@ typedef enum
DMC_NEXT_PRECHARGE_2,
DMC_NEXT_PRECHARGE_3,
DMC_NEXT_PRECHARGE_4
} DMC_NEXT_PRECHARGE_T;
}DMC_NEXT_PRECHARGE_T;
/**
* @brief Auto-Refresh Period Select
@ -178,7 +178,7 @@ typedef enum
DMC_AUTO_REFRESH_14,
DMC_AUTO_REFRESH_15,
DMC_AUTO_REFRESH_16,
} DMC_AUTO_REFRESH_T;
}DMC_AUTO_REFRESH_T;
/**
* @brief Active-to-active Command Period Select
@ -201,7 +201,7 @@ typedef enum
DMC_ATA_CMD_14,
DMC_ATA_CMD_15,
DMC_ATA_CMD_16,
} DMC_ATA_CMD_T;
}DMC_ATA_CMD_T;
/**
* @brief Clock PHASE
@ -210,7 +210,7 @@ typedef enum
{
DMC_CLK_PHASE_NORMAL,
DMC_CLK_PHASE_REVERSE
} DMC_CLK_PHASE_T;
}DMC_CLK_PHASE_T;
/**
* @brief DMC Memory Size
@ -231,7 +231,7 @@ typedef enum
DMC_MEMORY_SIZE_64MB,
DMC_MEMORY_SIZE_128MB,
DMC_MEMORY_SIZE_256MB,
} DMC_MEMORY_SIZE_T;
}DMC_MEMORY_SIZE_T;
/**
* @brief Open Banks Of Number
@ -254,7 +254,7 @@ typedef enum
DMC_BANK_NUMBER_14,
DMC_BANK_NUMBER_15,
DMC_BANK_NUMBER_16,
} DMC_BANK_NUMBER_T;
}DMC_BANK_NUMBER_T;
/**
* @brief Full refresh type
@ -263,7 +263,7 @@ typedef enum
{
DMC_REFRESH_ROW_ONE, //!< Refresh one row
DMC_REFRESH_ROW_ALL, //!< Refresh all row
} DMC_REFRESH_T;
}DMC_REFRESH_T;
/**
* @brief Precharge type
@ -272,7 +272,7 @@ typedef enum
{
DMC_PRECHARGE_IM, //!< Immediate precharge
DMC_PRECHARGE_DELAY, //!< Delayed precharge
} DMC_PRECHARE_T;
}DMC_PRECHARE_T;
/**
* @brief WRAP Burst Type
@ -281,7 +281,7 @@ typedef enum
{
DMC_WRAPB_4,
DMC_WRAPB_8,
} DMC_WRPB_T;
}DMC_WRPB_T;
/**@} end of group DMC_Enumerations*/
@ -304,7 +304,7 @@ typedef struct
uint32_t tCMD : 4; //!< DMC_ATA_CMD_T
uint32_t tXSR : 9; //!< auto-refresh commands, can be 0x000 to 0x1FF
uint16_t tRFP : 16; //!< Refresh period, can be 0x0000 to 0xFFFF
} DMC_TimingConfig_T;
}DMC_TimingConfig_T;
/**
* @brief Config struct definition
@ -317,7 +317,7 @@ typedef struct
DMC_COL_WIDTH_T colWidth; //!< Number of col address bits
DMC_CLK_PHASE_T clkPhase; //!< Clock phase
DMC_TimingConfig_T timing; //!< Timing
} DMC_Config_T;
}DMC_Config_T;
/**@} end of group DMC_Structure*/
@ -326,22 +326,22 @@ typedef struct
@{
*/
/** Enable / Disable */
/** Enable / Disable */
void DMC_Enable(void);
void DMC_Disable(void);
void DMC_EnableInit(void);
/** Global config */
void DMC_Config(DMC_Config_T *dmcConfig);
void DMC_ConfigStructInit(DMC_Config_T *dmcConfig);
void DMC_Config(DMC_Config_T* dmcConfig);
void DMC_ConfigStructInit(DMC_Config_T* dmcConfig);
/** Address */
void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth);
void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth);
/** Timing */
void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig);
void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig);
void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig);
void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig);
void DMC_ConfigStableTimePowerup(uint16_t stableTime);
void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num);
void DMC_ConfigRefreshPeriod(uint16_t period);

6
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_EINT_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -114,8 +114,8 @@ typedef struct
/** Reset and configuration */
void EINT_Reset(void);
void EINT_Config(EINT_Config_T *eintConfig);
void EINT_ConfigStructInit(EINT_Config_T *eintConfig);
void EINT_Config( EINT_Config_T* eintConfig);
void EINT_ConfigStructInit(EINT_Config_T* eintConfig);
/** Interrupt and flag */
void EINT_SelectSWInterrupt(uint32_t line);

28
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_EMMC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -276,8 +276,8 @@ typedef struct
EMMC_WAITE_SIGNAL_T waiteSignal;
EMMC_EXTENDEN_MODE_T extendedMode;
EMMC_WRITE_BURST_T writeBurst;
EMMC_NORSRAMTimingConfig_T *readWriteTimingStruct;
EMMC_NORSRAMTimingConfig_T *writeTimingStruct;
EMMC_NORSRAMTimingConfig_T* readWriteTimingStruct;
EMMC_NORSRAMTimingConfig_T* writeTimingStruct;
} EMMC_NORSRAMConfig_T;
/**
@ -303,8 +303,8 @@ typedef struct
EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
uint32_t TCLRSetupTime;
uint32_t TARSetupTime;
EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
} EMMC_NANDConfig_T;
/**
@ -315,9 +315,9 @@ typedef struct
EMMC_WAIT_FEATURE_T waitFeature;
uint32_t TCLRSetupTime;
uint32_t TARSetupTime;
EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T *IOSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
} EMMC_PCCARDConfig_T;
/**@} end of group EMMC_Structure*/
@ -332,12 +332,12 @@ void EMMC_ResetNAND(EMMC_BANK_NAND_T bank);
void EMMC_ResetPCCard(void);
/** EMMC Configuration */
void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig);
void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig);
void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig);
void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig);
void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig);
void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig);
void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig);
void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig);
void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig);
void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig);
/** EMMC bank control */
void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank);

4
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_FMC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -238,7 +238,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data);
FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page);
FMC_STATUS_T FMC_EnableReadOutProtection(void);
FMC_STATUS_T FMC_DisableReadOutProtection(void);
FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig);
FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig);
uint32_t FMC_ReadUserOptionByte(void);
uint32_t FMC_ReadOptionByteWriteProtection(void);
uint8_t FMC_GetReadProtectionStatus(void);

188
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_GPIO_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -49,10 +49,10 @@ extern "C" {
*/
typedef enum
{
GPIO_SPEED_10MHz = 1,
GPIO_SPEED_20MHz,
GPIO_SPEED_50MHz
} GPIO_SPEED_T;
GPIO_SPEED_10MHz = 1,
GPIO_SPEED_20MHz,
GPIO_SPEED_50MHz
}GPIO_SPEED_T;
/**
* @brief Configuration Mode enumeration
@ -67,7 +67,7 @@ typedef enum
GPIO_MODE_OUT_OD = 0x84, //!< General purpose output Open-drain
GPIO_MODE_AF_PP = 0x88, //!< Alternate function output Push-pull
GPIO_MODE_AF_OD = 0x8C, //!< Alternate function output Open-drain
} GPIO_MODE_T;
}GPIO_MODE_T;
/**
* @brief Definition of the GPIO pins
@ -98,108 +98,108 @@ typedef enum
*/
typedef enum
{
GPIO_NO_REMAP_SPI1 = 0x00000010,
GPIO_REMAP_SPI1 = 0x00000011,
GPIO_NO_REMAP_SPI1 = 0x00000010,
GPIO_REMAP_SPI1 = 0x00000011,
GPIO_NO_REMAP_I2C1 = 0x00000110,
GPIO_REMAP_I2C1 = 0x00000111,
GPIO_NO_REMAP_I2C1 = 0x00000110,
GPIO_REMAP_I2C1 = 0x00000111,
GPIO_NO_REMAP_USART1 = 0x00000210,
GPIO_REMAP_USART1 = 0x00000211,
GPIO_NO_REMAP_USART1 = 0x00000210,
GPIO_REMAP_USART1 = 0x00000211,
GPIO_NO_REMAP_USART2 = 0x00000310,
GPIO_REMAP_USART2 = 0x00000311,
GPIO_NO_REMAP_USART2 = 0x00000310,
GPIO_REMAP_USART2 = 0x00000311,
GPIO_NO_REMAP_USART3 = 0x00000430,
GPIO_PARTIAL_REMAP_USART3 = 0x00000431,
GPIO_FULL_REMAP_USART3 = 0x00000433,
GPIO_NO_REMAP_USART3 = 0x00000430,
GPIO_PARTIAL_REMAP_USART3 = 0x00000431,
GPIO_FULL_REMAP_USART3 = 0x00000433,
GPIO_NO_REMAP_TMR1 = 0x00000630,
GPIO_PARTIAL_REMAP_TMR1 = 0x00000631,
GPIO_FULL_REMAP_TMR1 = 0x00000633,
GPIO_NO_REMAP_TMR1 = 0x00000630,
GPIO_PARTIAL_REMAP_TMR1 = 0x00000631,
GPIO_FULL_REMAP_TMR1 = 0x00000633,
GPIO_NO_REMAP_TMR2 = 0x00000830,
GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831,
GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832,
GPIO_FULL_REMAP_TMR2 = 0x00000833,
GPIO_NO_REMAP_TMR2 = 0x00000830,
GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831,
GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832,
GPIO_FULL_REMAP_TMR2 = 0x00000833,
GPIO_NO_REMAP_TMR3 = 0x00000A30,
GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32,
GPIO_FULL_REMAP_TMR3 = 0x00000A33,
GPIO_NO_REMAP_TMR3 = 0x00000A30,
GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32,
GPIO_FULL_REMAP_TMR3 = 0x00000A33,
GPIO_NO_REMAP_TMR4 = 0x00000C10,
GPIO_REMAP_TMR4 = 0x00000C11,
GPIO_NO_REMAP_TMR4 = 0x00000C10,
GPIO_REMAP_TMR4 = 0x00000C11,
GPIO_NO_REMAP_CAN1 = 0x00000D30,
GPIO_REMAP1_CAN1 = 0x00000D32,
GPIO_REMAP2_CAN1 = 0x00000D33,
GPIO_NO_REMAP_CAN1 = 0x00000D30,
GPIO_REMAP1_CAN1 = 0x00000D32,
GPIO_REMAP2_CAN1 = 0x00000D33,
GPIO_NO_REMAP_PD01 = 0x00000F10,
GPIO_REMAP_PD01 = 0x00000F11,
GPIO_NO_REMAP_PD01 = 0x00000F10,
GPIO_REMAP_PD01 = 0x00000F11,
GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010,
GPIO_REMAP_TMR5CH4_LSI = 0x00001011,
GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010,
GPIO_REMAP_TMR5CH4_LSI = 0x00001011,
GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110,
GPIO_REMAP_ADC1_ETRGINJ = 0x00001111,
GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110,
GPIO_REMAP_ADC1_ETRGINJ = 0x00001111,
GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210,
GPIO_REMAP_ADC1_ETRGREG = 0x00001211,
GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210,
GPIO_REMAP_ADC1_ETRGREG = 0x00001211,
GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310,
GPIO_REMAP_ADC2_ETRGINJ = 0x00001311,
GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310,
GPIO_REMAP_ADC2_ETRGINJ = 0x00001311,
GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410,
GPIO_REMAP_ADC2_ETRGREG = 0x00001411,
GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410,
GPIO_REMAP_ADC2_ETRGREG = 0x00001411,
GPIO_NO_REMAP_CAN2 = 0x00001610,
GPIO_REMAP_CAN2 = 0x00001611,
GPIO_NO_REMAP_CAN2 = 0x00001610,
GPIO_REMAP_CAN2 = 0x00001611,
GPIO_NO_REMAP_SWJ = 0x00001870,
GPIO_REMAP_SWJ_NOJTRST = 0x00001871,
GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872,
GPIO_REMAP_SWJ_DISABLE = 0x00001874,
GPIO_NO_REMAP_SWJ = 0x00001870,
GPIO_REMAP_SWJ_NOJTRST = 0x00001871,
GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872,
GPIO_REMAP_SWJ_DISABLE = 0x00001874,
GPIO_NO_REMAP_EMMC_NADV = 0x00010A10,
GPIO_REMAP_EMMC_NADV = 0x00010A11,
} GPIO_REMAP_T;
GPIO_NO_REMAP_EMMC_NADV = 0x00010A10,
GPIO_REMAP_EMMC_NADV = 0x00010A11,
}GPIO_REMAP_T;
/**
* @brief gpio port source define
*/
typedef enum
{
GPIO_PORT_SOURCE_A,
GPIO_PORT_SOURCE_B,
GPIO_PORT_SOURCE_C,
GPIO_PORT_SOURCE_D,
GPIO_PORT_SOURCE_E,
GPIO_PORT_SOURCE_F,
GPIO_PORT_SOURCE_G,
} GPIO_PORT_SOURCE_T;
GPIO_PORT_SOURCE_A,
GPIO_PORT_SOURCE_B,
GPIO_PORT_SOURCE_C,
GPIO_PORT_SOURCE_D,
GPIO_PORT_SOURCE_E,
GPIO_PORT_SOURCE_F,
GPIO_PORT_SOURCE_G,
}GPIO_PORT_SOURCE_T;
/**
* @brief gpio pin source define
*/
typedef enum
{
GPIO_PIN_SOURCE_0,
GPIO_PIN_SOURCE_1,
GPIO_PIN_SOURCE_2,
GPIO_PIN_SOURCE_3,
GPIO_PIN_SOURCE_4,
GPIO_PIN_SOURCE_5,
GPIO_PIN_SOURCE_6,
GPIO_PIN_SOURCE_7,
GPIO_PIN_SOURCE_8,
GPIO_PIN_SOURCE_9,
GPIO_PIN_SOURCE_10,
GPIO_PIN_SOURCE_11,
GPIO_PIN_SOURCE_12,
GPIO_PIN_SOURCE_13,
GPIO_PIN_SOURCE_14,
GPIO_PIN_SOURCE_15,
} GPIO_PIN_SOURCE_T;
GPIO_PIN_SOURCE_0,
GPIO_PIN_SOURCE_1,
GPIO_PIN_SOURCE_2,
GPIO_PIN_SOURCE_3,
GPIO_PIN_SOURCE_4,
GPIO_PIN_SOURCE_5,
GPIO_PIN_SOURCE_6,
GPIO_PIN_SOURCE_7,
GPIO_PIN_SOURCE_8,
GPIO_PIN_SOURCE_9,
GPIO_PIN_SOURCE_10,
GPIO_PIN_SOURCE_11,
GPIO_PIN_SOURCE_12,
GPIO_PIN_SOURCE_13,
GPIO_PIN_SOURCE_14,
GPIO_PIN_SOURCE_15,
}GPIO_PIN_SOURCE_T;
/**@} end of group GPIO_Enumerations*/
@ -213,10 +213,10 @@ typedef enum
*/
typedef struct
{
uint16_t pin;
GPIO_SPEED_T speed;
GPIO_MODE_T mode;
} GPIO_Config_T;
uint16_t pin;
GPIO_SPEED_T speed;
GPIO_MODE_T mode;
}GPIO_Config_T;
/**@} end of group GPIO_Structure*/
@ -225,25 +225,25 @@ typedef struct
*/
/** Reset and common Configuration */
void GPIO_Reset(GPIO_T *port);
void GPIO_Reset(GPIO_T* port);
void GPIO_AFIOReset(void);
void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig);
void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig);
void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig);
void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig);
/** Read */
uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin);
uint16_t GPIO_ReadInputPort(GPIO_T *port);
uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin);
uint16_t GPIO_ReadOutputPort(GPIO_T *port);
uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin);
uint16_t GPIO_ReadInputPort(GPIO_T* port);
uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin);
uint16_t GPIO_ReadOutputPort(GPIO_T* port);
/** Write */
void GPIO_SetBit(GPIO_T *port, uint16_t pin);
void GPIO_ResetBit(GPIO_T *port, uint16_t pin);
void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue);
void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal);
void GPIO_SetBit(GPIO_T* port, uint16_t pin);
void GPIO_ResetBit(GPIO_T* port, uint16_t pin);
void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue);
void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal);
/** GPIO Configuration */
void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin);
void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin);
void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
void GPIO_EnableEventOutput(void);
void GPIO_DisableEventOutput(void);

96
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_I2C_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -283,59 +283,59 @@ typedef struct
*/
/** I2C reset and configuration */
void I2C_Reset(I2C_T *i2c);
void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig);
void I2C_ConfigStructInit(I2C_Config_T *i2cConfig);
void I2C_Enable(I2C_T *i2c);
void I2C_Disable(I2C_T *i2c);
void I2C_EnableGenerateStart(I2C_T *i2c);
void I2C_DisableGenerateStart(I2C_T *i2c);
void I2C_EnableGenerateStop(I2C_T *i2c);
void I2C_DisableGenerateStop(I2C_T *i2c);
void I2C_EnableAcknowledge(I2C_T *i2c);
void I2C_DisableAcknowledge(I2C_T *i2c);
void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address);
void I2C_EnableDualAddress(I2C_T *i2c);
void I2C_DisableDualAddress(I2C_T *i2c);
void I2C_EnableGeneralCall(I2C_T *i2c);
void I2C_DisableGeneralCall(I2C_T *i2c);
void I2C_Reset(I2C_T* i2c);
void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig);
void I2C_ConfigStructInit(I2C_Config_T* i2cConfig);
void I2C_Enable(I2C_T* i2c);
void I2C_Disable(I2C_T* i2c);
void I2C_EnableGenerateStart(I2C_T* i2c);
void I2C_DisableGenerateStart(I2C_T* i2c);
void I2C_EnableGenerateStop(I2C_T* i2c);
void I2C_DisableGenerateStop(I2C_T* i2c);
void I2C_EnableAcknowledge(I2C_T* i2c);
void I2C_DisableAcknowledge(I2C_T* i2c);
void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address);
void I2C_EnableDualAddress(I2C_T* i2c);
void I2C_DisableDualAddress(I2C_T* i2c);
void I2C_EnableGeneralCall(I2C_T* i2c);
void I2C_DisableGeneralCall(I2C_T* i2c);
/** Transmit Configuration */
void I2C_TxData(I2C_T *i2c, uint8_t data);
uint8_t I2C_RxData(I2C_T *i2c);
void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction);
uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister);
void I2C_EnableSoftwareReset(I2C_T *i2c);
void I2C_DisableSoftwareReset(I2C_T *i2c);
void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition);
void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState);
void I2C_EnablePECTransmit(I2C_T *i2c);
void I2C_DisablePECTransmit(I2C_T *i2c);
void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition);
void I2C_EnablePEC(I2C_T *i2c);
void I2C_DisablePEC(I2C_T *i2c);
uint8_t I2C_ReadPEC(I2C_T *i2c);
void I2C_EnableARP(I2C_T *i2c);
void I2C_DisableARP(I2C_T *i2c);
void I2C_EnableStretchClock(I2C_T *i2c);
void I2C_DisableStretchClock(I2C_T *i2c);
void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle);
void I2C_TxData(I2C_T* i2c, uint8_t data);
uint8_t I2C_RxData(I2C_T* i2c);
void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction);
uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister);
void I2C_EnableSoftwareReset(I2C_T* i2c);
void I2C_DisableSoftwareReset(I2C_T* i2c);
void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition);
void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState);
void I2C_EnablePECTransmit(I2C_T* i2c);
void I2C_DisablePECTransmit(I2C_T* i2c);
void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition);
void I2C_EnablePEC(I2C_T* i2c);
void I2C_DisablePEC(I2C_T* i2c);
uint8_t I2C_ReadPEC(I2C_T* i2c);
void I2C_EnableARP(I2C_T* i2c);
void I2C_DisableARP(I2C_T* i2c);
void I2C_EnableStretchClock(I2C_T* i2c);
void I2C_DisableStretchClock(I2C_T* i2c);
void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle);
/** DMA */
void I2C_EnableDMA(I2C_T *i2c);
void I2C_DisableDMA(I2C_T *i2c);
void I2C_EnableDMALastTransfer(I2C_T *i2c);
void I2C_DisableDMALastTransfer(I2C_T *i2c);
void I2C_EnableDMA(I2C_T* i2c);
void I2C_DisableDMA(I2C_T* i2c);
void I2C_EnableDMALastTransfer(I2C_T* i2c);
void I2C_DisableDMALastTransfer(I2C_T* i2c);
/** Interrupts and flags */
void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt);
void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt);
uint8_t I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent);
uint32_t I2C_ReadLastEvent(I2C_T *i2c);
uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag);
void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag);
uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag);
void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag);
void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt);
void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt);
uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent);
uint32_t I2C_ReadLastEvent(I2C_T* i2c);
uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag);
void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag);
/**@} end of group I2C_Fuctions*/
/**@} end of group I2C_Driver*/

10
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_IWDT_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -51,7 +51,7 @@ typedef enum
{
IWDT_KEYWORD_RELOAD = 0xAAAA,
IWDT_KEYWORD_ENABLE = 0xCCCC
} IWDT_KEYWORD_T;
}IWDT_KEYWORD_T;
/**
* @brief IWDT Write Access define
@ -60,7 +60,7 @@ typedef enum
{
IWDT_WRITEACCESS_ENABLE = 0x5555,
IWDT_WRITEACCESS_DISABLE = 0x0000
} IWDT_WRITEACCESS_T;
}IWDT_WRITEACCESS_T;
/**
* @brief IWDT Divider
@ -74,7 +74,7 @@ typedef enum
IWDT_DIVIDER_64 = 0x04,
IWDT_DIVIDER_128 = 0x05,
IWDT_DIVIDER_256 = 0x06
} IWDT_DIVIDER_T;
}IWDT_DIVIDER_T;
/**
* @brief IWDT Flag
@ -83,7 +83,7 @@ typedef enum
{
IWDT_FLAG_PSCU = BIT0,
IWDT_FLAG_CNTU = BIT1
} IWDT_FLAG_T;
}IWDT_FLAG_T;
/**@} end of group IWDT_Enumerations*/

24
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h
View File

@ -28,7 +28,7 @@
#define __APM32F10X_MISC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -50,19 +50,19 @@ extern "C" {
*/
typedef enum
{
NVIC_VECT_TAB_RAM = 0x20000000,
NVIC_VECT_TAB_FLASH = 0x08000000,
} NVIC_VECT_TAB_T;
NVIC_VECT_TAB_RAM = 0x20000000,
NVIC_VECT_TAB_FLASH = 0x08000000,
}NVIC_VECT_TAB_T;
/**
* @brief system low power mode
*/
typedef enum
{
NVIC_LOWPOWER_SEVONPEND = 0x10,
NVIC_LOWPOWER_SLEEPDEEP = 0x04,
NVIC_LOWPOWER_SLEEPONEXIT = 0x02
} NVIC_LOWPOWER_T;
NVIC_LOWPOWER_SEVONPEND = 0x10,
NVIC_LOWPOWER_SLEEPDEEP = 0x04,
NVIC_LOWPOWER_SLEEPONEXIT = 0x02
}NVIC_LOWPOWER_T;
/**
* @brief nvic priority group
@ -74,16 +74,16 @@ typedef enum
NVIC_PRIORITY_GROUP_2 = 0x500, //!< 2 bits for pre-emption priority,2 bits for subpriority
NVIC_PRIORITY_GROUP_3 = 0x400, //!< 3 bits for pre-emption priority,1 bits for subpriority
NVIC_PRIORITY_GROUP_4 = 0x300 //!< 4 bits for pre-emption priority,0 bits for subpriority
} NVIC_PRIORITY_GROUP_T;
}NVIC_PRIORITY_GROUP_T;
/**
* @brief SysTick Clock source
*/
typedef enum
{
SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00,
SYSTICK_CLK_SOURCE_HCLK = 0x01
} SYSTICK_CLK_SOURCE_T;
SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00,
SYSTICK_CLK_SOURCE_HCLK = 0x01
}SYSTICK_CLK_SOURCE_T;
/**@} end of group MISC_Enumerations*/

2
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_PMU_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"

30
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_QSPI_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -52,7 +52,7 @@ typedef enum
QSPI_FRF_STANDARD, //!< Standard mode
QSPI_FRF_DUAL, //!< Dual SPI
QSPI_FRF_QUAD //!< QUAD SPI
} QSPI_FRF_T;
}QSPI_FRF_T;
/**
* @brief Transmission mode
@ -63,7 +63,7 @@ typedef enum
QSPI_TRANS_MODE_TX, //!< TX mode only
QSPI_TRANS_MODE_RX, //!< RX mode only
QSPI_TRANS_MODE_EEPROM_READ //!< EEPROM read mode
} QSPI_TRANS_MODE_T;
}QSPI_TRANS_MODE_T;
/**
* @brief Clock polarity
@ -72,7 +72,7 @@ typedef enum
{
QSPI_CLKPOL_LOW,
QSPI_CLKPOL_HIGH
} QSPI_CLKPOL_T;
}QSPI_CLKPOL_T;
/**
* @brief Clock phase
@ -81,7 +81,7 @@ typedef enum
{
QSPI_CLKPHA_1EDGE,
QSPI_CLKPHA_2EDGE
} QSPI_CLKPHA_T;
}QSPI_CLKPHA_T;
/**
* @brief Data format size
@ -117,7 +117,7 @@ typedef enum
QSPI_DFS_30BIT,
QSPI_DFS_31BIT,
QSPI_DFS_32BIT
} QSPI_DFS_T;
}QSPI_DFS_T;
/**
* @brief QSPI flag
@ -130,7 +130,7 @@ typedef enum
QSPI_FLAG_RFNE = BIT3, //!< RX FIFO not empty flag
QSPI_FLAG_RFF = BIT4, //!< RX FIFO full flag
QSPI_FLAG_DCE = BIT6 //!< Data collision error
} QSPI_FLAG_T;
}QSPI_FLAG_T;
/**
* @brief QSPI interrupt source
@ -143,7 +143,7 @@ typedef enum
QSPI_INT_RFO = BIT3, //!< RX FIFO overflow interrupt
QSPI_INT_RFF = BIT4, //!< RX FIFO full interrupt
QSPI_INT_MST = BIT5 //!< Master interrupt
} QSPI_INT_T;
}QSPI_INT_T;
/**
* @brief QSPI interrupt flag
@ -156,7 +156,7 @@ typedef enum
QSPI_INT_FLAG_RFO = BIT3, //!< RX FIFO overflow interrupt flag
QSPI_INT_FLAG_RFF = BIT4, //!< RX FIFO full interrupt flag
QSPI_INT_FLAG_MST = BIT5 //!< Master interrupt flag
} QSPI_INT_FLAG_T;
}QSPI_INT_FLAG_T;
/**
* @brief Reception sample edge
@ -165,7 +165,7 @@ typedef enum
{
QSPI_RSE_RISING,
QSPI_RSE_FALLING
} QSPI_RSE_T;
}QSPI_RSE_T;
/**
* @brief Instruction length
@ -176,7 +176,7 @@ typedef enum
QSPI_INST_LEN_4BIT,
QSPI_INST_LEN_8BIT,
QSPI_INST_LEN_16BIT
} QSPI_INST_LEN_T;
}QSPI_INST_LEN_T;
/**
* @brief QSPI address length
@ -199,7 +199,7 @@ typedef enum
QSPI_ADDR_LEN_52BIT,
QSPI_ADDR_LEN_56BIT,
QSPI_ADDR_LEN_60BIT
} QSPI_ADDR_LEN_T;
}QSPI_ADDR_LEN_T;
/**
* @brief Instruction and address transmission mode
@ -209,7 +209,7 @@ typedef enum
QSPI_INST_ADDR_TYPE_STANDARD,
QSPI_INST_TYPE_STANDARD,
QSPI_INST_ADDR_TYPE_FRF
} QSPI_INST_ADDR_TYPE_T;
}QSPI_INST_ADDR_TYPE_T;
/**
* @brief Slave Select Toggle
@ -218,7 +218,7 @@ typedef enum
{
QSPI_SST_DISABLE,
QSPI_SST_ENABLE
} QSPI_SST_T;
}QSPI_SST_T;
/**@} end of group QSPI_Enumerations*/
@ -269,7 +269,7 @@ typedef struct
QSPI_CLKPOL_T clockPolarity; //!< Clock polarity
QSPI_CLKPHA_T clockPhase; //!< Clock phase
QSPI_DFS_T dataFrameSize; //!< Data frame size
} QSPI_Config_T;
}QSPI_Config_T;
/**@} end of group QSPI_Structure*/

4
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_RCM_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -339,7 +339,7 @@ void RCM_DisableRTCCLK(void);
/** Reads the clock frequency */
uint32_t RCM_ReadSYSCLKFreq(void);
uint32_t RCM_ReadHCLKFreq(void);
void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2);
void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2);
uint32_t RCM_ReadADCCLKFreq(void);
/** Enable or disable Periph Clock */

4
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_RTC_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -78,7 +78,7 @@ void RTC_ConfigPrescaler(uint32_t value);
void RTC_ConfigAlarm(uint32_t value);
uint32_t RTC_ReadDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchor(void);
void RTC_WaitForSynchro(void);
/** Interrupts and flags */
void RTC_EnableInterrupt(uint16_t interrupt);

24
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_SCI2C_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -52,7 +52,7 @@ typedef enum
SCI2C_SPEED_STANDARD = 1,
SCI2C_SPEED_FAST,
SCI2C_SPEED_HIGH
} SCI2C_SPEED_T;
}SCI2C_SPEED_T;
/**
* @brief Address mode
@ -61,7 +61,7 @@ typedef enum
{
SCI2C_ADDR_MODE_7BIT,
SCI2C_ADDR_MODE_10BIT
} SCI2C_ADDR_MODE_T;
}SCI2C_ADDR_MODE_T;
/**
* @brief SCI2C mode enumeration
@ -70,7 +70,7 @@ typedef enum
{
SCI2C_MODE_MASTER,
SCI2C_MODE_SLAVE
} SCI2C_MODE_T;
}SCI2C_MODE_T;
/**
* @brief Restart enable or disable
@ -79,7 +79,7 @@ typedef enum
{
SCI2C_RESTART_DISABLE,
SCI2C_RESTART_ENABLE
} SCI2C_RESTART_T;
}SCI2C_RESTART_T;
/**
* @brief Enable or disable generate stop condition
@ -88,7 +88,7 @@ typedef enum
{
SCI2C_STOP_DISABLE,
SCI2C_STOP_ENABLE
} SCI2C_STOP_T;
}SCI2C_STOP_T;
/**
* @brief Data direction
*/
@ -96,7 +96,7 @@ typedef enum
{
SCI2C_DATA_DIR_WRITE,
SCI2C_DATA_DIR_READ,
} SCI2C_DATA_DIR_T;
}SCI2C_DATA_DIR_T;
/**
* @brief SCI2C interrupt
@ -118,7 +118,7 @@ typedef enum
SCI2C_INT_RSTAD = BIT12, //!< Restart detect interrupt
SCI2C_INT_MOH = BIT13, //!< Master on hold interrupt
SCI2C_INT_ALL = BIT15 //!< All interrupt
} SCI2C_INT_T;
}SCI2C_INT_T;
/**
* @brief Flag enumeration
@ -135,7 +135,7 @@ typedef enum
SCI2C_FLAG_I2CEN = BIT8 | BIT0, //!< I2C enable flag
SCI2C_FLAG_SDWB = BIT8 | BIT1, //!< Slave disable while busy flag
SCI2C_FLAG_SRDL = BIT8 | BIT2 //!< Slave receive data lost flag
} SCI2C_FLAG_T;
}SCI2C_FLAG_T;
/**
* @brief Tx abort source
@ -158,7 +158,7 @@ typedef enum
SCI2C_TAS_SRI = BIT13, //!< Slave read done
SCI2C_TAS_USRARB = BIT14, //!< User abort
SCI2C_TAS_FLUCNT = BIT15 //!< Tx flush counter
} SCI2C_TAS_T;
}SCI2C_TAS_T;
/**
* @brief DMA Enable
@ -167,7 +167,7 @@ typedef enum
{
SCI2C_DMA_RX = BIT0,
SCI2C_DMA_TX = BIT1,
} SCI2C_DMA_T;
}SCI2C_DMA_T;
/**@} end of group SCI2C_Enumerations*/
@ -227,7 +227,7 @@ typedef struct
uint8_t txFifoThreshold; //!< Tx FIFO threshold
SCI2C_RESTART_T restart; //!< Enable or disable restart
SCI2C_ADDR_MODE_T addrMode; //!< Address mode. 7-bit or 10-bit mode.
} SCI2C_Config_T;
}SCI2C_Config_T;
/**@} end of group SCI2C_Structure*/

52
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_SDIO_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -51,7 +51,7 @@ typedef enum
{
SDIO_CLOCK_EDGE_RISING = 0x00000000,
SDIO_CLOCK_EDGE_FALLING = 0x00002000
} SDIO_CLOCK_EDGE_T;
}SDIO_CLOCK_EDGE_T;
/**
* @brief SDIO clock bypass
@ -60,7 +60,7 @@ typedef enum
{
SDIO_CLOCK_BYPASS_DISABLE = 0x00000000,
SDIO_CLOCK_BYPASS_ENABLE = 0x00000400
} SDIO_CLOCK_BYPASS_T;
}SDIO_CLOCK_BYPASS_T;
/**
* @brief SDIO clock power save
@ -69,7 +69,7 @@ typedef enum
{
SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000,
SDIO_CLOCK_POWER_SAVE_ENABLE = 0x00000200
} SDIO_CLOCK_POWER_SAVE_T;
}SDIO_CLOCK_POWER_SAVE_T;
/**
* @brief SDIO bus wide
@ -79,7 +79,7 @@ typedef enum
SDIO_BUS_WIDE_1B = 0x00000000,
SDIO_BUS_WIDE_4B = 0x00000800,
SDIO_BUS_WIDE_8B = 0x00001000
} SDIO_BUS_WIDE_T;
}SDIO_BUS_WIDE_T;
/**
* @brief SDIO hardware flow control
@ -88,7 +88,7 @@ typedef enum
{
SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000,
SDIO_HARDWARE_FLOW_CONTROL_ENABLE = 0x00004000
} SDIO_HARDWARE_FLOW_CONTROL_T;
}SDIO_HARDWARE_FLOW_CONTROL_T;
/**
* @brief SDIO power state
@ -97,7 +97,7 @@ typedef enum
{
SDIO_POWER_STATE_OFF = 0x00000000,
SDIO_POWER_STATE_ON = 0x00000003
} SDIO_POWER_STATE_T;
}SDIO_POWER_STATE_T;
/**
* @brief SDIO interrupt sources
@ -128,7 +128,7 @@ typedef enum
SDIO_INT_RXDA = 0x00200000,
SDIO_INT_SDIOINT = 0x00400000,
SDIO_INT_ATAEND = 0x00800000
} SDIO_INT_T;
}SDIO_INT_T;
/**
* @brief SDIO response
@ -138,7 +138,7 @@ typedef enum
SDIO_RESPONSE_NO = 0x00000000,
SDIO_RESPONSE_SHORT = 0x00000040,
SDIO_RESPONSE_LONG = 0x000000C0
} SDIO_RESPONSE_T;
}SDIO_RESPONSE_T;
/**
* @brief SDIO wait interrupt state
@ -148,7 +148,7 @@ typedef enum
SDIO_WAIT_NO = 0x00000000,
SDIO_WAIT_INT = 0x00000100,
SDIO_WAIT_PEND = 0x00000200
} SDIO_WAIT_T;
}SDIO_WAIT_T;
/**
* @brief SDIO CPSM state
@ -157,7 +157,7 @@ typedef enum
{
SDIO_CPSM_DISABLE = 0x00000000,
SDIO_CPSM_ENABLE = 0x00000400
} SDIO_CPSM_T;
}SDIO_CPSM_T;
/**
* @brief SDIO response registers
@ -168,7 +168,7 @@ typedef enum
SDIO_RES2 = 0x00000004,
SDIO_RES3 = 0x00000008,
SDIO_RES4 = 0x0000000C
} SDIO_RES_T;
}SDIO_RES_T;
/**
* @brief SDIO data block size
@ -190,7 +190,7 @@ typedef enum
SDIO_DATA_BLOCKSIZE_496B = 0x000000C0,
SDIO_DATA_BLOCKSIZE_8192B = 0x000000D0,
SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0
} SDIO_DATA_BLOCKSIZE_T;
}SDIO_DATA_BLOCKSIZE_T;
/**
* @brief SDIO transfer direction
@ -199,7 +199,7 @@ typedef enum
{
SDIO_TRANSFER_DIR_TO_CARD = 0x00000000,
SDIO_TRANSFER_DIR_TO_SDIO = 0x00000002
} SDIO_TRANSFER_DIR_T;
}SDIO_TRANSFER_DIR_T;
/**
* @brief SDIO transfer type
@ -208,7 +208,7 @@ typedef enum
{
SDIO_TRANSFER_MODE_BLOCK = 0x00000000,
SDIO_TRANSFER_MODE_STREAM = 0x00000004
} SDIO_TRANSFER_MODE_T;
}SDIO_TRANSFER_MODE_T;
/**
* @brief SDIO DPSM state
@ -217,7 +217,7 @@ typedef enum
{
SDIO_DPSM_DISABLE = 0x00000000,
SDIO_DPSM_ENABLE = 0x00000001
} SDIO_DPSM_T;
}SDIO_DPSM_T;
/**
* @brief SDIO flag
@ -248,7 +248,7 @@ typedef enum
SDIO_FLAG_RXDA = 0x00200000,
SDIO_FLAG_SDIOINT = 0x00400000,
SDIO_FLAG_ATAEND = 0x00800000
} SDIO_FLAG_T;
}SDIO_FLAG_T;
/**
* @brief SDIO read wait mode
@ -257,7 +257,7 @@ typedef enum
{
SDIO_READ_WAIT_MODE_CLK = 0x00000001,
SDIO_READ_WAIT_MODE_DATA2 = 0x00000000
} SDIO_READ_WAIT_MODE_T;
}SDIO_READ_WAIT_MODE_T;
/**@} end of group SDIO_Enumerations*/
@ -335,7 +335,7 @@ typedef struct
SDIO_BUS_WIDE_T busWide;
SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl;
uint8_t clockDiv;
} SDIO_Config_T;
}SDIO_Config_T;
/**
* @brief SDIO CMD Config structure definition
@ -347,7 +347,7 @@ typedef struct
SDIO_RESPONSE_T response;
SDIO_WAIT_T wait;
SDIO_CPSM_T CPSM;
} SDIO_CmdConfig_T;
}SDIO_CmdConfig_T;
/**
* @brief SDIO Data Config structure definition
@ -360,7 +360,7 @@ typedef struct
SDIO_TRANSFER_DIR_T transferDir;
SDIO_TRANSFER_MODE_T transferMode;
SDIO_DPSM_T DPSM;
} SDIO_DataConfig_T;
}SDIO_DataConfig_T;
/**@} end of group SDIO_Structure*/
@ -371,8 +371,8 @@ typedef struct
/** SDIO reset and configuration */
void SDIO_Reset(void);
void SDIO_Config(SDIO_Config_T *sdioConfig);
void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig);
void SDIO_Config(SDIO_Config_T* sdioConfig);
void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig);
void SDIO_EnableClock(void);
void SDIO_DisableClock(void);
void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState);
@ -384,13 +384,13 @@ void SDIO_DisableDMA(void);
/** Command */
void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig);
void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdconfig);
void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdconfig);
uint8_t SDIO_ReadCommandResponse(void);
uint32_t SDIO_ReadResponse(SDIO_RES_T res);
/** SDIO data configuration */
void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig);
void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig);
void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig);
void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig);
uint32_t SDIO_ReadDataCounter(void);
void SDIO_WriteData(uint32_t data);
uint32_t SDIO_ReadData(void);

102
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_SPI_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -53,7 +53,7 @@ typedef enum
SPI_DIRECTION_2LINES_RXONLY = 0x0400,
SPI_DIRECTION_1LINE_RX = 0x8000,
SPI_DIRECTION_1LINE_TX = 0xC000
} SPI_DIRECTION_T;
}SPI_DIRECTION_T;
/**
* @brief SPI mode
@ -62,7 +62,7 @@ typedef enum
{
SPI_MODE_MASTER = 0x0104,
SPI_MODE_SLAVE = 0x0000
} SPI_MODE_T;
}SPI_MODE_T;
/**
* @brief SPI Data length
@ -71,7 +71,7 @@ typedef enum
{
SPI_DATA_LENGTH_16B = 0x0800,
SPI_DATA_LENGTH_8B = 0x0000
} SPI_DATA_LENGTH_T;
}SPI_DATA_LENGTH_T;
/**
* @brief SPI Clock Polarity
@ -80,7 +80,7 @@ typedef enum
{
SPI_CLKPOL_LOW = 0x0000,
SPI_CLKPOL_HIGH = 0x0002
} SPI_CLKPOL_T;
}SPI_CLKPOL_T;
/**
* @brief SPI Clock Phase
@ -89,7 +89,7 @@ typedef enum
{
SPI_CLKPHA_1EDGE = 0x0000,
SPI_CLKPHA_2EDGE = 0x0001
} SPI_CLKPHA_T;
}SPI_CLKPHA_T;
/**
* @brief SPI Slave Select management
@ -98,7 +98,7 @@ typedef enum
{
SPI_NSS_SOFT = 0x0200,
SPI_NSS_HARD = 0x0000
} SPI_NSS_T;
}SPI_NSS_T;
/**
* @brief SPI BaudRate Prescaler
@ -113,7 +113,7 @@ typedef enum
SPI_BAUDRATE_DIV_64 = 0x0028,
SPI_BAUDRATE_DIV_128 = 0x0030,
SPI_BAUDRATE_DIV_256 = 0x0038,
} SPI_BAUDRATE_DIV_T;
}SPI_BAUDRATE_DIV_T;
/**
* @brief SPI MSB LSB transmission
@ -122,7 +122,7 @@ typedef enum
{
SPI_FIRSTBIT_MSB = 0x0000,
SPI_FIRSTBIT_LSB = 0x0080
} SPI_FIRSTBIT_T;
}SPI_FIRSTBIT_T;
/**
* @brief I2S Mode
@ -133,7 +133,7 @@ typedef enum
I2S_MODE_SLAVE_RX = 0x0100,
I2S_MODE_MASTER_TX = 0x0200,
I2S_MODE_MASTER_RX = 0x0300
} I2S_MODE_T;
}I2S_MODE_T;
/**
* @brief I2S Standard
@ -145,7 +145,7 @@ typedef enum
I2S_STANDARD_LSB = 0x0020,
I2S_STANDARD_PCMSHORT = 0x0030,
I2S_STANDARD_PCMLONG = 0x00B0
} I2S_STANDARD_T;
}I2S_STANDARD_T;
/**
* @brief I2S data length
@ -165,7 +165,7 @@ typedef enum
{
I2S_MCLK_OUTPUT_DISABLE = 0x0000,
I2S_MCLK_OUTPUT_ENABLE = 0x0200,
} I2S_MCLK_OUTPUT_T;
}I2S_MCLK_OUTPUT_T;
/**
* @brief I2S Audio divider
@ -182,7 +182,7 @@ typedef enum
I2S_AUDIO_DIV_11K = 11025,
I2S_AUDIO_DIV_8K = 8000,
I2S_AUDIO_DIV_DEFAULT = 2
} I2S_AUDIO_DIV_T;
}I2S_AUDIO_DIV_T;
/**
* @brief I2S Clock Polarity
@ -191,7 +191,7 @@ typedef enum
{
I2S_CLKPOL_LOW = 0x0000,
I2S_CLKPOL_HIGH = 0x0008
} I2S_CLKPOL_T;
}I2S_CLKPOL_T;
/**
* @brief SPI Direction select
@ -200,7 +200,7 @@ typedef enum
{
SPI_DIRECTION_RX = 0xBFFF,
SPI_DIRECTION_TX = 0x4000
} SPI_DIRECTION_SELECT_T;
}SPI_DIRECTION_SELECT_T;
/**
* @brief SPI interrupts definition
@ -214,7 +214,7 @@ typedef enum
SPI_INT_CRCE = 0x2010,
SPI_INT_ME = 0x2020,
I2S_INT_UDR = 0x2008
} SPI_I2S_INT_T;
}SPI_I2S_INT_T;
/**
* @brief SPI flags definition
@ -229,7 +229,7 @@ typedef enum
SPI_FLAG_ME = 0x0020,
SPI_FLAG_OVR = 0x0040,
SPI_FLAG_BSY = 0x0080
} SPI_FLAG_T;
}SPI_FLAG_T;
/**
* @brief SPI I2S DMA requests
@ -238,7 +238,7 @@ typedef enum
{
SPI_I2S_DMA_REQ_TX = 0x0002,
SPI_I2S_DMA_REQ_RX = 0x0001
} SPI_I2S_DMA_REQ_T;
}SPI_I2S_DMA_REQ_T;
/**@} end of group SPI_Enumerations*/
@ -261,7 +261,7 @@ typedef struct
SPI_DIRECTION_T direction;
SPI_BAUDRATE_DIV_T baudrateDiv;
uint16_t crcPolynomial;
} SPI_Config_T;
}SPI_Config_T;
/**
* @brief I2S Config structure definition
@ -274,7 +274,7 @@ typedef struct
I2S_MCLK_OUTPUT_T MCLKOutput;
I2S_AUDIO_DIV_T audioDiv;
I2S_CLKPOL_T polarity;
} I2S_Config_T;
}I2S_Config_T;
/**@} end of group SPI_Structure*/
@ -283,44 +283,44 @@ typedef struct
*/
/** Reset and Configuration */
void SPI_I2S_Reset(SPI_T *spi);
void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig);
void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig);
void SPI_ConfigStructInit(SPI_Config_T *spiConfig);
void I2S_ConfigStructInit(I2S_Config_T *i2sConfig);
void SPI_Enable(SPI_T *spi);
void SPI_Disable(SPI_T *spi);
void I2S_Enable(SPI_T *spi);
void I2S_Disable(SPI_T *spi);
void SPI_I2S_Reset(SPI_T* spi);
void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig);
void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig);
void SPI_ConfigStructInit(SPI_Config_T* spiConfig);
void I2S_ConfigStructInit(I2S_Config_T* i2sConfig);
void SPI_Enable(SPI_T* spi);
void SPI_Disable(SPI_T* spi);
void I2S_Enable(SPI_T* spi);
void I2S_Disable(SPI_T* spi);
void SPI_I2S_TxData(SPI_T *spi, uint16_t data);
uint16_t SPI_I2S_RxData(SPI_T *spi);
void SPI_SetSoftwareNSS(SPI_T *spi);
void SPI_ResetSoftwareNSS(SPI_T *spi);
void SPI_EnableSSOutput(SPI_T *spi);
void SPI_DisableSSOutput(SPI_T *spi);
void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length);
void SPI_I2S_TxData(SPI_T* spi, uint16_t data);
uint16_t SPI_I2S_RxData(SPI_T* spi);
void SPI_SetSoftwareNSS(SPI_T* spi);
void SPI_ResetSoftwareNSS(SPI_T* spi);
void SPI_EnableSSOutput(SPI_T* spi);
void SPI_DisableSSOutput(SPI_T* spi);
void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length);
/** DMA */
void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq);
void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq);
void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
/** CRC */
void SPI_TxCRC(SPI_T *spi);
void SPI_EnableCRC(SPI_T *spi);
void SPI_DisableCRC(SPI_T *spi);
uint16_t SPI_ReadTxCRC(SPI_T *spi);
uint16_t SPI_ReadRxCRC(SPI_T *spi);
uint16_t SPI_ReadCRCPolynomial(SPI_T *spi);
void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction);
void SPI_TxCRC(SPI_T* spi);
void SPI_EnableCRC(SPI_T* spi);
void SPI_DisableCRC(SPI_T* spi);
uint16_t SPI_ReadTxCRC(SPI_T* spi);
uint16_t SPI_ReadRxCRC(SPI_T* spi);
uint16_t SPI_ReadCRCPolynomial(SPI_T* spi);
void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction);
/** Interrupts and flag */
void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt);
void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt);
uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag);
void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag);
uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag);
void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag);
void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
/**@} end of group SPI_Fuctions*/
/**@} end of group SPI_Driver*/

198
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h
View File

@ -26,7 +26,7 @@
#define __APM32F10X_TMR_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -546,121 +546,121 @@ typedef struct
*/
/** Reset and Configuration */
void TMR_Reset(TMR_T *tmr);
void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig);
void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig);
void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig);
void TMR_Reset(TMR_T* tmr);
void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig);
void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OCConfig);
void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig);
void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig);
void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig);
void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig);
void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig);
void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig);
void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode);
void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision);
void TMR_Enable(TMR_T *tmr);
void TMR_Disable(TMR_T *tmr);
void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig);
void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode);
void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision);
void TMR_Enable(TMR_T* tmr);
void TMR_Disable(TMR_T* tmr);
/** PWM Configuration */
void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig);
void TMR_EnablePWMOutputs(TMR_T *tmr);
void TMR_DisablePWMOutputs(TMR_T *tmr);
void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig);
void TMR_EnablePWMOutputs(TMR_T* tmr);
void TMR_DisablePWMOutputs(TMR_T* tmr);
/** DMA */
void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource);
void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource);
void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource);
void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource);
/** Configuration */
void TMR_ConfigInternalClock(TMR_T *tmr);
void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource);
void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
void TMR_ConfigInternalClock(TMR_T* tmr);
void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource);
void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter);
void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter);
void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter);
void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode);
void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode);
void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
TMR_IC_POLARITY_T IC2Polarity);
void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
void TMR_EnableAutoReload(TMR_T *tmr);
void TMR_DisableAutoReload(TMR_T *tmr);
void TMR_EnableSelectCOM(TMR_T *tmr);
void TMR_DisableSelectCOM(TMR_T *tmr);
void TMR_EnableCCDMA(TMR_T *tmr);
void TMR_DisableCCDMA(TMR_T *tmr);
void TMR_EnableCCPreload(TMR_T *tmr);
void TMR_DisableCCPreload(TMR_T *tmr);
void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
void TMR_EnableUpdate(TMR_T *tmr);
void TMR_DisableUpdate(TMR_T *tmr);
void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource);
void TMR_EnableHallSensor(TMR_T *tmr);
void TMR_DisableHallSensor(TMR_T *tmr);
void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource);
void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode);
void TMR_EnableMasterSlaveMode(TMR_T *tmr);
void TMR_DisableMasterSlaveMode(TMR_T *tmr);
void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter);
void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload);
void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1);
void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2);
void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3);
void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4);
void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
uint16_t TMR_ReadCaputer1(TMR_T *tmr);
uint16_t TMR_ReadCaputer2(TMR_T *tmr);
uint16_t TMR_ReadCaputer3(TMR_T *tmr);
uint16_t TMR_ReadCaputer4(TMR_T *tmr);
uint16_t TMR_ReadCounter(TMR_T *tmr);
uint16_t TMR_ReadPrescaler(TMR_T *tmr);
void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
void TMR_EnableAutoReload(TMR_T* tmr);
void TMR_DisableAutoReload(TMR_T* tmr);
void TMR_EnableSelectCOM(TMR_T* tmr);
void TMR_DisableSelectCOM(TMR_T* tmr);
void TMR_EnableCCDMA(TMR_T* tmr);
void TMR_DisableCCDMA(TMR_T* tmr);
void TMR_EnableCCPreload(TMR_T* tmr);
void TMR_DisableCCPreload(TMR_T* tmr);
void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
void TMR_EnableUpdate(TMR_T* tmr);
void TMR_DisableUpdate(TMR_T* tmr);
void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource);
void TMR_EnableHallSensor(TMR_T* tmr);
void TMR_DisableHallSensor(TMR_T* tmr);
void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource);
void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode);
void TMR_EnableMasterSlaveMode(TMR_T* tmr);
void TMR_DisableMasterSlaveMode(TMR_T* tmr);
void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter);
void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload);
void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1);
void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2);
void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3);
void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4);
void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
uint16_t TMR_ReadCaputer1(TMR_T* tmr);
uint16_t TMR_ReadCaputer2(TMR_T* tmr);
uint16_t TMR_ReadCaputer3(TMR_T* tmr);
uint16_t TMR_ReadCaputer4(TMR_T* tmr);
uint16_t TMR_ReadCounter(TMR_T* tmr);
uint16_t TMR_ReadPrescaler(TMR_T* tmr);
/** Interrupts and Event */
void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt);
void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt);
void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources);
void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt);
void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt);
void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources);
/** flags */
uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag);
void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag);
uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag);
void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag);
uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag);
void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag);
uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag);
void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag);
/**@} end of group TMR_Fuctions*/
/**@} end of group TMR_Driver*/

82
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_USART_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -240,64 +240,64 @@ typedef struct
*/
/** USART Reset and Configuration */
void USART_Reset(USART_T *usart);
void USART_Config(USART_T *uart, USART_Config_T *usartConfig);
void USART_ConfigStructInit(USART_Config_T *usartConfig);
void USART_Address(USART_T *usart, uint8_t address);
void USART_Enable(USART_T *usart);
void USART_Disable(USART_T *usart);
void USART_Reset(USART_T* usart);
void USART_Config(USART_T* uart, USART_Config_T* usartConfig);
void USART_ConfigStructInit(USART_Config_T* usartConfig);
void USART_Address(USART_T* usart, uint8_t address);
void USART_Enable(USART_T* usart);
void USART_Disable(USART_T* usart);
/** Clock communication */
void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig);
void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig);
void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig);
void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig);
/** DMA mode */
void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq);
void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq);
void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq);
void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq);
/** Mute mode */
void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup);
void USART_EnableMuteMode(USART_T *usart);
void USART_DisableMuteMode(USART_T *usart);
void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup);
void USART_EnableMuteMode(USART_T* usart);
void USART_DisableMuteMode(USART_T* usart);
/** LIN mode */
void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length);
void USART_EnableLIN(USART_T *usart);
void USART_DisableLIN(USART_T *usart);
void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length);
void USART_EnableLIN(USART_T* usart);
void USART_DisableLIN(USART_T* usart);
/** Transmit and receive */
void USART_EnableTx(USART_T *usart);
void USART_DisableTx(USART_T *usart);
void USART_EnableRx(USART_T *usart);
void USART_DisableRx(USART_T *usart);
void USART_TxData(USART_T *usart, uint16_t data);
uint16_t USART_RxData(USART_T *usart);
void USART_TxBreak(USART_T *usart);
void USART_EnableTx(USART_T* usart);
void USART_DisableTx(USART_T* usart);
void USART_EnableRx(USART_T* usart);
void USART_DisableRx(USART_T* usart);
void USART_TxData(USART_T* usart, uint16_t data);
uint16_t USART_RxData(USART_T* usart);
void USART_TxBreak(USART_T* usart);
/** Smartcard mode */
void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime);
void USART_ConfigPrescaler(USART_T *usart, uint8_t div);
void USART_EnableSmartCard(USART_T *usart);
void USART_DisableSmartCard(USART_T *usart);
void USART_EnableSmartCardNACK(USART_T *usart);
void USART_DisableSmartCardNACK(USART_T *usart);
void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime);
void USART_ConfigPrescaler(USART_T* usart, uint8_t div);
void USART_EnableSmartCard(USART_T* usart);
void USART_DisableSmartCard(USART_T* usart);
void USART_EnableSmartCardNACK(USART_T* usart);
void USART_DisableSmartCardNACK(USART_T* usart);
/** Half-duplex mode */
void USART_EnableHalfDuplex(USART_T *usart);
void USART_DisableHalfDuplex(USART_T *usart);
void USART_EnableHalfDuplex(USART_T* usart);
void USART_DisableHalfDuplex(USART_T* usart);
/** IrDA mode */
void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode);
void USART_EnableIrDA(USART_T *usart);
void USART_DisableIrDA(USART_T *usart);
void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode);
void USART_EnableIrDA(USART_T* usart);
void USART_DisableIrDA(USART_T* usart);
/** Interrupt and flag */
void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt);
void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt);
uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag);
void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag);
uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag);
void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag);
void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt);
void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt);
uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag);
void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag);
uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag);
void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag);
/**@} end of group USART_Fuctions*/
/**@} end of group USART_Driver*/

4
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h
View File

@ -27,7 +27,7 @@
#define __APM32F10X_WWDT_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "apm32f10x.h"
@ -53,7 +53,7 @@ typedef enum
WWDT_TIME_BASE_2 = 0x00000080,
WWDT_TIME_BASE_4 = 0x00000100,
WWDT_TIME_BASE_8 = 0x00000180
} WWDT_TIME_BASE_T;
}WWDT_TIME_BASE_T;
/**@} end of group WWDT_Enumerations*/

114
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c
View File

@ -47,14 +47,14 @@
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_Reset(ADC_T *adc)
void ADC_Reset(ADC_T* adc)
{
if (adc == ADC1)
if(adc == ADC1)
{
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1);
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1);
}
else if (adc == ADC2)
else if(adc == ADC2)
{
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2);
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2);
@ -77,7 +77,7 @@ void ADC_Reset(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig)
void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig)
{
uint32_t reg;
@ -107,7 +107,7 @@ void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig)
*
* @retval None
*/
void ADC_ConfigStructInit(ADC_Config_T *adcConfig)
void ADC_ConfigStructInit(ADC_Config_T* adcConfig)
{
adcConfig->mode = ADC_MODE_INDEPENDENT;
adcConfig->scanConvMode = DISABLE;
@ -126,7 +126,7 @@ void ADC_ConfigStructInit(ADC_Config_T *adcConfig)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_Enable(ADC_T *adc)
void ADC_Enable(ADC_T* adc)
{
adc->CTRL2_B.ADCEN = BIT_SET;
}
@ -140,7 +140,7 @@ void ADC_Enable(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_Disable(ADC_T *adc)
void ADC_Disable(ADC_T* adc)
{
adc->CTRL2_B.ADCEN = BIT_RESET;
}
@ -154,7 +154,7 @@ void ADC_Disable(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableDMA(ADC_T *adc)
void ADC_EnableDMA(ADC_T* adc)
{
adc->CTRL2_B.DMAEN = BIT_SET;
}
@ -168,7 +168,7 @@ void ADC_EnableDMA(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableDMA(ADC_T *adc)
void ADC_DisableDMA(ADC_T* adc)
{
adc->CTRL2_B.DMAEN = BIT_RESET;
}
@ -182,7 +182,7 @@ void ADC_DisableDMA(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ResetCalibration(ADC_T *adc)
void ADC_ResetCalibration(ADC_T* adc)
{
adc->CTRL2_B.CALRST = BIT_SET;
}
@ -196,7 +196,7 @@ void ADC_ResetCalibration(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc)
uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc)
{
uint8_t ret;
ret = (adc->CTRL2_B.CALRST) ? BIT_SET : BIT_RESET;
@ -212,7 +212,7 @@ uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_StartCalibration(ADC_T *adc)
void ADC_StartCalibration(ADC_T* adc)
{
adc->CTRL2_B.CAL = BIT_SET;
}
@ -226,7 +226,7 @@ void ADC_StartCalibration(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc)
uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc)
{
uint8_t ret;
ret = (adc->CTRL2_B.CAL) ? BIT_SET : BIT_RESET;
@ -242,7 +242,7 @@ uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableSoftwareStartConv(ADC_T *adc)
void ADC_EnableSoftwareStartConv(ADC_T* adc)
{
adc->CTRL2 |= 0x00500000;
}
@ -256,7 +256,7 @@ void ADC_EnableSoftwareStartConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableSoftwareStartConv(ADC_T *adc)
void ADC_DisableSoftwareStartConv(ADC_T* adc)
{
adc->CTRL2 &= 0xFFAFFFFF;
}
@ -270,7 +270,7 @@ void ADC_DisableSoftwareStartConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc)
uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc)
{
uint8_t ret;
ret = (adc->CTRL2_B.REGSWSC) ? BIT_SET : BIT_RESET;
@ -289,7 +289,7 @@ uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number)
void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number)
{
adc->CTRL1_B.DISCNUMCFG |= number - 1;
}
@ -303,7 +303,7 @@ void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableDiscMode(ADC_T *adc)
void ADC_EnableDiscMode(ADC_T* adc)
{
adc->CTRL1_B.REGDISCEN = BIT_SET;
}
@ -317,7 +317,7 @@ void ADC_EnableDiscMode(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableDiscMode(ADC_T *adc)
void ADC_DisableDiscMode(ADC_T* adc)
{
adc->CTRL1_B.REGDISCEN = BIT_RESET;
}
@ -366,11 +366,11 @@ void ADC_DisableDiscMode(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime)
{
uint32_t temp1 = 0;
uint32_t temp2 = 0;
if (channel > ADC_CHANNEL_9)
if(channel > ADC_CHANNEL_9)
{
temp1 = adc->SMPTIM1;
temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10));
@ -389,7 +389,7 @@ void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t
adc->SMPTIM2 = temp1;
}
if (rank < 7)
if(rank < 7)
{
temp1 = adc->REGSEQ3;
temp2 = REGSEQC_SET_REGSEQ3 << (5 * (rank - 1));
@ -398,7 +398,7 @@ void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t
temp1 |= temp2;
adc->REGSEQ3 = temp1;
}
else if (rank < 13)
else if(rank < 13)
{
temp1 = adc->REGSEQ2;
temp2 = REGSEQC_SET_REGSEQ2 << (5 * (rank - 7));
@ -427,7 +427,7 @@ void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableExternalTrigConv(ADC_T *adc)
void ADC_EnableExternalTrigConv(ADC_T* adc)
{
adc->CTRL2_B.REGEXTTRGEN = BIT_SET;
}
@ -441,7 +441,7 @@ void ADC_EnableExternalTrigConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableExternalTrigConv(ADC_T *adc)
void ADC_DisableExternalTrigConv(ADC_T* adc)
{
adc->CTRL2_B.REGEXTTRGEN = BIT_RESET;
}
@ -455,7 +455,7 @@ void ADC_DisableExternalTrigConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
uint16_t ADC_ReadConversionValue(ADC_T *adc)
uint16_t ADC_ReadConversionValue(ADC_T* adc)
{
return (uint16_t) adc->REGDATA;
}
@ -469,7 +469,7 @@ uint16_t ADC_ReadConversionValue(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc)
uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc)
{
return (*(__IOM uint32_t *) RDG_ADDRESS);
}
@ -483,7 +483,7 @@ uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableAutoInjectedConv(ADC_T *adc)
void ADC_EnableAutoInjectedConv(ADC_T* adc)
{
adc->CTRL1_B.INJGACEN = BIT_SET;
}
@ -497,7 +497,7 @@ void ADC_EnableAutoInjectedConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableAutoInjectedConv(ADC_T *adc)
void ADC_DisableAutoInjectedConv(ADC_T* adc)
{
adc->CTRL1_B.INJGACEN = BIT_RESET;
}
@ -511,7 +511,7 @@ void ADC_DisableAutoInjectedConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableInjectedDiscMode(ADC_T *adc)
void ADC_EnableInjectedDiscMode(ADC_T* adc)
{
adc->CTRL1_B.INJDISCEN = BIT_SET;
}
@ -525,7 +525,7 @@ void ADC_EnableInjectedDiscMode(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableInjectedDiscMode(ADC_T *adc)
void ADC_DisableInjectedDiscMode(ADC_T* adc)
{
adc->CTRL1_B.INJDISCEN = BIT_RESET;
}
@ -558,7 +558,7 @@ void ADC_DisableInjectedDiscMode(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
{
adc->CTRL2_B.INJGEXTTRGSEL = RESET;
adc->CTRL2_B.INJGEXTTRGSEL |= extTrigInjecConv;
@ -573,7 +573,7 @@ void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T ex
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableExternalTrigInjectedConv(ADC_T *adc)
void ADC_EnableExternalTrigInjectedConv(ADC_T* adc)
{
adc->CTRL2_B.INJEXTTRGEN = BIT_SET;
}
@ -587,7 +587,7 @@ void ADC_EnableExternalTrigInjectedConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableExternalTrigInjectedConv(ADC_T *adc)
void ADC_DisableExternalTrigInjectedConv(ADC_T* adc)
{
adc->CTRL2_B.INJEXTTRGEN = BIT_RESET;
}
@ -601,7 +601,7 @@ void ADC_DisableExternalTrigInjectedConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc)
void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc)
{
adc->CTRL2_B.INJEXTTRGEN = BIT_SET;
adc->CTRL2_B.INJSWSC = BIT_SET;
@ -616,7 +616,7 @@ void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc)
void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc)
{
adc->CTRL2_B.INJEXTTRGEN = BIT_RESET;
adc->CTRL2_B.INJSWSC = BIT_RESET;
@ -631,7 +631,7 @@ void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc)
uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc)
{
uint8_t ret;
ret = (adc->CTRL2_B.INJSWSC) ? BIT_SET : BIT_RESET;
@ -682,7 +682,7 @@ uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
{
uint32_t temp1 = 0;
uint32_t temp2 = 0;
@ -690,9 +690,9 @@ void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_
if (channel > ADC_CHANNEL_9)
{
temp1 = adc->SMPTIM1;
temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10));
temp2 = SMPCYCCFG_SET_SMPTIM1 << (3*(channel - 10));
temp1 &= ~temp2;
temp2 = (uint32_t)sampleTime << (3 * (channel - 10));
temp2 = (uint32_t)sampleTime << (3*(channel - 10));
temp1 |= temp2;
adc->SMPTIM1 = temp1;
}
@ -706,7 +706,7 @@ void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_
adc->SMPTIM2 = temp1;
}
temp1 = adc->INJSEQ;
temp3 = (temp1 & INJSEQ_SET_INJSEQLEN) >> 20;
temp3 = (temp1 & INJSEQ_SET_INJSEQLEN)>> 20;
temp2 = INJSEQ_SET_INJSEQC << (5 * (uint8_t)((rank + 3) - (temp3 + 1)));
temp1 &= ~temp2;
temp2 = (uint32_t)channel << (5 * (uint8_t)((rank + 3) - (temp3 + 1)));
@ -726,7 +726,7 @@ void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length)
void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length)
{
adc->INJSEQ_B.INJSEQLEN = RESET;
adc->INJSEQ_B.INJSEQLEN |= length - 1;
@ -751,7 +751,7 @@ void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet)
void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet)
{
__IOM uint32_t tmp = 0;
@ -777,14 +777,14 @@ void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel)
uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel)
{
__IOM uint32_t temp = 0;
temp = (uint32_t)adc;
temp += channel + INJDATA_OFFSET;
return (uint16_t)(*(__IOM uint32_t *) temp);
return (uint16_t) (*(__IOM uint32_t*) temp);
}
/*!
@ -806,7 +806,7 @@ uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog)
void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog)
{
adc->CTRL1 &= 0xFF3FFDFF;
adc->CTRL1 |= analogWatchdog;
@ -821,7 +821,7 @@ void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableAnalogWatchdog(ADC_T *adc)
void ADC_DisableAnalogWatchdog(ADC_T* adc)
{
adc->CTRL1 &= 0xFF3FFDFF;
}
@ -841,7 +841,7 @@ void ADC_DisableAnalogWatchdog(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold)
void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold)
{
adc->AWDHT = highThreshold;
adc->AWDLT = lowThreshold;
@ -877,7 +877,7 @@ void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel)
void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel)
{
adc->CTRL1_B.AWDCHSEL = BIT_RESET;
adc->CTRL1 |= channel;
@ -892,7 +892,7 @@ void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableTempSensorVrefint(ADC_T *adc)
void ADC_EnableTempSensorVrefint(ADC_T* adc)
{
adc->CTRL2_B.TSVREFEN = BIT_SET;
}
@ -906,7 +906,7 @@ void ADC_EnableTempSensorVrefint(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableTempSensorVrefint(ADC_T *adc)
void ADC_DisableTempSensorVrefint(ADC_T* adc)
{
adc->CTRL2_B.TSVREFEN = BIT_RESET;
}
@ -926,7 +926,7 @@ void ADC_DisableTempSensorVrefint(ADC_T *adc)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt)
void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt)
{
uint8_t mask;
@ -949,7 +949,7 @@ void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt)
void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt)
{
uint8_t mask;
@ -974,7 +974,7 @@ void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag)
uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag)
{
return (adc->STS & flag) ? SET : RESET;
}
@ -996,7 +996,7 @@ uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag)
void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag)
{
adc->STS = ~(uint32_t)flag;
}
@ -1016,7 +1016,7 @@ void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag)
uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag)
{
uint8_t bitStatus = RESET;
uint32_t itmask = 0;
@ -1051,7 +1051,7 @@ uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag)
*
* @note adc can be ADC1, ADC2 or ADC3.
*/
void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag)
void ADC_ClearIntFlag(ADC_T* adc, uint16_t flag)
{
uint8_t mask = 0;

11
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c
View File

@ -128,19 +128,16 @@ void BAKPR_DisableInterrupt(void)
*/
void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure)
{
if (soure == BAKPR_RTC_OUTPUT_SOURCE_NONE)
if(soure == BAKPR_RTC_OUTPUT_SOURCE_NONE)
{
BAKPR->CLKCAL = RESET;
}
else if (soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK)
} else if(soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK)
{
BAKPR->CLKCAL_B.CALCOEN = BIT_SET;
}
else if (soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM)
} else if(soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM)
{
BAKPR->CLKCAL_B.ASPOEN = BIT_SET;
}
else if (soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND)
} else if(soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND)
{
BAKPR->CLKCAL_B.ASPOSEL = BIT_SET;
}

200
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c
View File

@ -47,7 +47,7 @@
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_Reset(CAN_T *can)
void CAN_Reset(CAN_T* can)
{
if (can == CAN1)
{
@ -72,7 +72,7 @@ void CAN_Reset(CAN_T *can)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
{
uint8_t initStatus = ERROR;
uint32_t wait_ack = 0x00000000;
@ -83,18 +83,18 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
can->MCTRL_B.INITREQ = BIT_SET;
/** Wait the acknowledge */
while (((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF))
while(((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF))
{
wait_ack++;
}
/** Check acknowledge */
if (((can->MSTS_B.INITFLG) != BIT_SET))
if(((can->MSTS_B.INITFLG) != BIT_SET))
{
initStatus = ERROR;
}
else
{
if (canConfig->autoBusOffManage == ENABLE)
if(canConfig->autoBusOffManage == ENABLE)
{
can->MCTRL_B.ALBOFFM = BIT_SET;
}
@ -103,7 +103,7 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
can->MCTRL_B.ALBOFFM = BIT_RESET;
}
if (canConfig->autoWakeUpMode == ENABLE)
if(canConfig->autoWakeUpMode == ENABLE)
{
can->MCTRL_B.AWUPCFG = BIT_SET;
}
@ -112,7 +112,7 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
can->MCTRL_B.AWUPCFG = BIT_RESET;
}
if (canConfig->nonAutoRetran == ENABLE)
if(canConfig->nonAutoRetran == ENABLE)
{
can->MCTRL_B.ARTXMD = BIT_SET;
}
@ -121,7 +121,7 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
can->MCTRL_B.ARTXMD = BIT_RESET;
}
if (canConfig->rxFIFOLockMode == ENABLE)
if(canConfig->rxFIFOLockMode == ENABLE)
{
can->MCTRL_B.RXFLOCK = BIT_SET;
}
@ -130,7 +130,7 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
can->MCTRL_B.RXFLOCK = BIT_RESET;
}
if (canConfig->txFIFOPriority == ENABLE)
if(canConfig->txFIFOPriority == ENABLE)
{
can->MCTRL_B.TXFPCFG = BIT_SET;
}
@ -152,12 +152,12 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
wait_ack = 0;
/** Wait the acknowledge */
while (((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF))
while(((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF))
{
wait_ack++;
}
/** Check acknowledge */
if (((can->MSTS_B.INITFLG) != BIT_RESET))
if(((can->MSTS_B.INITFLG) != BIT_RESET))
{
initStatus = ERROR;
}
@ -180,14 +180,14 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig)
{
can->FCTRL_B.FINITEN = BIT_SET;
can->FACT &= ~(1 << filterConfig->filterNumber);
/** Filter Scale */
if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
if(filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
{
/** 16-bit scale for the filter */
can->FSCFG &= ~(1 << filterConfig->filterNumber);
@ -201,7 +201,7 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
(0x0000FFFF & filterConfig->filterIdHigh);
}
if (filterConfig->filterScale == CAN_FILTER_SCALE_32BIT)
if(filterConfig->filterScale == CAN_FILTER_SCALE_32BIT)
{
can->FSCFG |= (1 << filterConfig->filterNumber);
@ -215,7 +215,7 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
}
/** Filter Mode */
if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
if(filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
{
can->FMCFG &= ~(1 << filterConfig->filterNumber);
}
@ -225,17 +225,17 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
}
/** Filter FIFO assignment */
if (filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
if(filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
{
can->FFASS &= ~(1 << filterConfig->filterNumber);
}
if (filterConfig->filterFIFO == CAN_FILTER_FIFO_1)
if(filterConfig->filterFIFO == CAN_FILTER_FIFO_1)
{
can->FFASS |= (1 << filterConfig->filterNumber);
}
/** Filter activation */
if (filterConfig->filterActivation == ENABLE)
if(filterConfig->filterActivation == ENABLE)
{
can->FACT |= (1 << filterConfig->filterNumber);
}
@ -251,7 +251,7 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_ConfigStructInit(CAN_Config_T *canConfig)
void CAN_ConfigStructInit(CAN_Config_T* canConfig)
{
canConfig->autoBusOffManage = DISABLE;
canConfig->autoWakeUpMode = DISABLE;
@ -274,7 +274,7 @@ void CAN_ConfigStructInit(CAN_Config_T *canConfig)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_EnableDBGFreeze(CAN_T *can)
void CAN_EnableDBGFreeze(CAN_T* can)
{
can->MCTRL_B.DBGFRZE = ENABLE;
}
@ -288,7 +288,7 @@ void CAN_EnableDBGFreeze(CAN_T *can)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_DisableDBGFreeze(CAN_T *can)
void CAN_DisableDBGFreeze(CAN_T* can)
{
can->MCTRL_B.DBGFRZE = DISABLE;
}
@ -300,7 +300,7 @@ void CAN_DisableDBGFreeze(CAN_T *can)
*
* @retval None
*/
void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum)
void CAN_SlaveStartBank(CAN_T* can, uint8_t bankNum)
{
can->FCTRL_B.FINITEN = SET;
can->FCTRL_B.CAN2BN = bankNum;
@ -318,35 +318,33 @@ void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage)
uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage)
{
uint8_t transmit_milbox = 0;
/** Select one empty transmit mailbox */
if ((can->TXSTS & 0x04000000) == 0x04000000)
if((can->TXSTS & 0x04000000) == 0x04000000)
{
transmit_milbox = 0;
}
else if ((can->TXSTS & 0x08000000) == 0x08000000)
else if((can->TXSTS & 0x08000000) == 0x08000000)
{
transmit_milbox = 1;
}
else if ((can->TXSTS & 0x10000000) == 0x10000000)
else if((can->TXSTS & 0x10000000) == 0x10000000)
{
transmit_milbox = 2;
}
else
} else
{
return 3; //!< No mailbox is empty
}
/** Set up the Id */
can->sTxMailBox[transmit_milbox].TXMID &= 0x00000001;
if (TxMessage->typeID == CAN_TYPEID_STD)
if(TxMessage->typeID == CAN_TYPEID_STD)
{
can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->stdID << 21) | (TxMessage->remoteTxReq);
}
else
} else
{
can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->extID << 3) | (TxMessage->typeID) | (TxMessage->remoteTxReq);
}
@ -380,53 +378,45 @@ uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
{
uint32_t state = 0;
switch (TxMailbox)
{
case (CAN_TX_MAILBIX_0):
state = can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000);
case (CAN_TX_MAILBIX_0):
state = can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000);
break;
case (CAN_TX_MAILBIX_1):
state = can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000);
case (CAN_TX_MAILBIX_1):
state = can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000);
break;
case (CAN_TX_MAILBIX_2):
state = can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000);
case (CAN_TX_MAILBIX_2):
state = can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000);
break;
default:
state = 0;
default:
state = 0;
break;
}
switch (state)
{
/** Transmit pending */
case (0x0):
state = 2;
/** Transmit pending */
case (0x0): state = 2;
break;
/** Transmit failed */
case (0x00000001 | 0x04000000):
state = 0;
/** Transmit failed */
case (0x00000001 | 0x04000000): state = 0;
break;
case (0x00000100 | 0x08000000):
state = 0;
case (0x00000100 | 0x08000000): state = 0;
break;
case (0x00010000 | 0x10000000):
state = 0;
case (0x00010000 | 0x10000000): state = 0;
break;
/** Transmit succeeded */
case (0x00000001 | 0x00000002 | 0x04000000):
state = 1;
/** Transmit succeeded */
case (0x00000001 | 0x00000002 | 0x04000000):state = 1;
break;
case (0x00000100 | 0x00000200 | 0x08000000):
state = 1;
case (0x00000100 | 0x00000200 | 0x08000000):state = 1;
break;
case (0x00010000 | 0x00020000 | 0x10000000):
state = 1;
case (0x00010000 | 0x00020000 | 0x10000000):state = 1;
break;
default:
state = 0;
default: state = 0;
break;
}
return (uint8_t) state;
@ -447,7 +437,7 @@ uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
{
switch (TxMailbox)
{
@ -481,11 +471,11 @@ void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage)
void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage)
{
/** Get the Id */
RxMessage->typeID = ((uint8_t)0x04 & (can->sRxMailBox[FIFONumber].RXMID));
if (RxMessage->typeID == CAN_TYPEID_STD)
if(RxMessage->typeID == CAN_TYPEID_STD)
{
RxMessage->stdID = (can->sRxMailBox[FIFONumber].RXMID >> 21) & 0x000007FF;
}
@ -507,7 +497,7 @@ void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMess
RxMessage->data[6] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE6;
RxMessage->data[7] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE7;
if (FIFONumber == CAN_RX_FIFO_0)
if(FIFONumber == CAN_RX_FIFO_0)
{
can->RXF0_B.RFOM0 = BIT_SET;
}
@ -531,9 +521,9 @@ void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMess
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
{
if (FIFONumber == CAN_RX_FIFO_0)
if(FIFONumber == CAN_RX_FIFO_0)
{
can->RXF0_B.RFOM0 = BIT_SET;
}
@ -557,9 +547,9 @@ void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
{
if (FIFONumber == CAN_RX_FIFO_0)
if(FIFONumber == CAN_RX_FIFO_0)
{
return can->RXF0 & 0x03;
}
@ -586,53 +576,53 @@ uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode)
uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
{
uint8_t states = 0;
uint32_t time_out = 0x0000FFFF;
if (operatingMode == CAN_OPERATING_MODE_INIT)
if(operatingMode == CAN_OPERATING_MODE_INIT)
{
can->MCTRL_B.SLEEPREQ = BIT_RESET;
can->MCTRL_B.INITREQ = BIT_SET;
while ((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
while((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
{
time_out --;
}
if ((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET))
if((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET))
{
states = 1;
}
}
else if (operatingMode == CAN_OPERATING_MODE_NORMAL)
else if(operatingMode == CAN_OPERATING_MODE_NORMAL)
{
can->MCTRL_B.SLEEPREQ = BIT_RESET;
can->MCTRL_B.INITREQ = BIT_RESET;
time_out = 0x0000FFFF;
while ((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
while((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
{
time_out --;
}
if ((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET))
if((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET))
{
states = 1;
}
}
else if (operatingMode == CAN_OPERATING_MODE_SLEEP)
else if(operatingMode == CAN_OPERATING_MODE_SLEEP)
{
can->MCTRL_B.SLEEPREQ = BIT_SET;
can->MCTRL_B.INITREQ = BIT_RESET;
time_out = 0x0000FFFF;
while ((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0))
while((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0))
{
time_out --;
}
if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
{
states = 1;
}
@ -651,12 +641,12 @@ uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_SleepMode(CAN_T *can)
uint8_t CAN_SleepMode(CAN_T* can)
{
can->MCTRL_B.SLEEPREQ = BIT_SET;
can->MCTRL_B.INITREQ = BIT_RESET;
if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
{
return 1;
}
@ -674,16 +664,16 @@ uint8_t CAN_SleepMode(CAN_T *can)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_WakeUpMode(CAN_T *can)
uint8_t CAN_WakeUpMode(CAN_T* can)
{
uint32_t time_out = 0x0000FFFF;
can->MCTRL_B.SLEEPREQ = BIT_RESET;
while ((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
while((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
{
time_out --;
}
if (can->MSTS_B.SLEEPFLG == BIT_RESET)
if(can->MSTS_B.SLEEPFLG == BIT_RESET)
{
return 1;
}
@ -699,7 +689,7 @@ uint8_t CAN_WakeUpMode(CAN_T *can)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_ReadLastErrorCode(CAN_T *can)
uint8_t CAN_ReadLastErrorCode(CAN_T* can)
{
return can->ERRSTS_B.LERRC;
}
@ -713,7 +703,7 @@ uint8_t CAN_ReadLastErrorCode(CAN_T *can)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_ReadRxErrorCounter(CAN_T *can)
uint8_t CAN_ReadRxErrorCounter(CAN_T* can)
{
return can->ERRSTS_B.RXERRCNT;
}
@ -727,7 +717,7 @@ uint8_t CAN_ReadRxErrorCounter(CAN_T *can)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can)
uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can)
{
return can->ERRSTS_B.TXERRCNT;
}
@ -758,7 +748,7 @@ uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts)
void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts)
{
can->INTEN |= interrupts;
}
@ -789,7 +779,7 @@ void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts)
void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts)
{
can->INTEN &= ~interrupts;
}
@ -821,13 +811,13 @@ void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
{
uint8_t status = 0;
if ((flag & 0x00F00000) != RESET)
if((flag & 0x00F00000) != RESET )
{
if ((can->ERRSTS & (flag & 0x000FFFFF)) != RESET)
if((can->ERRSTS & (flag & 0x000FFFFF)) != RESET)
{
status = SET;
}
@ -836,9 +826,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
status = RESET;
}
}
else if ((flag & 0x01000000) != RESET)
else if((flag & 0x01000000) != RESET )
{
if ((can->MSTS & (flag & 0x000FFFFF)) != RESET)
if((can->MSTS & (flag & 0x000FFFFF)) != RESET )
{
status = SET;
}
@ -847,9 +837,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
status = RESET ;
}
}
else if ((flag & 0x08000000) != RESET)
else if((flag & 0x08000000) != RESET )
{
if ((can->TXSTS & (flag & 0x000FFFFF)) != RESET)
if((can->TXSTS & (flag & 0x000FFFFF)) != RESET )
{
status = SET;
}
@ -858,9 +848,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
status = RESET;
}
}
else if ((flag & 0x02000000) != RESET)
else if((flag & 0x02000000) != RESET )
{
if ((can->RXF0 & (flag & 0x000FFFFF)) != RESET)
if((can->RXF0 & (flag & 0x000FFFFF)) != RESET )
{
status = SET;
}
@ -871,7 +861,7 @@ uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
}
else
{
if ((can->RXF1 & (flag & 0x000FFFFF)) != RESET)
if((can->RXF1 & (flag & 0x000FFFFF)) != RESET)
{
status = SET;
}
@ -905,27 +895,27 @@ uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag)
void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag)
{
uint32_t flagtmp = 0;
/** ERRSTS register */
if (flag == 0x30F00070)
if(flag == 0x30F00070)
{
can->ERRSTS = RESET;
}
else
{
flagtmp = flag & 0x000FFFFF;
if ((flag & 0x02000000) != RESET)
if((flag & 0x02000000) != RESET)
{
can->RXF0 = flagtmp;
}
else if ((flag & 0x04000000) != RESET)
else if((flag & 0x04000000) != RESET)
{
can->RXF1 = flagtmp;
}
else if ((flag & 0x08000000) != RESET)
else if((flag & 0x08000000) != RESET)
{
can->TXSTS = flagtmp;
}
@ -962,11 +952,11 @@ void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag)
*
* @note CAN2 applies only to APM32F103xC device.
*/
uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag)
uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag)
{
uint8_t status = 0;
if ((can->INTEN & flag) != RESET)
if((can->INTEN & flag) != RESET)
{
switch (flag)
{
@ -1050,7 +1040,7 @@ uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag)
*
* @note CAN2 applies only to APM32F103xC device.
*/
void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag)
void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag)
{
switch (flag)
{

2
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c
View File

@ -75,7 +75,7 @@ uint32_t CRC_CalculateCRC(uint32_t data)
*/
uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen)
{
while (bufLen--)
while(bufLen--)
{
CRC->DATA = *buf++;
}

6
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c
View File

@ -63,7 +63,7 @@ void DAC_Reset(void)
*
* @retval None
*/
void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig)
void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig)
{
uint32_t tmp1 = 0, tmp2 = 0;
@ -88,7 +88,7 @@ void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig)
*
* @retval None
*/
void DAC_ConfigStructInit(DAC_Config_T *dacConfig)
void DAC_ConfigStructInit(DAC_Config_T* dacConfig)
{
/** Initialize the DAC_Trigger member */
dacConfig->trigger = DAC_TRIGGER_NONE;
@ -403,7 +403,7 @@ uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel)
tmp += 0x0000002C + ((uint32_t)channel >> 2);
/** Returns the DAC channel data output register value */
return (uint16_t)(*(__IO uint32_t *) tmp);
return (uint16_t) (*(__IO uint32_t*) tmp);
}
/**@} end of group DAC_Fuctions*/

4
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c
View File

@ -46,7 +46,7 @@
*/
uint32_t DBGMCU_ReadDEVID(void)
{
return (DBGMCU->IDCODE_B.EQR);
return(DBGMCU->IDCODE_B.EQR);
}
/*!
@ -58,7 +58,7 @@ uint32_t DBGMCU_ReadDEVID(void)
*/
uint32_t DBGMCU_ReadREVID(void)
{
return (DBGMCU->IDCODE_B.WVR);
return(DBGMCU->IDCODE_B.WVR);
}
/*!

65
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c
View File

@ -54,51 +54,51 @@ void DMA_Reset(DMA_Channel_T *channel)
channel->CHMADDR = 0;
channel->CHPADDR = 0;
if (channel == DMA1_Channel1)
if(channel == DMA1_Channel1)
{
DMA1->INTFCLR |= 0xFFFFFFF0;
}
else if (channel == DMA1_Channel2)
else if(channel == DMA1_Channel2)
{
DMA1->INTFCLR |= 0xFFFFFF0F;
}
else if (channel == DMA1_Channel3)
else if(channel == DMA1_Channel3)
{
DMA1->INTFCLR |= 0xFFFFF0FF;
}
else if (channel == DMA1_Channel4)
else if(channel == DMA1_Channel4)
{
DMA1->INTFCLR |= 0xFFFF0FFF;
}
else if (channel == DMA1_Channel5)
else if(channel == DMA1_Channel5)
{
DMA1->INTFCLR |= 0xFFF0FFFF;
}
else if (channel == DMA1_Channel6)
else if(channel == DMA1_Channel6)
{
DMA1->INTFCLR |= 0xFF0FFFFF;
}
else if (channel == DMA1_Channel7)
else if(channel == DMA1_Channel7)
{
DMA1->INTFCLR |= 0xF0FFFFFF;
}
else if (channel == DMA2_Channel1)
else if(channel == DMA2_Channel1)
{
DMA2->INTFCLR |= 0xFFFFFFF0;
}
else if (channel == DMA2_Channel2)
else if(channel == DMA2_Channel2)
{
DMA2->INTFCLR |= 0xFFFFFF0F;
}
else if (channel == DMA2_Channel3)
else if(channel == DMA2_Channel3)
{
DMA2->INTFCLR |= 0xFFFFF0FF;
}
else if (channel == DMA2_Channel4)
else if(channel == DMA2_Channel4)
{
DMA2->INTFCLR |= 0xFFFF0FFF;
}
else if (channel == DMA2_Channel5)
else if(channel == DMA2_Channel5)
{
DMA2->INTFCLR |= 0xFFF0FFFF;
}
@ -115,7 +115,7 @@ void DMA_Reset(DMA_Channel_T *channel)
*
* @note DMA2 Channel only for APM32 High density devices.
*/
void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig)
void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig)
{
channel->CHCFG_B.DIRCFG = dmaConfig->dir;
channel->CHCFG_B.CIRMODE = dmaConfig->loopMode;
@ -138,7 +138,7 @@ void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig)
*
* @retval None
*/
void DMA_ConfigStructInit(DMA_Config_T *dmaConfig)
void DMA_ConfigStructInit( DMA_Config_T* dmaConfig)
{
dmaConfig->peripheralBaseAddr = 0;
dmaConfig->memoryBaseAddr = 0;
@ -312,24 +312,22 @@ void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt)
*/
uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
{
if ((flag & 0x10000000) != RESET)
if((flag & 0x10000000) != RESET )
{
if ((DMA2->INTSTS & flag) != RESET)
if((DMA2->INTSTS & flag ) != RESET )
{
return SET ;
}
else
} else
{
return RESET ;
}
}
else
{
if ((DMA1->INTSTS & flag) != RESET)
if((DMA1->INTSTS & flag ) != RESET )
{
return SET ;
}
else
} else
{
return RESET ;
}
@ -397,11 +395,10 @@ uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
*/
void DMA_ClearStatusFlag(uint32_t flag)
{
if ((flag & 0x10000000) != RESET)
if((flag & 0x10000000) != RESET)
{
DMA2->INTFCLR = flag;
}
else
} else
{
DMA1->INTFCLR = flag;
}
@ -468,24 +465,21 @@ void DMA_ClearStatusFlag(uint32_t flag)
*/
uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
{
if ((flag & 0x10000000) != RESET)
if((flag & 0x10000000) != RESET )
{
if ((DMA2->INTSTS & flag) != RESET)
if((DMA2->INTSTS & flag ) != RESET )
{
return SET ;
}
else
} else
{
return RESET ;
}
}
else
} else
{
if ((DMA1->INTSTS & flag) != RESET)
if((DMA1->INTSTS & flag ) != RESET )
{
return SET ;
}
else
} else
{
return RESET ;
}
@ -552,11 +546,10 @@ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
*/
void DMA_ClearIntFlag(uint32_t flag)
{
if ((flag & 0x10000000) != RESET)
if((flag & 0x10000000) != RESET)
{
DMA2->INTFCLR = flag;
}
else
} else
{
DMA1->INTFCLR = flag;
}

12
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c
View File

@ -45,10 +45,10 @@
*
* @retval None
*/
void DMC_Config(DMC_Config_T *dmcConfig)
void DMC_Config(DMC_Config_T * dmcConfig)
{
DMC->SW_B.MCSW = 1;
while (!DMC->CTRL1_B.INIT);
while(!DMC->CTRL1_B.INIT);
DMC->CFG_B.BAWCFG = dmcConfig->bankWidth;
DMC->CFG_B.RAWCFG = dmcConfig->rowWidth;
@ -60,7 +60,7 @@ void DMC_Config(DMC_Config_T *dmcConfig)
DMC_ConfigTiming(&dmcConfig->timing);
DMC->CTRL1_B.MODESET = 1;
while (!DMC->CTRL1_B.MODESET);
while(!DMC->CTRL1_B.MODESET);
DMC->CTRL2_B.RDDEN = 1;
DMC->CTRL2_B.RDDCFG = 7;
@ -73,7 +73,7 @@ void DMC_Config(DMC_Config_T *dmcConfig)
*
* @retval None
*/
void DMC_ConfigStructInit(DMC_Config_T *dmcConfig)
void DMC_ConfigStructInit(DMC_Config_T * dmcConfig)
{
dmcConfig->bankWidth = DMC_BANK_WIDTH_2;
dmcConfig->clkPhase = DMC_CLK_PHASE_REVERSE;
@ -91,7 +91,7 @@ void DMC_ConfigStructInit(DMC_Config_T *dmcConfig)
*
* @retval None
*/
void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig)
void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig)
{
DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS;
DMC->TIM0_B.DTIMSEL = timingConfig->tRCD;
@ -116,7 +116,7 @@ void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig)
*
* @retval None
*/
void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig)
void DMC_ConfigTimingStructInit(DMC_TimingConfig_T * timingConfig)
{
timingConfig->latencyCAS = DMC_CAS_LATENCY_3;
timingConfig->tARP = DMC_AUTO_REFRESH_10;

10
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c
View File

@ -60,12 +60,12 @@ void EINT_Reset(void)
*
* @retval None
*/
void EINT_Config(EINT_Config_T *eintConfig)
void EINT_Config(EINT_Config_T* eintConfig)
{
uint32_t temp = 0;
temp = (uint32_t)EINT_BASE;
if (eintConfig->lineCmd != DISABLE)
if(eintConfig->lineCmd != DISABLE)
{
EINT->IMASK &= ~eintConfig->line;
EINT->EMASK &= ~eintConfig->line;
@ -104,7 +104,7 @@ void EINT_Config(EINT_Config_T *eintConfig)
*
* @retval None
*/
void EINT_ConfigStructInit(EINT_Config_T *eintConfig)
void EINT_ConfigStructInit(EINT_Config_T* eintConfig)
{
eintConfig->line = EINT_LINENONE;
eintConfig->mode = EINT_MODE_INTERRUPT;
@ -137,7 +137,7 @@ uint8_t EINT_ReadStatusFlag(EINT_LINE_T line)
{
uint8_t status = RESET;
if ((EINT->IPEND & line) != (uint32_t)RESET)
if((EINT->IPEND & line) != (uint32_t)RESET)
{
status = SET;
}
@ -176,7 +176,7 @@ uint8_t EINT_ReadIntFlag(EINT_LINE_T line)
enablestatus = EINT->IMASK & line;
if ((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
if((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
status = SET;
}

82
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c
View File

@ -53,7 +53,7 @@
void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank)
{
/** EMMC_BANK1_NORSRAM_1 */
if (bank == EMMC_BANK1_NORSRAM_1)
if(bank == EMMC_BANK1_NORSRAM_1)
{
EMMC_Bank1->SNCTRL_T[bank] = 0x000030DB;
}
@ -78,7 +78,7 @@ void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank)
*/
void EMMC_ResetNAND(EMMC_BANK_NAND_T bank)
{
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
/** Set the EMMC_Bank2 registers to their reset values */
EMMC_Bank2->CTRL2 = 0x00000018;
@ -121,7 +121,7 @@ void EMMC_ResetPCCard(void)
*
* @retval None
*/
void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
{
/** Bank1 NOR/SRAM control register configuration */
EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] =
@ -138,7 +138,7 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
emmcNORSRAMConfig->extendedMode |
emmcNORSRAMConfig->writeBurst;
if (emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR)
if(emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR)
{
EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] |= 0x00000040;
}
@ -154,7 +154,7 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
emmcNORSRAMConfig->readWriteTimingStruct->accessMode;
/** Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
if (emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE)
if(emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE)
{
EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] =
(uint32_t)emmcNORSRAMConfig->writeTimingStruct->addressSetupTime |
@ -177,7 +177,7 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
*
* @retval None
*/
void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig)
void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig)
{
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
@ -201,7 +201,7 @@ void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig)
(emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
(emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
if (emmcNANDConfig->bank == EMMC_BANK2_NAND)
if(emmcNANDConfig->bank == EMMC_BANK2_NAND)
{
/** EMMC_BANK2_NAND registers configuration */
EMMC_Bank2->CTRL2 = tmppcr;
@ -225,30 +225,30 @@ void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig)
*
* @retval None
*/
void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig)
void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig)
{
/** Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */
EMMC_Bank4->CTRL4 = (uint32_t)emmcPCCardConfig->waitFeature | EMMC_MEMORY_DATA_WIDTH_16BIT |
(emmcPCCardConfig->TCLRSetupTime << 9) |
(emmcPCCardConfig->TARSetupTime << 13);
(emmcPCCardConfig->TCLRSetupTime << 9) |
(emmcPCCardConfig->TARSetupTime << 13);
/** Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */
EMMC_Bank4->CMSTIM4 = (uint32_t)emmcPCCardConfig->commonSpaceTimingStruct->setupTime |
(emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
(emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
(emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
(emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
(emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
(emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
/** Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */
EMMC_Bank4->AMSTIM4 = (uint32_t)emmcPCCardConfig->attributeSpaceTimingStruct->setupTime |
(emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
(emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
(emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
(emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
(emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
(emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
/** Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */
EMMC_Bank4->IOSTIM4 = (uint32_t)emmcPCCardConfig->IOSpaceTimingStruct->setupTime |
(emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
(emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
(emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
(emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
(emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
(emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
}
/*!
@ -258,7 +258,7 @@ void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig)
*
* @retval None
*/
void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
{
/** Reset NOR/SRAM Init structure parameters values */
emmcNORSRAMConfig->bank = EMMC_BANK1_NORSRAM_1;
@ -298,7 +298,7 @@ void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
*
* @retval None
*/
void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig)
void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig)
{
/** Reset NAND Init structure parameters values */
emmcNANDConfig->bank = EMMC_BANK2_NAND;
@ -325,7 +325,7 @@ void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig)
*
* @retval None
*/
void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig)
void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig)
{
/** Reset PCCARD Init structure parameters values */
emmcPCCardConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE;
@ -391,7 +391,7 @@ void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank)
*/
void EMMC_EnableNAND(EMMC_BANK_NAND_T bank)
{
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->CTRL2_B.MBKEN = BIT_SET;
}
@ -413,7 +413,7 @@ void EMMC_EnableNAND(EMMC_BANK_NAND_T bank)
*/
void EMMC_DisableNAND(EMMC_BANK_NAND_T bank)
{
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->CTRL2_B.MBKEN = BIT_RESET;
}
@ -459,7 +459,7 @@ void EMMC_DisablePCCARD(void)
*/
void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank)
{
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->CTRL2 |= 0x00000040;
}
@ -482,7 +482,7 @@ void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank)
*/
void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank)
{
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->CTRL2 &= 0x000FFFBF;
}
@ -506,7 +506,7 @@ uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank)
{
uint32_t eccval = 0x00000000;
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
eccval = EMMC_Bank2->ECCRS2;
}
@ -536,11 +536,11 @@ uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank)
*/
void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
{
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->STSINT2 |= interrupt;
}
else if (bank == EMMC_BANK3_NAND)
else if(bank == EMMC_BANK3_NAND)
{
EMMC_Bank3->STSINT3 |= interrupt;
}
@ -569,11 +569,11 @@ void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
*/
void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
{
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->STSINT2 &= ~interrupt;
}
else if (bank == EMMC_BANK3_NAND)
else if(bank == EMMC_BANK3_NAND)
{
EMMC_Bank3->STSINT3 &= ~interrupt;
}
@ -606,11 +606,11 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
{
uint32_t tmpsr = 0x00000000;
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
tmpsr = EMMC_Bank2->STSINT2;
}
else if (bank == EMMC_BANK3_NAND)
else if(bank == EMMC_BANK3_NAND)
{
tmpsr = EMMC_Bank3->STSINT3;
}
@ -619,7 +619,7 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
tmpsr = EMMC_Bank4->STSINT4;
}
/** Get the flag status */
if ((tmpsr & flag) != RESET)
if((tmpsr & flag) != RESET)
{
return SET;
}
@ -648,11 +648,11 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
*/
void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
{
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->STSINT2 &= ~flag;
}
else if (bank == EMMC_BANK3_NAND)
else if(bank == EMMC_BANK3_NAND)
{
EMMC_Bank3->STSINT3 &= ~flag;
}
@ -683,11 +683,11 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
{
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
tmpsr = EMMC_Bank2->STSINT2;
}
else if (bank == EMMC_BANK3_NAND)
else if(bank == EMMC_BANK3_NAND)
{
tmpsr = EMMC_Bank3->STSINT3;
}
@ -699,7 +699,7 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
itstatus = tmpsr & flag;
itenable = tmpsr & (flag >> 3);
if ((itstatus != RESET) && (itenable != RESET))
if((itstatus != RESET) && (itenable != RESET))
{
return SET;
}
@ -728,11 +728,11 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
*/
void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
{
if (bank == EMMC_BANK2_NAND)
if(bank == EMMC_BANK2_NAND)
{
EMMC_Bank2->STSINT2 &= ~(flag >> 3);
}
else if (bank == EMMC_BANK3_NAND)
else if(bank == EMMC_BANK3_NAND)
{
EMMC_Bank3->STSINT3 &= ~(flag >> 3);
}

114
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c
View File

@ -140,7 +140,7 @@ FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr)
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.PAGEERA = BIT_SET;
FMC->ADDR = pageAddr;
@ -168,7 +168,7 @@ FMC_STATUS_T FMC_EraseAllPage(void)
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.MASSERA = BIT_SET;
FMC->CTRL2_B.STA = BIT_SET;
@ -195,12 +195,12 @@ FMC_STATUS_T FMC_EraseOptionBytes(void)
uint16_t rdtemp = 0x00A5;
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
if (FMC_GetReadProtectionStatus() != RESET)
if(FMC_GetReadProtectionStatus() != RESET)
{
rdtemp = 0x00;
}
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
@ -210,18 +210,18 @@ FMC_STATUS_T FMC_EraseOptionBytes(void)
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.OBE = BIT_RESET;
FMC->CTRL2_B.OBP = BIT_SET;
OB->RDP = rdtemp;
status = FMC_WaitForLastOperation(0x000B0000);
if (status != FMC_STATUS_TIMEOUT)
if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
else if (status != FMC_STATUS_TIMEOUT)
else if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
@ -247,13 +247,13 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
__IOM uint32_t temp = 0;
#ifdef APM32F10X_HD
__set_PRIMASK(1);
#endif
#ifdef APM32F10X_HD
__set_PRIMASK(1);
#endif
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.PG = BIT_SET;
@ -261,11 +261,11 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
temp = address + 2;
*(__IOM uint16_t *) temp = data >> 16;
*(__IOM uint16_t*) temp = data >> 16;
status = FMC_WaitForLastOperation(0x000B0000);
FMC->CTRL2_B.PG = BIT_RESET;
@ -276,9 +276,9 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
}
}
#ifdef APM32F10X_HD
__set_PRIMASK(0);
#endif
#ifdef APM32F10X_HD
__set_PRIMASK(0);
#endif
return status;
}
@ -300,13 +300,13 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
#ifdef APM32F10X_HD
__set_PRIMASK(1);
#endif
#ifdef APM32F10X_HD
__set_PRIMASK(1);
#endif
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.PG = BIT_SET;
*(__IOM uint16_t *)address = data;
@ -314,9 +314,9 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data)
FMC->CTRL2_B.PG = BIT_RESET;
}
#ifdef APM32F10X_HD
__set_PRIMASK(0);
#endif
#ifdef APM32F10X_HD
__set_PRIMASK(0);
#endif
return status;
}
@ -340,7 +340,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
@ -348,7 +348,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
FMC->CTRL2_B.OBP = BIT_SET;
*(__IOM uint16_t *)address = data;
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_TIMEOUT)
if(status == FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
@ -361,11 +361,11 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
*
* @param page:the address of the pages to be write protection
* This parameter can be any combination of the following values:
* for APM32F10X_LD ：
* for APM32F10X_LD £º
* @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_28_31
* for APM32F10X_MD ：
* for APM32F10X_MD £º
* @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_124_127
* for APM32F10X_HD ：
* for APM32F10X_HD £º
* @arg FLASH_WRP_PAGE_0_1 to FLASH_WRP_PAGE_60_61 or FLASH_WRP_PAGE_62_127
* @arg FMC_WRP_PAGE_ALL
*
@ -388,34 +388,34 @@ FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page)
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
FMC->CTRL2_B.OBP = BIT_SET;
if (WPP0_Data != 0xFF)
if(WPP0_Data != 0xFF)
{
OB->WRP0 = WPP0_Data;
status = FMC_WaitForLastOperation(0x000B0000);
}
if ((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF))
if((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF))
{
OB->WRP1 = WPP1_Data;
status = FMC_WaitForLastOperation(0x000B0000);
}
if ((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF))
if((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF))
{
OB->WRP2 = WPP2_Data;
status = FMC_WaitForLastOperation(0x000B0000);
}
if ((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF))
if((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF))
{
OB->WRP3 = WPP3_Data;
status = FMC_WaitForLastOperation(0x000B0000);
}
if (status != FMC_STATUS_TIMEOUT)
if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
@ -440,7 +440,7 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void)
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
@ -450,20 +450,20 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void)
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.OBE = BIT_RESET;
FMC->CTRL2_B.OBP = BIT_SET;
OB->RDP = 0x00A5;
OB->RDP = 0x0000;
status = FMC_WaitForLastOperation(0x000B0000);
if (status != FMC_STATUS_TIMEOUT)
if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
else if (status != FMC_STATUS_TIMEOUT)
else if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBE = BIT_RESET;
}
@ -488,7 +488,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->OBKEY = 0x45670123;
FMC->OBKEY = 0xCDEF89AB;
@ -497,20 +497,20 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.OBE = BIT_RESET;
FMC->CTRL2_B.OBP = BIT_SET;
OB->RDP = 0x00;
OB->RDP = 0x00A5;
status = FMC_WaitForLastOperation(0x000B0000);
if (status != FMC_STATUS_TIMEOUT)
if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
}
else if (status != FMC_STATUS_TIMEOUT)
else if(status != FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBE = BIT_RESET;
}
@ -529,7 +529,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
* @arg FMC_STATUS_COMPLETE
* @arg FMC_STATUS_TIMEOUT
*/
FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig)
FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
@ -538,14 +538,14 @@ FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig)
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_COMPLETE)
if(status == FMC_STATUS_COMPLETE)
{
FMC->CTRL2_B.OBP = BIT_SET;
OB->USER = (uint32_t)userConfig->iwdtSet | \
(uint32_t)userConfig->stopSet | \
(uint32_t)userConfig->stdbySet | 0xF8;
status = FMC_WaitForLastOperation(0x000B0000);
if (status == FMC_STATUS_TIMEOUT)
if(status == FMC_STATUS_TIMEOUT)
{
FMC->CTRL2_B.OBP = BIT_RESET;
}
@ -588,7 +588,7 @@ uint8_t FMC_GetReadProtectionStatus(void)
{
uint8_t flagstatus = RESET;
if (FMC->OBCS_B.READPROT != RESET)
if(FMC->OBCS_B.READPROT != RESET)
{
flagstatus = SET;
}
@ -623,7 +623,7 @@ uint8_t FMC_ReadPrefetchBufferStatus(void)
*/
void FMC_EnableInterrupt(FMC_INT_T interrupt)
{
if (interrupt == FMC_INT_ERR)
if(interrupt == FMC_INT_ERR)
{
FMC->CTRL2_B.ERRIE = ENABLE;
}
@ -645,7 +645,7 @@ void FMC_EnableInterrupt(FMC_INT_T interrupt)
*/
void FMC_DisableInterrupt(FMC_INT_T interrupt)
{
if (interrupt == FMC_INT_ERR)
if(interrupt == FMC_INT_ERR)
{
FMC->CTRL2_B.ERRIE = DISABLE;
}
@ -670,11 +670,11 @@ void FMC_DisableInterrupt(FMC_INT_T interrupt)
*/
uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag)
{
if (flag == FMC_FLAG_OBE)
if(flag == FMC_FLAG_OBE)
{
return FMC->OBCS_B.OBE;
}
else if ((FMC->STS & flag) != RESET)
else if((FMC->STS & flag ) != RESET)
{
return SET;
}
@ -713,15 +713,15 @@ FMC_STATUS_T FMC_ReadStatus(void)
{
FMC_STATUS_T status = FMC_STATUS_COMPLETE;
if (FMC->STS_B.BUSYF == BIT_SET)
if(FMC->STS_B.BUSYF == BIT_SET)
{
status = FMC_STATUS_BUSY;
}
else if (FMC->STS_B.PEF == BIT_SET)
else if(FMC->STS_B.PEF == BIT_SET)
{
status = FMC_STATUS_ERROR_PG;
}
else if (FMC->STS_B.WPEF == BIT_SET)
else if(FMC->STS_B.WPEF == BIT_SET)
{
status = FMC_STATUS_ERROR_WRP;
}
@ -751,12 +751,12 @@ FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut)
status = FMC_ReadStatus();
/** Wait for a Flash operation to complete or a TIMEOUT to occur */
while ((status == FMC_STATUS_BUSY) && (timeOut != 0))
while((status == FMC_STATUS_BUSY) && (timeOut !=0))
{
status = FMC_ReadStatus();
timeOut--;
}
if (timeOut == 0x00)
if(timeOut == 0x00)
{
status = FMC_STATUS_TIMEOUT;
}

34
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c
View File

@ -46,7 +46,7 @@
*
* @retval None
*/
void GPIO_Reset(GPIO_T *port)
void GPIO_Reset(GPIO_T* port)
{
RCM_APB2_PERIPH_T APB2Periph;
@ -106,7 +106,7 @@ void GPIO_AFIOReset(void)
*
* @retval None
*/
void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig)
void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
{
uint8_t i;
uint32_t mode;
@ -181,7 +181,7 @@ void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig)
*
* @retval None
*/
void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig)
void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig)
{
gpioConfig->pin = GPIO_PIN_ALL;
gpioConfig->speed = GPIO_SPEED_20MHz;
@ -199,7 +199,7 @@ void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig)
*
* @retval The input port pin value
*/
uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin)
uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
{
uint8_t ret;
@ -216,7 +216,7 @@ uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin)
*
* @retval GPIO input data port value
*/
uint16_t GPIO_ReadInputPort(GPIO_T *port)
uint16_t GPIO_ReadInputPort(GPIO_T* port)
{
return ((uint16_t)port->IDATA);
}
@ -232,7 +232,7 @@ uint16_t GPIO_ReadInputPort(GPIO_T *port)
*
* @retval The output port pin value
*/
uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin)
uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
{
uint8_t ret;
@ -250,7 +250,7 @@ uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin)
*
* @retval output data port value
*/
uint16_t GPIO_ReadOutputPort(GPIO_T *port)
uint16_t GPIO_ReadOutputPort(GPIO_T* port)
{
return ((uint16_t)port->ODATA);
}
@ -266,7 +266,7 @@ uint16_t GPIO_ReadOutputPort(GPIO_T *port)
*
* @retval None
*/
void GPIO_SetBit(GPIO_T *port, uint16_t pin)
void GPIO_SetBit(GPIO_T* port, uint16_t pin)
{
port->BSC = (uint32_t)pin;
}
@ -282,7 +282,7 @@ void GPIO_SetBit(GPIO_T *port, uint16_t pin)
*
* @retval None
*/
void GPIO_ResetBit(GPIO_T *port, uint16_t pin)
void GPIO_ResetBit(GPIO_T* port, uint16_t pin)
{
port->BC = (uint32_t)pin;
}
@ -304,7 +304,7 @@ void GPIO_ResetBit(GPIO_T *port, uint16_t pin)
*
* @retval None
*/
void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal)
void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal)
{
if (bitVal != BIT_RESET)
{
@ -326,7 +326,7 @@ void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal)
*
* @retval None
*/
void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue)
void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
{
port->ODATA = (uint32_t)portValue;
}
@ -342,7 +342,7 @@ void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue)
*
* @retval None
*/
void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin)
void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin)
{
uint32_t val = 0x00010000;
@ -471,7 +471,7 @@ void GPIO_ConfigPinRemap(GPIO_REMAP_T remap)
regVal = AFIO->REMAP1;
}
if (remap >> 8 == 0x18)
if(remap >> 8 == 0x18)
{
regVal &= 0xF0FFFFFF;
AFIO->REMAP1 &= 0xF0FFFFFF;
@ -514,28 +514,28 @@ void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSou
if (pinSource <= GPIO_PIN_SOURCE_3)
{
shift = pinSource << 2;
AFIO->EINTSEL1 &= (uint32_t)~(0x0f << shift);
AFIO->EINTSEL1 &= (uint32_t )~(0x0f << shift);
AFIO->EINTSEL1 |= portSource << shift;
}
else if (pinSource <= GPIO_PIN_SOURCE_7)
{
shift = (pinSource - GPIO_PIN_SOURCE_4) << 2;
AFIO->EINTSEL2 &= (uint32_t)~(0x0f << shift);
AFIO->EINTSEL2 &= (uint32_t )~(0x0f << shift);
AFIO->EINTSEL2 |= portSource << shift;
}
else if (pinSource <= GPIO_PIN_SOURCE_11)
{
shift = (pinSource - GPIO_PIN_SOURCE_8) << 2;
AFIO->EINTSEL3 &= (uint32_t)~(0x0f << shift);
AFIO->EINTSEL3 &= (uint32_t )~(0x0f << shift);
AFIO->EINTSEL3 |= portSource << shift;
}
else if (pinSource <= GPIO_PIN_SOURCE_15)
{
shift = (pinSource - GPIO_PIN_SOURCE_12) << 2;
AFIO->EINTSEL4 &= (uint32_t)~(0x0f << shift);
AFIO->EINTSEL4 &= (uint32_t )~(0x0f << shift);
AFIO->EINTSEL4 |= portSource << shift;
}
}

120
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c
View File

@ -45,9 +45,9 @@
*
* @retval None
*/
void I2C_Reset(I2C_T *i2c)
void I2C_Reset(I2C_T* i2c)
{
if (i2c == I2C1)
if(i2c == I2C1)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
@ -68,7 +68,7 @@ void I2C_Reset(I2C_T *i2c)
*
* @retval None
*/
void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
{
uint16_t tmpreg = 0, freqrange = 0;
uint32_t PCLK1 = 8000000, PCLK2 = 0;
@ -79,15 +79,15 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
/** I2C CTRL2 Configuration */
RCM_ReadPCLKFreq(&PCLK1, &PCLK2);
freqrange = PCLK1 / 1000000;
i2c->CTRL2_B.CLKFCFG = freqrange;
i2c->CTRL2_B.CLKFCFG= freqrange;
/** I2C CLKCTRL Configuration */
i2c->CTRL1_B.I2CEN = BIT_RESET;
if (i2cConfig->clockSpeed <= 100000)
if(i2cConfig->clockSpeed <= 100000)
{
result = (PCLK1 / (i2cConfig->clockSpeed << 1));
if (result < 0x04)
if(result < 0x04)
{
result = 0x04;
}
@ -97,7 +97,7 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
/** Configure speed in fast mode */
else
{
if (i2cConfig->dutyCycle == I2C_DUTYCYCLE_2)
if(i2cConfig->dutyCycle == I2C_DUTYCYCLE_2)
{
result = (PCLK1 / (i2cConfig->clockSpeed * 3));
}
@ -107,7 +107,7 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
result |= I2C_DUTYCYCLE_16_9;
}
if ((result & 0x0FFF) == 0)
if((result & 0x0FFF) == 0)
{
result |= 0x0001;
}
@ -136,7 +136,7 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
*
* @retval None
*/
void I2C_ConfigStructInit(I2C_Config_T *i2cConfig)
void I2C_ConfigStructInit(I2C_Config_T* i2cConfig)
{
i2cConfig->clockSpeed = 5000;
i2cConfig->mode = I2C_MODE_I2C;
@ -153,7 +153,7 @@ void I2C_ConfigStructInit(I2C_Config_T *i2cConfig)
*
* @retval None
*/
void I2C_Enable(I2C_T *i2c)
void I2C_Enable(I2C_T* i2c)
{
i2c->CTRL1_B.I2CEN = ENABLE;
}
@ -165,7 +165,7 @@ void I2C_Enable(I2C_T *i2c)
*
* @retval None
*/
void I2C_Disable(I2C_T *i2c)
void I2C_Disable(I2C_T* i2c)
{
i2c->CTRL1_B.I2CEN = DISABLE;
}
@ -177,7 +177,7 @@ void I2C_Disable(I2C_T *i2c)
*
* @retval None
*/
void I2C_EnableGenerateStart(I2C_T *i2c)
void I2C_EnableGenerateStart(I2C_T* i2c)
{
i2c->CTRL1_B.START = BIT_SET;
}
@ -189,7 +189,7 @@ void I2C_EnableGenerateStart(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableGenerateStart(I2C_T *i2c)
void I2C_DisableGenerateStart(I2C_T* i2c)
{
i2c->CTRL1_B.START = BIT_RESET;
}
@ -201,7 +201,7 @@ void I2C_DisableGenerateStart(I2C_T *i2c)
*
* @retval None
*/
void I2C_EnableGenerateStop(I2C_T *i2c)
void I2C_EnableGenerateStop(I2C_T* i2c)
{
i2c->CTRL1_B.STOP = BIT_SET;
}
@ -213,7 +213,7 @@ void I2C_EnableGenerateStop(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableGenerateStop(I2C_T *i2c)
void I2C_DisableGenerateStop(I2C_T* i2c)
{
i2c->CTRL1_B.STOP = BIT_RESET;
}
@ -225,7 +225,7 @@ void I2C_DisableGenerateStop(I2C_T *i2c)
*
* @retval None
*/
void I2C_EnableAcknowledge(I2C_T *i2c)
void I2C_EnableAcknowledge(I2C_T* i2c)
{
i2c->CTRL1_B.ACKEN = ENABLE;
}
@ -237,7 +237,7 @@ void I2C_EnableAcknowledge(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableAcknowledge(I2C_T *i2c)
void I2C_DisableAcknowledge(I2C_T* i2c)
{
i2c->CTRL1_B.ACKEN = DISABLE;
}
@ -251,7 +251,7 @@ void I2C_DisableAcknowledge(I2C_T *i2c)
*
* @retval None
*/
void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address)
void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address)
{
i2c->SADDR2_B.ADDR2 = address;
}
@ -263,7 +263,7 @@ void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address)
*
* @retval None
*/
void I2C_EnableDualAddress(I2C_T *i2c)
void I2C_EnableDualAddress(I2C_T* i2c)
{
i2c->SADDR2_B.ADDRNUM = ENABLE;
}
@ -275,7 +275,7 @@ void I2C_EnableDualAddress(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableDualAddress(I2C_T *i2c)
void I2C_DisableDualAddress(I2C_T* i2c)
{
i2c->SADDR2_B.ADDRNUM = DISABLE;
}
@ -287,7 +287,7 @@ void I2C_DisableDualAddress(I2C_T *i2c)
*
* @retval None
*/
void I2C_EnableGeneralCall(I2C_T *i2c)
void I2C_EnableGeneralCall(I2C_T* i2c)
{
i2c->CTRL1_B.SRBEN = ENABLE;
}
@ -299,7 +299,7 @@ void I2C_EnableGeneralCall(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableGeneralCall(I2C_T *i2c)
void I2C_DisableGeneralCall(I2C_T* i2c)
{
i2c->CTRL1_B.SRBEN = DISABLE;
}
@ -313,7 +313,7 @@ void I2C_DisableGeneralCall(I2C_T *i2c)
*
* @retval None
*/
void I2C_TxData(I2C_T *i2c, uint8_t data)
void I2C_TxData(I2C_T* i2c, uint8_t data)
{
i2c->DATA_B.DATA = data;
}
@ -325,7 +325,7 @@ void I2C_TxData(I2C_T *i2c, uint8_t data)
*
* @retval received data
*/
uint8_t I2C_RxData(I2C_T *i2c)
uint8_t I2C_RxData(I2C_T* i2c)
{
return i2c->DATA_B.DATA;
}
@ -343,9 +343,9 @@ uint8_t I2C_RxData(I2C_T *i2c)
* @arg I2C_DIRECTION_RX: Receiver mode
* @retval None
*/
void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction)
void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction)
{
if (direction != I2C_DIRECTION_TX)
if(direction != I2C_DIRECTION_TX)
{
i2c->DATA_B.DATA = address | 0x0001;
}
@ -375,7 +375,7 @@ void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction)
*
* @retval The value of the read register
*/
uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister)
uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
{
switch (i2cRegister)
{
@ -411,7 +411,7 @@ uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister)
*
* @retval None
*/
void I2C_EnableSoftwareReset(I2C_T *i2c)
void I2C_EnableSoftwareReset(I2C_T* i2c)
{
i2c->CTRL1_B.SWRST = ENABLE;
}
@ -423,7 +423,7 @@ void I2C_EnableSoftwareReset(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableSoftwareReset(I2C_T *i2c)
void I2C_DisableSoftwareReset(I2C_T* i2c)
{
i2c->CTRL1_B.SWRST = DISABLE;
}
@ -437,9 +437,9 @@ void I2C_DisableSoftwareReset(I2C_T *i2c)
*
* @retval None
*/
void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition)
void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition)
{
if (NACKPosition == I2C_NACK_POSITION_NEXT)
if(NACKPosition == I2C_NACK_POSITION_NEXT)
{
i2c->CTRL1_B.ACKPOS = BIT_SET;
}
@ -460,9 +460,9 @@ void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition)
* @arg I2C_SMBUSALER_HIGH: SMBus Alert pin high
* @retval None
*/
void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState)
void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState)
{
if (SMBusState == I2C_SMBUSALER_LOW)
if(SMBusState == I2C_SMBUSALER_LOW)
{
i2c->CTRL1_B.ALERTEN = BIT_SET;
}
@ -479,7 +479,7 @@ void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState)
*
* @retval None
*/
void I2C_EnablePECTransmit(I2C_T *i2c)
void I2C_EnablePECTransmit(I2C_T* i2c)
{
i2c->CTRL1_B.PEC = BIT_SET;
}
@ -491,7 +491,7 @@ void I2C_EnablePECTransmit(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisablePECTransmit(I2C_T *i2c)
void I2C_DisablePECTransmit(I2C_T* i2c)
{
i2c->CTRL1_B.PEC = BIT_RESET;
}
@ -507,9 +507,9 @@ void I2C_DisablePECTransmit(I2C_T *i2c)
* @arg I2C_PEC_POSITION_CURRENT: indicates that current byte is PEC
* @retval None
*/
void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition)
void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition)
{
if (PECPosition == I2C_PEC_POSITION_NEXT)
if(PECPosition == I2C_PEC_POSITION_NEXT)
{
i2c->CTRL1_B.ACKPOS = BIT_SET;
}
@ -526,7 +526,7 @@ void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition)
*
* @retval None
*/
void I2C_EnablePEC(I2C_T *i2c)
void I2C_EnablePEC(I2C_T* i2c)
{
i2c->CTRL1_B.PECEN = BIT_SET;
}
@ -538,7 +538,7 @@ void I2C_EnablePEC(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisablePEC(I2C_T *i2c)
void I2C_DisablePEC(I2C_T* i2c)
{
i2c->CTRL1_B.PECEN = BIT_RESET;
}
@ -550,7 +550,7 @@ void I2C_DisablePEC(I2C_T *i2c)
*
* @retval value of PEC
*/
uint8_t I2C_ReadPEC(I2C_T *i2c)
uint8_t I2C_ReadPEC(I2C_T* i2c)
{
return i2c->STS2_B.PECVALUE;
}
@ -562,7 +562,7 @@ uint8_t I2C_ReadPEC(I2C_T *i2c)
*
* @retval None
*/
void I2C_EnableARP(I2C_T *i2c)
void I2C_EnableARP(I2C_T* i2c)
{
i2c->CTRL1_B.ARPEN = BIT_SET;
}
@ -574,7 +574,7 @@ void I2C_EnableARP(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableARP(I2C_T *i2c)
void I2C_DisableARP(I2C_T* i2c)
{
i2c->CTRL1_B.ARPEN = BIT_RESET;
}
@ -586,7 +586,7 @@ void I2C_DisableARP(I2C_T *i2c)
*
* @retval None
*/
void I2C_EnableStretchClock(I2C_T *i2c)
void I2C_EnableStretchClock(I2C_T* i2c)
{
i2c->CTRL1_B.CLKSTRETCHD = BIT_RESET;
}
@ -598,7 +598,7 @@ void I2C_EnableStretchClock(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableStretchClock(I2C_T *i2c)
void I2C_DisableStretchClock(I2C_T* i2c)
{
i2c->CTRL1_B.CLKSTRETCHD = BIT_SET;
}
@ -614,9 +614,9 @@ void I2C_DisableStretchClock(I2C_T *i2c)
* @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2
* @retval None
*/
void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle)
void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle)
{
if (dutyCycle == I2C_DUTYCYCLE_16_9)
if(dutyCycle == I2C_DUTYCYCLE_16_9)
{
i2c->CLKCTRL_B.FDUTYCFG = BIT_SET;
}
@ -633,7 +633,7 @@ void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle)
*
* @retval None
*/
void I2C_EnableDMA(I2C_T *i2c)
void I2C_EnableDMA(I2C_T* i2c)
{
i2c->CTRL2_B.DMAEN = ENABLE;
}
@ -645,7 +645,7 @@ void I2C_EnableDMA(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableDMA(I2C_T *i2c)
void I2C_DisableDMA(I2C_T* i2c)
{
i2c->CTRL2_B.DMAEN = DISABLE;
}
@ -657,7 +657,7 @@ void I2C_DisableDMA(I2C_T *i2c)
*
* @retval None
*/
void I2C_EnableDMALastTransfer(I2C_T *i2c)
void I2C_EnableDMALastTransfer(I2C_T* i2c)
{
i2c->CTRL2_B.LTCFG = BIT_SET;
}
@ -669,7 +669,7 @@ void I2C_EnableDMALastTransfer(I2C_T *i2c)
*
* @retval None
*/
void I2C_DisableDMALastTransfer(I2C_T *i2c)
void I2C_DisableDMALastTransfer(I2C_T* i2c)
{
i2c->CTRL2_B.LTCFG = BIT_RESET;
}
@ -687,7 +687,7 @@ void I2C_DisableDMALastTransfer(I2C_T *i2c)
*
* @retval None
*/
void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt)
void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt)
{
i2c->CTRL2 |= interrupt;
}
@ -705,7 +705,7 @@ void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt)
*
* @retval None
*/
void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt)
void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt)
{
i2c->CTRL2 &= ~interrupt;
}
@ -736,7 +736,7 @@ void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt)
*
* @retval Status: SUCCESS or ERROR
*/
uint8_t I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent)
uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0, flag2 = 0;
@ -747,7 +747,7 @@ uint8_t I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent)
lastevent = (flag1 | flag2) & 0x00FFFFFF;
if ((lastevent & i2cEvent) == i2cEvent)
if((lastevent & i2cEvent) == i2cEvent)
{
return SUCCESS;
}
@ -761,7 +761,7 @@ uint8_t I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent)
*
* @retval The last event
*/
uint32_t I2C_ReadLastEvent(I2C_T *i2c)
uint32_t I2C_ReadLastEvent(I2C_T* i2c)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0, flag2 = 0;
@ -806,7 +806,7 @@ uint32_t I2C_ReadLastEvent(I2C_T *i2c)
*
* @retval Status: flag SET or RESET
*/
uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
{
uint8_t status = 0;
@ -914,7 +914,7 @@ uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
* a read operation to I2C_STS1 register (I2C_ReadStatusFlag())
* followed by a write operation to I2C_DATA register (I2C_TxData()).
*/
void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
{
switch (flag)
{
@ -968,13 +968,13 @@ void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
*
* @retval Status: flag SET or RESET
*/
uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag)
uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
{
uint32_t enablestatus = 0;
enablestatus = ((flag & 0x07000000) >> 16) & (i2c->CTRL2);
flag &= 0x00FFFFFF;
if (((i2c->STS1 & flag) != RESET) && enablestatus)
if(((i2c->STS1 & flag) != RESET) && enablestatus)
{
return SET;
}
@ -1014,7 +1014,7 @@ uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag)
* a read operation to I2C_STS1 register (I2C_ReadIntFlag())
* followed by a write operation to I2C_DATA register (I2C_TxData()).
*/
void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag)
void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag)
{
i2c->STS1 = (uint16_t)~(flag & 0x00FFFFFF);
}

2
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c
View File

@ -132,7 +132,7 @@ uint8_t IWDT_ReadStatusFlag(uint16_t flag)
{
uint8_t bitStatus = RESET;
if ((IWDT->STS & flag) != (uint32_t)RESET)
if((IWDT->STS & flag) != (uint32_t)RESET)
{
bitStatus = SET;
}

100
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c
View File

@ -62,7 +62,7 @@
*/
void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup)
{
SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup;
SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup;
}
/*!
@ -79,53 +79,53 @@ void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup)
*/
void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority)
{
uint32_t tempPriority, tempPrePri, tempSubPri;
uint32_t priorityGrp;
uint32_t tempPriority, tempPrePri, tempSubPri;
uint32_t priorityGrp;
/** Get priority group */
priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
/** Get priority group */
priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
/** get pre-emption priority and subpriority */
switch (priorityGrp)
{
case NVIC_PRIORITY_GROUP_0:
tempPrePri = 0;
tempSubPri = 4;
break;
/** get pre-emption priority and subpriority */
switch(priorityGrp)
{
case NVIC_PRIORITY_GROUP_0:
tempPrePri = 0;
tempSubPri = 4;
break;
case NVIC_PRIORITY_GROUP_1:
tempPrePri = 1;
tempSubPri = 3;
break;
case NVIC_PRIORITY_GROUP_1:
tempPrePri = 1;
tempSubPri = 3;
break;
case NVIC_PRIORITY_GROUP_2:
tempPrePri = 2;
tempSubPri = 2;
break;
case NVIC_PRIORITY_GROUP_2:
tempPrePri = 2;
tempSubPri = 2;
break;
case NVIC_PRIORITY_GROUP_3:
tempPrePri = 3;
tempSubPri = 1;
break;
case NVIC_PRIORITY_GROUP_3:
tempPrePri = 3;
tempSubPri = 1;
break;
case NVIC_PRIORITY_GROUP_4:
tempPrePri = 4;
tempSubPri = 0;
break;
case NVIC_PRIORITY_GROUP_4:
tempPrePri = 4;
tempSubPri = 0;
break;
default:
NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
tempPrePri = 0;
tempSubPri = 4;
break;
}
default:
NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
tempPrePri = 0;
tempSubPri = 4;
break;
}
tempPrePri = 4 - tempPrePri;
tempSubPri = 4 - tempSubPri;
tempPriority = preemptionPriority << tempPrePri;
tempPriority |= subPriority & (0x0f >> tempSubPri);
tempPriority <<= 4;
NVIC->IP[irq] = (uint8_t)tempPriority;
tempPrePri = 4 - tempPrePri;
tempSubPri = 4 - tempSubPri;
tempPriority = preemptionPriority << tempPrePri;
tempPriority |= subPriority & (0x0f >> tempSubPri);
tempPriority <<= 4;
NVIC->IP[irq] = (uint8_t)tempPriority;
/** enable the selected IRQ */
NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
@ -174,7 +174,7 @@ void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset)
*/
void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
{
SCB->SCR |= lowPowerMode;
SCB->SCR |= lowPowerMode;
}
/*!
@ -190,7 +190,7 @@ void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
*/
void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
{
SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode);
SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode);
}
/*!
@ -205,14 +205,14 @@ void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
*/
void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource)
{
if (clkSource == SYSTICK_CLK_SOURCE_HCLK)
{
SysTick->CTRL |= (uint32_t)BIT2;
}
else
{
SysTick->CTRL &= (uint32_t)(~BIT2);
}
if (clkSource == SYSTICK_CLK_SOURCE_HCLK)
{
SysTick->CTRL |= (uint32_t)BIT2;
}
else
{
SysTick->CTRL &= (uint32_t)(~BIT2);
}
}
/**@} end of group MISC_Fuctions*/

22
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c
View File

@ -102,7 +102,7 @@ void PMU_DisablePVD(void)
/*!
* @brief Configure a voltage threshold detected by a power supply voltage detector (PVD).
*
* @param level：specifies the PVD detection level
* @param level£ºspecifies the PVD detection level
* This parameter can be one of the following values:
* @arg PMU_PVD_LEVEL_2V2 : Config PVD detection level to 2.2V
* @arg PMU_PVD_LEVEL_2V3 : Config PVD detection level to 2.3V
@ -171,9 +171,9 @@ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry)
/** Set LPDSCFG bit according to regulator value */
PMU->CTRL_B.LPDSCFG = regulator;
/** Set Cortex System Control Register */
SCB->SCR |= (uint32_t)0x04;
SCB->SCR |= (uint32_t )0x04;
/** Select STOP mode entry*/
if (entry == PMU_STOP_ENTRY_WFI)
if(entry == PMU_STOP_ENTRY_WFI)
{
/** Request Wait For Interrupt */
__WFI();
@ -202,7 +202,7 @@ void PMU_EnterSTANDBYMode(void)
/** Select STANDBY mode */
PMU->CTRL_B.PDDSCFG = BIT_SET;
/** Set Cortex System Control Register */
SCB->SCR |= (uint32_t)0x04;
SCB->SCR |= (uint32_t )0x04;
#if defined ( __CC_ARM )
__force_stores();
#endif
@ -214,7 +214,7 @@ void PMU_EnterSTANDBYMode(void)
/*!
* @brief Read the specified PWR flag is set or not.
*
* @param flag：Reads the status of specifies the flag.
* @param flag£ºReads the status of specifies the flag.
* This parameter can be one of the following values:
* @arg PMU_FLAG_WUE : Wake Up flag
* @arg PMU_FLAG_SB : StandBy flag
@ -226,15 +226,15 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
{
uint8_t BitStatus = BIT_RESET;
if (flag == PMU_FLAG_WUE)
if(flag == PMU_FLAG_WUE)
{
BitStatus = PMU->CSTS_B.WUEFLG;
}
else if (flag == PMU_FLAG_SB)
else if(flag == PMU_FLAG_SB)
{
BitStatus = PMU->CSTS_B.SBFLG;
}
else if (flag == PMU_FLAG_PVDO)
else if(flag == PMU_FLAG_PVDO)
{
BitStatus = PMU->CSTS_B.PVDOFLG;
}
@ -244,7 +244,7 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
/*!
* @brief Clears the PWR's pending flags.
*
* @param flag：Clears the status of specifies the flag.
* @param flag£ºClears the status of specifies the flag.
* This parameter can be one of the following values:
* @arg PMU_FLAG_WUE : Wake Up flag
* @arg PMU_FLAG_SB : StandBy flag
@ -253,11 +253,11 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
*/
void PMU_ClearStatusFlag(PMU_FLAG_T flag)
{
if (flag == PMU_FLAG_WUE)
if(flag == PMU_FLAG_WUE)
{
PMU->CTRL_B.WUFLGCLR = BIT_SET;
}
else if (flag == PMU_FLAG_SB)
else if(flag == PMU_FLAG_SB)
{
PMU->CTRL_B.SBFLGCLR = BIT_SET;
}

10
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c
View File

@ -73,7 +73,7 @@ void QSPI_Reset(void)
*
* @retval None
*/
void QSPI_Config(QSPI_Config_T *qspiConfig)
void QSPI_Config(QSPI_Config_T * qspiConfig)
{
QSPI->CTRL1_B.CPHA = qspiConfig->clockPhase;
QSPI->CTRL1_B.CPOL = qspiConfig->clockPolarity;
@ -585,19 +585,19 @@ void QSPI_ClearIntFlag(uint32_t flag)
{
volatile uint32_t dummy = 0;
if (flag & QSPI_INT_FLAG_TFO)
if(flag & QSPI_INT_FLAG_TFO)
{
dummy = QSPI->TFOIC;
}
else if (flag & QSPI_INT_FLAG_RFO)
else if(flag & QSPI_INT_FLAG_RFO)
{
dummy = QSPI->RFOIC;
}
else if (flag & QSPI_INT_FLAG_RFU)
else if(flag & QSPI_INT_FLAG_RFU)
{
dummy = QSPI->RFUIC;
}
else if (flag & QSPI_INT_FLAG_MST)
else if(flag & QSPI_INT_FLAG_MST)
{
dummy = QSPI->MIC;
}

88
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c
View File

@ -490,43 +490,43 @@ uint32_t RCM_ReadSYSCLKFreq(void)
switch (sysClock)
{
/** sys clock is HSI */
case RCM_SYSCLK_SEL_HSI:
sysClock = HSI_VALUE;
break;
/** sys clock is HSI */
case RCM_SYSCLK_SEL_HSI:
sysClock = HSI_VALUE;
break;
/** sys clock is HSE */
case RCM_SYSCLK_SEL_HSE:
sysClock = HSE_VALUE;
break;
/** sys clock is HSE */
case RCM_SYSCLK_SEL_HSE:
sysClock = HSE_VALUE;
break;
/** sys clock is PLL */
case RCM_SYSCLK_SEL_PLL:
pllMull = RCM->CFG_B.PLLMULCFG + 2;
pllSource = RCM->CFG_B.PLLSRCSEL;
/** sys clock is PLL */
case RCM_SYSCLK_SEL_PLL:
pllMull = RCM->CFG_B.PLLMULCFG + 2;
pllSource = RCM->CFG_B.PLLSRCSEL;
/** PLL entry clock source is HSE */
if (pllSource == BIT_SET)
{
sysClock = HSE_VALUE * pllMull;
/** HSE clock divided by 2 */
if (pllSource == RCM->CFG_B.PLLHSEPSC)
/** PLL entry clock source is HSE */
if (pllSource == BIT_SET)
{
sysClock >>= 1;
sysClock = HSE_VALUE * pllMull;
/** HSE clock divided by 2 */
if (pllSource == RCM->CFG_B.PLLHSEPSC)
{
sysClock >>= 1;
}
}
/** PLL entry clock source is HSI/2 */
else
{
sysClock = (HSI_VALUE >> 1) * pllMull;
}
}
/** PLL entry clock source is HSI/2 */
else
{
sysClock = (HSI_VALUE >> 1) * pllMull;
}
break;
break;
default:
sysClock = HSI_VALUE;
break;
default:
sysClock = HSI_VALUE;
break;
}
return sysClock;
@ -561,7 +561,7 @@ uint32_t RCM_ReadHCLKFreq(void)
*
* @retval None
*/
void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2)
void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2)
{
uint32_t hclk, divider;
uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
@ -992,20 +992,20 @@ uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag)
switch (reg)
{
case 0:
reg = RCM->CTRL;
break;
case 0:
reg = RCM->CTRL;
break;
case 1:
reg = RCM->BDCTRL;
break;
case 1:
reg = RCM->BDCTRL;
break;
case 2:
reg = RCM->CSTS;
break;
case 2:
reg = RCM->CSTS;
break;
default:
break;
default:
break;
}
if (reg & bit)
@ -1035,7 +1035,7 @@ void RCM_ClearStatusFlag(void)
/*!
* @brief Reads the specified RCM interrupt Flag
*
* @param flag ：Reads specifies RCM interrupt flag.
* @param flag £ºReads specifies RCM interrupt flag.
* This parameter can be one of the following values:
* @arg RCM_INT_LSIRDY : LSI ready interrupt flag
* @arg RCM_INT_LSERDY : LSE ready interrupt flag
@ -1048,7 +1048,7 @@ void RCM_ClearStatusFlag(void)
*/
uint8_t RCM_ReadIntFlag(RCM_INT_T flag)
{
return (RCM->INT &flag) ? SET : RESET;
return (RCM->INT& flag) ? SET : RESET;
}
/*!

10
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c
View File

@ -144,7 +144,7 @@ uint32_t RTC_ReadDivider(void)
*/
void RTC_WaitForLastTask(void)
{
while (RTC->CSTS_B.OCFLG == BIT_RESET)
while(RTC->CSTS_B.OCFLG == BIT_RESET)
{
}
}
@ -156,10 +156,10 @@ void RTC_WaitForLastTask(void)
*
* @retval None
*/
void RTC_WaitForSynchor(void)
void RTC_WaitForSynchro(void)
{
RTC->CSTS_B.RSYNCFLG = BIT_RESET;
while (RTC->CSTS_B.RSYNCFLG == BIT_RESET);
while(RTC->CSTS_B.RSYNCFLG == BIT_RESET);
}
/*!
@ -189,7 +189,7 @@ void RTC_EnableInterrupt(uint16_t interrupt)
*/
void RTC_DisableInterrupt(uint16_t interrupt)
{
RTC->CTRL &= (uint32_t)~interrupt;
RTC->CTRL &= (uint32_t )~interrupt;
}
/*!
@ -207,7 +207,7 @@ void RTC_DisableInterrupt(uint16_t interrupt)
*/
uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag)
{
return (RTC->CSTS & flag) ? SET : RESET;
return (RTC->CSTS & flag) ? SET : RESET;
}
/*!

42
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c
View File

@ -47,7 +47,7 @@
*/
void SCI2C_Reset(SCI2C_T *i2c)
{
if (i2c == I2C3)
if(i2c == I2C3)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
@ -78,7 +78,7 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig)
i2c->CTRL2_B.I2CEN = BIT_RESET;
if (sci2cConfig->mode == SCI2C_MODE_MASTER)
if(sci2cConfig->mode == SCI2C_MODE_MASTER)
{
i2c->CTRL1_B.MST = BIT_SET;
i2c->CTRL1_B.SLADIS = BIT_SET;
@ -98,17 +98,17 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig)
i2c->CTRL1_B.SAM = sci2cConfig->addrMode;
i2c->SLAADDR = sci2cConfig->slaveAddr;
if (sci2cConfig->speed == SCI2C_SPEED_STANDARD)
if(sci2cConfig->speed == SCI2C_SPEED_STANDARD)
{
i2c->SSCLC = sci2cConfig->clkLowPeriod;
i2c->SSCHC = sci2cConfig->clkHighPeriod;
}
else if (sci2cConfig->speed == SCI2C_SPEED_FAST)
else if(sci2cConfig->speed == SCI2C_SPEED_FAST)
{
i2c->FSCLC = sci2cConfig->clkLowPeriod;
i2c->FSCHC = sci2cConfig->clkHighPeriod;
}
else if (sci2cConfig->speed == SCI2C_SPEED_HIGH)
else if(sci2cConfig->speed == SCI2C_SPEED_HIGH)
{
i2c->HSCLC = sci2cConfig->clkLowPeriod;
i2c->HSCHC = sci2cConfig->clkHighPeriod;
@ -159,7 +159,7 @@ uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag)
{
uint8_t ret = RESET;
if (flag & BIT8)
if(flag & BIT8)
{
ret = i2c->STS2 & flag ? SET : RESET;
}
@ -228,47 +228,47 @@ void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
{
volatile uint32_t dummy = 0;
if (flag == SCI2C_INT_ALL)
if(flag == SCI2C_INT_ALL)
{
dummy = i2c->INTCLR;
}
else if (flag == SCI2C_INT_RFU)
else if(flag == SCI2C_INT_RFU)
{
dummy = i2c->RFUIC;
}
else if (flag == SCI2C_INT_RFO)
else if(flag == SCI2C_INT_RFO)
{
dummy = i2c->RFOIC;
}
else if (flag == SCI2C_INT_TFO)
else if(flag == SCI2C_INT_TFO)
{
dummy = i2c->TFOIC;
}
else if (flag == SCI2C_INT_RR)
else if(flag == SCI2C_INT_RR)
{
dummy = i2c->RRIC;
}
else if (flag == SCI2C_INT_TA)
else if(flag == SCI2C_INT_TA)
{
dummy = i2c->TAIC;
}
else if (flag == SCI2C_INT_RD)
else if(flag == SCI2C_INT_RD)
{
dummy = i2c->RDIC;
}
else if (flag == SCI2C_INT_ACT)
else if(flag == SCI2C_INT_ACT)
{
dummy = i2c->AIC;
}
else if (flag == SCI2C_INT_STPD)
else if(flag == SCI2C_INT_STPD)
{
dummy = i2c->STPDIC;
}
else if (flag == SCI2C_INT_STAD)
else if(flag == SCI2C_INT_STAD)
{
dummy = i2c->STADIC;
}
else if (flag == SCI2C_INT_GC)
else if(flag == SCI2C_INT_GC)
{
dummy = i2c->GCIC;
}
@ -731,17 +731,17 @@ void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable)
*/
void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod)
{
if (speed == SCI2C_SPEED_STANDARD)
if(speed == SCI2C_SPEED_STANDARD)
{
i2c->SSCLC = lowPeriod;
i2c->SSCHC = highPeriod;
}
else if (speed == SCI2C_SPEED_FAST)
else if(speed == SCI2C_SPEED_FAST)
{
i2c->FSCLC = lowPeriod;
i2c->FSCHC = highPeriod;
}
else if (speed == SCI2C_SPEED_HIGH)
else if(speed == SCI2C_SPEED_HIGH)
{
i2c->HSCLC = lowPeriod;
i2c->HSCHC = highPeriod;
@ -895,7 +895,7 @@ void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt)
*/
void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit)
{
if (speed == SCI2C_SPEED_HIGH)
if(speed == SCI2C_SPEED_HIGH)
{
i2c->HSSSL = limit;
}

64
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c
View File

@ -65,7 +65,7 @@ void SDIO_Reset(void)
*
* @retval None
*/
void SDIO_Config(SDIO_Config_T *sdioConfig)
void SDIO_Config(SDIO_Config_T* sdioConfig)
{
uint32_t tmp = 0;
@ -73,7 +73,7 @@ void SDIO_Config(SDIO_Config_T *sdioConfig)
tmp &= 0xFFFF8100;
tmp |= (sdioConfig->clockDiv | sdioConfig->clockPowerSave | sdioConfig->clockBypass | sdioConfig->busWide |
sdioConfig->clockEdge | sdioConfig->hardwareFlowControl);
sdioConfig->clockEdge | sdioConfig->hardwareFlowControl);
SDIO->CLKCTRL = tmp;
}
@ -85,14 +85,14 @@ void SDIO_Config(SDIO_Config_T *sdioConfig)
*
* @retval None
*/
void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig)
void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig)
{
sdioConfig->clockDiv = 0x00;
sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING;
sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE;
sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
sdioConfig->busWide = SDIO_BUS_WIDE_1B;
sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
sdioConfig->clockDiv = 0x00;
sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING;
sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE;
sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
sdioConfig->busWide = SDIO_BUS_WIDE_1B;
sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
}
/*!
@ -188,7 +188,7 @@ void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig)
tmpreg = SDIO->CMD;
tmpreg &= 0xFFFFF800;
tmpreg |= (uint32_t)cmdConfig->cmdIndex | cmdConfig->response
| cmdConfig->wait | cmdConfig->CPSM;
| cmdConfig->wait | cmdConfig->CPSM;
SDIO->CMD = tmpreg;
}
@ -200,13 +200,13 @@ void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig)
* @retval None
*
*/
void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdConfig)
void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdConfig)
{
cmdConfig->argument = 0x00;
cmdConfig->cmdIndex = 0x00;
cmdConfig->response = SDIO_RESPONSE_NO;
cmdConfig->wait = SDIO_WAIT_NO;
cmdConfig->CPSM = SDIO_CPSM_DISABLE;
cmdConfig->argument = 0x00;
cmdConfig->cmdIndex = 0x00;
cmdConfig->response = SDIO_RESPONSE_NO;
cmdConfig->wait = SDIO_WAIT_NO;
cmdConfig->CPSM = SDIO_CPSM_DISABLE;
}
/*!
@ -236,11 +236,11 @@ uint8_t SDIO_ReadCommandResponse(void)
*/
uint32_t SDIO_ReadResponse(SDIO_RES_T res)
{
__IO uint32_t tmp = 0;
__IO uint32_t tmp = 0;
tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res;
tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res;
return (*(__IO uint32_t *) tmp);
return (*(__IO uint32_t *) tmp);
}
/*!
@ -250,7 +250,7 @@ uint32_t SDIO_ReadResponse(SDIO_RES_T res)
*
* @retval None
*/
void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig)
void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
{
uint32_t tmpreg = 0;
@ -263,7 +263,7 @@ void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig)
tmpreg &= 0xFFFFFF08;
tmpreg |= (uint32_t)dataConfig->dataBlockSize | dataConfig->transferDir
| dataConfig->transferMode | dataConfig->DPSM;
| dataConfig->transferMode | dataConfig->DPSM;
SDIO->DCTRL = tmpreg;
}
@ -275,14 +275,14 @@ void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig)
*
* @retval None
*/
void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig)
void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig)
{
dataConfig->dataTimeOut = 0xFFFFFFFF;
dataConfig->dataLength = 0x00;
dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B;
dataConfig->transferDir = SDIO_TRANSFER_DIR_TO_CARD;
dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK;
dataConfig->DPSM = SDIO_DPSM_DISABLE;
dataConfig->dataTimeOut = 0xFFFFFFFF;
dataConfig->dataLength = 0x00;
dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B;
dataConfig->transferDir = SDIO_TRANSFER_DIR_TO_CARD;
dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK;
dataConfig->DPSM = SDIO_DPSM_DISABLE;
}
/*!
@ -300,7 +300,7 @@ uint32_t SDIO_ReadDataCounter(void)
/*!
* @brief Write the SDIO Data
*
* @param Data：Write 32-bit data
* @param Data£ºWrite 32-bit data
*
* @retval None
*/
@ -394,7 +394,7 @@ void SDIO_DisableStartReadWait(void)
*/
void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)
{
*(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode;
*(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode;
}
/*!
* @brief Enables SDIO SD I/O Mode Operation
@ -405,7 +405,7 @@ void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)
*/
void SDIO_EnableSDIO(void)
{
*(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET;
*(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET;
}
/*!
@ -417,7 +417,7 @@ void SDIO_EnableSDIO(void)
*/
void SDIO_DisableSDIO(void)
{
*(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET;
*(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET;
}
/*!

96
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c
View File

@ -45,19 +45,19 @@
*
* @retval None
*/
void SPI_I2S_Reset(SPI_T *spi)
void SPI_I2S_Reset(SPI_T* spi)
{
if (spi == SPI1)
if(spi == SPI1)
{
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
}
else if (spi == SPI2)
else if(spi == SPI2)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
}
else if (spi == SPI3)
else if(spi == SPI3)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3);
@ -73,13 +73,13 @@ void SPI_I2S_Reset(SPI_T *spi)
*
* @retval None
*/
void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig)
void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
{
spi->CTRL1 &= 0x3040;
spi->CTRL1 |= (uint16_t)((uint32_t)spiConfig->direction | spiConfig->mode |
spiConfig->length | spiConfig->polarity |
spiConfig->phase | spiConfig->nss |
spiConfig->baudrateDiv | spiConfig->firstBit);
spiConfig->length | spiConfig->polarity |
spiConfig->phase | spiConfig->nss |
spiConfig->baudrateDiv | spiConfig->firstBit);
spi->CRCPOLY = spiConfig->crcPolynomial;
}
@ -92,7 +92,7 @@ void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig)
*
* @retval None
*/
void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
{
uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1;
uint32_t tmp = 0;
@ -102,14 +102,14 @@ void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
spi->I2SCFG &= 0xF040;
spi->I2SPSC = 0x0002;
if (i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT)
if(i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT)
{
spi->I2SPSC_B.ODDPSC = 0;
spi->I2SPSC_B.I2SPSC = 2;
}
else
{
if (i2sConfig->length == I2S_DATA_LENGHT_16B)
if(i2sConfig->length == I2S_DATA_LENGHT_16B)
{
packetSize = 1;
}
@ -120,13 +120,13 @@ void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
sysClock = RCM_ReadSYSCLKFreq();
if (i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE)
if(i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE)
{
tmp = (uint16_t)(((((sysClock / 256) * 10) / i2sConfig ->audioDiv)) + 5);
}
else
{
tmp = (uint16_t)(((((sysClock / (32 * packetSize)) * 10) / i2sConfig ->audioDiv)) + 5);
tmp = (uint16_t)(((((sysClock / (32 * packetSize)) *10 ) / i2sConfig ->audioDiv )) + 5);
}
tmp = tmp / 10;
@ -160,7 +160,7 @@ void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
*
* @retval None
*/
void SPI_ConfigStructInit(SPI_Config_T *spiConfig)
void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
{
spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX;
spiConfig->mode = SPI_MODE_SLAVE;
@ -180,7 +180,7 @@ void SPI_ConfigStructInit(SPI_Config_T *spiConfig)
*
* @retval None
*/
void I2S_ConfigStructInit(I2S_Config_T *i2sConfig)
void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
{
i2sConfig->mode = I2S_MODE_SLAVE_TX;
i2sConfig->standard = I2S_STANDARD_PHILLIPS;
@ -196,7 +196,7 @@ void I2S_ConfigStructInit(I2S_Config_T *i2sConfig)
*
* @retval None
*/
void SPI_Enable(SPI_T *spi)
void SPI_Enable(SPI_T* spi)
{
spi->CTRL1_B.SPIEN = BIT_SET;
}
@ -208,7 +208,7 @@ void SPI_Enable(SPI_T *spi)
*
* @retval None
*/
void SPI_Disable(SPI_T *spi)
void SPI_Disable(SPI_T* spi)
{
spi->CTRL1_B.SPIEN = BIT_RESET;
}
@ -220,7 +220,7 @@ void SPI_Disable(SPI_T *spi)
*
* @retval None
*/
void I2S_Enable(SPI_T *spi)
void I2S_Enable(SPI_T* spi)
{
spi->I2SCFG_B.I2SEN = BIT_SET;
}
@ -232,7 +232,7 @@ void I2S_Enable(SPI_T *spi)
*
* @retval None
*/
void I2S_Disable(SPI_T *spi)
void I2S_Disable(SPI_T* spi)
{
spi->I2SCFG_B.I2SEN = BIT_RESET;
}
@ -248,9 +248,9 @@ void I2S_Disable(SPI_T *spi)
* @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
* @retval None
*/
void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
{
if (dmaReq == SPI_I2S_DMA_REQ_TX)
if(dmaReq == SPI_I2S_DMA_REQ_TX)
{
spi->CTRL2_B.TXDEN = ENABLE;
}
@ -271,9 +271,9 @@ void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
* @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
* @retval None
*/
void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
{
if (dmaReq == SPI_I2S_DMA_REQ_TX)
if(dmaReq == SPI_I2S_DMA_REQ_TX)
{
spi->CTRL2_B.TXDEN = DISABLE;
}
@ -292,7 +292,7 @@ void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
*
* @retval None
*/
void SPI_I2S_TxData(SPI_T *spi, uint16_t data)
void SPI_I2S_TxData(SPI_T* spi, uint16_t data)
{
spi->DATA = data;
}
@ -306,7 +306,7 @@ void SPI_I2S_TxData(SPI_T *spi, uint16_t data)
*
* @retval None
*/
uint16_t SPI_I2S_RxData(SPI_T *spi)
uint16_t SPI_I2S_RxData(SPI_T* spi)
{
return spi->DATA;
}
@ -318,7 +318,7 @@ uint16_t SPI_I2S_RxData(SPI_T *spi)
*
* @retval None
*/
void SPI_SetSoftwareNSS(SPI_T *spi)
void SPI_SetSoftwareNSS(SPI_T* spi)
{
spi->CTRL1_B.ISSEL = BIT_SET;
}
@ -330,7 +330,7 @@ void SPI_SetSoftwareNSS(SPI_T *spi)
*
* @retval None
*/
void SPI_ResetSoftwareNSS(SPI_T *spi)
void SPI_ResetSoftwareNSS(SPI_T* spi)
{
spi->CTRL1_B.ISSEL = BIT_RESET;
}
@ -342,7 +342,7 @@ void SPI_ResetSoftwareNSS(SPI_T *spi)
*
* @retval None
*/
void SPI_EnableSSOutput(SPI_T *spi)
void SPI_EnableSSOutput(SPI_T* spi)
{
spi->CTRL2_B.SSOEN = BIT_SET;
}
@ -354,7 +354,7 @@ void SPI_EnableSSOutput(SPI_T *spi)
*
* @retval None
*/
void SPI_DisableSSOutput(SPI_T *spi)
void SPI_DisableSSOutput(SPI_T* spi)
{
spi->CTRL2_B.SSOEN = BIT_RESET;
}
@ -371,7 +371,7 @@ void SPI_DisableSSOutput(SPI_T *spi)
*
* @retval None
*/
void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length)
void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length)
{
spi->CTRL1_B.DFLSEL = BIT_RESET;
spi->CTRL1 |= length;
@ -384,7 +384,7 @@ void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length)
*
* @retval None
*/
void SPI_TxCRC(SPI_T *spi)
void SPI_TxCRC(SPI_T* spi)
{
spi->CTRL1_B.CRCNXT = BIT_SET;
}
@ -396,7 +396,7 @@ void SPI_TxCRC(SPI_T *spi)
*
* @retval None
*/
void SPI_EnableCRC(SPI_T *spi)
void SPI_EnableCRC(SPI_T* spi)
{
spi->CTRL1_B.CRCEN = BIT_SET;
}
@ -407,7 +407,7 @@ void SPI_EnableCRC(SPI_T *spi)
* @param spi: The SPIx can be 1,2,3
*
*/
void SPI_DisableCRC(SPI_T *spi)
void SPI_DisableCRC(SPI_T* spi)
{
spi->CTRL1_B.CRCEN = BIT_RESET;
}
@ -419,7 +419,7 @@ void SPI_DisableCRC(SPI_T *spi)
*
* @retval The SPI transmit CRC register value
*/
uint16_t SPI_ReadTxCRC(SPI_T *spi)
uint16_t SPI_ReadTxCRC(SPI_T* spi)
{
return spi->TXCRC_B.TXCRC;
}
@ -431,7 +431,7 @@ uint16_t SPI_ReadTxCRC(SPI_T *spi)
*
* @retval The SPI receive CRC register value
*/
uint16_t SPI_ReadRxCRC(SPI_T *spi)
uint16_t SPI_ReadRxCRC(SPI_T* spi)
{
return spi->RXCRC_B.RXCRC;
}
@ -443,7 +443,7 @@ uint16_t SPI_ReadRxCRC(SPI_T *spi)
*
* @retval The SPI CRC Polynomial register value
*/
uint16_t SPI_ReadCRCPolynomial(SPI_T *spi)
uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
{
return spi->CRCPOLY_B.CRCPOLY;
}
@ -459,9 +459,9 @@ uint16_t SPI_ReadCRCPolynomial(SPI_T *spi)
* @arg SPI_DIRECTION_TX: Selects Tx transmission direction
* @retval None
*/
void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction)
void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction)
{
if (direction == SPI_DIRECTION_TX)
if(direction == SPI_DIRECTION_TX)
{
spi->CTRL1 |= SPI_DIRECTION_TX;
}
@ -483,9 +483,9 @@ void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction)
* @arg SPI_I2S_INT_ERR: Error interrupt
* @retval None
*/
void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
{
spi->CTRL2 |= (interrupt >> 8);
spi->CTRL2 |= (interrupt >> 8);
}
/*!
@ -500,9 +500,9 @@ void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
* @arg SPI_I2S_INT_ERR: Error interrupt
* @retval None
*/
void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
{
spi->CTRL2 &= ~(interrupt >> 8);
spi->CTRL2 &= ~(interrupt >> 8);
}
/*!
@ -523,9 +523,9 @@ void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
*
* @retval SET or RESET
*/
uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
{
if ((spi->STS & flag) != RESET)
if((spi->STS & flag) != RESET)
{
return SET;
}
@ -553,7 +553,7 @@ uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
* a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag())
* followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
*/
void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
{
spi->STS_B.CRCEFLG = BIT_RESET;
}
@ -574,12 +574,12 @@ void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
*
* @retval SET or RESET
*/
uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
{
uint32_t intEnable;
uint32_t intStatus;
intEnable = (uint32_t)(spi->CTRL2 & (flag >> 8));
intEnable = (uint32_t)(spi->CTRL2 & (flag>>8));
intStatus = (uint32_t)(spi->STS & flag);
if (intEnable && intStatus)
@ -608,7 +608,7 @@ uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
* a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag())
* followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
*/
void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
{
spi->STS_B.CRCEFLG = BIT_RESET;
}

242
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c
View File

@ -38,10 +38,10 @@
@{
*/
static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
/*!
* @brief Deinitializes the TMRx peripheral registers to their default reset values.
@ -51,7 +51,7 @@ static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
* @retval None
*
*/
void TMR_Reset(TMR_T *tmr)
void TMR_Reset(TMR_T* tmr)
{
if (tmr == TMR1)
{
@ -104,12 +104,12 @@ void TMR_Reset(TMR_T *tmr)
*
* @retval None
*/
void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig)
void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig)
{
uint16_t temp;
if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
(tmr == TMR4) || (tmr == TMR5))
(tmr == TMR4) || (tmr == TMR5))
{
temp = tmr->CTRL1;
temp &= 0x038F;
@ -141,7 +141,7 @@ void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig)
*
* @retval None
*/
void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
{
tmr->CCEN_B.CC1EN = BIT_RESET;
@ -173,7 +173,7 @@ void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
*
* @retval None
*/
void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
{
tmr->CCEN_B.CC2EN = BIT_RESET;
@ -210,7 +210,7 @@ void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
*
* @retval None
*/
void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
{
tmr->CCEN_B.CC3EN = BIT_RESET;
@ -246,7 +246,7 @@ void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
*
* @retval None
*/
void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
{
tmr->CCEN_B.CC4EN = BIT_RESET;
@ -275,7 +275,7 @@ void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
*
* @retval None
*/
void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig)
void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig)
{
if (ICConfig->channel == TMR_CHANNEL_1)
{
@ -308,15 +308,15 @@ void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig)
*
* @retval None
*/
void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig)
void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig)
{
tmr->BDT = (BDTConfig->IMOS) << 10 | \
(BDTConfig->RMOS) << 11 | \
(BDTConfig->lockLevel) << 8 | \
(BDTConfig->deadTime) | \
(BDTConfig->BRKState) << 12 | \
(BDTConfig->BRKPolarity) << 13 | \
(BDTConfig->automaticOutput) << 14;
tmr->BDT = (BDTConfig->IMOS)<<10 |\
(BDTConfig->RMOS)<<11 |\
(BDTConfig->lockLevel)<<8 |\
(BDTConfig->deadTime) |\
(BDTConfig->BRKState)<<12 |\
(BDTConfig->BRKPolarity)<<13 |\
(BDTConfig->automaticOutput)<<14;
}
/*!
@ -326,7 +326,7 @@ void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig)
*
* @retval None
*/
void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig)
void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig)
{
baseConfig->period = 0xFFFF;
baseConfig->division = 0x0000;
@ -342,7 +342,7 @@ void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig)
*
* @retval None
*/
void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig)
void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig)
{
OCConfig->mode = TMR_OC_MODE_TMRING;
OCConfig->outputState = TMR_OC_STATE_DISABLE;
@ -361,7 +361,7 @@ void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig)
*
* @retval None
*/
void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig)
void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig)
{
ICConfig->channel = TMR_CHANNEL_1;
ICConfig->polarity = TMR_IC_POLARITY_RISING;
@ -377,7 +377,7 @@ void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig)
*
* @retval None
*/
void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig)
void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig)
{
BDTConfig->RMOS = TMR_RMOS_STATE_DISABLE;
BDTConfig->IMOS = TMR_IMOS_STATE_DISABLE;
@ -395,7 +395,7 @@ void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig)
*
* @retval None
*/
void TMR_Enable(TMR_T *tmr)
void TMR_Enable(TMR_T* tmr)
{
tmr->CTRL1_B.CNTEN = ENABLE;
}
@ -407,7 +407,7 @@ void TMR_Enable(TMR_T *tmr)
*
* @retval None
*/
void TMR_Disable(TMR_T *tmr)
void TMR_Disable(TMR_T* tmr)
{
tmr->CTRL1_B.CNTEN = DISABLE;
}
@ -421,7 +421,7 @@ void TMR_Disable(TMR_T *tmr)
*
* @retval None
*/
void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig)
void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig)
{
uint16_t icpolarity = TMR_IC_POLARITY_RISING;
uint16_t icselection = TMR_IC_SELECTION_DIRECT_TI;
@ -467,7 +467,7 @@ void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig)
*
* @retval None
*/
void TMR_EnablePWMOutputs(TMR_T *tmr)
void TMR_EnablePWMOutputs(TMR_T* tmr)
{
tmr->BDT_B.MOEN = ENABLE;
}
@ -479,7 +479,7 @@ void TMR_EnablePWMOutputs(TMR_T *tmr)
*
* @retval None
*/
void TMR_DisablePWMOutputs(TMR_T *tmr)
void TMR_DisablePWMOutputs(TMR_T* tmr)
{
tmr->BDT_B.MOEN = DISABLE;
}
@ -495,7 +495,7 @@ void TMR_DisablePWMOutputs(TMR_T *tmr)
*
* @retval None
*/
void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength)
void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength)
{
tmr->DCTRL = (uint32_t)baseAddress | (uint32_t)burstLength;
}
@ -517,7 +517,7 @@ void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T
* @retval None
*
*/
void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource)
void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource)
{
tmr->DIEN |= dmaSource;
}
@ -539,7 +539,7 @@ void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource)
* @retval None
*
*/
void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource)
void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource)
{
tmr->DIEN &= ~dmaSource;
}
@ -551,7 +551,7 @@ void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource)
*
* @retval None
*/
void TMR_ConfigInternalClock(TMR_T *tmr)
void TMR_ConfigInternalClock(TMR_T* tmr)
{
tmr->SMCTRL_B.SMFSEL = DISABLE;
}
@ -569,7 +569,7 @@ void TMR_ConfigInternalClock(TMR_T *tmr)
* @arg TMR_TRIGGER_SOURCE_ITR3: TMR Internal Trigger 3
* @retval None
*/
void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
{
TMR_SelectInputTrigger(tmr, triggerSource);
tmr->SMCTRL_B.SMFSEL = 0x07;
@ -595,8 +595,8 @@ void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSour
*
* @retval None
*/
void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter)
void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter)
{
if (triggerSource == 0x06)
{
@ -632,7 +632,7 @@ void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
*
* @retval None
*/
void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter)
{
TMR_ConfigETR(tmr, prescaler, polarity, filter);
@ -662,7 +662,7 @@ void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
*
* @retval None
*/
void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter)
{
TMR_ConfigETR(tmr, prescaler, polarity, filter);
@ -689,7 +689,7 @@ void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
*
* @retval None
*/
void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
TMR_EXTTRG_POL_T polarity, uint16_t filter)
{
tmr->SMCTRL &= 0x00FF;
@ -711,7 +711,7 @@ void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
* @arg TMR_PSC_RELOAD_IMMEDIATE: The Prescaler is loaded immediately
* @retval None
*/
void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode)
void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode)
{
tmr->PSC = prescaler;
tmr->CEG_B.UEG = pscReloadMode;
@ -731,7 +731,7 @@ void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscRel
* @arg TMR_COUNTER_MODE_CENTERALIGNED3: Timer Center Aligned Mode3
* @retval None
*/
void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode)
void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode)
{
tmr->CTRL1_B.CNTDIR = BIT_RESET;
tmr->CTRL1_B.CAMSEL = BIT_RESET;
@ -756,7 +756,7 @@ void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode)
*
* @retval None
*/
void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
{
tmr->SMCTRL_B.TRGSEL = BIT_RESET;
tmr->SMCTRL_B.TRGSEL = triggerSource;
@ -785,7 +785,7 @@ void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
* @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling
* @retval None
*/
void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
TMR_IC_POLARITY_T IC2Polarity)
{
tmr->SMCTRL_B.SMFSEL = BIT_RESET;
@ -812,7 +812,7 @@ void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC
* @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF
* @retval None
*/
void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
{
tmr->CCM1_COMPARE_B.OC1MOD = BIT_RESET;
tmr->CCM1_COMPARE_B.OC1MOD = forcesAction;
@ -829,7 +829,7 @@ void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
* @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF
* @retval None
*/
void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
{
tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET;
tmr->CCM1_COMPARE_B.OC2MOD = forcesAction;
@ -847,7 +847,7 @@ void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
*
* @retval None
*/
void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
{
tmr->CCM2_COMPARE_B.OC3MOD = BIT_RESET;
tmr->CCM2_COMPARE_B.OC3MOD = forcesAction;
@ -865,7 +865,7 @@ void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
*
* @retval None
*/
void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
{
tmr->CCM2_COMPARE_B.OC4MOD = BIT_RESET;
tmr->CCM2_COMPARE_B.OC4MOD = forcesAction;
@ -878,7 +878,7 @@ void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
*
* @retval None
*/
void TMR_EnableAutoReload(TMR_T *tmr)
void TMR_EnableAutoReload(TMR_T* tmr)
{
tmr->CTRL1_B.ARPEN = ENABLE;
}
@ -890,7 +890,7 @@ void TMR_EnableAutoReload(TMR_T *tmr)
*
* @retval None
*/
void TMR_DisableAutoReload(TMR_T *tmr)
void TMR_DisableAutoReload(TMR_T* tmr)
{
tmr->CTRL1_B.ARPEN = DISABLE;
}
@ -902,7 +902,7 @@ void TMR_DisableAutoReload(TMR_T *tmr)
*
* @retval None
*/
void TMR_EnableSelectCOM(TMR_T *tmr)
void TMR_EnableSelectCOM(TMR_T* tmr)
{
tmr->CTRL2_B.CCUSEL = ENABLE;
}
@ -913,7 +913,7 @@ void TMR_EnableSelectCOM(TMR_T *tmr)
*
* @retval None
*/
void TMR_DisableSelectCOM(TMR_T *tmr)
void TMR_DisableSelectCOM(TMR_T* tmr)
{
tmr->CTRL2_B.CCUSEL = DISABLE;
}
@ -925,7 +925,7 @@ void TMR_DisableSelectCOM(TMR_T *tmr)
*
* @retval None
*/
void TMR_EnableCCDMA(TMR_T *tmr)
void TMR_EnableCCDMA(TMR_T* tmr)
{
tmr->CTRL2_B.CCDSEL = ENABLE;
}
@ -937,7 +937,7 @@ void TMR_EnableCCDMA(TMR_T *tmr)
*
* @retval None
*/
void TMR_DisableCCDMA(TMR_T *tmr)
void TMR_DisableCCDMA(TMR_T* tmr)
{
tmr->CTRL2_B.CCDSEL = DISABLE;
}
@ -949,7 +949,7 @@ void TMR_DisableCCDMA(TMR_T *tmr)
*
* @retval None
*/
void TMR_EnableCCPreload(TMR_T *tmr)
void TMR_EnableCCPreload(TMR_T* tmr)
{
tmr->CTRL2_B.CCPEN = ENABLE;
}
@ -961,7 +961,7 @@ void TMR_EnableCCPreload(TMR_T *tmr)
*
* @retval None
*/
void TMR_DisableCCPreload(TMR_T *tmr)
void TMR_DisableCCPreload(TMR_T* tmr)
{
tmr->CTRL2_B.CCPEN = DISABLE;
}
@ -977,7 +977,7 @@ void TMR_DisableCCPreload(TMR_T *tmr)
* @arg TMR_OC_PRELOAD_ENABLE
* @retval None
*/
void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
{
tmr->CCM1_COMPARE_B.OC1PEN = OCPreload;
}
@ -993,7 +993,7 @@ void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
* @arg TMR_OC_PRELOAD_ENABLE
* @retval None
*/
void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
{
tmr->CCM1_COMPARE_B.OC2PEN = OCPreload;
}
@ -1009,7 +1009,7 @@ void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
* @arg TMR_OC_PRELOAD_ENABLE
* @retval None
*/
void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
{
tmr->CCM2_COMPARE_B.OC3PEN = OCPreload;
}
@ -1025,7 +1025,7 @@ void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
* @arg TMR_OC_PRELOAD_ENABLE
* @retval Nonee
*/
void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
{
tmr->CCM2_COMPARE_B.OC4PEN = OCPreload;
}
@ -1041,7 +1041,7 @@ void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
* @arg TMR_OC_FAST_ENABLE
* @retval None
*/
void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
{
tmr->CCM1_COMPARE_B.OC1FEN = OCFast;
}
@ -1057,7 +1057,7 @@ void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
* @arg TMR_OC_FAST_ENABLE
* @retval None
*/
void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
{
tmr->CCM1_COMPARE_B.OC2FEN = OCFast;
}
@ -1073,7 +1073,7 @@ void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
* @arg TMR_OC_FAST_ENABLE
* @retval None
*/
void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
{
tmr->CCM2_COMPARE_B.OC3FEN = OCFast;
}
@ -1089,7 +1089,7 @@ void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
* @arg TMR_OC_FAST_ENABLE
* @retval None
*/
void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
{
tmr->CCM2_COMPARE_B.OC4FEN = OCFast;
}
@ -1105,7 +1105,7 @@ void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
* @arg TMR_OC_CLEAR_ENABLE
* @retval None
*/
void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
{
tmr->CCM1_COMPARE_B.OC1CEN = OCClear;
}
@ -1121,7 +1121,7 @@ void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
* @arg TMR_OC_CLEAR_ENABLE
* @retval None
*/
void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
{
tmr->CCM1_COMPARE_B.OC2CEN = OCClear;
}
@ -1137,7 +1137,7 @@ void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
* @arg TMR_OC_CLEAR_ENABLE
* @retval None
*/
void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
{
tmr->CCM2_COMPARE_B.OC3CEN = OCClear;
}
@ -1153,7 +1153,7 @@ void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
* @arg TMR_OC_CLEAR_ENABLE
* @retval None
*/
void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
{
tmr->CCM2_COMPARE_B.OC4CEN = OCClear;
}
@ -1169,7 +1169,7 @@ void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
* @arg TMR_OC_POLARITY_LOW: Output Compare active low
* @retval Nonee
*/
void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
{
tmr->CCEN_B.CC1POL = polarity;
}
@ -1185,7 +1185,7 @@ void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
* @arg TMR_OC_NPOLARITY_LOW: Output Compare active low
* @retval None
*/
void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
{
tmr->CCEN_B.CC1NPOL = nPolarity;
}
@ -1201,7 +1201,7 @@ void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
* @arg TMR_OC_POLARITY_LOW: Output Compare active low
* @retval None
*/
void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
{
tmr->CCEN_B.CC2POL = polarity;
}
@ -1217,7 +1217,7 @@ void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
* @arg TMR_OC_NPOLARITY_LOW: Output Compare active low
* @retval None
*/
void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
{
tmr->CCEN_B.CC2NPOL = nPolarity;
}
@ -1233,7 +1233,7 @@ void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
* @arg TMR_OC_POLARITY_LOW: Output Compare active low
* @retval None
*/
void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
{
tmr->CCEN_B.CC3POL = polarity;
}
@ -1249,7 +1249,7 @@ void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
* @arg TMR_OC_NPOLARITY_LOW: Output Compare active low
* @retval None
*/
void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
{
tmr->CCEN_B.CC3NPOL = nPolarity;
}
@ -1265,7 +1265,7 @@ void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
* @arg TMR_OC_POLARITY_LOW: Output Compare active low
* @retval None
*/
void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
{
tmr->CCEN_B.CC4POL = polarity;
}
@ -1283,7 +1283,7 @@ void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
* @arg TMR_CHANNEL_4: Timer Channel 4
* @retval None
*/
void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
{
tmr->CCEN |= BIT_SET << channel;
}
@ -1301,7 +1301,7 @@ void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
* @arg TMR_CHANNEL_4: Timer Channel 4
* @retval None
*/
void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
{
tmr->CCEN &= BIT_RESET << channel;
}
@ -1318,7 +1318,7 @@ void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
* @arg TMR_CHANNEL_3: Timer Channel 3
* @retval None
*/
void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
{
tmr->CCEN |= 0x04 << channel;
}
@ -1335,7 +1335,7 @@ void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
* @arg TMR_CHANNEL_3: Timer Channel 3
* @retval None
*/
void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
{
tmr->CCEN &= BIT_RESET << channel;
}
@ -1364,7 +1364,7 @@ void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
* @arg TMR_OC_MODE_PWM2
* @retval None
*/
void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
{
tmr->CCEN &= BIT_RESET << channel;
@ -1393,7 +1393,7 @@ void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
*
* @retval None
*/
void TMR_EnableUpdate(TMR_T *tmr)
void TMR_EnableUpdate(TMR_T* tmr)
{
tmr->CTRL1_B.UD = DISABLE;
}
@ -1405,7 +1405,7 @@ void TMR_EnableUpdate(TMR_T *tmr)
*
* @retval None
*/
void TMR_DisableUpdate(TMR_T *tmr)
void TMR_DisableUpdate(TMR_T* tmr)
{
tmr->CTRL1_B.UD = ENABLE;
}
@ -1421,7 +1421,7 @@ void TMR_DisableUpdate(TMR_T *tmr)
* @arg TMR_UPDATE_SOURCE_REGULAR
* @retval None
*/
void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource)
void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource)
{
if (updateSource != TMR_UPDATE_SOURCE_GLOBAL)
{
@ -1440,7 +1440,7 @@ void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource)
*
* @retval None
*/
void TMR_EnableHallSensor(TMR_T *tmr)
void TMR_EnableHallSensor(TMR_T* tmr)
{
tmr->CTRL2_B.TI1SEL = ENABLE;
}
@ -1452,7 +1452,7 @@ void TMR_EnableHallSensor(TMR_T *tmr)
*
* @retval None
*/
void TMR_DisableHallSensor(TMR_T *tmr)
void TMR_DisableHallSensor(TMR_T* tmr)
{
tmr->CTRL2_B.TI1SEL = DISABLE;
}
@ -1468,7 +1468,7 @@ void TMR_DisableHallSensor(TMR_T *tmr)
* @arg TMR_SPM_SINGLE
* @retval None
*/
void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode)
void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode)
{
tmr->CTRL1_B.SPMEN = singlePulseMode;
}
@ -1491,7 +1491,7 @@ void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode)
* @arg TMR_TRGO_SOURCE_OC4REF
* @retval None
*/
void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource)
void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource)
{
tmr->CTRL2_B.MMSEL = TRGOSource;
}
@ -1509,7 +1509,7 @@ void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource)
* @arg TMR_SLAVE_MODE_EXTERNAL1
* @retval None
*/
void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode)
void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode)
{
tmr->SMCTRL_B.SMFSEL = slaveMode;
}
@ -1521,7 +1521,7 @@ void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode)
*
* @retval None
*/
void TMR_EnableMasterSlaveMode(TMR_T *tmr)
void TMR_EnableMasterSlaveMode(TMR_T* tmr)
{
tmr->SMCTRL_B.MSMEN = ENABLE;
}
@ -1533,7 +1533,7 @@ void TMR_EnableMasterSlaveMode(TMR_T *tmr)
*
* @retval None
*/
void TMR_DisableMasterSlaveMode(TMR_T *tmr)
void TMR_DisableMasterSlaveMode(TMR_T* tmr)
{
tmr->SMCTRL_B.MSMEN = DISABLE;
}
@ -1547,7 +1547,7 @@ void TMR_DisableMasterSlaveMode(TMR_T *tmr)
*
* @retval None
*/
void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter)
void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter)
{
tmr->CNT = counter;
}
@ -1561,7 +1561,7 @@ void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter)
*
* @retval None
*/
void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload)
void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload)
{
tmr->AUTORLD = autoReload;
}
@ -1575,7 +1575,7 @@ void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload)
*
* @retval None
*/
void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1)
void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1)
{
tmr->CC1 = compare1;
}
@ -1589,7 +1589,7 @@ void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1)
*
* @retval None
*/
void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2)
void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2)
{
tmr->CC2 = compare2;
}
@ -1603,7 +1603,7 @@ void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2)
*
* @retval None
*/
void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3)
void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3)
{
tmr->CC3 = compare3;
}
@ -1617,7 +1617,7 @@ void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3)
*
* @retval None
*/
void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4)
void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4)
{
tmr->CC4 = compare4;
}
@ -1635,7 +1635,7 @@ void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4)
* @arg TMR_IC_PSC_8: capture is done once every 8 events
* @retval None
*/
void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
{
tmr->CCM1_CAPTURE_B.IC1PSC = BIT_RESET;
tmr->CCM1_CAPTURE_B.IC1PSC = prescaler;
@ -1653,7 +1653,7 @@ void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
* @arg TMR_IC_PSC_8: capture is done once every 8 events
* @retval None
*/
void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
{
tmr->CCM1_CAPTURE_B.IC2PSC = BIT_RESET;
tmr->CCM1_CAPTURE_B.IC2PSC = prescaler;
@ -1672,7 +1672,7 @@ void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
* @arg TMR_IC_PSC_8: capture is done once every 8 events
* @retval None
*/
void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
{
tmr->CCM2_CAPTURE_B.IC3PSC = BIT_RESET;
tmr->CCM2_CAPTURE_B.IC3PSC = prescaler;
@ -1691,7 +1691,7 @@ void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
* @arg TMR_IC_PSC_8: capture is done once every 8 events
* @retval None
*/
void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
{
tmr->CCM2_CAPTURE_B.IC4PSC = BIT_RESET;
tmr->CCM2_CAPTURE_B.IC4PSC = prescaler;
@ -1709,7 +1709,7 @@ void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
* @arg TMR_CLOCK_DIV_4: TDTS = 4*Tck_tim
* @retval None
*/
void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision)
void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision)
{
tmr->CTRL1_B.CLKDIV = clockDivision;
}
@ -1721,7 +1721,7 @@ void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision)
*
* @retval Capture Compare 1 Register value.
*/
uint16_t TMR_ReadCaputer1(TMR_T *tmr)
uint16_t TMR_ReadCaputer1(TMR_T* tmr)
{
return tmr->CC1;
}
@ -1733,7 +1733,7 @@ uint16_t TMR_ReadCaputer1(TMR_T *tmr)
*
* @retval Capture Compare 2 Register value.
*/
uint16_t TMR_ReadCaputer2(TMR_T *tmr)
uint16_t TMR_ReadCaputer2(TMR_T* tmr)
{
return tmr->CC2;
}
@ -1745,7 +1745,7 @@ uint16_t TMR_ReadCaputer2(TMR_T *tmr)
*
* @retval Capture Compare 3 Register value.
*/
uint16_t TMR_ReadCaputer3(TMR_T *tmr)
uint16_t TMR_ReadCaputer3(TMR_T* tmr)
{
return tmr->CC3;
}
@ -1757,7 +1757,7 @@ uint16_t TMR_ReadCaputer3(TMR_T *tmr)
*
* @retval Capture Compare 4 Register value.
*/
uint16_t TMR_ReadCaputer4(TMR_T *tmr)
uint16_t TMR_ReadCaputer4(TMR_T* tmr)
{
return tmr->CC4;
}
@ -1769,7 +1769,7 @@ uint16_t TMR_ReadCaputer4(TMR_T *tmr)
*
* @retval Counter Register value.
*/
uint16_t TMR_ReadCounter(TMR_T *tmr)
uint16_t TMR_ReadCounter(TMR_T* tmr)
{
return tmr->CNT;
}
@ -1781,7 +1781,7 @@ uint16_t TMR_ReadCounter(TMR_T *tmr)
*
* @retval Prescaler Register value.
*/
uint16_t TMR_ReadPrescaler(TMR_T *tmr)
uint16_t TMR_ReadPrescaler(TMR_T* tmr)
{
return tmr->PSC;
}
@ -1805,7 +1805,7 @@ uint16_t TMR_ReadPrescaler(TMR_T *tmr)
*
* @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
*/
void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt)
void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt)
{
tmr->DIEN |= interrupt;
}
@ -1829,7 +1829,7 @@ void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt)
*
* @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
*/
void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt)
void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt)
{
tmr->DIEN &= ~interrupt;
}
@ -1853,7 +1853,7 @@ void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt)
*
* @note TMR6 and TMR7 can only generate an TMR_EVENT_UPDATE.
*/
void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources)
void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources)
{
tmr->CEG = eventSources;
}
@ -1881,7 +1881,7 @@ void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources)
*
* @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE.
*/
uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag)
uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag)
{
return (tmr->STS & flag) ? SET : RESET;
}
@ -1909,7 +1909,7 @@ uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag)
*
* @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE.
*/
void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag)
void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag)
{
tmr->STS = ~flag;
}
@ -1933,9 +1933,9 @@ void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag)
*
* @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
*/
uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag)
uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag)
{
if (((tmr->STS & flag) != RESET) && ((tmr->DIEN & flag) != RESET))
if (((tmr->STS & flag) != RESET ) && ((tmr->DIEN & flag) != RESET))
{
return SET;
}
@ -1964,7 +1964,7 @@ uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag)
*
* @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
*/
void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag)
void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag)
{
tmr->STS = ~flag;
}
@ -1982,7 +1982,7 @@ void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag)
*
* @retval None
*/
static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
{
uint16_t tmpchctrl = 0;
@ -1994,7 +1994,7 @@ static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
tmr->CCM1_CAPTURE_B.IC1F = ICfilter;
if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
(tmr == TMR4) || (tmr == TMR5))
(tmr == TMR4) || (tmr == TMR5))
{
tmr->CCEN_B.CC1POL = BIT_RESET;
tmr->CCEN_B.CC1EN = BIT_SET;
@ -2026,7 +2026,7 @@ static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
*
* @retval None
*/
static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
{
uint16_t tmpchctrl = 0;
@ -2038,7 +2038,7 @@ static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
tmr->CCM1_CAPTURE_B.IC2F = ICfilter;
if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
(tmr == TMR4) || (tmr == TMR5))
(tmr == TMR4) || (tmr == TMR5))
{
tmr->CCEN_B.CC2POL = BIT_RESET;
tmr->CCEN_B.CC2EN = BIT_SET;
@ -2070,7 +2070,7 @@ static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
*
* @retval None
*/
static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
{
uint16_t tmpchctrl = 0;
@ -2082,7 +2082,7 @@ static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
tmr->CCM2_CAPTURE_B.IC3F = ICfilter;
if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
(tmr == TMR4) || (tmr == TMR5))
(tmr == TMR4) || (tmr == TMR5))
{
tmr->CCEN_B.CC3POL = BIT_RESET;
tmr->CCEN_B.CC3EN = BIT_SET;
@ -2114,7 +2114,7 @@ static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
*
* @retval None
*/
static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
{
uint16_t tmpchctrl = 0;

80
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c
View File

@ -47,7 +47,7 @@
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Reset(USART_T *usart)
void USART_Reset(USART_T* usart)
{
if (USART1 == usart)
{
@ -87,7 +87,7 @@ void USART_Reset(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Config(USART_T *uart, USART_Config_T *usartConfig)
void USART_Config(USART_T* uart, USART_Config_T* usartConfig)
{
uint32_t temp, fCLK, intDiv, fractionalDiv;
@ -132,7 +132,7 @@ void USART_Config(USART_T *uart, USART_Config_T *usartConfig)
*
* @retval None
*/
void USART_ConfigStructInit(USART_Config_T *usartConfig)
void USART_ConfigStructInit(USART_Config_T* usartConfig)
{
usartConfig->baudRate = 9600;
usartConfig->wordLength = USART_WORD_LEN_8B;
@ -153,7 +153,7 @@ void USART_ConfigStructInit(USART_Config_T *usartConfig)
*
* @note The usart can be USART1, USART2, USART3
*/
void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig)
void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig)
{
usart->CTRL2_B.CLKEN = clockConfig->clock;
usart->CTRL2_B.CPHA = clockConfig->phase;
@ -169,7 +169,7 @@ void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig)
* @retval None
*
*/
void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig)
void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig)
{
clockConfig->clock = USART_CLKEN_DISABLE;
clockConfig->phase = USART_CLKPHA_1EDGE;
@ -186,7 +186,7 @@ void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Enable(USART_T *usart)
void USART_Enable(USART_T* usart)
{
usart->CTRL1_B.UEN = BIT_SET;
}
@ -200,7 +200,7 @@ void USART_Enable(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Disable(USART_T *usart)
void USART_Disable(USART_T* usart)
{
usart->CTRL1_B.UEN = BIT_RESET;
}
@ -220,7 +220,7 @@ void USART_Disable(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq)
void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq)
{
usart->CTRL3 |= dmaReq;
}
@ -240,7 +240,7 @@ void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq)
void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq)
{
usart->CTRL3 &= (uint32_t)~dmaReq;
}
@ -256,7 +256,7 @@ void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_Address(USART_T *usart, uint8_t address)
void USART_Address(USART_T* usart, uint8_t address)
{
usart->CTRL2_B.ADDR = address;
}
@ -275,7 +275,7 @@ void USART_Address(USART_T *usart, uint8_t address)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup)
void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup)
{
usart->CTRL1_B.WUPMCFG = wakeup;
}
@ -289,7 +289,7 @@ void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableMuteMode(USART_T *usart)
void USART_EnableMuteMode(USART_T* usart)
{
usart->CTRL1_B.RXMUTEEN = BIT_SET;
}
@ -303,7 +303,7 @@ void USART_EnableMuteMode(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableMuteMode(USART_T *usart)
void USART_DisableMuteMode(USART_T* usart)
{
usart->CTRL1_B.RXMUTEEN = BIT_RESET;
}
@ -322,7 +322,7 @@ void USART_DisableMuteMode(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length)
void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length)
{
usart->CTRL2_B.LBDLCFG = length;
}
@ -336,7 +336,7 @@ void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableLIN(USART_T *usart)
void USART_EnableLIN(USART_T* usart)
{
usart->CTRL2_B.LINMEN = BIT_SET;
}
@ -350,7 +350,7 @@ void USART_EnableLIN(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableLIN(USART_T *usart)
void USART_DisableLIN(USART_T* usart)
{
usart->CTRL2_B.LINMEN = BIT_RESET;
}
@ -364,7 +364,7 @@ void USART_DisableLIN(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableTx(USART_T *usart)
void USART_EnableTx(USART_T* usart)
{
usart->CTRL1_B.TXEN = BIT_SET;
}
@ -378,7 +378,7 @@ void USART_EnableTx(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableTx(USART_T *usart)
void USART_DisableTx(USART_T* usart)
{
usart->CTRL1_B.TXEN = BIT_RESET;
}
@ -392,7 +392,7 @@ void USART_DisableTx(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableRx(USART_T *usart)
void USART_EnableRx(USART_T* usart)
{
usart->CTRL1_B.RXEN = BIT_SET;
}
@ -406,7 +406,7 @@ void USART_EnableRx(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableRx(USART_T *usart)
void USART_DisableRx(USART_T* usart)
{
usart->CTRL1_B.RXEN = BIT_RESET;
}
@ -422,7 +422,7 @@ void USART_DisableRx(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_TxData(USART_T *usart, uint16_t data)
void USART_TxData(USART_T* usart, uint16_t data)
{
usart->DATA_B.DATA = data;
}
@ -436,7 +436,7 @@ void USART_TxData(USART_T *usart, uint16_t data)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
uint16_t USART_RxData(USART_T *usart)
uint16_t USART_RxData(USART_T* usart)
{
return (uint16_t)(usart->DATA_B.DATA);
}
@ -450,7 +450,7 @@ uint16_t USART_RxData(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_TxBreak(USART_T *usart)
void USART_TxBreak(USART_T* usart)
{
usart->CTRL1_B.TXBF = BIT_SET;
}
@ -466,7 +466,7 @@ void USART_TxBreak(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3
*/
void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime)
void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime)
{
usart->GTPSC_B.GRDT = guardTime;
}
@ -482,7 +482,7 @@ void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime)
*
* @note The usart can be USART1, USART2, USART3
*/
void USART_ConfigPrescaler(USART_T *usart, uint8_t div)
void USART_ConfigPrescaler(USART_T* usart, uint8_t div)
{
usart->GTPSC_B.PSC = div;
}
@ -496,7 +496,7 @@ void USART_ConfigPrescaler(USART_T *usart, uint8_t div)
*
* @note The Smart Card mode is not available for UART4 and UART5
*/
void USART_EnableSmartCard(USART_T *usart)
void USART_EnableSmartCard(USART_T* usart)
{
usart->CTRL3_B.SCEN = BIT_SET;
}
@ -510,7 +510,7 @@ void USART_EnableSmartCard(USART_T *usart)
*
* @note The Smart Card mode is not available for UART4 and UART5
*/
void USART_DisableSmartCard(USART_T *usart)
void USART_DisableSmartCard(USART_T* usart)
{
usart->CTRL3_B.SCEN = BIT_RESET;
}
@ -524,7 +524,7 @@ void USART_DisableSmartCard(USART_T *usart)
*
* @note The Smart Card mode is not available for UART4 and UART5
*/
void USART_EnableSmartCardNACK(USART_T *usart)
void USART_EnableSmartCardNACK(USART_T* usart)
{
usart->CTRL3_B.SCNACKEN = BIT_SET;
}
@ -538,7 +538,7 @@ void USART_EnableSmartCardNACK(USART_T *usart)
*
* @note The Smart Card mode is not available for UART4 and UART5
*/
void USART_DisableSmartCardNACK(USART_T *usart)
void USART_DisableSmartCardNACK(USART_T* usart)
{
usart->CTRL3_B.SCNACKEN = BIT_RESET;
}
@ -552,7 +552,7 @@ void USART_DisableSmartCardNACK(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableHalfDuplex(USART_T *usart)
void USART_EnableHalfDuplex(USART_T* usart)
{
usart->CTRL3_B.HDEN = BIT_SET;
}
@ -566,7 +566,7 @@ void USART_EnableHalfDuplex(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableHalfDuplex(USART_T *usart)
void USART_DisableHalfDuplex(USART_T* usart)
{
usart->CTRL3_B.HDEN = BIT_RESET;
}
@ -584,7 +584,7 @@ void USART_DisableHalfDuplex(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode)
void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode)
{
usart->CTRL3_B.IRLPEN = IrDAMode;
}
@ -598,7 +598,7 @@ void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableIrDA(USART_T *usart)
void USART_EnableIrDA(USART_T* usart)
{
usart->CTRL3_B.IREN = BIT_SET;
}
@ -612,7 +612,7 @@ void USART_EnableIrDA(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableIrDA(USART_T *usart)
void USART_DisableIrDA(USART_T* usart)
{
usart->CTRL3_B.IREN = BIT_RESET;
}
@ -637,7 +637,7 @@ void USART_DisableIrDA(USART_T *usart)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt)
void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt)
{
uint32_t temp;
@ -679,7 +679,7 @@ void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt)
void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt)
{
uint32_t temp;
@ -723,7 +723,7 @@ void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag)
uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag)
{
return (usart->STS & flag) ? SET : RESET;
}
@ -744,7 +744,7 @@ uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag)
void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag)
{
usart->STS &= (uint32_t)~flag;
}
@ -771,7 +771,7 @@ void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag)
uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag)
{
uint32_t itFlag, srFlag;
@ -816,7 +816,7 @@ uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag)
*
* @note The usart can be USART1, USART2, USART3, UART4 and UART5
*/
void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag)
void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag)
{
uint32_t srFlag;

2
bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c
View File

@ -139,7 +139,7 @@ void WWDT_Enable(uint8_t counter)
*/
uint8_t WWDT_ReadFlag(void)
{
return (uint8_t)(WWDT->STS);
return (uint8_t) (WWDT->STS);
}
/*!

267
bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h
View File

@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@ -27,78 +27,107 @@
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
@ -129,8 +158,8 @@
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return (__regControl);
register uint32_t __regControl __ASM("control");
return(__regControl);
}
@ -141,8 +170,8 @@ __STATIC_INLINE uint32_t __get_CONTROL(void)
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
register uint32_t __regControl __ASM("control");
__regControl = control;
}
@ -153,8 +182,8 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control)
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
@ -165,8 +194,8 @@ __STATIC_INLINE uint32_t __get_IPSR(void)
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
@ -177,8 +206,8 @@ __STATIC_INLINE uint32_t __get_APSR(void)
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
@ -189,8 +218,8 @@ __STATIC_INLINE uint32_t __get_xPSR(void)
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
@ -201,8 +230,8 @@ __STATIC_INLINE uint32_t __get_PSP(void)
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
@ -213,8 +242,8 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
@ -225,8 +254,8 @@ __STATIC_INLINE uint32_t __get_MSP(void)
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
@ -237,8 +266,8 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
@ -249,8 +278,8 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void)
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
@ -280,8 +309,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
@ -292,8 +321,8 @@ __STATIC_INLINE uint32_t __get_BASEPRI(void)
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
@ -305,8 +334,8 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
@ -317,8 +346,8 @@ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
@ -329,8 +358,8 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
@ -346,10 +375,10 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr);
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return (0U);
return(0U);
#endif
}
@ -363,10 +392,10 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
(void)fpscr;
#endif
}
@ -462,8 +491,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
rev16 r0, r0
bx lr
}
#endif
@ -477,8 +506,8 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
revsh r0, r0
bx lr
}
#endif
@ -511,22 +540,22 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
@ -550,9 +579,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
@ -563,9 +592,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
@ -576,9 +605,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
@ -591,9 +620,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
@ -606,9 +635,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
@ -621,9 +650,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
@ -664,8 +693,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
rrx r0, r0
bx lr
}
#endif
@ -735,20 +764,20 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
return max;
}
return val;
else if (val < min)
{
return min;
}
}
return val;
}
/**
@ -760,25 +789,25 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint3
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
return max;
}
return (uint32_t)val;
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/**@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
@ -859,7 +888,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
/**@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

1042
bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h
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File diff suppressed because it is too large Load Diff

849
bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h
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File diff suppressed because it is too large Load Diff

326
bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@ -31,243 +31,251 @@
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#include <cmsis_ccs.h>
#ifndef __ASM
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#include <cmsis_csm.h>
#ifndef __ASM
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#error Unknown compiler.
#endif

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bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h
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bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_iccarm.h
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bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h
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@ -23,9 +23,9 @@
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H

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bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h
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bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h
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