From 23786ee481698063b64d8dff37c7ac6e4351e406 Mon Sep 17 00:00:00 2001 From: yuanzihao Date: Sat, 11 Mar 2023 12:21:31 +0800 Subject: [PATCH] [GD32]add gd32470z-lckfb (#7022) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * --复制gd32450z-eval 作为立创梁山派 gd32470z-lckfb的模板进行移植 * -修改模板keil工程的配置，IROM需要注意总共为1024k，分为Code area 和Data area ，IRAM1为 ： 512K-64K=448K=458752=0x70000。 -重新用ENV生成编译固件 片上SRAM可分为4块，分别为SRAM0（112KB）、SRAM1（16KB）、SRAM2（64KB）和TCMSRAM（64KB）。SRAM0、SRAM1和SRAM2可以被所有的AHB主机访问，然而，TCMSRAM（紧耦合存储器SRAM）只可被Cortex ® -M4内核的数据总线访问。BKPSRAM（备份SRAM）应用于备份域，即使当VDD供电电源掉电时，该SRAM仍可保持其内容。附加SRAM（ADDSRAM）只在一些特殊的GD32F4xx器件中可用。由于采用AHB互联矩阵，上述SRAM块可以同时被不同的AHB主机访问，例如，即使CPU正在访问SRAM0，USBHS也可以访问SRAM1。 * -修改IAR编译的链接脚本 * --修改Flash和RAM大小 -RAM大小为448k是因为512K-64K=448K，其中后面的64K为TCMSRAM（紧耦合存储器SRAM）只可被Cortex ® -M4内核的数据总线访问，先不要乱分配 * -修改MDK链接脚本 * -修改board.h * -修改MCU型号 * -Finsh控制台和LED1闪灯程序工作正常，串口控制台名称错误，从uart改为uart0 -Scons正常生成工程 * -发现GD32固件库当前没有240Mhz的时钟配置，将固件库升级为GD32F4xx_Firmware_Library_V3.0.3-发布时间为2023-01-04 * -修改bsp/gd32/arm/gd32407v-start/board/SConscript文件 * -修改led1和change logs * -按照提交规范使能 One ELF Section per Function（MDK） 并用scons重新生成工程 * -发现整个GD32的IAR模板工程template.eww 是没有的，所以当前是不支持IAR开发的，需要后面学习一下IAR使用再实现了。 * -使用formatting源码格式化工具跑一边gd32470z-lckfb目录 * -使用formatting源码格式化工具跑一遍[components/net/netdev/src/netdev.c] -三个月前的提交多了几个空格 --- .github/workflows/action.yml | 1 + bsp/gd32/README.md | 2 +- bsp/gd32/arm/README.md | 1 + bsp/gd32/arm/gd32470z-lckfb/.config | 714 ++++ bsp/gd32/arm/gd32470z-lckfb/Kconfig | 21 + bsp/gd32/arm/gd32470z-lckfb/README.md | 116 + bsp/gd32/arm/gd32470z-lckfb/SConscript | 15 + bsp/gd32/arm/gd32470z-lckfb/SConstruct | 60 + .../gd32470z-lckfb/applications/SConscript | 15 + .../arm/gd32470z-lckfb/applications/main.c | 36 + bsp/gd32/arm/gd32470z-lckfb/board/Kconfig | 241 ++ bsp/gd32/arm/gd32470z-lckfb/board/SConscript | 28 + bsp/gd32/arm/gd32470z-lckfb/board/board.c | 85 + bsp/gd32/arm/gd32470z-lckfb/board/board.h | 47 + .../gd32470z-lckfb/board/gd32f4xx_libopt.h | 45 + .../board/linker_scripts/link.icf | 40 + .../board/linker_scripts/link.ld | 142 + .../board/linker_scripts/link.sct | 15 + bsp/gd32/arm/gd32470z-lckfb/figures/board.png | Bin 0 -> 405988 bytes bsp/gd32/arm/gd32470z-lckfb/project.ewd | 3056 +++++++++++++++++ bsp/gd32/arm/gd32470z-lckfb/project.ewp | 2321 +++++++++++++ bsp/gd32/arm/gd32470z-lckfb/project.eww | 10 + bsp/gd32/arm/gd32470z-lckfb/project.uvoptx | 917 +++++ bsp/gd32/arm/gd32470z-lckfb/project.uvproj | 838 +++++ bsp/gd32/arm/gd32470z-lckfb/project.uvprojx | 732 ++++ bsp/gd32/arm/gd32470z-lckfb/rtconfig.h | 201 ++ bsp/gd32/arm/gd32470z-lckfb/rtconfig.py | 150 + bsp/gd32/arm/gd32470z-lckfb/template.ewp | 1892 ++++++++++ bsp/gd32/arm/gd32470z-lckfb/template.uvoptx | 185 + bsp/gd32/arm/gd32470z-lckfb/template.uvproj | 628 ++++ bsp/gd32/arm/gd32470z-lckfb/template.uvprojx | 412 +++ bsp/gd32/arm/libraries/.ignore_format.yml | 9 + .../CMSIS/GD/GD32F4xx/Include/gd32f4xx.h | 74 +- .../Source/ARM/startup_gd32f405_425.s | 423 +++ .../Source/ARM/startup_gd32f407_427.s | 429 +++ .../Source/ARM/startup_gd32f450_470.s | 454 +++ .../Source/IAR/startup_gd32f405_425.s | 602 ++++ .../Source/IAR/startup_gd32f407_427.s | 617 ++++ .../Source/IAR/startup_gd32f450_470.s | 666 ++++ .../GD/GD32F4xx/Source/system_gd32f4xx.c | 443 ++- .../CMSIS/core_cm4.h | 6 +- .../CMSIS/core_cmFunc.h | 144 +- .../CMSIS/core_cmInstr.h | 496 +-- .../Include/gd32f4xx_adc.h | 605 ++-- .../Include/gd32f4xx_can.h | 339 +- .../Include/gd32f4xx_crc.h | 41 +- .../Include/gd32f4xx_ctc.h | 45 +- .../Include/gd32f4xx_dac.h | 47 +- .../Include/gd32f4xx_dbg.h | 54 +- .../Include/gd32f4xx_dci.h | 45 +- .../Include/gd32f4xx_dma.h | 160 +- .../Include/gd32f4xx_enet.h | 315 +- .../Include/gd32f4xx_exmc.h | 91 +- .../Include/gd32f4xx_exti.h | 115 +- .../Include/gd32f4xx_fmc.h | 116 +- .../Include/gd32f4xx_fwdgt.h | 42 +- .../Include/gd32f4xx_gpio.h | 77 +- .../Include/gd32f4xx_i2c.h | 431 ++- .../Include/gd32f4xx_ipa.h | 75 +- .../Include/gd32f4xx_iref.h | 43 +- .../Include/gd32f4xx_misc.h | 58 +- .../Include/gd32f4xx_pmu.h | 247 +- .../Include/gd32f4xx_rcu.h | 174 +- .../Include/gd32f4xx_rtc.h | 47 +- .../Include/gd32f4xx_sdio.h | 39 +- .../Include/gd32f4xx_spi.h | 117 +- .../Include/gd32f4xx_syscfg.h | 37 +- .../Include/gd32f4xx_timer.h | 126 +- .../Include/gd32f4xx_tli.h | 103 +- .../Include/gd32f4xx_trng.h | 75 +- .../Include/gd32f4xx_usart.h | 215 +- .../Include/gd32f4xx_wwdgt.h | 46 +- .../Source/gd32f4xx_adc.c | 919 ++--- .../Source/gd32f4xx_can.c | 511 ++- .../Source/gd32f4xx_crc.c | 6 +- .../Source/gd32f4xx_ctc.c | 86 +- .../Source/gd32f4xx_dac.c | 163 +- .../Source/gd32f4xx_dbg.c | 35 +- .../Source/gd32f4xx_dci.c | 67 +- .../Source/gd32f4xx_dma.c | 473 ++- .../Source/gd32f4xx_enet.c | 859 ++--- .../Source/gd32f4xx_exmc.c | 395 ++- .../Source/gd32f4xx_exti.c | 64 +- .../Source/gd32f4xx_fmc.c | 470 ++- .../Source/gd32f4xx_fwdgt.c | 129 +- .../Source/gd32f4xx_gpio.c | 55 +- .../Source/gd32f4xx_i2c.c | 241 +- .../Source/gd32f4xx_ipa.c | 178 +- .../Source/gd32f4xx_iref.c | 7 +- .../Source/gd32f4xx_misc.c | 61 +- .../Source/gd32f4xx_pmu.c | 323 +- .../Source/gd32f4xx_rcu.c | 649 ++-- .../Source/gd32f4xx_rtc.c | 275 +- .../Source/gd32f4xx_sdio.c | 107 +- .../Source/gd32f4xx_spi.c | 393 +-- .../Source/gd32f4xx_syscfg.c | 25 +- .../Source/gd32f4xx_timer.c | 497 +-- .../Source/gd32f4xx_tli.c | 164 +- .../Source/gd32f4xx_trng.c | 49 +- .../Source/gd32f4xx_usart.c | 254 +- .../Source/gd32f4xx_wwdgt.c | 97 +- .../device/class/audio/Include/audio_core.h | 226 +- .../class/audio/Include/audio_out_itf.h | 67 +- .../device/class/audio/Source/audio_core.c | 762 ++-- .../device/class/audio/Source/audio_out_itf.c | 218 +- .../device/class/cdc/Include/cdc_acm_core.h | 42 +- .../device/class/cdc/Source/cdc_acm_core.c | 250 +- .../device/class/dfu/Include/dfu_core.h | 49 +- .../device/class/dfu/Include/dfu_mem.h | 85 + .../device/class/dfu/Source/dfu_core.c | 292 +- .../device/class/dfu/Source/dfu_mem.c | 245 ++ .../class/hid/Include/custom_hid_core.h | 34 +- .../class/hid/Include/standard_hid_core.h | 36 +- .../device/class/hid/Source/custom_hid_core.c | 201 +- .../class/hid/Source/standard_hid_core.c | 208 +- .../device/class/iap/Include/usb_iap_core.h | 40 +- .../device/class/iap/Source/usb_iap_core.c | 208 +- .../device/class/msc/Include/usbd_msc_bbb.h | 38 +- .../device/class/msc/Include/usbd_msc_core.h | 34 +- .../device/class/msc/Include/usbd_msc_mem.h | 36 +- .../device/class/msc/Include/usbd_msc_scsi.h | 44 +- .../device/class/msc/Source/usbd_msc_bbb.c | 66 +- .../device/class/msc/Source/usbd_msc_core.c | 216 +- .../device/class/msc/Source/usbd_msc_scsi.c | 148 +- .../class/printer/Include/printer_core.h | 34 +- .../class/printer/Source/printer_core.c | 154 +- .../device/core/Include/usbd_core.h | 38 +- .../device/core/Include/usbd_enum.h | 38 +- .../device/core/Include/usbd_transc.h | 34 +- .../device/core/Source/usbd_core.c | 36 +- .../device/core/Source/usbd_enum.c | 130 +- .../device/core/Source/usbd_transc.c | 42 +- .../driver/Include/drv_usb_core.h | 63 +- .../driver/Include/drv_usb_dev.h | 36 +- .../driver/Include/drv_usb_host.h | 36 +- .../driver/Include/drv_usb_hw.h | 51 +- .../driver/Include/drv_usb_regs.h | 56 +- .../driver/Include/drv_usbd_int.h | 34 +- .../driver/Include/drv_usbh_int.h | 42 +- .../driver/Source/drv_usb_core.c | 79 +- .../driver/Source/drv_usb_dev.c | 60 +- .../driver/Source/drv_usb_host.c | 49 +- .../driver/Source/drv_usbd_int.c | 71 +- .../driver/Source/drv_usbh_int.c | 114 +- .../host/class/hid/Include/usbh_hid_core.h | 132 +- .../class/hid/Include/usbh_standard_hid.h | 101 + .../host/class/hid/Source/usbh_hid_core.c | 169 +- .../host/class/hid/Source/usbh_standard_hid.c | 276 ++ .../host/class/msc/Include/usbh_msc_bbb.h | 122 +- .../host/class/msc/Include/usbh_msc_core.h | 42 +- .../host/class/msc/Include/usbh_msc_scsi.h | 36 +- .../host/class/msc/Source/usbh_msc_bbb.c | 228 +- .../host/class/msc/Source/usbh_msc_core.c | 303 +- .../host/class/msc/Source/usbh_msc_fatfs.c | 52 +- .../host/class/msc/Source/usbh_msc_scsi.c | 272 +- .../host/core/Include/usbh_core.h | 79 +- .../host/core/Include/usbh_enum.h | 37 +- .../host/core/Include/usbh_pipe.h | 46 +- .../host/core/Include/usbh_transc.h | 35 +- .../host/core/Source/usbh_core.c | 233 +- .../host/core/Source/usbh_enum.c | 58 +- .../host/core/Source/usbh_pipe.c | 59 +- .../host/core/Source/usbh_transc.c | 67 +- .../ustd/class/cdc/usb_cdc.h | 34 +- .../ustd/class/hid/usb_hid.h | 36 +- .../ustd/class/msc/msc_bbb.h | 38 +- .../ustd/class/msc/msc_scsi.h | 34 +- .../ustd/class/msc/usb_msc.h | 34 +- .../ustd/common/usb_ch9_std.h | 36 +- components/net/netdev/src/netdev.c | 2 +- 170 files changed, 26786 insertions(+), 9323 deletions(-) create mode 100644 bsp/gd32/arm/gd32470z-lckfb/.config create mode 100644 bsp/gd32/arm/gd32470z-lckfb/Kconfig create mode 100644 bsp/gd32/arm/gd32470z-lckfb/README.md create mode 100644 bsp/gd32/arm/gd32470z-lckfb/SConscript create mode 100644 bsp/gd32/arm/gd32470z-lckfb/SConstruct create mode 100644 bsp/gd32/arm/gd32470z-lckfb/applications/SConscript create mode 100644 bsp/gd32/arm/gd32470z-lckfb/applications/main.c create mode 100644 bsp/gd32/arm/gd32470z-lckfb/board/Kconfig create mode 100644 bsp/gd32/arm/gd32470z-lckfb/board/SConscript create mode 100644 bsp/gd32/arm/gd32470z-lckfb/board/board.c create mode 100644 bsp/gd32/arm/gd32470z-lckfb/board/board.h create mode 100644 bsp/gd32/arm/gd32470z-lckfb/board/gd32f4xx_libopt.h create mode 100644 bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.icf create mode 100644 bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.ld create mode 100644 bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.sct create mode 100644 bsp/gd32/arm/gd32470z-lckfb/figures/board.png create mode 100644 bsp/gd32/arm/gd32470z-lckfb/project.ewd create mode 100644 bsp/gd32/arm/gd32470z-lckfb/project.ewp create mode 100644 bsp/gd32/arm/gd32470z-lckfb/project.eww create mode 100644 bsp/gd32/arm/gd32470z-lckfb/project.uvoptx create mode 100644 bsp/gd32/arm/gd32470z-lckfb/project.uvproj create mode 100644 bsp/gd32/arm/gd32470z-lckfb/project.uvprojx create mode 100644 bsp/gd32/arm/gd32470z-lckfb/rtconfig.h create mode 100644 bsp/gd32/arm/gd32470z-lckfb/rtconfig.py create mode 100644 bsp/gd32/arm/gd32470z-lckfb/template.ewp create mode 100644 bsp/gd32/arm/gd32470z-lckfb/template.uvoptx create mode 100644 bsp/gd32/arm/gd32470z-lckfb/template.uvproj create mode 100644 bsp/gd32/arm/gd32470z-lckfb/template.uvprojx create mode 100644 bsp/gd32/arm/libraries/.ignore_format.yml create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f405_425.s create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f407_427.s create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f450_470.s create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f405_425.s create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f407_427.s create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f450_470.s create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Include/dfu_mem.h create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Source/dfu_mem.c create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Include/usbh_standard_hid.h create mode 100644 bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Source/usbh_standard_hid.c diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 77aee2fdb7..8c4940b131 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -82,6 +82,7 @@ jobs: - {RTT_BSP: "gd32/arm/gd32307e-start", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "gd32/arm/gd32407v-start", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "gd32/arm/gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "gd32/arm/gd32470z-lckfb", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "gd32vf103v-eval", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"} - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"} diff --git a/bsp/gd32/README.md b/bsp/gd32/README.md index 2f9263244b..b7f94cc13b 100644 --- a/bsp/gd32/README.md +++ b/bsp/gd32/README.md @@ -21,7 +21,7 @@ GD32 系列 BSP 目前支持情况如下表所示： | **F4 系列** | | | [gd32407v-start](arm/gd32407v-start) | 兆易创新 官方 GD32407V-START 开发板 | | [gd32450z-eval](arm/gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 | -| | | +| [gd32470z-lckfb](arm/gd32470z-lckfb) | 立创梁山派 GD32F470ZGT6 开发板 | | **RISC-V 系列** | | | **VF1 系列** | | | [gd32vf103v-eval](risc-v/gd32vf103v-eval) | 兆易创新 官方 GGD32VF103V-EVAL 开发板 | diff --git a/bsp/gd32/arm/README.md b/bsp/gd32/arm/README.md index abb9515a5e..383b7ae3e6 100644 --- a/bsp/gd32/arm/README.md +++ b/bsp/gd32/arm/README.md @@ -20,6 +20,7 @@ GD32 ARM 系列 BSP 目前支持情况如下表所示： | **F4 系列** | | | [gd32407v-start](gd32407v-start) | 兆易创新 官方 GD32407V-START 开发板 | | [gd32450z-eval](gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 | +| [gd32470z-lckfb](gd32470z-lckfb) | 立创梁山派 GD32F470ZGT6 开发板 | 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示： diff --git a/bsp/gd32/arm/gd32470z-lckfb/.config b/bsp/gd32/arm/gd32470z-lckfb/.config new file mode 100644 index 0000000000..8486dc4b9e --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/.config @@ -0,0 +1,714 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=11 +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +# CONFIG_RT_USING_DFS_DEVFS is not set +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_RTT_ESP_IDF is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_SERIES_GD32F4xx=y +CONFIG_SOC_GD32470Z=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_USBH is not set + +# +# Board extended module Drivers +# diff --git a/bsp/gd32/arm/gd32470z-lckfb/Kconfig b/bsp/gd32/arm/gd32470z-lckfb/Kconfig new file mode 100644 index 0000000000..609eb0745e --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/gd32/arm/gd32470z-lckfb/README.md b/bsp/gd32/arm/gd32470z-lckfb/README.md new file mode 100644 index 0000000000..93c1e6f463 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/README.md @@ -0,0 +1,116 @@ +# GD32470-LCKFB梁山派开发板BSP说明 + +## 简介 + +GD32470Z-LCKFB梁山派是立创开发板推出的一款GD32F470系列的开发板，最高主频高达240M，该开发板具有丰富的板载资源，是基于GD32F470ZGT6的全国产化开源开发板，图片如下： + +![board](figures/board.png) + +> 2022年12月05号后立创·梁山派开发板主控从GD32F450ZGT6升级到了GD32F470ZGT6 两款芯片兼容主要差别GD32F450ZGT6主频200、SDRAM 256K，GD32F470ZGT6主频240、SDRAM 512K。 + +该开发板常用 **板载资源** 如下： + +- GD32F470ZGT6，主频 240MHz，CPU内核：ARM Cortex-M4，1024KB FLASH ，512KB RAM +- 常用外设 + + - 用户LED ：4个，LED1 (PE3），LED2（PD7），LED3（PG3），LED4（PA5） + - 电源指示灯：一个红色LED + - 按键：3个，KEY_UP（PA0），RESET(NRST)，BOOT0（PB2） + - General TM * 10、Advanced TM * 2、Basic TM * 2 + - SysTick * 1 + - 看门狗 * 2 + - RTC * 1 + - USART * 4、UART * 4 + - I2C * 3、I2S * 2 + - SPI * 6 + - SDIO * 1 + - CAN * 2 + - USBFS+HS + - 以太网 * 1 + - TFT-LCD + - EXMC/SDRAM * 1 + - ADC * 3 + - DAC * 2 + - 最多支持114GPIOs +- 调试接口：CMSIS-DAP +- 支持RGB接口和MCU屏幕接口 +- 一路SDIO-TF卡 +- SPI Flash：W25Q64 +- SDRAM：W9825G6KH-6I +- 一路Type-C USB +- 调试接口引出了SWD和UART +- 双2*20PIN 2.54排针引出了68个可编程IO +- 开发板更多信息请查看[立创开发板官网](https://lckfb.com/) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +|:-------- |:--------:|:-------------------------------- | +| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...113 | +| UART | 支持 | UART0 - UART7 | +| **扩展模块** | **支持情况** | **备注** | +| 暂无 | 暂不支持 | 暂不支持 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK5工程，支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用调试器连接开发板到 PC，使用USB2TTL连接USART0，并给开发板供电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.0.0 build Mar 3 2023 00:43:44 + 2006 - 2022 Copyright by RT-Thread team +msh /> +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口1的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [yuanzihao](https://github.com/zihao-yuan/), 邮箱： diff --git a/bsp/gd32/arm/gd32470z-lckfb/SConscript b/bsp/gd32/arm/gd32470z-lckfb/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/gd32/arm/gd32470z-lckfb/SConstruct b/bsp/gd32/arm/gd32470z-lckfb/SConstruct new file mode 100644 index 0000000000..0701e74ed5 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +gd32_library = 'GD32F4xx_Firmware_Library' +rtconfig.BSP_LIBRARY_TYPE = gd32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/gd32/arm/gd32470z-lckfb/applications/SConscript b/bsp/gd32/arm/gd32470z-lckfb/applications/SConscript new file mode 100644 index 0000000000..9bb9abae89 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/gd32/arm/gd32470z-lckfb/applications/main.c b/bsp/gd32/arm/gd32470z-lckfb/applications/main.c new file mode 100644 index 0000000000..dc801496bf --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/applications/main.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 BruceOu first implementation + * 2023-03-05 yuanzihao change the LED pins + */ + +#include +#include +#include +#include + +/* defined the LED1 pin: PE3 */ +#define LED1_PIN GET_PIN(E, 3) + +int main(void) +{ + int count = 1; + + /* set LED1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED1_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/gd32/arm/gd32470z-lckfb/board/Kconfig b/bsp/gd32/arm/gd32470z-lckfb/board/Kconfig new file mode 100644 index 0000000000..2b0c0ce10f --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/board/Kconfig @@ -0,0 +1,241 @@ +menu "Hardware Drivers Config" + +config SOC_SERIES_GD32F4xx + bool + default y + +config SOC_GD32470Z + bool + select SOC_SERIES_GD32F4xx + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default y + + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default n + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART4 + bool "Enable UART4" + default n + + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART5 + bool "Enable UART5" + default n + + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART6 + bool "Enable UART6" + default n + + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 + select RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART7 + bool "Enable UART7" + default n + + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 + select RT_SERIAL_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 216 + default 24 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 216 + default 25 + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM10 + bool "Enable TIM10" + default n + + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + + config BSP_USING_TIM12 + bool "Enable TIM13" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + config BSP_USING_USBD + bool "Enable USB Device" + select RT_USING_USB_DEVICE + default n + + menuconfig BSP_USING_USBH + bool "Enable USB Host" + select RT_USING_USB_HOST + default n + if BSP_USING_USBH + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + + source "../libraries/gd32_drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/gd32/arm/gd32470z-lckfb/board/SConscript b/bsp/gd32/arm/gd32470z-lckfb/board/SConscript new file mode 100644 index 0000000000..dd76970852 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/board/SConscript @@ -0,0 +1,28 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +startup_path_prefix = SDK_LIB + +if rtconfig.PLATFORM in ['gcc']: + src += [startup_path_prefix + '/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.s'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += [startup_path_prefix + '/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += [startup_path_prefix + '/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s'] + +CPPDEFINES = ['GD32F470'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/gd32/arm/gd32470z-lckfb/board/board.c b/bsp/gd32/arm/gd32470z-lckfb/board/board.c new file mode 100644 index 0000000000..5f0ce9bc58 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/board/board.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 BruceOu first implementation + */ +#include +#include +#include +#include + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(SysTick_IRQn, 0); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial GD32 board. + */ +void rt_hw_board_init() +{ + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x08000000 */ + SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); +#endif + + SystemClock_Config(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef BSP_USING_SDRAM + rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END); +#else + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +} + +/*@}*/ diff --git a/bsp/gd32/arm/gd32470z-lckfb/board/board.h b/bsp/gd32/arm/gd32470z-lckfb/board/board.h new file mode 100644 index 0000000000..3006da3290 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/board/board.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 BruceOu first implementation + */ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "gd32f4xx.h" +#include "drv_usart.h" +#include "drv_gpio.h" + +#include "gd32f4xx_exti.h" + +#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */ +#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */ + +// Internal SRAM memory size[Kbytes] <8-512> +// Default: 448 +#ifdef __ICCARM__ +// Use *.icf ram symbal, to avoid hardcode. +extern char __ICFEDIT_region_RAM_end__; +#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ +#else +#define GD32_SRAM_SIZE 448 +#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) +#endif + +#ifdef __ARMCC_VERSION +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END GD32_SRAM_END + +#endif + diff --git a/bsp/gd32/arm/gd32470z-lckfb/board/gd32f4xx_libopt.h b/bsp/gd32/arm/gd32470z-lckfb/board/gd32f4xx_libopt.h new file mode 100644 index 0000000000..d26e3d15ec --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/board/gd32f4xx_libopt.h @@ -0,0 +1,45 @@ +/*! + \file gd32f4xx_libopt.h + \brief library optional for gd32f4xx +*/ + +/* + Copyright (C) 2016 GigaDevice + + 2016-10-19, V1.0.0, firmware for GD32F4xx +*/ + +#ifndef GD32F4XX_LIBOPT_H +#define GD32F4XX_LIBOPT_H +#include "gd32f4xx_rcu.h" +#include "gd32f4xx_adc.h" +#include "gd32f4xx_can.h" +#include "gd32f4xx_crc.h" +#include "gd32f4xx_ctc.h" +#include "gd32f4xx_dac.h" +#include "gd32f4xx_dbg.h" +#include "gd32f4xx_dci.h" +#include "gd32f4xx_dma.h" +//#include "gd32f4xx_enet.h" +#include "gd32f4xx_exmc.h" +#include "gd32f4xx_exti.h" +#include "gd32f4xx_fmc.h" +#include "gd32f4xx_fwdgt.h" +#include "gd32f4xx_gpio.h" +#include "gd32f4xx_syscfg.h" +#include "gd32f4xx_i2c.h" +#include "gd32f4xx_ipa.h" +#include "gd32f4xx_iref.h" +#include "gd32f4xx_pmu.h" +#include "gd32f4xx_rcu.h" +#include "gd32f4xx_rtc.h" +#include "gd32f4xx_sdio.h" +#include "gd32f4xx_spi.h" +#include "gd32f4xx_timer.h" +#include "gd32f4xx_tli.h" +#include "gd32f4xx_trng.h" +#include "gd32f4xx_usart.h" +#include "gd32f4xx_wwdgt.h" +#include "gd32f4xx_misc.h" + +#endif /* GD32F4XX_LIBOPT_H */ diff --git a/bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.icf new file mode 100644 index 0000000000..0c38c55897 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2006FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +export symbol __ICFEDIT_region_RAM_end__; + +define symbol __region_RAM1_start__ = 0x10000000; +define symbol __region_RAM1_end__ = 0x1000FFFF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section FSymTab }; +keep { section VSymTab }; +keep { section .rti_fn* }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.ld b/bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.ld new file mode 100644 index 0000000000..5bec095bfb --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.ld @@ -0,0 +1,142 @@ +/* + * linker script for GD32F4xx with GNU ld + * BruceOu 2021-12-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 448k /* 448KB sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.sct b/bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.sct new file mode 100644 index 0000000000..56a5b1213b --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00070000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/gd32/arm/gd32470z-lckfb/figures/board.png b/bsp/gd32/arm/gd32470z-lckfb/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..45f85c7db68498d87e51b6dd31b1dc04921f6172 GIT binary patch literal 405988 zcmeFYWmH_v_a+)31QIN`ySp|n!QI`pacJBvAwclp4haNzmqtTycXxMpn0MR3wm!A%bf}VoB+>`G4{zSQL6VjdQ+e|SF5u0Zwa?z5P<241@ zF&V$oFnQQHKw7_f!!P9FU~FmwbRjVTT3Fc&kez_r$VjZr1jsZ2@+|TWqCiV4DK96W zs+WSAsh5o@j~SVeAPK(*FQfxIpo=kyhn=mxGp~mL+24M7A=j^unaN20lDOCikp07y zmb?;)D98y&!o|eKXv)IELc+zv1mNTZnwSDiI2cISSlHN@Spdu|Jd7;dyleno0D$D* zgA6jDlbJcMikQT|!$Ix@$Shr49C(?T-QC@p+}W8xP8Q6pJUl$iENskdY>W^JMrTiZ z7h?}bduQ_h^dJUwHg&RcaIpf}lf3q5Yyxt15g>yw`_C-w9OUKyt7CiTe`N)c8ncJ7 z12ZcV3$vZw>(u^IJG-a=|1UQFr_|1Bo(@1}6`(W7)yWj15_9tZG=_-pe?QPGA%q)V zMJFqWUW{$UK&GyCKzkQyF#$5jFHB}uX1pxM08@aO85biLJ1Y+(w=oA7BR4Cz38S%@ zxfur!3nvFVkLiE<`Jc6CSBmLM09vn9xZgpHkvgM>!Y%H9m* z?o9itqkpC>26VD=1DZ)Vf$T{B3YpjHf5HF&z-GeE&B4OR!(+n9$ivRT!N_CG&c?{i z&c?=W$_)haaPg4++urQ|t?-y3OfkP&%714$|9J#4$JfjMas|lEe>oG-9^yex5LaO? z^?8DL;2R}5HSz1i>9%{l)2~hQ|Ed{QT51Q5+WuCS@8LmOk)EaY}4O zl!hfubg=t(kV3d9v^!AE@$sMz2a}>HKT49!Rh|0VT=lIewlx6CQjFXpSL9_5{H?dx zJtZl1aejYh>FMO=CDOU5sj>g<8`8<4!NLAHYjtG~Obs?xz)(X-bFPyjTHwcbl(#33 zR%XDk;E>XU-qaxH;(|s_E>Rpf*6Nbt*`c|?I#1^}%N*pAs#G4_Wa=7fni66Xy@giw zB@H~J7BpBQUT$6z652Bj9$_J=i!=S)qG}YdqT-x91C42#9Ns)o&W*)=%{@z2=AM0h z`&7^x7OXyr5k0*nA>g_L4^w3}YL3RHStBt{91OOiqFxnDcOD#PN995`EXmpC6gF7x zq|ns4!Tsd0P!FqourKh@twywliug^av0cIYS=0o#$>f(~v&{ATUnrZ-x#@doV z&F}5$*6RAsi`@bJ{rAm9^ARq8x=T{kC@qBESyPh=@BmbBNJ(j+%vyqu*L$A^rw?f` z)P`!UN^1vcSph`_i$S`1Jq6mS88tJd?&Si@mq*Sr3{MizJxktC9XgYGI(~{s$HCbP;W##(|4o%Nb zmH;E@cBayw3;g>^>zX*(sN~>%hfH$1y< zhu&|s9+y>q zXvN{&r}XdFeJokd=SFk2)GhC?EtZLn=?K&z{to$Ik!Ad@G-jQedV3%vVf7w{t`cI`cP+maB8QPen@neR10ocMi`ejpkq! zbp!L-ouCkMuy_Ey54KYNT$ERm9+%aCW_O1%5Bpq79p?NZ(es~9G)iN*+9KCaJ(d|G zIvG4$C1brf&A{nx9eVw2tp%MdnZ&$CtyxbD7*^KTDP{>_fE0A{4ixc-j4Mj+%^2n~ zwO1RrzxJqT&E>-f9K-?Y0#O$&46R&SG}Euf`qi&bZH09DtNvHaH3^STgh+scMXIzu%R` zEIhUkBPXX#8$M*ynJwniKcdXpV)6;_J2NzBYekpWenspB#?AN(y#`RDXXS=ZHI(R} zI(Kn|Ku@oBj!ykycn%vwZNjF3@_Fbotb|Cgy&qnk46yXJR)C+rwbs^WeuexlNl>AOJJBm7A?z?uV!*bSi>qt%c^@)pIN#EXkSUUtf zsBEy*EYr`4uNVUU(DDJ2QQji9??|=jx8l3KZ6a7nES&N(*vG`P`Z&RFLlq4-l>A%@ z9Ie3A?ti032#6S~Qr?NDk^tEG4HsDp%xy7NFW^y^AU81d)obkxR4ZDH+-A7`pcNb0 zHcopkvyE89RO*UxmCSQBcJjb4O+B`*7xfs1A(jAG{xwU;_ugh*jwMptr}HjcLe{rNH; zws}^eQXWO%D*0Hcj!5e|a9ODKRM%sbo3q!v6qWk4rwXI&uc1G9#Ra;VJ$HVu8N0n1 zy+TCBo6J7-P`(k z<<3-vZpPs8B&O$SqVc5hN3Xr?W6QWn%sO4H_iVX;&Jmktzh}zCn+F$$cQ3dtP&Fo9 zKu|wCPJm~RYL3PZfbWBG(yk}RH{Na=Hd4@})USc6p%{r+i9BR=sv1md-RvRt#@kPM zMAf$RW+#a(&|aAgI>QsHUPerx6_Mav^b=7g3g9LW{i?{3=>tF~Me5@7Ou5w#WbQhB z7!R1dD=4q1CE0&GQ@K{WZUoa04~0U#_-j37&Z4xsH1VL>ryH9&dyXmr^S=JBzD7Fi z8S^yQTKAT9n$IoCH~=%&@}In6iRE#lYjPy?D8fcOrf$2+Ug>5SIDlHLPj9xePg4CO$&uM03m7 z>eE&<>eWc@ueK4+@6=eN`gO{5)t=sPrqe9*-cs7Jh z?Nu?nedXD8yCrU}m6Y-GLTxhpS>4jslw|(-<`eN=@12QB=+Y-?mqS*op7y=r!Rqus z;1vbf*djLA7wFd@beF?T0j40arrsOgIX5q6wwN)Kahy6-^#;%9K$-5>&j^I999xD* zPaGEf$u(Oh#M0LbI?C%!v4E+!*eU(WbZ2Qw%~nA}G~BB*9i$*uDp*xQE{PAAk|KG) zeKppgPukm|qDT4}n{|6%J);T3%=v01cokjJzc^h!5)$zG!itnNEe&G*Ic4BfdDp*2}=#tA%RFlkKGyI!K-+F1$ zh2{JiP8_z>9KZxym5$E*V$eCV9!bP-rmA2FvU_ilwQ}GycmfdXoMYiE;VZJHy%!Lk z1Daj@-2N?s*TcsS9P+VT=3uJ32v5E(Ux;yD|3O$YK+&ePUH>7mb2<)5mjmOkxGEeP zdcwGme0CkIWt0KOS7gz|J>SQV@>xy~=?f?6J)1K7-U@!KYce(u=Od0`NprK1dJ4$qV)r29o*z%c@Uv&hD>m5^71i~0L)z-}0$VXp z;&ju7g)4S zT?JjW{B+RS#IuHD?M%)+_$Z2HJvUS=k36Cx$IHn>LVj=xadu6tIIosOsq}!Y!7nKL z;Oj0o+Xxf$_7gR9PG)4YTTYHm-{sap=9Y=J-F3?ExzrJp{!;&tv4?lBU;^Pw&GH;^ zrb`WUBB6xUQ#J2$ub>^*#q7!{CH-42x@WTEj^v*QB$H9BeGOlr9%mRQTUDXR2cYu{%KHp|U3Ma}Cg zC-6MRW2fvqI(O&+PNwPL=7~idV@>Ff#5NOG?H#3n3Ivj3r>f)<($;PDOpM zRT4B2p4YtYz>H!l+&|=B#j!Uss&&(lV^SfSsxiaW`NwXIdaH|(EabqJeaSDjbPIUy zPS+(`Kj5q9Y=DUM+*zWN=_M(hPH@#oVGH2LVdNYH_Q>y@`m`}i{8NJT53@xxw&*Rw z1Zhmgt`ySgmF%nPl4E!5e+3&dY{Tbe|K1}`x|S0EDHzPAZv@1qsz&nTBMj=S7G2Ob zOT`R_@t z)@;y#Gh=AEy+d3D@d*YSKH<9ryhU`Xr_6s@{iY4+^D}K%*ua(hck)N2pXJr<675OedX*o++~i;?MbWi&PG(5j2#bzm#|e=W^a zc?_Nu?2NlA=2&>or5@_UxlAV1g-2Vd+I9|FcZn;8J-Z_>hUy3bNHV;`~ z3jsSsg>XRqg-ygz^fDxinY62sbBr$Kh`{|%L8g6$HKI^F1vR6*{OqfNuA z&_~={hXpBmyF=z=^lN1iw$!mjmg2TT7gC$HJCu|~fFfzr;bV?6h1t}sboIzo3sjiD z6ZtNcKM_-Q2m{r_uE_3G1HHemnFjtn=VN3MGV;uH_ltt`Y|B{?!HP_^L^kdzstn*F z=})XNv@e!t%H(%O6=~cB1-s!~s8)DXrHf*bm5EcA#a2ns^64Kb6}VjzOqpO;c97 z<~y@mIDX(!{egF^!$zK2XfupvnS{CY?keD?UUYYvntlQ)UkKMjR>XPFF~(8}us}{fece-ZeK_Po=w| zO zJ?r9+3yJI||Ey6z6zM<9h83X98)E|8Qv=xp6J$uSLMgm#?os zXRi|qW46gRo0?N8%jPP%k37fmZWiYu2%4ZipiTk(vT^s3)@E=N>+jsuM zJ|dcH6}^SBriTVs^aLCMp@^>HMMlH6F#_4|!Ren>#5$H&$aYt#b|D>Ayys>ty6>9? z%UTomT;@@w`9#;;de~8{lmP_B9(!Le8l{i)l?A>N)Rt|iG&Knny9rhizx!JTfckDg z{#%s(Q^t~rrdUqObd4KGy?S|>_JDg%ymxKTIq0Z?JzaYSh)Knl6|`B;SA-^@APHtu zF9Nd(*O#CO&_5&1=m@y=!ndwCTHl9TNl%SwO7bp@YXxucBK}=oL7$dS9aY6o%5_I} z+Eh^%Whd=c=uhhIVkDP%+hRWPI(@D_E1pseX)%FB7E1{N=VmLaAJ*hH%Wj*V13wm+ zfWu$+s`=u|GM~6N%8c0ByV{~;OX^fjQkwDpPGR*TuS+8dUNa3w17WGgf7&#b*RaM^ zWtmGS?np!1ANZ>xC0NAIV7x&fMwGOim^pq#1+N~q~pVcf3mWx zT9?<%P_ohQb;Stt0}G^iD1efqdxeEo;;d?oG71oQ#x0SenrZh$KTyC206EQGj1g>e zxC8Bi+Dy0+{`&u^rxUGy5fw~dK+-!eKs@akM+ZHHaDv9$*cuh`CCWVhuv&6?P0B`p zb6xw`$i2e|XThhjyGY~*`2-zBEgTKDqi}zE=rtSMME}m}8+k>Pa2Lw1ue!wgH=qBg z=1P$4ZP~>5OF;jtOfwl=z&B;q?-pAVJ`<`R7|*pN4no9J_SH<1-7$&>5P|p8I1xVl z;@b)MYH_Z?Y2g(b-4**^Fr9I!^IYUa-vytPG850$?vn&HznR}%ZvZVm#c9hc1NZ<(RT zXME|E?SHuV6(H1^Ch$I$=6r!iz-K`5M!T(9JT{)T@y9Qr4IUv;YyQrxo_zL^7l}VY z!LVMiki@s@hV39z4;L9>jtF-kX(OSJ3Y;}fEoE9Z?ap|9d|LvXkQ7vkz@4f1ISFSa zg0IgY94-40h@e$$^5_z%m-4WEkN&a302T@cveHs~*($2w|5B7}=LTL@I#MSKc7|1L z8a9RTog1Hj$0e@^Qd5ta4%RopWWFoql18hSYu8DjYum%5_Z;HbxEYYA$}&jWLumR6 zccAa$v4l{nm+YkOWZLSrN-!A>k@J{!m=3se*SD;^AdI77>4}@}OXUy(JR2P{pjCVPt>2d;9cocu3u#e_ekWeaxNb?d? z(Q4esr*$-i_Wu2kd1x$Fb9GK%bB(IPV2qy5GOkDSKN$*OZ;RZbeRhQ8k(EQX3DhQ8 z3KMoa$@b0}vG&sGmJ%mw%W|$;LEv!NiUc&4P@vj@Njy7J)CvK@)d$E@vEw(kLovLT zG;u1t=N4U^7@Yq>lf;CDc>{&3ME|@5Dmdi>tXN@`7t?3Ep%1sy;_Y6TSuH6Wa^h4S z>4Z@EmgH@%q$9RD11=uiI{6q*?U~Y3rKlD9y#wyjj@rO>jkg3PxJXSA#*P+u26Rj@ zR%PdyX2Y3H8Eb}42ET$1o^aOKla>#n(BMBsI@5+<@fA0t0q13 zs17na-{Lm}N{fm*83))yUPw?K)GIP`_9^l!0}zo+SMzqtS7@q@p=NGk3SH&$&7TGyp$);*>j{*NihEH#!+}wOaHg z018sG%nuJp;TosHmZ1_O%+=78R1cy5Rb}`^#MoAQ8c96d{$oa)$JlWP2VZ}c(Li~%p&)2eoJu=GO;nMij8?S^`$RttJ}!* zRJPl;Kp{;eO^gGgUzmKZMD);^mBT|tO^oD5ss|q%Ka^@rf3e?=qU*M-$jlFe{>K@y zq2N?4c*T;*k%|XCQ7FWLaX1s!YbrUGB$OHTAQ~TQx}Dgdj0gV1t}k-$wa_~7Q7r?Y8b=S zemVVggRN7*_Ag)g(w^pRXTD&yy;HgVdXn421T$?v1E0KCQ1xv5>yT|#&9|l4An+d* zMF!9&A2{R>U8daEAWoS5=nN|JYRPLuC4=Jn- zhRho$l@lUziTj-UPK`~%Ha6^ZeG_7`vJc3Nk94gw z%-hI^0=mvxcqU7FB@@*_2jfjh(PkG-Yt&(W&RczpJkr0R$co%ZTT#=w@d*PoJX%C& zzbBJfh@uiPFr)*lw6Rf_5%VmhldnD3nes}aPv$(TGV5TB3>f-B^~F&pXMuQg@R*~% z=x9})-J;i$(CzYQiaUi&OM_bn3zY4ij;b%-V6GX{3Ja|<;_$})Mz&+BR-9L-k*n;7 zO?6q7Mz54X<31(9~TCC~etALl}dEpuB6+=7H>aq!UZUU#fSoWgb+=(G~H zpHqi>1p$YxnHWh$jXX?s_~~knP^?{D7`{%D1ltj9%j#P~8yezv)~0H>fcP<894H&I zlj*@)uiv~I*4vhK@e_UQNF8fl)1L`_ogr^6=&SUcQJRLP<$WGH9d zM?jaI>xK?oKjcn?I+eO0^2uhGW>$!WiFeznJE-N6d*B0w={3%~gd%XGFLuU6T3!KI z#VPEgV+3cKUt$uYh$=oOy83nm)wKFhve!k#Zvjl}McKrsviP0E_qQ9;T#8mh*}toS z&_M{=vXZW4c$ePP`OV#Nj!;TZ_0#6q3Da!N63u4>dO&?&TMVqzYdSW9syZ6;d<=U$ z&WSeAFR%g|{{;!r{^TyO5U|4fiY9%Dd@jeb_&pqn6kN`{A>aXh8#t^xZ%_By6~fC( zuSnD1p*|t;gZLW)CfqjOGL=j&V!cSL8os7NR@;Z;=pAutq37c%*tEJd*;g3x<%O&2 zN7?`I#sq{G0xn;H%S8)F@N!hh7o`yVbb`r*0s$h63Xd}(Z(lGA!At*nq9HsYiXzZp zw-AUTa4GQX__|fIfghqK2i>!w5V3<{IO2OM6?g9ydOadYuMMRhyQE{Z<8>iKBK!6y z-a!K}5VTc4S6}AAyVMm#w;B}R6y#g(;Q0zt>ejOkeR}-=dqT{DuU9=z|NedrJ@oxq z>-Znm8046SSRGCfRvwoZ7lb+;w%AeJ_L+uxPD8hurD~3+h;7_@iEp-`-arN3aWRMP zkEg@Tw6ZemH>a${Iqk8daK-T&uidRjHwUB989_mCjcy2VrEv|k6rRP0zk_48zddhl zyGVW8y=JjP+4Qr>AB z-brC~Bq)BDh6whx*PE8XF-q`$VB@>z=?w3KQd}W{^rq-J28u!B(}cUw&)7vj#X|4& zvsv;4!W%wv7P36_6Hgy z2RFqtnl~6Id>t%q!-a*khalPMuC`6XwJ{#lu!lq2+lI6Iz?LP0=H+myr7O-}7zP6d z42HKC`SeC;#gr=tX09LI44!iFftV050%@$VcauGOvTk*qAYSOB-7G9q65r;^E^88L z`tyH2(ae4{5i$)2W`bIc=sC!Y~}{8zlhJV`CDuTO)Eqm|X3t+Ha$a{K0l^Amq^ ztJ}ln`U=DIDwoE`$NV(dp_GyFR^mAIm(K~BFK1KTe|^b8_6M`>v&wU1%w)~4BC5F5 zA}b45eR3~yc8-+2qYQ{baCN?kU8RAZQ`(fw|x^#Sx zVf_g8>9g9`U^vSZ18*yswtdt{)tLqSy`w89695P_E(=FL+O=RciANp`T)m@tXYf6^ z$;`r~cSVP|Yq-Rn_jaCY(j=7mq?+pu97J~h=V#@YCpB$;WJJ-N9Afw)VjL0(c4MPT zG#snNmNwz%_4eYrG-_+b1*b^rqodsyFhA>pJ!s}7#B!AD%k4ZnM*~1cz1Zh>_i*p% z-uYbOWp}FG`oOgQRKh3Zzyl$i{S0|GKQHn`>Sgnd>(53F+x!VW-hO^y*WMdDN8TxW z!yphBVUU4OTY154%gE71qrYOIgXU?|=cQI9@gOOE*dvL!4^a8Tg!?N;x)}S!@XB<2 z(aczlqe)sF)gj?o9t|#O@3k;qoFqbe_q1$xTnMlNGiFHHC~RRt>FUe_bLl#DclYs( zb?lP0O-fL&GcLN`I#H#6X{01d`$!d0Ex*Bvw_%b(AdUV!O^Em5>?2vndGOC?KPz6Y^e?r1g zxqV~boNUu`(&@AxfcxGN=X>t8{1K2!FAQKZbklM&vVKG=5u@Rt)IStZs~!=$i3v{ zezk==4+R5T4%ahO+Sd`MdmlvjW(el9FBJxTY+L#&`^z8uggUZ{oChtp4=q-ML#EZn zwDL|Yg7&IATu{SUiY}fXJI-13jFZ?dH=r?+LK-0$&O>`q;#G(>nxErF=^oq>I+CW@GaMu?-$q=wIAtJX3R)4zRNY^! zBjt8bI<6TQw`#>-gz>0q{i)mJc%H^Iw&&;U^+O1ivzVvG13F({;EOtc7NYZ``eVu(gG0Jn zFnRoaaQry>oRrpX9Z=_EJF|u)!hm0X)lYqLW16F{?-9k~!31UKbj@AoCtKZQ4<0T=jO-NR*DLHPJtUDyjNTbjE(OJLc- zA&S`Cev^L*N^(`8Z7CKS9_Nv@|AwlqkML~C75o#;)d`tcaMAgfpdc!`G0j4x#cZ!K zeE|llgAi<^BPR`PT8ZvCanfFYfvN}BAJ4&(4yfS_bL^@%9+fSa?%Um`Lu1tY;Ouit zhTV@L?Iz&fQTyty73Ls@kM;@dKRX(f8l~*gq%sEKKyf^ab}omrBu6Yb8vqMBJc(UA zLY+HXfdC&%*CSTRo5UIHiUf39Uo_(3oztI|n=Kw*)}6uQZ0dbeNC^Zbbdi4YfJd+B z8FU7gW}QF9yZ2I4y@oo-t$r7Wb1j(+ZgM-;VuG51Cn!S6BjE3mU?Hjt=-0d*5N>{* z_K5C>%7=QMk~kDN`6W}zH6pSi)D10`8-e*22&K~=VwcX z%>!!T2cJ#(*pu%In!@wj>jqigMgcd}vQ9CT>Z7upH+MdwY^n{0{V5kYzJh3+8Ej0` zh(RT6>pztk(oh&>eSHO)?lG%He;U>}#;|o1hO7Q!T(^v|5)^yJe78;0aMxZv)QOLk z6jmhB)>MY-M`_^?bZ4l#ZSpsCwYBxGc;>P2@d+ZTgW!0WB0oUY_c0hSO%dXl zv|Yz3h?>c-d><^??(gT|TP4qJ<=|NL?xO};A|zkbhu}m7nqpMN9+&p3Rej~g2z$R4 zmTJ_@fwR7^SEV!az2q$?g=}JOia+Ux=p2=H}7x zxmKR^r!PJ=FHv1H&vv(#GepF*%BPXAwwj{Lx5nG#=uC$ELjG08m%-gAC?FiB2`|j@ zDw!+GqPqU9Nfkd(ZPD$Mgvycp)qYE+M%U>uLBaXSheO^&OQcL;j`uIz$QDJK12@D} ze+C>y^lA~1Zr7rK!nBfB;RdgkZ5yL;ndst}X2=f2yTZ=z3Ce%%v81-X3t zz5cScargQA_mZ@Ty*St^y-9pbRJxuSy(xMQjL6WBd_?;@OM4A9VJ3#SJ@YA}XWuC; zkv-tP2GA}Op#?S9cv}82+|<+69wjIYf0K$VnP&QU@c9XUA>M|`)Q`_sOQk<&S7@_g zS4^y#U_{BwCppCUnI4~MV@x7fD7R#?jM0|%b{q+^=vo?@TS@M`<+`}nel8(W;Vft) zg(|j|;VGsKTW7qmwunOo{qde2{ZhyVSfApM=hEU4DWT+7F{gpq?A>n7+hSddh?dX5W&u!2qlDfCvuoWl8l z!a#_Hy>AKR-$iR^cRvCm&gAdvIgK{wym9>MD&f zBc~rBPj~l|?%I5PxK1Noo`goNjk^k~lO~4Bp~wG`S6}TBAOk zThs5^!m`<+4vs$YTE9Kh2jk@brFhhb?0Ep^I^yhipTQ`@LjHUMfvx;b@t zP4!$Rla@L|mO0BCAb#Cdl>H&~4L^UyQ+55VfrBwJhWX|0C%+5~0z@ni@{Na{9`dQe z7?=$|d8E3@=!2n{?Rb@~aw0|X)IjP6a;!F?Y^%bjAp!QhLbz68s|8oW%pc(%BEtm! zCNt>Zk~{rrOdZ*|mQn!%XK-fkAhFQ%Tf(CT?%6Y>YCj(Rul^9YAZUDRM4{kk+Y%i+<9e(f$gih=}ah`R$e!$39)8z7NYr1DHE-p3<QEJj7Ro?1<}-R)ZzpuB@UX&Vc1*C8hB@`&)dc><6jFbd61lfql*F z^*GBjdY`=uM=`xa4}*UwJ)| zADzi0r0;jR+j@?`*LuAjgwVxtxn)?;T(PqoB!C?@f@#<=I#a*%J5vC3Jg3^X(I~)w z%#+l%16`U6xWkUh^gEe?i|@+TslBDkvRk!z%OJ!t_r5#0tLNohX(yEu4yEkSIyv=D#<{qI`Z*H_QcG~T9oSmb@_6Ot0soqQfe8QLc zgxcCC*P0V{xCc!g`Ycq?PRet_(-YjogJ$qDJ;N%zN85A(*4x;r)OlUiiG_l(f)Pud z3wnd{*h{ZSbwFv8CjQA32gsmop10_F*@9!=nq++9Kplh8li1MUI9~FiNXBUrUpkS> z8_*S}o5LxgHYF8nR*NT402k+_Xv31QJLV$P$D3X3#ey~{yJbzw)?}aR`K;{EsQ-?d zyQaz>=-(%EfJWOl;xeoG3HwuyD**0-H>UYc!5cVxy@7w~)P6BOSNEP>C5chJ|tdgh{h#U?{&6}O|D z^ThL~y&b&w47U5JGGTXDL5D?yd9gV>u9wm+O5>9hi88yQd^*1$b|w=xdowI$r5#lj zq#Yd<6dcjzEnyVXoT4}}v0alk6QwyvSsm1R&X${vuyL|p;dlID-8d66es z%HFg(8Dml%!P%2np@A#<_Zt<*pq#kF{Kn27r*POA#NFE z82ZSu))h-OUt3@aw~~l`ODN8K`fgeCu+dafT7S*4I3?k#T)XUg8SN3R2$hlS;$jcA8q2T&871XH zOF@no@f?li3hopRwk#^T5s8yTdNEx?R-Jdz7Hgsou&gOV4E+J7RZy{y!XNSDw%VF~ z4@>D{dRh<9x0uI9q9+(~C-Mhw^nZLyJozXeDsvBZP!K6kz_<^4pshPA6{ydzinZ`W zr)_9>Y~ed$s{OJ$Hq;;WFo4e<+c{%cu(aRQzi9~{n$uqLZh!SMh z(V4ub)-ot>y=i!-QsV%H2B6#31JK z?t{qP$Y&yPS#dHQ*XVjj{_%pW(U$k6`90;ZDjjOf%m-d77kQ5zPu3t3>3N~=MNx0P zuTp+k8}!iwhP>xx8Ti5mX!}=4e>IsB&bbg8cJccCOmXEnh209b!PX5c>67N6pE>70 zk(T^{-@(qe8L34bB|72yqO8(z(7;haBlHOo5mIwwzaH{QVCMYLc6|}Y-+LN~*zo}s zL8aY$xYBx#sANs%tbYJoBhLLkEd0UJ>r&(_ZF8+B&#&>Y3^*`IJ;Fd7u4{t9jDE;* zPMxBz@!NV8zUDI`elfO_eRb3NHw0G+AQW4<6*?$U-rLgzmur~{+>H}A!0K64M{`0K z-NPA$a4_$*lLMGt&aG#x+<9jjXc~C_i3~c?ksFlFNbnLB>PrLdCS+sK8u<2cz|enB zOPa6G-O$_nVc_BVO2608H|kl#P-}?G8i2Gzr#XP#YJt6pwCPQKvPIM=Mr97SGik3= z1P@~vhj8?WLB=#jN=a!fg@5}OA&$)vW^>H6hnGKdkt(&~s)lf44ZW3|I zPq?f2{Vi&-G;wdtc&$Ms=h4iC3OlO$3s;MBj`M>zSzcq?7{^OVOKA30EY%0^ zAkT~NYm7b~M``|ZN^O{O44akux(i}(Q$g&rTQjJ%hAHF7&eN-hh}1BVy=8l+&70v< z)272qQ#xN`5Av22wHdZb#3lU5 z%~i|8ajWkM)(znk8*W3x?e2`=;}%=k#|cGEMq<+g?Ip)vBf#YMy>Edn+@yTqDmBQC zHi@xcELUj|*k- zvN#1E5Ycp4|LqZ=M!rlmcm3deM< z9?;Ufqdf4a&r5GQZ)!TvOK&M2Oik?!nR+tF$oiOT87W{eOgN3vR+bm>O>+tlL9L4= zLaMCjNHb&#+O-J)5V^m?)1j#BFD?m7XW@4bWn0BnS8cYou`05V=)0iyzPMbL0OVd- z#z^%;{%c7gK~Dalco`djaQjo;%i6qcx%fWK74%hMX9hv8I(L-gW#{_5>HIuB?>H~Q zqAMD{aOv2`t<;t0{K{8$@=m1l?gW8cS1^&UjTw8zklK*Pn(C}7VIRH2} zh`y;-?s8q$qiq+@154I@!s4AtLR*z8Ynu2=03L-v|4669!o6Xfi)0)=n@(Gfn> z&`V2)Vw9!dU~z&!JMKF!?mL?ndh{l1H{w$1SrcmU6O2KO zL65Dq(aog?W)6DN!@esYVsfX$OFrE{xgMOSog;&^__Gv4A*;=XQlw_(OWlOq>7clq zEDT|$l(kJF@Y}eY#VOlm2q5Z1lc!Cb`prQ`Vz5+yvP3+2WOu*c+UhI$5M{uv<8xVA ztS9C*XDd*Z?(6~wm-NTsazUY9fr{4pua#u)`rgLFr;dUYp)4EakjskD7n@xx8c zE^^m`Pd2m6wF4{{BUZEuj!{mqSUf(GdPCP*qYj{LjO)|b`6t+?#t@HC?-r*CNAWCt zpSl(BUJd54(n|nXZWBn}EuixPB^)gOjseYsJrdC{ra?=9S8H)Dw%;lxtdCkWzDcTxtx2GX7KQ!$q zpl)`_pQU6%mH79$5CPeAMR}@k3C73`Ml5SJL@O(bXi#&xW;Sjl`3*YZ#Xe}%QUwK& z>-<4KyD8G48!5IzEu8^PT5hD@mDoJ&iOX;8>5RMwjNvOgPc6gX1$DHfVjZfhT2o-2 z73bZx9p%H{Ha1b#dZ#%#?S9xzZ318PwNftGuE!n|j&NX(;URwo&w=F$P$!6%mV|DF zmr$C5KCigX@~nh?0cu=75L|7aeDoYW2(x{^pgo5{a-!Q=TWO}w5Dx>{zVh*Tq<3bM zjLvvyEWxAbccJf^9Ck`97I%l0BSTo%wt#w*mcXb^N3xvcG<)vCo#XLcN*wNxk%w2GOe-`-*BSnDj zG@QF`l5nQSP+?h1c4t~ae1cdPcP4?ANx>$U$D>9Jn^A7va6V(A85FBpi(DMsQmI4{ z>bE8X8-jvxjD*(C^^s#%o>q)UTW%9P)AuGBXGy{9$}97nmDUwU?t(I1cSn=FZ|pR%(zg7cRCNP6Zs2S4|@Y`+^)~F;D=TQGNa){ zY-GQ5L*~oU?FjF2o3pX=7Cv_-of^xXmkf1WtfgZ(9G*)E_I>#7 z4Q~W3IKQQ?y9Jf{AXkecGInmdE=j`RiwU!w|9IVJp?ki1e%yql_jHUgElP1?Y%{AZ z>8g$(1W=epDVb3*hUcj7ZwBA!0r-a4r-v?k)_+g6KkjoHjvA!AZm^hx)(5C9eM^4k7&|};Z;qBMlb=kG#Z67eMumAbM4ybB$uNl1cP+mWr|y13 zCJNIKlOAjX@nIChcOlEGxyT`Msy*IxDDeK7)#}n!o^LbxZvdY_V83uITG2u0rsKpK zX#ZFTNtjbN*7jP6yu16qlkRtODf8Iiq2+^vWZ~ww0^AeUU7Q8oUS58>{q#?t+qv`Q z@^}B2K8j{JsI>&#w_5&SS$*zg{?XGr!&_Zj!>7Wh7M$!^lqpQiM8KEiuci&VI%>c4ST>ir#HupIZDi`|_SV+Exc9}qwRLrM zB_;MQ9NUt1cW^A6FCt-4pj%XXzW=ctet$8WSp>$MA5G?6={o<{O~qDh-ED<>-Azq7 z<#ngr$C}D10=_R9sBR86>pi`V5x=(ocdj$479kgFxyez*>#6ZHYSrEvZ-mQt1Cf-W ztJM+1==B=j(TGC9lAn z^rvQYUDq^SWn9xJsJpYG33ZPm31qtu3!>;#<~a0 zz#k2Tw2^oySk@_@xcgdlU@+RSswM85P=ax{zlI`Ue`74#P(yo7DCEX_jLxV#uR0!T zQ1aS_CRR0ve10Vs4^^+4Xp1VZM2E(d!q`Bwa-eN@#E4fk82*rNqBPj%8&Rs-DyoMk z;-NreEL5+g218Y)&22t^=|n?YwRbGuP?I+pn)uHx(NJ?~Fd7Q1TGAH#&n>aG1Dmg9Sn3ve(BfF4(iO?2?inr^EzXvPav)h;R8n4EyRuGXL7Tlk z*Y76$em&`LREPbp^DbQt%&5Aqs!7G$swfeoSFQ1qo=0oc#(&d#BZfbcY*f9PqA5vF zGC~5b5$%8@GX;&S{1osOjFPog?<&n>=!Vy;>6&gdY6Z<+f5eDX>3YFLL`xbGzgN?G zb$?#O8_^Vfzm_U6&Ah)i&A(}{rC%N8IZefUp&aH?xGH5zmsoeKDMyqB%MIN!3Z^K( zspK({ADy46wdI(QX=`_OP10>Wb!yR~Q>SQVvTM=Kx~3+&b45-0`I)lf9Y5QfC!Z31 zy&k;*1Pp*3|8h~{hRB8c@4tVY%zQpap;-Rv%F5!La@IxowcYO>Ir839M_xNc5nI>J z^8EZt5!B_Mv*R_2-dMozzMS*&SHH>;aNp6s;=Z5%*;R8HHw3=BVUPtZngPEQ3N10c zzjsfVjlQ8>rYL27Bh>$a5%o=&5#LKKX3)2Gms#(t*l=IN+Iq9G!q;NH>h_ggY*;(= ztK1O1v1Vv(GwtR3#+84Ih8AyY@YP@PhSs*2;~{so+3c=3e%HaZaZ?Sso6Y^dJ6~;9 ztsR*DWy4DiA1L($o#q1}KF5&n8|JgVh7ETdd}+cAM15msL4~i{47N2)-&gNzHuY$z z(CqPX>MEkYqE*Yy=NkrsW=~r*&idtN62`_lR$Z0?Zaft(-&f9!kiyTke^pe%lDYQc zX9{OM)7`2p-rKb`T>Iqq=byg!-W4n8@AdC|;S2xz^>?0p@3pO4cb5OhIjfvl6tP!U z-v8#&R}*$I@FjM`E9uX~JXa=`EN*le6y+(mwIUAuxa$5|)?~`Rz^JvVIl^u-#2E z3qB)V86xL*cNaA^)$Q!sy7sk>O?PfTvAtl+J13Ujxv69K+Vhjb!QI_WT&yhb(T=|< z+UvJIIT#o~z~H)MiV}N8?PqS%OY~jfia()hki_dY0%$0mAWfkAmq7Zl=*|(ibfGPgHaA9xlx2DZyTnpN>sWT>oMT0vO>NLOZ zc8{46cmMIrZ}7Kn2U*qomb=RA-R&E>@~pe!i93$CJ2oad){dFayVvHKub$sswya@o z$jt3nJ8@}M==_M;;~vx>W)pn7&E>7A>9)2a`8BZ!Lf+|2l&g(Uq0p9dU`L#z+Y`|=N}+_ zqBK_qz@mu!@yE|q=IH(PD`@!6iWN&Y)zW<}wrXvOGU0Q3 zPTpU9bm?yvb5-bB0=7T3<5jg^S|=-6m58Q9}Zxwu~m{R%00VFy2)bBdevN$ ziDKs*Zs$|S{b7-St9|bJ3SDhflD*!>2G{S-kFU}>!aZv!iQYu6x4?)@8#UfWud1qw z-`lEs8~?e~uSHsOYev1j-drsi33&PPyd+Y8vRBg!68;{8LgfdHRY}bt^Qw_XRgDw` zwMGhuQ%NH@qIrjte(y+gLGP-(6nDU-`SoDRH1{94Y8W=7%5Nym|d*j@cf5=gz0-n`m!7H=A*U!0ejGzx-ti{`zDc ztT#*6u3dhg$z`OM&1MRI$GFzgp-y*Obj@u8n@UEVQ=%vhmj1L*|Lyp@{kH`G#G0J+-#}12Q_D z<+49uD1Oj!OYgEWYDNXgO)REkIFr8%My0#sGY2&(TF&7j1gy;T4Z;dE|%dANk6P6`MD2 zet7dEo1Z2PKeGAtf4%dyt>L}a{gfUi1D70pz%ER@lo9YHE7u~p@>@F`t$RzFI7p+9 z?Y-?!f8h&1x|hb+AAb1Z*H_&8`n~s(gts3#wRKT#lkA{^vu3%aQ4?#J48zTm$h9mU z?x&HnpYwTUS*msA_7*_R@InR-f;cS)vT;al4>JH zqZ%<srLCHmAJ3f##m1u_~gc{1I=XQ5~cpy1I9J%HM06f7WT5-+GSy zTh5iRq*{waMQ2&%Dih$!lG|>p^j2gd(^Xr+Z`1p7M~-WoNWW{3JiBzu(r+)_vgO-L zH?Lp6dHvF*+aFoK`Qd*pcw>=JaJLMB`CZ&yR&AMG42&-t00D!!0^kkPe=TZ1|JA>* ztE}u3{w>+L_0+LDpTBnn`C{|>AAbFj^^dTEH~(uX| ze22{EU7_z^esb+Z>0KQB8fSbh<^yX(|GW9BYvQ=4<9y7#`^?&V%m=oTZC^bVJ%0JE z^9RhuLphX?E%1RP27yqvQ^0|D9aF1+X|Hu!& zxb%nX*FQpE+>bo6c?J2G?(q8cU)l1=Bj5SgCr@qNSzNi=RxriD_us$wNzY;qq_P6G zi|sd@UAZP(|G9*VcUcpsj=Xd4kACzzd6y$#`T!rMQ0?A(|K&UP{^$!2ys?%P%pE;b z(94CRq5@WT2{#1p=BijFTmwtiq2{X4`I&B^oY~L3xv40}ih%2KI19REw>w%9?9EeE zuSacgoj-pfsg@o0n{D%vDC!h-yS4nyMJOs;Hh(wWgQ5#!`nhL+zztS(RnL z0Zmi&l%Z)!uc~;<5{By6lZt8tltwL=dyJ+-RP{vk-jrWe4Lx;YJi^a9OsT8<{!~xi z2no1wx!n;5=RxN;IV)MQb&EyLa=r|Sg@0vjXsa5PrR8i*tfHd2|3UiQ{>3~0Zt0ds zR*-qWzIpwY^{f$>cPAYgF40GP8f zfAwtNo`3xJqRRV!R=IB7xxRCi`E{qZt}J+Z^H;WPS-*M9mKB@7xRkzWwyapc`P=`n zWy^Q|{LjC=Y0=iM;>!GUtFwJQaj#f?8a*v?^7N6#Robzm0i5EqpI|dO%>x;?tZEx@6tOR z2mkV)?|f~|bS~}ntJbF)?z!@O#}Uok-Vv->_I%!|tGUlUoA=@Wb7a%m%iB9Pjb3^3 z$g9(|*Z%bLPaRY*_Z+DzyX(&P3a_?4`9{IEyPw?Dn0|iKv+CvTM}p~pe&^Nwmvf(8 z1+rrB4F!N zD?7O6OW8)g`CRx*;qQ@mesu4@y#DZt6|aBc-g{}hm*jiz>nm0~{rbHtUZ>wq4O`dN zil+>8i)>kP28*{_W2}{t-E0;c(x~ED2i4= z5pXb&QVefEO^{D>6>oBw!eB*DYP!-I=+V5Yq3CL^KT@Mm3_Kc0DxAM8vY?F_)vFsd zUN!kZQq^XRUL(RK$rK>dkyLHm>uuEhdXIlqqd(&J>#y|mq-Y1ft|n7Gsh;syBWd%1 z=n0Eb)|8V|(rvfVWxp18XJ+l#w?tgv`&Rc@McKwj?^_1WU)S{Z+N~W+zkTPEPyXGO zhw1my*Vq5+BTqlP`Qa5`-?C-t(k<(s{6D|=wsxIHY_c;6;sV9NWa108E(%1rgp>rlJ=z(IO}KxT zXZA#{Tum>#np>KC)svfhpT{HmAG}Yw&vV~>{O8%`@#NmOEs>k+xk{_APSMhR_vI=z z9}0idSAkG->v!H z_vO+b&wD(cZE2b;Tei)Ud*#Y~iL2W#U-c~e|Ji&0=qB#`?pHIGqsSUGiU-Y%Z7e|m zTVA1PWKuKONS5*1Fw(J&Enz^5on*5~z4nsYi%s0(G=ysuFWowZO?S&aZ3EPG)nM}^ zS@22dc`otk;g*oxG3qW&OWC^*y^j^26M_``h-EkUnfv{GN0QC&+yC{&8cC!1AvDsw z=KcA33+)wNMLVU?tQsmw-KsI6jl#RDffaAvGQk|`*8DuvKVLez<==m^`NiwkMVtm4 zpF;rNI(Yi@Ujl-W0v<_+QmNHArh+9K+B||GER$qA&=!H$ZPsHew195@c2Z_#=8WH2 z8S$Q0dt2b5C)F!g4pwT`XS~1wV06@Q1oWzgH_I}KzhEV;(ta7KGv*&Zj?^x~?crWv zFJkbAMnqx6;LptFdydEO&Mjvz!nI|}gx6tDxFqfiseu4Vyewu->6T5W9^<0?j& zJ(xS#R0RkQ?nVHvjg{=!;v%`QSf1dT0l*}~gvkKSGCYIuiTElrGUGZgQB;A8We`rK z@Hsw!v@qoPGWEO|!a-OJ$wkX02FYaxI6WhULrfSUoI>=a!xDdj^T`DWy;q^v1Hb5t>fe4Rs*^n$n$EO)DP)%^}rMc zH?DsoD}l2k3*hW{m;nC$6Hk;s{h$B&!_Tjs1^s)i?9c!2LrsyQi}`}UFvIQ%gJ2L4 zBg`H@fI{#KErMIG7d$Qh*r|=}t)5yvyQEOZ2uR=&9E3H}-9WsE6!4tMq=_pzk+!zx zw#b4{DPJs4iiG2POsA&4{ON&?o{e5jW}Z8<^8UTO+*5c%b;h^0~shUJ!cD+RwN0U!F;vc3i6FF4o1 z{OmRh6QX)J$d>#M$0M=5Wn*R4NCZQ@Xe5CLOVi1~X%jRYwe{a^d+zMgLX(cYTJNZP zZHti4YStQ$JM(v*!u&PofA}H7Z~kXO?^<+KVmxJN+n_B{eZCMn-Qx(_kqpkoMWAzm zwT_;Y<=I}CQo+F`Nja%Si;GzyfEy^W6 z-;|9R?ylL=#^+QOj*NvmvygfL(xmlv)mg3i7feZw-t&=R+U++RPeJgUAUHjB9}ThS z*y)DH4Td(awgDRm(lsu>crh!1vm*=O?05)&RRL@{`xig#F8j~V3(Gz)D=Ygy|L5LU zR`uq)k(5a!5G*DTIS_q^fWnBu6Yfy?&6^aZZ~4c%QSWwKN3jrxLPK+g5q0z-63^}> zb|e&BiqaIy&KQGiMaai?ivcqn0&wJ=Ux4-eu+vguAC&aeW$BV z@7{eHf}qn1IK|({hDu@F`nCG8$8Usof&ljW@imRx-4ab5kVL|1UTfIvtwIDI!;K2N z$5yU<|FS7{8pi-m9krhwDEjNhv;cm45x=3Qt*`)b2dt!oC|;>t2QWrEIy{3DQ?Eq zTZY1MATOS(^Gul+mWbZ;UhaV{nytGJ%BJ+?!9Am99?5bA{!i-vMyHD_SBb4i0Rw+k z3A}oC1UIQb2)2X%9Ul*;Klk_rC%Az9{uTjjnSOUN{mQ(2tT*2<>K!awdA1tsU_{`T z2QOkTFxa3mfUyVoe9>!X@ACh?66w_Bw`k^M(AjZCa|)ZEjrmSB1pR|QWa z1T5dMi77&4lI>$3Fm~yNgh`?290|#i>V6%HtRFiH2uV}(jsCzuH2zk zTZDdueb@rMu5b4J)5O3{HAD%Uc6GXY*p_;nR={!7gXF31L31ZZnw|^1_ktan%(W+WYC;&A9EWGTO+oWWzZ3_8zFe?>|2%8`jn1B?~V%>3{Ajb2biFlSjqKwuadGXvgN;tp>g88_-Z)h z;~8kfu#pyvMIS|zq)dveDAJ&PeUd9A7IWc%6z9-1%HU=UzJ0vR?F&o3C<%2q!u6Ku zvM^eFhU6+3CLESXDU6WK_e+wiUaFO5#PfWC3t@X77j^}t7i&2LU=Grds-R9}Dzn*U zTdb{7c%MDGC-p2vUbPnko>gYo5|!ptR?p(GW32)n2DfwC;294szS5gB-dhQNU~GZL z=83YmezyLrtQR;tvH;GGhghJK|NOyN8H~oyfBB!k9Q1B)HJaV}L}oGBio}}R17W&; zx4V52BRBn4|8yHsRh=$4G4ed(Z(kqW5QFWfi6<2uQir;`z@>}F?`9sHb>mC%!#~Gwi59d z4ABU{D~o=ewm}1cvDuCX?mslkT46dYb0H``$-8D;+`d{DFLIYGwNgP~ z-wfm8`(M0jNvaBXdsDE=k$%sMUf?u%ucd>quBrLKX)s?~x?r_UyJ1hh+cR!n{9NPH zEx_N7j>G7xblSS)6Azs+2%v!-I9pn+$YEc#eld$XJF+7S;OtlgFbLpZApmz*mvwiS zm7Oj7yvf^X^b4LvQKnGV4mU(VyWQyK@3^qIf%Y?gvu7`1A4^9;kF5Koucz-N!0^cI z>|SECGPg)Io$8CtxMx%3`{|!N^UOc}G^0~9x_8m|9KTov>DnIS7WlU=G85+ zJ;yWfy<1^F#ISvz98O&xVB+8Vy2ez4ZrBT~D0PGum*Mz7cH0Nhe}6R&PJ^COgT$tb zR)gDPU80qY#{j=>@B#~-3HP&$05<#4KXauQ07#|uDfEQm0wFv(FO5(^N8*T_}FN6vl!Q9;3AnwkP z7K_-}tlrzxO$iF24IiekBNu$Y2)~YCl}}O5$0k4B(oZF5ni8913$caG;Xs(>7@E97 zGaTb10}MmcJn0iD8A@r;J~Bj0G{qGxmuY$WM?t4>jP-BXkqsaB?z9f&z$_=$zBmC8tx?V6gfP zZL#gP##9P1lE997HH$lYzR8X(fV1N+06+UII+g$Pf2=G!`*~q^HKK6YUhNvac|w?I zU-Er1SaBG%8zAg&uUUM>J%KP{hzidW_ zqRIbw29N&{e}HlNKJA-{p~{3-rQ?-NnZRWn1s%tC_bA{cTKFy{8&Bi(ktXPS-VJ)f zniQZfUN4RStonerzSR)1rSp(hSC2Kuymc)GgWqFi7C(9SF?1F;V^1(>;67PEh0wXsj%#A6 zHIq|;(P}?nC`ak2YC-_!Oa5DPUTuOTlSy#}0Qf2wkR%$3U6u{cAo&|$L=rtq$~4JH zH0h&gk%T{nJRfDKFnOLze-)?zDF%4yj)c}{(JD-crP&lF}ST$(R&0PxKG+cYqkWD#+)9n{}%3f|PTVkAU zibXn34SD?5-X#iH*f}lug&}kkJVQ$_t3u=BLk7deu961zu=L=@NUPHR`|QY$EP%5k zGjKlX6YKv23E&_8aCJ3w9vqAm_2xSTVWKp#1i%vr6ustNw+Eea+)EU&|BT-+{E7kM5>^!ap%_42p{h6L4iCq#d`^PO}+mbmSW% z5zxQ*R`$Wm1H-BfIs@SE4ya8CajmMxrjpU#wIFr<`XwrRCzznkMvUP6!^Xu|oJhb; zn}B*&q==N!3M?1D2G_e@H~VA<55=u~4qY@>z>(ZS$gunCQ-z2%Bh zA8S6kshYTruq;X^T(fIJ%hjNmn>Jg!D06&(gJ=NK^C`&SzpcQRc)7iYLj% zuL8}80f~p|R#A$flQct%QJO@GxHvpRieWw~MiFRTVGjL;XC#t~(!9j+T)=hbe7~yz z0l4CZvWzHd0w1s=RY;^KCF|94lflANE|MK1*pUvxIy+kQfohZ*nd%;UUmLNkb-Fu{t`#$jna_CiU@QfDX-kW9QOC)DBlsr-v$KuJMO(ma=lkC7 z-rH~%w<8>!Z6cmhY80GWggw9UxwK7qQD6SaGv7k<=D+pKpD6c7A;%vSmlZcH1@Nsj zZ{zWdL{>e)DY1R)E|kX~7IgKn+3~xAu;NQ0jTG>raa}b*_hA?C>D<1)=b;fkU2|@J&CweFRExqmSOh}eP?d|>+PfN<>E<;on)OhI4?$kwa?G6{2m>{`$7(a&vp22sHK!V-h=h)M}J=RTW}vrM#;4TqJ>UU);UB zchw{+i00-kGb~9Z6LcN`xK`xCoahrb(u~A}MUfGuDCk|bLZmtRO2{XY6~2VXiRFmK zGFyBLeHADlcME+LZi#e&j*6VbF;@ans#pq;%pHua11B)^E_jzm zt{>rj#x=uBCtUo@J_y2E^TH1rwu6DZ;q_plJyTCJQxm#yN$p8B>^TMGmx~USVHRTo zHxQNiP&9PfIh476nYS9OR_oB2q2t2%xWO=yRg4yHjBpNciEVHetNGEY; zM|NZZoE?h_7<&`Xj&)a0;qHSg_ii|lZ#K94{br{pZOqiPw6yrmdUr=hN4v9S!Yrh1 zZWne=_(9wG>$F?n9|Hi-j=bIXlKtPX33_CtyNMXMsm!SnQYm2?S5*IQnq~+nH{fB- zgOYvji;Ipg<`AW9&!)^Ip79B%g0bTFM^4>G+K2gp?}^cV@I`>>){?iSQ}#m?GzReQ zm-~$Kqs?w} z{>9O)b}WIXs>@csHduH2iQ6d!41R+r_7$buARz!BiCs3XH9L*w{15ZfDNTvPpY0Tc z79ro?cdM>{#JSni9!4hXA~=aDqJ_2CH+06qUr{Xh0-6 zo~6YENzzi7DW^c#(k#vRD2bsrvgO}A^GprN&XnJPK&*1~nuL_GB%bF(EXR|y>k92d zOz!6?gl`vJkMyyNo+)sJ`5Df|h^~H`cX86b{#qCMeinEe8ob+gZ$I7iWl2N&4W}zo zs`$+m=TM!%Jv}MwbXi%(2VUm*GU7hm+cDj1K4rG1Yzs-l_(vZJ=C$nFwZ`^dr*(Wh zC-sVm_$yrWI6DjmZAq{(Q?ul?tP?mpvH;GG2Lbr2-#@V)31BsgxB7kWUcDZCkN|<+ z5S+@NHU7_;23BSz$3GR z#OpU83M*9^Bc5hsI&=!^N1?MW0QJTL0jzrfFyl+)=n~Nz&%{}!BcbC<&Cd5p>A3E( z=v8;0j)FGT+#3(3F)ezf(OwTgA&%28AqK0Ju%Hgs)Yu`S*=@B#s1;ID9sU-p=a^?= zNL)1VD{&?9d;NrGVnVpsNiIkgm0pnUv!Q5PJNggrTTvW8C>nb_)DmamwVSId;p_wo(lD?!~qB#*NlGcdyB^G@ZZipn! z7m(t)jSR`uGVGN=n3o{_iltm!I9eeVkYrf2groe7>kbmaGko|rE}ChLimqCzR#KE@ z+K9HOYscl+i@Nf(sZNSG7AuqbyXfa#k{8^wI1}Qt%8n2@y&kt9oH9B+hH(oL_sP;d zo#VaOm2d;5b4Il&tOj(Y+8I02cuma)E^Bh2b%@3GLE_09@f4rt(lN>4nFSXrcx!bg<)5DU);xOoThIKH z@+gzA=58p*Gf<6ZqM*|*VK5t;7K5ZscgJ4EADC-&UkKLXiuV@cP|>fu=PCgMcxx5z zMTqNg%&wlQE<^&j$(!Sc>lAkf0xR^B@(Z5f40+eVpY^_|2^cVzOAqJa;UVVQ4XA^*5#9sjXjb!4R#0BF& z4mtI`=Hp55iXMwHqWTPRr|W@N}nB59KKg+!KR$*4q%Ea#JEd?HOV z632)kl4TiySAt`1C;sG_ZzZV!g}w?2PA-~&g<*=6I1^1{N zMlu*?U+cliNM&~Kic$k49OXNQJf5NPoSe?iJ)Ng?ce!zt3+7{;d&aGGRzK3dLqnxQ z2KTAnhDcMHTK%J}@U;LoUSt(;c4PsZ9ZOFhiwYRA^ZBW_wifj|-M!$kL}WGQI}v1C z-10qVjzq|R%z9?R;}JXtK}E{(&J9)IumlYZ=v@bCz_Zwqo2>L{x^S1S(52+U_PMQ%|(E}@!c)+oER__PuIx&WO&G~N6sY)b)r@C=R zq?em6>(^%h34aQn#5Akl}KpvcS2m2^OV_) zD;YcUPn2k12c>H(3}TP39h{_~d>y#}50Jp1h`|MnTL5P~o6wIi7>`^IUy77nbQ6k#-daBofK#P}miUhNCW#7I|6@^XF)0rnZ7{g*kNZit@Gl zT$lFkvY3>>@SMJ`&Tt|TE#6e(NCl9kfqM-X+w574iB3I$iX+%b+>@HyKy)5Q06q>! zW2nP0ZXFu`=*+!m&pAcWo%+Zs7z_rh!2khULa*D|={-`W?y#)!wV!9hptB+a1rdpw?YgbRO*{`dEvHz<9J)#HZ>(H;b9$i}GCZtbqF zo}I$&2n%P`f|LlruYaxJ0?$weOHBaQsg*c%I$ZU6Ng9%}n4hbA014UqB9+rAz%}WT z(2Eo{W!%A;w5Rxe6*um6>}oQTyIjX<1sq>e!y|rwJ`)147kt2dV1dT9pdkut%;D{X z&h1d{3Ieh8hs}oe2Of)fLho0b1LLXQEg0(}dm%C%6!6PUMZbOm44D}PTr`k2K{qye zFMnu+l;2*ce3jq3(``OJ#InZwIG@m&j~{lL51S9G{O#?{Kj*@8tVr@K z$pvV}C;EQHh>TB)l9b4h)N)B=M4H@)o>3%ohvSk=CJl+CnGh+t7^or5avT#b2uQRX zg`6gybRn55(=sPf5+C5C0?VCnSY)`Fs1&|rk@nTrx_C+n^y)738cv+J_^f=S#L*3% z1#Ov9l(+#yPlmhT{8g(^_5?xMtG$rGVf@MpMAadu(|KyT!{Z(@c-+>{9(eHPjN?|1 z$KYufIywY*M~C^di+LrPtCiO(vI;mmvH;GG2LTu>;BE}y?(N!Pv)_$z;V}yaf3M#i zdf;XI4gG|>#UOb629Md(0S%HWiCJvOoAs=?qLscJd-u7xhHZeBXSqb&*>*M=?vosBmmv>ovp*5-c*5*XLL$~S&^+`N`$A8_Qp(V2IG z{)OaVv)k!3e^|HS=v$C>W<_6u3eb{>#4vpe zO}P-q%OWYOUj>q5LbrW14fQK&2C3UScO))!I|`kK8H(qnurErwEIyj!86HtM%(GFE zzr#zlwS4Q0bjgxb7`<+e9nL8|aJAg4b)-GlsW)#+Tb$GNI0`dWII#4E?u$qzmo>!> zBIPTHvMwt1UW{FW82smLne?8pK*J07fn z-#7~q%p2T8;~)3_Wi^s&ssbKa zhuaYXfT2gADiBrW8&@T;DXvTPKEm!(WoevoT$i!y>M~Tm^-u@#J+W5t2c+`e?FNpU z{!0S`SeI75@%xKkpdnpU4NGXZW?$x-G{JbR1XedBeXn%?h9*A`E?r2HxJy$ z1*abftRfi6;Pw?rso_kd9tZe+Rn%ex+f)uinGUrZL#n89k6NSy0XX>jE5t#XiO<27 z=@nacboGCukYrqO5eq-bBMwG6l0%|(ITgK4hh+rf&~k=MvLxdR&==_NMurxXK9Yjg zza$u^nR4{uB*>XC&DL|WNN;2~mJ?|gxQl5K&7hXcG#3!XD`6y%>F{}mcF`_IfZ+n*fh6xILA;+xrif!>7I&!RW;uz#obJ0X#5Zgji{MQ*ihZLov7RC z5vF&VoxNt~5L8k*KKIar_v;)19cBZ+K zv=4YCDB$O-2fh8qUcs*yaM@>%SueCd)NGc7Mm|sp$m4H!LyYg_)^4bVHInW}sJ0_~ z{l*f@a;64WJk@tlcYjE-=H9R?wQ{uP(J4wxs&m92oM7}{r0%@{PO+WR#P2atFY0py zV2FZ-Vw9g?0vE2Hsy?)#(~Jmgz~UD!Z9L+``K!o&zuO6og53~@HEkY`REvYZgf z6EOl2xGgG6G{e&@OBPooL|S4*hGHpFBz;gBniIoe))!)B9~X#{XfBwhNcYSs!uc z)D4Xr#>aE&tT`UTxaWBOa92sN4CgX6zIHyVfU_eD;Ouy?0#@^Ykzmt~4x0ref&C!b z1dm(qmLI;ZJTxIpAeB6UBen!#k2e?8+VkN3T(=HFv1VrniKB|L*gGg?Hr8c$t6OZm z`_O!#hw*n2+BJ8V?)a~?Ji2damXd!dfK`XJMpLuY2~4FQX;M+pI1Op{?w3Bn&5)*6 zk2QGf4o`SebvT@ez@A5V0^>LJ$9f?G3rS@#Sqm3Ox8gLUZUFGb^-ui%s|jYjjCB^{COABfXVbN(qaqKebp(Q(oXH6!e}5=YQ(&kd>_ zlCa{1e!)SN!D>xPwG}aq`Y4_eIm*X{L&5V(dsla93?q96rky7ILw@jl3^*p@c~hC zg(ZfO!htZy%C4x)lF<5>sg*>U4=}Ye%O#QH0%6Muj^{b4bsw|p5+4pE5r7q?JtwE5 z?#?oA>^ThJp1WhA)ou)`Q}~*yihHp7?dee+#AU$^2mJ=W)9De=wWh&fs2lHn)Q?Hd zu|gbH-H_*^+bQ@v4#w1`NT7h%f0gwCXGa#m*>OLBfB(cAEB|c@N#N>kZ>8St0SBZo zVVD5Drk{Vr%5JN{ik5;@B*9}C%Gpo_{z`=2zIEUNU5BHfk0!7WIIVwEeqG&Ci?HtQ zq~G{M!;v2V=6kHmcN>`F|G!o5BK~h_?ps^!Rvb^WURBz<_AR;)n(iBIv`ry<9DkJeuMzVCvnIGcAGo!vVz%s8O#c^V`D2{zFPr<5BM?!VL8y> zc5Ug}{I&VmwTlyhdoLs&v5yO8XTI~4)9Iczo1GnQL&*^bRN}DZ<_2?d`+BH_1ug3B zkQ1EhgM?#-)v}ZT-$EQJ?Z|ZuY;Hbj(T5;0hl|CwedjOkto*pUy=fM zM4DtcIm{uMJY!*Ksh=0i&vUdzBBM-z<|T`Zg#N%+Inm{s;Td!_&>L5VbLtG1DDTzU zmv%$yQ9J)Gwj{*87Z7vHp!ac4Pp~l96U0v7y|K!U@gZo#*&;YSNY{?*9(nK#R&?cR z5ITlD9YY4EyE0a#b{g(plU2akkp*yeJVF6O_|%}c(%gbAr8r_p@Vlu;ev2j`6G^aI zp%&J7&iE_aK}L`Cz5VvvFRepkWVX7A7^u0GHZ;fQ(*2M$8TAYFnoBqQP1SGKEg`2a zQ`R|??K_`RzxNl?Krbt*bvwSOQg!z$;s=%GxcjM2eYX#Yf==D*9{H<~{ z*hfa75pd%xT|?-cd~Bi=eV)hMe!-J?FF7SXvjdaNJtv@b600LSFME?6Bxi9b%u*Bu3~GG zEmZ?6rE}G)93Xtb+jTb?EP%7)0YmixzwyCXb>Y-(^nat{d$~qk-%Q^*}&=vGzLNUp596g{AQsv|#oz()NDTQ380rc~`9$U% z8TI*mtVpwAk_^+7%#a*X%c13AS`x{SB+AhWIzfhgq$m|LG96~>qhg>Sz<~96hUCOR zIEff+32-y}`Xw1rIt^SGI zSp}ROSpa9p0~PSfv8maq>h8T-gR#TyF?6)Id)hr7|HPxsrHa|=L6n}bqJI-PogcOR zYvJnWM@IT=+R-1b!7}6MDlW zsR9^Qx~YVqga#?kC-DDePBAG7{5IyGmQ@?E^>iQPAnop}vcJD>^~mbg)r}>cp7C)D z>^N~lcKcgGj{|TEv|W1MQM}uX`IDL3^+;7(5ht-SJ5fdwqj8TmTDcVFy%#wyU|p z_7uEczWnlY5D4w)dUMr4kyD3Fvvl6VjvcLXf-=d=FC;?Aq&)MJg%!;%hD7ufX)bz& z7Fl+=DAm(Q^!n&18>SO79Yug8Ls3#kO1BV(MM|a%!Zd>fFLe%5k&3zK9eN{$6!AH( zg68=s!&_)E90FT)G#Zr{o|AZsNL6qFi4Wh|7ZC4Al)@ne933~*NzsBTyM3{Qbv&J8 zduHLXtz+A^ZQHhOJL%YVI<{?eY^S4+oxHJaCnx)?wf7&GpX!?R+%-mx;)$WrN1)vT z;#w#uJWhvSpK)!J@h_buYK{$HGs72Tb>7@&UNrHZ8pv*4)_!!>-vi<02b^*^&hHuB zHl49QR)PG>bNc@#jdtArzAUl#IXKk;SGA%`K)+v@e}x8*^x%D8(V9Ed^ml?+TlR zw9GnbOUIB%L4K5w(_QipzE?$6u~YZA+4sJN=sJ+CwY|1tOWs^FX5g0@#>Yz&xSpK?SLVA zhh!0|e~s_IT zn$X>eFOy`8$i<^XT`&8-xr4L_q=a5@Q{3KhXnQG}PJ z;QtkDj-4BZ&h9$2$b{Rf6q_?dOJXY>e$q}pZo{C1Cb9C5Ov^%1tNX88QkIhCCEn2T z^zfryyqNXh&L1hjHOVA4&0oA8@*vD5spxBONi4GJkCHc`EJL}5xG&>HDu!U(fy=w~ zX4syaVHFyiO26ZXi_YjcoPnq%fvY^K;)^cWBWMh*w6UeWSu4&nn!v`alOozfni{o? zZb;kJ(2N2$W5$u=W+blSA@6hoaKpSUJ55Sw>_5_+O((RbgkS_ohXxu>PAFqdetsd{ zVdDqH_rS}l^2PXSo^^XJgYl!kwKi7xPWp?s{bEG)2bZ2JrDW8o(kjv{(#k3Zc7>S& zl&(cFBwny0^s><=YAAkW_yuBFM^;r7#B;>bn^YoWB4E2flFn@S2u#Lg5d*MzMC9SI z^K|2jlH7^=gK*T#GMcv1IKW#Y(I$b%bZnDdC9)d~(yUPTD9LIiD)PRyW2!VuQX9+N z7MdgVHj!83i@`r<481zbM#c8Yb_l2-AW&AjMvU0Y=~0&pZ)1K6==Ax(k^oUxcB8vJ z>W*Ev6Gh_(NB+n1OBb(3a05v@R+VqK)zek|DJL0@#2Geba7%htHi;8pnzy=7FE)jJ ziu<}p9=d&8NVxs?qVs1ll9%JA8U*&EtESdi67s3`ZKM}8(R*?%Ik_-7Q49Ca@&4-9 z?l{!IlDx$F34ii1heZm}%l!D?U{52r!nn#DGMWuR3aCjYVL29Vu(_!#;>hZuWai*T zvB=0$SC)BpJ#Lxivki$TkjaC*$V0P3pW?S?j7WLgP>UZPS(IiZTsj@uGobT{8JM=4qwM>XRcsFf|^6RBcu%2lfQ$l#gu6H z;^WY1MOrl2`p7Z%)CH5)je*AE5K-D^!HQ-@MRF`EEEC~m7V$|#%_lsRF(kp4m$W3P z2Jr+gY-72mWF-;j^is^p-Uzi3T9Zs9I-wS;vY#&C)3=(%B;wDka8!m-_4cL2ml?o> zH{#Pdqef1$6QyC(ial{7j8~*{$yEX1zyOXG_`=I|6UA@>Jv6vZP(xSWweHZ4qublv zF%VDR@t~=3YXf!91#%^M1rChe74_4vK=q+H@iG&cR%T6ktCBo!JK=J_=BA? zNx%|QkaUu>p^MmqfaqAj8p*v-=zm+0M(WQLX_rVLc}c@&rSeH3v8{`MEqk?<#S?MN zAR>jj*``EpnHW`~HkdarRt=YQS^@0YY;~JZ>}jJc{4g!ZXIl{{5DGp8afwal4#AjV zvIE+VXoMF5Lbi};l2AefjpTDONS`+fT&g7pVb^}|^}XMpeQ(u--%Et(-%ANGecub$ ze&0TV?@K$f=R_}X9wr%KR~SG$ozRND-iF_-P%h?EhEr6_koHZjS?E;gWapK$h`lhS7m{SfY+X>~S(T#^VqB6A z$Y_8||6nO}4vYKc49k*@bqy+O(k9KLm@t9dJml;(#v68vw4ngXM)TCj>2woxBubDp zyGQLYiQ1|xrDX>RTFBTs0WU79TYH%-0uSv(R^rCtX?)l-*sJScvy5G>W&cN5!axw< ze9Lj3%q=al+f8ILoDW(+ZRI{GLr$$;eSv&rR$_>tS4e?^eTCg`pM(M5V}cURA_3cy z`(yQAMmv8w3$YqSh2`wjX`)tVeiesmK%)-Fzzpv4!t9+~QVD-Zb-=(9b-YX7CPb~S zK=t#Y!A|i=4fmRm4lA2uSr7wVi)0gXj7ml^l=8PM_6^lUdxmN$6Np$vl;#CbfBX8Q zOwXfQU80KBs9T4XQbcvTaG=ysan^V=WZ@}GTU3-2eNBspjWSK{7G+L zsxHJ;LCz?+eggh>HiqdBZz-D^|I7wp>`#vYc~+>6(-CrdjN$}yePfm(xr0Z7TstO! zTE0K^6UN6vfIL@3^=AxsAdD^BAEU`eK;+zbU|_iW9)p26aZ{_JdFg(IGiVci=Ac)~Tvgn}cvO=>Q-7a(&rHWRM_u1=lBAkY-YzT~=CPcY+0Xh#P ze#ziRE3VD*x4~}6se#T9vR?M zp9-bAhgck`kT*(xCY&Nl9q3Y4#+vTQ^^mMkK5HE*Cle|w1%#0|Y84S>dU))x7fOUG zs|Ai8{q^-jcyC9OZ3;&sTk?ITdiH|2l}}cp+jB&tc_WFC$hYk?O$PWyaW1+MD60kf z(sZOL;LDxpMx>zkWl1w8K)vC@@%i(zSMXz_yb!z?Uvn1>7!In=;lW*p7gLaI8vD~! zU||;f*yQflW=6<;V6`wXr#7Iy9wlvh`9;rE)$Bvmyz%CbbEoMQGcPlpaFjy@N^nB~ zOtTIgj->wX#4J*5Se|fn@nwL7@AXFTAx0$fU->{G&*C-#Y;20GHHxm zlFUR3RdRM@SjeR^nNo4d$%4`zcXWw3j&Rzp6#RHniPi-wxwP3VDGg2bL?#o|hL9Qp zSP`52ic2$DOgCaBz(0>fl&t)>SqAdYRZAwkkY;D*$U`dr5HXiP!GU5glp%7osC4Z$ zH`2;Td#L{St`pe5Bl7u97wQT4{na`Z&Ws{#sEYQ0)>0sb%VvSAV>f2Y@dVOx(|+6w zXCc8Ic5TA{_zIr?N4kI`@hfvrNF&hQJBEShmyojlvar^ej<7d0$j*{sCkBE%Ijcmb zy1s?%-P_y4Jc}8R1E2hITHE%=jU)U%JE$5CAf@Wk$Y>@9f$#XYP%(Cl-UT!EK+t?)2>OP)@!DEBo}EO%%s6pYIO+rPB_Q` z5_;k=t6eh2Cg0f-vvkxN9L3_ul7?VReV~814*LiD;rFQ;vV?4p#X5Uqp4vs3{orgR zO}bM2_qH_WYJf);!~FW038qD2+>7i_5m0m`8>Bzowl8*|zyyl>gj*nq>jt=4NGyjS6_5iK}9xS~V?Cgy(1$RCsYG>8kJKsXmadEExf%+Gp%r2a&%!VUkws|jj zb{{g2*#k`V^+?$KKPQWf7Z(TA8{82�_b7Vf^2jZO>6qRO?DSngO z%tEXtejRc$Y{5*3P8Mb*{?=Iut)0V4YDIpLGZ;~O!!8i^g(Nz{MaV{=P=n1UO_3^U z2L;S3o`U%B_r7d7N`r?7@L{%})Ba!HQ5roqQq{T}C_b$2Afz~uK2DFcOiG5b>~b`| z=aclZ_Cnz~g<~M?_k(+nR)-__2F>zgE&un!s0&=l$FIJUnBA;nhuV*Mo3!)O!m@imA+HS`_Y7+^pu!Ji`KIHzww%>&jxFyq3d^g6HW)? zk5K&^DIE&Kle!gQ2%Ba1SMvXeOM=G7_83}w*QwLbBr*<}klUY~=9^D!; zC;mfTo}X<4BYVSvJ|{@n&je{cj;bGwU!7lltG%Vx)TBuCa4XE9&*x+=|1^vhqVIJr zHiLhubxD9-9SWx1>W6&jPl`BI!??P+Ut?zDv!{92#y&oH1t#tcQJX!pzRKeMBvF>GPD%Mi1{PZCc zNVu4<&Dwm>UkIYF-?9)~{u+=M1q{Hbo+lOyuJmZ$r4;4sIiHS>BoThjZH})dLr>?C zb|D3JeX$v2m6sx0t=O4ukgTNccGqcu?Vw97OT_1?B9JWMWYKvc(|d<%Af(`tr}9J9 zzRi(Vr>NAn3XK!H``W*0`RE&O$UM=ep_9L-peEKucTA9Opc(2y6DgjnoZYqN#I)67 zd8)fIVSGGQ3;K6Bnjs;#A%4$Dya5!Tjb{68P?)Y7K4j7*k@!TU6v!U)FcP-!PmuVt5HS58^KSuQhcEZ)r+=};8TYc~M9DT~Y)?chr?Q^hLO6vX` zh1Zr&lh^aw32%Zx`}Rb3o;VYWneQIAiu~>rhWrPsz^z&+MZWmA36X$UCsTHAn$p$_ zbE|ugmvI!}D*Yf=JG>&}p_d(?($sJ&o`vZrKq$XJLZ3v}kw{wKAmc_M>`9`jFiBNScD6#;HFfoNenYZvq{ycWXVpwiPpcrWG-wxRgAN` zo@i^6^%ed8y#CFCS?Hf*|5+#m`n{r8twt~oThNj%ZM{G{ndkR(lz?yj3X661XQnro zMW|kPrOjcB=f~aN)9LLfjgK}ZaOCk$$>$JoUAzuV8~tzl+@1Hchc2~5YrwQ7=0TWT zMi2Il;HS#wg475aM0qO(M@rD`ubInT-x9~@8D6FpK$GQ$QEQkSnC#|z0U<9i^iaZ( z8_qrOR#U&v`?oNW!jR(&DKv-=$c2q-h#ZjMlxH_&Wm+#+UHpuuAHQ6^8jk|Lp@orH z7coqT8SBk}w(UlWnn1YxvEy$#c$eGXf22sYfMDPqJ zX=RL5FM6hVTkWg?9KXxeb(zsH084Px`ktUjIq%>`?Ud>jr0mqT>rV4FQo3jGmV95g zlKET#{A8YR`+6k8r{{e5dDVa(1oqdL9}Aw}e}*-il;QINJB_JJ)sh#(IQQ7bCYuX& zjvj;|5ETi{={S^p{?DO7-HB3EP49$bJptP7bv`ACZ6u*|MtHCvD*->U)}!4zi>+qV zlK$gFGI-0hWS)rv!o{k(67NllT0{NrNN{!P_S#InxBaxhv4{?`cm%r^!5?MC54m^&o z*%njXQ(z!M%IglGLbZf>MNWnTeVBHZL+c?!;)o&!Zfzsdo%~>Oip<71tjK~xd}K{% zJ2lWQe=;7^O&X8-W@6}(lI{o+pSLv*Qi(q5PS)|zi+f$+rp3j1GL5X6cZ>bN`Q)QV zn&^_un5mPZOu|dOM#*Bp@l+XD(0x;k&9cf*zl>Mlyy?PWtaM058nDp0^U;W~0pf*g zdTtO~MRrs)xkA-4yG-=b)q~M0LSmgzMI~eyF{x~9CZG>3YRvH|m)INgjUWgZy&pmF z&_=ijLp0qQX(Vn7;r6e~JQ#jGl>p+tor?y6CVb*B28+?p@SM*0PUpfErOvf3%=aYw z)*6uiNTtRwSe?XizY^ru+FE}>1rG=sw(upP?YY4R6nL{>~eJnFZmUDd7 zxeNuA`z98fyuuF0)Gyn`)6*LCov zihWj32;0B9@Hg&vwY^0N(kEy-K#^%*rbU~SolB0egAcQ~yjtvm-)XFLO-^S1&C1_0 z5U+VN_~?fa0?a*5f+n)#PQpg&h;vJQY)#kaeJ&sVh5Vy*XJf{0Qa6pP9d)086lD0; zZS`=$!;V>bV~8k1I_Umj-TK^FNMCron;3rtDwZ}?!O^1o7=;xHBxuFPP~+i&T>bLGy_Mr1wa6~Q)fq^ z)81(u3~1eEt8{V^M_@}tzwM<^%^$L;^t*w}OHfBg&$|e1Qq2qG4>yvLhmXgZG=mH? zlCaTZtR#74{4UKfXAtl3W=k%%B)df!o8J{mx_t#P4u^-d!iKg;k13C#Pma zp)q_-L$R06)5w0-$gG{ySk|(q?Fzq|v@;Jgr$*T5|K7MCSqoUZwPquR3Lq)oo1)^ufL?_nt;<^7^ko z1FF9YvEAG5@$Bjnfci=h5V5^4Tmb}xl@U>&jTlzIk4i9L!>(0JaDLMFBo|lnb-&&F z_PPCe<+J_$)zdEs@jHFzm+h{|SwNk1poN5zfksxO!PMHL78ely$gR<%bfBec+~<%- z4iF3|&VRYGFLf1t?WShAVaKF&PlU;OOjYUFg&q-uqdJ7U)feZMPN9uz#gE3KH0X9N zPT?8@@Z3z$Z-1C2iez^OP*Kj-9ISAQz0#ZCRWv1%xWDe<3DdSA*nuB>GKQH%dALOx zlOV|~qC`Xo=-%F)4zxLSr&f7Ob{2x){5^AcFkAj|j5{a7^tP#bN2hO=eIojd`Qp1m z=-Ua%K-PKcD*Ty{I@ND%*>W5k#$GV!>2K-B*$QKB>B4qu#|5{pWtpTGA{KHJ)|yOl z7R}v3UHAA~tzWx!7RozEycZ38R<=R8#3Sk1N03AmkU@$W9r7UHdoe_2n6(|R+e3{d zuGsxXkFC}!056aXAzcA1qSe^gR8_4j(8BQJY&=*KAnRH=Y@xkx3+8K%rPEIyw=C51U9^L`$on4fWR7Gr=A6jzt$?9g1Z=q|W!c zl(-M!p&kw~Bv#ihEx_%$au4YtYiA)iLGqW4XDjen zT?BJP-O>cFu39`+N1$?yt9T#JPM6%Kn;HS^3^IP1H=ls26K%APDaa}M#Cxil@Kyz+#)0_m_9yukAnYMFlw-BgH-iHTJh!lUsGQsh(Q$E&FWd@8O=3t@%Gj^ zq@EUhJ2S!S?Dgz$DC8*{*g5pTe*R5@Pa8&EUeA-@oU9>zOH~zd52vGm4=elsJh^RuWB0lJBj*luH^WKRE}#1aa)bEXqg`&J@Lgi|M~G3)6X!rJMOg$ zCwNWizJi&DXVSZL_y^UY8yGGO(*!b?bMUgfJ$04+Kza z2r3r~++`qgSgyq;%IfOftdLc!c!orZhdUhf!ii0R=?kTf)6t$qh}6+hFfxvAamWm~ zV9>B39@5r6l?xcLD3+{IizG@75SwT~fY;v=J2|zpiQcL!^O^+-0n|a{) zK@?9Hxoc;1F2@OTD|=n{%;Xyv%Pn)=kAzrdOSu?yEJy!5`4~PU*x0|a$#L7y(wSmZOW(jJ0JRiRr5-`eEO$QDgH>jyxs7Y^;O+jipf;lw-fW7=_nj*+0Io zsW7*!B%5aWS|*$1=`L#1MC0u4)v+1;cH$(_N04YxpmcPLCbDxg1HX+&L~ZA-?%=Jy zxonb_+qR&JX5eF8{o=qT)v99LM@#@_Pw)Fr{U#E z(Wq|n&fg*F8JP`#c$ttx;QGS?^slCCd8!*E9`Tp4R!MkF(-H<8ceOAKNrQK>g&*Y;bcttsR z?LByhe;4b^Ir&v`0hacKQ)z%SN^i(Qx6$NY(`vk_45it4 z|3c^CG(4;P%XX%8WH1Qu$Dr9tG0uY$S~v!`WH+6|pQs4r=uO8=E^Oh|KpWJNB;Sq% zWA$*325VF+{u-Q>uI!SC-d5V{>^iqwk{;dS%uLRBn+L*lBYf&JfS;ve-U#T|}kM-cS( z7RhL(j|^p=sekX{hxvc`(L|S@p+4l07DY3`mClLb8QQY(O}^o$c!?H;Vd#bkoeI$6CpRDj#JnF7VMw1Lug^HgdIj4K>npiGr9H%<6D3YDI(^&$-fC&)=P%v;b2Rx~ zra_~~n~Qn3h><*AqQ(>O7b%N|9iEC;rkYnq7=jj($D0Ry|Kla1>3<86P^n)DTt5%w zSS+kSFYmIs*#yY6-93Y@EdF|>|IfKBvr^6Z?GlWP*5z4==bfd_0nfKAt4@1~HKF(E zLO#annSYv?4`y!poUG5kD={AdexI|MKE2T*dcghU?CU*1k}3WcRKTi8d4!ShTJ(Db zr3&QH;X{bZ`weXLA?=S}WS!u9Z~?y}eBa$)2xxj6yTJqhNQWqNyBkE!96>^1Uc%Qk z1+y==bLy4-xBzi<-K?_Tn!Ig@_N&QO&h~2!So8~dR6^OMwlU|xUa-lyYD2mTIgv!Q zT)HG!`?K=o=i8oa>ICw-hNzedEa4yrjMQLlud}5gKN_8g%?gMmCq>0@RnL2%MZHJW zZPSizYiTDW*o_Xc87(D>r`73(cwLuEzY98BCj0f=FO#<;i~N5Ynwpx`OOVyBOETZj z=i85%Rl*>en#VtmCj902U+K?D1o%^`bdYgoo5c+e$u?P z#MNt55x@9*O~wbLRN}OC3(Rq+FUY4P147+1tmQ*#@}!iIYZ6|0bVe#(>?S5bHL(Tq zWtetkPK{!`q7#@Nn?=#eNn%4Z=cHX1LeqBHrQPd7oyo?TAe;g)#7B4ArRzr(vuTlM zs$Qa?6m4xi!}E6Dr@&v%d3{FeOM<;?0zt(IiXm-1ik%tpsEPqlgie2-aO18x{T7&u z^T6_izbq1c?Vst}5Hb$VMeFlNDe2Cu@2emis@UN(tsxD!%D&@OTkVk;ft#y#`X<61mkJ|2tXCB zh1RF$akjdEtJQpy)Pb1G6|e_>RZ3rTBZE4+JBVsRs`He8!NB%N{f#@57x(z{B?p}t zo3nocf$n*l& zl-OHFaAlHqr8GFPRTzmRvTA?C;Bm|d+RNEc{y@Blu^lJ~CJs=aHrUWC_-5{v3W;hk z|6t!?Uat|mdNpK9fgNwk`O3A{O|I(vT7r9QY!(kh${F8eU`w%%HM@Bq%T|pdrlE&< zRRJq4=+4v|F*qHr^Y2~Yq0WRmp(=PPdK+6sg76Vx%hTxLwwWzdenG=NKnY$;MXpjr zn3r=yXBg{VxyOiLM8kcM<&N=dtU;7adpj}M75*=%w_DK^hKHMS67L7{R>Y-8a>8A}x=5iuB}b&yBqpk1 zK}m;&zT7)Vi~-N$@D64vq3}cbV{UpIoyo1MLq?((Xcv-tO)-z*oWYr>`GqKNNAxdw zbe2He86V|i(RFyOmh=l0G>DJMvIaPa$>|4naipAeFix<6Y%`z@5i9x>;UP$YmQ!Z! z1T)sOXBqk0uMTZ3nt<~+kDRsfWsP%hl0fF_TZnC=9-QbiJSk#3s2WCseg~v~+G>d}H6pQCsPSb>&vjfaj zQVS@`%1(G{)1Fz;-Svu()?|(X zzzquJlXF{{uesl36;Lz}m&~~!tSqpz*-P>i6v*eXSGw-_%q3H}Tu+`I-53gVOh?cI*GZU`@Ma-twW zh}iA=Hsw4UCM^$Iyo(fvf$Q_iJXLxFGx~~xhlEifrKM?h)vkV(s&Rxt*|e%#&w4= z<~a>r9R6NJ*eol>wU2N-UTL_cDq-( zA`N!OC~D1r?1)u7(>jzc<}gENcL1Nk*NKumbAT{ey}vDeAc8gl;CGi>dnoP<+C>eF zc$?%O9d^=*1)eX)yqb-DA_Ir*U<$jHtCOcZ=pe_=>D03gAkcYR@MCDZU+$#9PP41M zgo1KGT%sIk-x08E%3ZU{W{v;jN{4#;k}) zp|61-W1wsPP5NklW|T^P)^(~y^=W6J5ZZVHaG4J)s|j(Lw7nUO=nb}boEi}MH!Xe} z7GrM*w}b=J8iS5MCqWo-N3Y9IdN;&E)W=^P)mWeead?CL5(A#$#*)CjwH33+ zkK>lMtaecHmpC`Ku9CQm9zWRQrnAk28u47il{1{Djb=w3@hhqdcdvLM6JJ@p_m4<_ zqM$aIq+~~<4ekr)9%MC;Oe(jMXD&XZj^4ATQ0XVLp`x!pE7p>;tk^c8ZVg3#$6>5Z z>wZjn$k{q{?$9If!Zubtpk~40moTNOP&z>iNo}+ytPFF=OYb|N*dm7;@T((7Tv)l& z8v7eK{&Nz3M^HyM;On0%tU-CufZ^_TyT!;~)lx`TdWvISnbM}t&SKH6!l|xu*L5xG zdrgggP8OK|;Lo*c|8G!;ZHnKvJjV7098~PE2cD9;s5H^z8tJ{3`g2*AD=$m6Y556R zD4c3Ey-Ur2sGvPEFadJ4;K-{ceqhEfnqNC+KJSDpQY!Dp)<-(dw}qn5{`$+m%4+;B zZl;!OTT~cfIw{d}9Ia;K8RFl6Z*d8PU+jm#pq=3?I>RSRm~qOz{dV+a`s+pU4qg~A z&sjU$#f+``IrJPi@{W8b7Y;VSRIzh$RnhN^w>P>sr-np4yp|9bak-h%mA^ljETC|b z08ukXF6-V$l zS+7wgEI~>JpG1a-S)g4#9}t#90c_>0(Ql9bVicGboX9VB4De`jNHk;Xq;aUj*=_>q zJFO${Kh*vV%6d~Q4>ml7=$~lCGFJDWT8B-3i#FkwQ$2hm7p7_fr7_sy0uGL zE6{=ItA#fc$qHbm7dZUWc^2LK)HaUG)MzliI**q6vnLE>RfY)s$<)$YE-ATEJDh2T zSjq+sbV@o9faEx?E9Jg6Q?tup^u(XLh4`=-7k^0?$}y_9m9rpfy!a zD4;LWe}PvlT>3Lpft@V2z>PX!co<+gbOnE?l3MdZgZFb~M}B`IB29(PQ&w`N-tbzl z50HSq372wNN2rf@S^F=DZuadz**J8T|jW3;3BJ9U4;-x*+&Zv^T(|)@3 zN#BJvEW9_DkMWI(?ziJVyA5}`$%wu_Snw=du7CVodKeb&rf8;Mu7hlltC&z3w;Z9+a38hN1n`8lSu^1Kvgt%x_dHUZ zH&N|3UAjJymS z>fS^Q3;LUgsU z+D&U_tc_mFsGqhe9n&7VMKKtE@+)C6v+Zbbv>I8HukzFQ>|$rhLZfFy5qXw7878sdLW5%8i|$ zJlWpt6f@!By%w^fJQqq)dKo)gF|sv!bs-hxWJAh!Vu_k7pHJGcbs{=*L^85{u~t!1 zHy;F3XaTwl6b~fHj8jlriP7xR74*@L;-kGlZc#^*lfRHC=aeW-3Z;;+TVazn^H!o} z=dzi4ntSY~%jQ47F%$Y09Z5+EnQfozw0rlNNc0%>5Qc&{i zraVJL6uP_+yYx%Xn|6oLVxA2DLq%F6UXvKHz3fil$HI zEs#i2|P`zsu&27%^eu0x`j!v55`>n!VfrPV6 zX7`0g%SKY|88|K*LF3aK->si!hZ)F%H0l{L$Uuk@-y5M|OBWwToT4HyWbvxEap7F>mw66Wx;DD`! zm;`DYf6=FoA^Y3n%rkglg(&C!MH015@9VTI@RdT=)$n*aKiS4llr zcsEn2W)MEeXKt-ia;&wkxWLYL>0xy$b(?q~7JTjc67z|WhmMcDB!6p>WJ$7^LsO_y ziKU!l?(kOLTo59DpW>-M-;|^lQIL^pL=03>G^f6iN72a54*H9u^Ev#mfM>0C0E~O z-u+(`y2|P>#X+$ai$;w5c?M#^X(TVrdv`%{`JmAhOQv|bc2T{F9(ykc$1GX%kgJJQ zpe+>P#d2w+f4)z}rsTivqg%VC442?vU8-PX46#;knYck5=`ouJKRF2NIA5t z=wzA`R`E{{dC|M6XJE_;;gi$di$j}+fr-i74)lxe;~i^ujDaP{d;jm8$x6)75;>~38EZPM@~@6Yzp@ir z?%*i~ZxEv8Z|LM8j?R<)vp%`Tr*0+L?8pWv8)wbci?D7N02d#jAu6|Mv~QN$%)98Q zQ;;OQrH}t)z%5QE{<%S|bG5HP)k;Ztb*-Gh(6|+HAR-TiqzZ`aym}36X}=xOB|$+H z8op$1M7WzF!f81w@&rE?8^TdZrlt|ZJpKcQ?;tHxvAsIo%%wV7o|(}bJf_9!#|F>Q z#s;!nMx-|KOlM4wSQSCySpm_H^XT5){6kQ^HHUoT)LsnIY>5WCmidfkQ%81L<$2F- zq3OJ~t1}fSIyW@`_)LjNr{mgmp}10)9#{YRvJaZN!7Tjk?rXQc1Ho-A^h37m%)n!} z`srKwLmO)N5H}?VCPR3~Lnv#{n}VpQ^l*UchO3@%?NDpC%h_9I1xw7(uTlXs&efvp z`pVcchN7LTrji@AhdH=WuH1E-o)(o>T9DP zWT12$M7oR*wA@`KP!S&ZhxPrb=MR6s;V;S+#Ud2vc}Tpr9>22tF28#{afKnr{5_ELy~eHlFH0A-xTJf3kLI$e3Gij6njSH!)E-Gyd?hc%PnX#yeO{z zc`Hh6qQLs<{_-d)9Xff&Y)bU_(iChd+q<)5DD2&$d(++dd!KygkydNabT*%SA%eS& zTox7C7ST%Uw}be9XZ6dpwM&=`T-B+i z9%@0<^haTN{=Wco4SLfJ(z*r}xPOaeV?FJvvv_`; zQOPQc6JN6&l9tB{aMB65YVLij=bg=u2%ku2*iv(danvE5t}(b*%-^QfPwe&n{&Xa> zKEJh`_;Nd0pK5uYRLIkN{F-EK(X`Ycyn)`wGR0&zOhg3Q+>Srxg7V-ep5A53Oc|9poZ*dNn@%ayr}2FRFiI3Io>OK&&a;I|9~P$^>|aYy_de;nIiAZ7PPmL!hZG zZiBD-O1zwMuWS2Vx4kj;K;RpF@1O{46L?Vn@eBkOf_~^xRp9sxd=ASjthZUYdC2e8 zkznmWT^q1@pYg^9+~EC*|9#4C1iICU&;bZ_Fz{Pn>FDtJz9D?j{*6L$hw0WRSs2sd zTi|B?PPL{+1HntINp}>pYilW22m}siFZB^>N+XS)Q=S|<8Zdlr^cf}aM@D^yOe`(G zSlhsESVyCDu0h9!8I9+j#$LK7`Y02pCixY_0Cd0xK8Emg45mFC+0n$8@b(=afR0cG zB-5Zp@5eegV^d*3mx}sw&L$qyEHimuB)F!PZntPaGXP}Ze)xvr_Rc2^oGW?%p2vZS z)IMD?Ie?RK5ESQ-**0z1+9A^QM~b>x+5M2oK*Dyrr$CR_WsI(5P35Gl*NEm*%Inx! z|3*vk@l-bFU&TuKG+%-Al!kKKosGnQ-)o{UTK_aArlkZHlOUB(cth7BhVLiL@SWT@ znUO|WY}5%igBTEnn-?W6C>uZwJ})Lxu~JxB=cm}|bjeS700z}zK0+gVJ+@$#8yBJPDj7VmKNCsZkB^U8M|*r#)IEhO}Vm(G6f3bL( z18t1|Gxr6jdGG8jQkNW(YzrbZUn*k@n4Fw32GONUdrZ@H9E=)Uv}s8`2sC`$#^^8p z=RsfIZhHHo#N#gyQ@Jg$kE8c~DX`=Avy7rtddbzErdJb0*tI__eed&2k-gpY@Ux!x zN*xhSt*x~n13Az7H)q&%n6~x~xIABDEZAVbq2>mWn8TJtTVALW>^n zt@KS1#jfS~>mLLIGf(=%rCB!qF*HomwJ9dIAnv^au~BC6dsT9FXci!@%o1z(zM%2^ zXtHF(g`#kKGtQ=J@_UKXHx`x9Qq|2KmtcYuAcfz2-XBSSUHkF_p)W?gMctffsB5X zoXdL{EU{aFPLyz=JK<(2sYl_KCizq0rza$PENSTI`>(DkPNvX0V{|xjZPr(Gu^=3Z z%igfUMyK=ve1HI__G34MPQ>U=Dtrjfh)VW!f^GLt-o<%|&>XQ~TxUnG+F` z7Wk0Np*(FOG*D)XUzJl{GW@r3rw9vK*1=0t-8|)+Ph%h zUW>x2k6=?4dZb1(W;44!j2^=Xw|JJl{w*!+65ejJF`^}X(sj{Pk)eKyFSAq6;`(m z&423|p)5}Vk1(YkKE(1ug9ZIH0yU_GhJObD-qm9 ztK4G*p{&RR!cGqXy0vVVzOgFA zAhy#;%&QENEComLBn@ZT-e$M5>@lp{OJF0+QdX7XQBnO`j@2v5y>Fr7R_$3~v(0>o zSLX?CWMOwVP;))s^v{}+yyMB$!fX9f$MUPo`~ioRsI<_JVzYhXq}87<`RcZ740+*f zUs7CG_0~_YioA8nroHE#Z150Ha?R44hXsB zAWw0ma`n!Wx~7*5=8P7=NERUk6up)R3ewoNmB`iwxic>=eXPQcnTm#?JNy1cZ6*%r z>5km?P?2V#Hr0dNvgoui;FOvje;@tTYP@pF-g!q_`?vQA6u76o;L~qp;nnV81fSwH z82OW5NaT>!OJ?B1x@kSHF?tXX-xY9-rMGR|zci1nRP|Hkht3Tiq!*kLW;eWiuyQ`S z$~I*bF&ybv6*iGXQLQ@}p}jz-S|BsG2SN|eFM!9H&1wO}8tIY?z^9Y}=T;-@-* zo^F|BcooUHgp;1^7nRyA&Sr>c_hOl(xR=$eYdEf|t#|7xBP1jhqn74#SOjh@2H&nP zp&ZftsfW8YW;tOvJ-3;}@61-z%o03GxemAXyJq<1ES15{6;)uy#GqE6pUGXWTDG`x zRsXNEs4BUyLzpmRIxL!W=ec-6&@&kT)IFqOQJ~!dk>UP*85I1%H_u z>cIMObV53hV9d3)FH&@9jc!{-=`RhCPf9xc@_#L~!6NfGfI`N8Zv*okLl9R0gBQj} z;=lBTX^s>6T^MrR^3h9=8>}$zQo_PyuDF3 zMz>WA(%d*bu8Avmt>gOdwVMJ+QQRhIA=xp%b@kxsqFU37)MyoZLq zZn7hHM=?p(wE|perUPI_cGI+MsAXfx*$s1ywjbHhXrsK>hRI9CbCL_U#YL9Fn;@x40$JqrBGjvq)XS(H?Vs8)7`PZ# z6XV|v`IoN=D_7ol8G`N{>OJF33hvv}^pT*&bS0lPcU>c$WR+}XWBahVYSyo@IjkZ^ z7sp=W(u{eY8DO2?zP#PhhIrP?1a*85QiQD=0CjOy%x4{odQ^rLRWPFTV6|f7lY@j z65J98utRa}!rb^9oY=@PV?~GH+rodeZFx}%Fm4?a;f zLEjIwE`((_SDdg+UCa!g(rS5i|1s-mLnV6iV8kvs|BF{-DAVMVlBzD$Jer2WVQKhH zd0P3I`B-BSsd$y0Tv=;>3sBtdK~MqFW#w2U_Fh$tTRy>Q8;_5cTT9Qt23?TL4B@+i`eY?D4G z`#`j|Y!Ui|X;gdP3Hn<}5-LgV^i;#J;GchxKe!|N%AhSqezRUvVAcNfA{6_>P;!v< z?pG)p87*(p`LOMx(n8~wybKjPeJ;p&utS@Y>PjOyZ&^nuIWQSpB4RO<23iOZs4SyN zw?h!=A#093ulvSI>(oNo5HhCR|i3orJ>#a4B9Sn)S!Un1Bg_ zo66v`%FfZ#g!c7HP~8f5^`lCS-OTN)r7kZDD^iaM&nbjTvr#EMz-|x}4<(gECn;G4 zAzO?Ep{--f;qIorl*-J7b4Gpc9lC2edHjbXV@3Kv^N0?I)8c=q;f49w%{8$U-5O&cPf{N&`pTvhj`LL&&$UxmtoGEFnV|->f5foB$Clt6RF!(BG z7z-%GnT}Y(_YU%&!pXm~(;=Zn#Q0g5Ir?m8uVw+u+HR-!LWma%J>Pq>0Dt7HHow~3 znSq?cl?D07&VT3w8%^}M^Lj#Zm0P+39%GnHN$jb~0Uvrg>9KDV0K$HuVtptilB1?G zq!JqYNYbiR9g{u0Z+-CGZx$L@v6Nw<=oH_$3GWTW8OVsetHs|;S>Ro98d#DU+JHSh z+aXUsOiibWI^8q_tZj5=Ju$B~8v4BHth?}k4B>P7n6BLk-rvk8yzhj-K@*kV(gTdY zA`UM&5G4q;Jsbk(H%IyVX+T9$T({I&i?EkNM^=yECm}A#DD{b1@0BFY8hKHcWqLtXYiHUxS7s2 z!x)un0i%M!&Jwct#sJ+|@<|NSTuq87V~Hr!XhkTRh4?{z=Tq0jDh|z_Uf{>Qe*16Y zW0?3sH*pBAdHBoM zK@In+h&22!O()^sP8>5fQw$*gzZ~|}FqI+~*>0Z#lFcZt!->nih3iwZ%T`3tv@1^4 zk6D2CuhRUIUKt1kyqxcXO&FD>$-m)-=vmOw^0GPgNM~jiXamfe^>S7)nQD{zSF=4~VC=#>cvPz7P3W^CO(a(J1zF7qUwgTQk|FiQ%jICa31O9w^3 zI`lo`$p+y6P@jiM!0Joi)e^#|WEsF0tuDPdUL4!14Vx`2ETkgXy1N_Z40^w;?-SS= z%_z`;uyIfIfoFEs&^Me`xLJ*va6hA9QbjgnQ=E!n=ErVjun`%h^>|K33>B}a+W#qq zwCDb;$@z^x2ZIR6QD7eAKQG4k;AK)+?`N(E3sqcGwi*0J*~k4c_Tvq*CuE4bm|Yu# zDoZ<6tKL4TPv89tkxz;*$-av+*Wxr&T#8`w?T6(RT^+5gSp5b~YB9&x)jw@jssv?A zODM_OqjNb<6UD|2xS`%!=^MA?7A6vwK_IA`^hx0n8M&ox-Qjip6=u_(O>{*U$CfRL z+6`hO1o|UQ(E#-ZlxHNA%ol`!u&STa@@#4;eZ=`1a@6ZjcT=I%|8pu4%`c#^$pa7o zv*Dh(_<`bvD@35SBn?eF>M+2pb=(3z)wyl{Kgm1?!1OdkyeMu8zYIz;`sNTGrnJ{K zk{aOz|M!aew`S9OghmKtLUq%(6`5Mwwm3{hv*Pp$d526bP=j9#dda3Pb48FJ2k+k? z#A8}(M(OCfIl#e})Da?@tbOrNiqQ=OksQGf+2eT@3Nh(xM4)1WLXh+8TZd5%&1gCd zwq5%%!>NiA(0Ds7>F*oJ&oS$4DXei~cSjuM24TW+T9#xN-GSLzh*c1Lo8-Nu%E6VoZ-m!6*rr5U#++2_~@e<@^abL zu=`7uxp?y267hO?PDn__r8cwbIZ=L6lZZr#wyknCaLpcQyr3n^81y&E?aQFt*h>IZ z)msb3V!tnnUnLUIJ~Q8Ur0fw8vZ=e8iO?UM4|Ck~;pZtjufg6T8|8O)XGe;_%LW=#pEr5>ev)#B)8BuhWaSrxORk-k~PWpEp`4Iga z+DdPXW#nf5cjZjDiIss!>8((LJ zHTFy=oKvR+?Y-l8{HTQ8O8Ap8g{_;_D>7mv-RGuYpP93D4Ld33w+xmW-!Vi>sc*ck zl}{qd#aQOr?H%1rMiJ0y^>%MOGWtu~d|w-9a`N|11lLcW4P;npzwvxE5#M5q)Lf)L z8HSW(QaM%LN?27YS-Fw>Nr2!G#uLxopP`*cw^2;g((^m;L|bbu=y?pmV`7Qf@WtT* z*E8?n=k;LnoD6kryyUJ%q%c^&b)j`TEW)SsKy*@Ao)cAIPap{~vv~Hk2mvCNV^Tl3 zGot-|OP|?8ObD~zNqMVBXY+1wYmO}s$E3@HuvjN*dbQW4Q7^)lp_Ps~KK?f+8({eyeJm%nrxA_<49x{(MV~!meQl6F&(GJZj8-Dq zIZ8$5Pl}iS1^FUSOiY${`$c6l^<{Ex62AyY9oo6leO-1s=0BfQPFT1g=`n0XR`0H7 zEea+6?gJ#THhJ&Nia3)mcS42=w^vuEh+9=ta{QudGF2^r7PICHv|A>dwZ`|P+(ebY(9eWs~YoC)Yp_f_jsqFp=l-<&W z*U8^H=h@QMW&8bbRNMH~vC8hMis+3CviLLaPQ4d8;`2SnQq&>~8DwA= z^e1$Hk^9BD@K5>F?8KZ`a_(5Yn&rT*yClYDx40^dVf zEs8@jh=;`Ada`qY>%TQ>)ry0^LI48i#*ZtB7bNkYH+1KNLDZPB0rZ2!FBIG8*3e?1 zSr8XyekTBJw$w1VVl|SK_*I{XCAdUNwVFsU|BUp?i+3`vKyejvliDMofu9RtL?n6 z1lOC0sr3nA)$okph|9e=EzcRg+GcaW5s?O=#aeq|^R3c4z{XMpZ5HYE^#ysW1!Lz@q0@WrAmW2osL%(y8|`J)JWZTj=@`UT*`dS~|X zRILKWwBiLyxy)lFB>vZYBGLqvGflr+thPA>Mx`dR($l}yxvi=jrqEtSb3&f6Qtu5K z_@QA`bXG)f(WFFcYG6H}U~3jj)abLD%N24{Q2nsrEyZ%dN0>l`6EO1 zR27sK%tx`)mn(;6(kZ=_Q~oYxCO4>24qlzKA&M}*0u$JdnE$Cu!y)iTe1T8!K`tt= zx7pURMD6GsM%WBnpzi%m*J|$jLFu&7`|DnBK{X&pDAXySoOSqX{dMmoPX!zGig^#;B!9naDD~1;kfDZ z`EWj{ce$zShkrop-cufUt1kAK7S35$@OD&VBmD(fjBbMmn-nmZ)S2Y;O5#8lGnQeL zFr8uw;*>CrVwk;%wy|+5aGu6Qcyd`KX50aZCZXr>><1>?eKC39ab!})RICa16t54c zenNdjkwz8;xDq4z5iO=2Q9@rC74xvDZhEQFUq^Ed{)qT4U*@II@JM++op7a%YDUP0 znC!Mzm>=EDq5XD4Kj>GTf8&kC@ZlaJ!wlE{L?4z)!<=4}god=aRCM0|Z_zJhizYBC zVjF{fh+~%-K)(XK`=^~e3$FAvi`rCU?8u!YQ5^&}h!uZ(qwg;l^-fo0VK44pxG z3w%|u$Ys)qYdaMUAYri{Eum_I!HQ!JUEdvjpq~BR`H*gyMep` zZ%-9M+vBdo37-}Aa?7>IZ?>bZ(*%a@PfCG47f(I4y7z0eoybIi7gw(g9nPQqcqIql#FXpr2R!lyTCMtJSD?a?NaU)>Z3Nc~ya_KC@fIFSV6{)xy-y z(hIEbH!^nvXI+s)OPIt>QtgW|%7=B^{!zT)%AXG}YQBM#+HbW!qAw>C=d?$9fR+R?G)z|@Jo#YNSid~^B_6Tea1Y;jIQE`(OUnEgqJQ2LBjrvjv+?BaNQ^BO9^H(cEN32y*fg8(zK^^}K2XmR%)hSf3D`CTqj6{@g0$;bO zv>-Bycgc}wX#b0rbmU48tq!#4&V5<>Cyi^TB#*r( zdIGOSPmPw(lCFlB2@csbF$~YqF84VyKyQr;GdG?53~FNNgzo zrFx0fK?Yy0p?jHpAm$ehH(dKkB-zmOOpp=4H*G}vE-lVW+pm>_h#4M_f5W2*(lN(3 z5!yMk0gwTQg0L5-?8Uo1!a?UbZL=Y3k{5xpM5~EgJQ!jKmkvf69jAf3Vaa-tv*_g> z`vt(8_j->5G&db#iR1^VEW)0i$Hag0YhQJoxm^yYeGM{Mq0IlLsbRbYNW6jlRU=a=%*c(Np=Bng+Bu4<^bU&^>EvR8 zaXP+*5wbIevc-dc2W``3)4esi$F`;Cbfs8Vg%Yn=)0aC#t-OX$d?J{(Iiymt>?9T^ zOq0}*H>T$YxiI|5rg6NIWh}#`arAF0ZA&^kM@)GXu5}~sb1t)zPwK!ogkOTpoL__? z{S;@shNRe?DSoqq$|aa#3TC|UDh60TyS*^mYpp z2t$d>?EMjCBy_h5E>2< zZ`BWPj`$7?r}&&TZ_nH0{NDcv7;706Vrf#hJ=|>6Lx5f~JcRbLz?G90Gix_^bo}}n z+K$1-#x_`UFm2a*AUvRzen-q+4a6~Q`)-qQl6c%81-RS6zJ7h{O%B=BLnP;Zf>?s_Av2mc)uXxHN)L4(>a z55DDwhyHku$n4pHa_k|NwC;$5>CsELM#~_!cVY5p&({+k7{s;XFX zkD&YxRKSHJC5u&TRe=(7V5r2oG9$j7U9wTi7fF-zg@+>znm+X(-nzpZmPe!%@zkbu zAD8MRPMDSzHu<>-Sk@Z3iBn=vn+Q^Br}l=VE6p^?s%_PJuV-x?dPN`H9`i^J?A=$E z;r)eQQ5m;pj@Em3ov39=mJ^St&Bu+1ny{5%D?Y{`@Gls;%2kb}iSYLb7svy) ztYX0vhfgHeKTZ}Xt93sM>L-4nZ0Vosslr8o^yrW7bL%^NwPM+v@rQNb?$mo zE8m%F3!mRRo%guW_MNF|bZsw4Ex=AQfQ629=iM%H6Ve1_ar%2ZuFhVi&HiyX4pvs# zG~n6#(j|34n$#I$!87 z^7wI2LCrKx2XX!GJL*3~B-sT<{#>7D66O{WhFxcb*^(x@3fx7JK<)!r*2q2UX0mWe zag6U;(CZL-u=ukTD%`hiwK%%dfrH7Rc{JFt?@b7{qa=EEUW zeBBslL{5&Di%gFoOmtndcRu(}nNAUS6P33IjdFzL#IzQH9_5Tb4e;iN|{EHlY z%g0TcLty!eI`A@@C>6i-2Q?Ydty&R1kb&qhq2h@tdtviC~%g0ht`zXtu zWp$yzS;tDu6izK|o}qB>0~;(uqGl_;?}uzXxXZK*RPq*9)W;JSnoI3ub0p4&ulr=i zHH#Z!Akk*ap(XmbheE{gP~R+I$p0ik)kP>QuQmJEm?7d)4y--f-^D|s%N{=$&%vIi zDrq*Iepam?Jj(j-I5Xs(eknF@jyD%TnpxVe(?xa zlhIH@2mSzmpz!kiE_=pe3#^C4RfDrOt%n$yGf(1HIkzS#`@L4^QvhCjb8YRn1^FEX zTQFAit0{c;RaRXZ$bTzfh{%eG*+vyP{?ZfU=sci|8BiMO>wp=Q` zJl9i@6b!X-S%{_3mhYrteO{R9q^?VSo3SaGoE?xwb+`<_D!oXeZZ5A5zT`QxNIFHh zDZ`Q~U~j9r%2pA}nP1MTW0WO~qMsS5z7{ zy+MWV41VE6wBT+6@7{sHpC5PVzj{2HI-!IJ_7uui`Hyw+?*WhS24zist);U}mBhwt z;aGK^z$V;)WZVePZ~ua&X}eL3LOm4gmCDs?lm+v)7+2kUU32B2W}Bc=*B<2xCX3#9 zXy>&U2a|+il4y^hSz|>!`b71uZ#$i8VPrq``W7*0 z_Yl_3lMLF?p}d{Al%v4aPIh*d?4+R+fZ&1oX_~fBZZ5tGIvrP6U2|g`7QDG4Ti;?! zIh{m2fTBPJT)*F_UXq!jX5r<||K5wPcjh?`Tc9*$<|-U?x}E<{g{uK4Ba7`|T1?*Y z6eIK28^90RhvpTvS^YkVR)Y5h7Ri;vToPQ%b>OL8c|FBJF#wS98X^G*8iEG=hWfi7{CfFU zz;=!Qegy|Io1X{O><*bu+E62Php(nNNOp*;slp)pGPFdoOk}K3tK- zC2UwteHnT9JHL1o-ap@*SYONXP`__z$9&Eb>2x>|kVaz0pZRwfYJY{T4WE8=1NazN ztjQNkCyVy$rBlMqfnt;}|0T0q7v&|dsajJ;!Gvz+yeZH+|H%O5)%`f zoi%E-HA?-z!vikSe0-JM1++KfSz7h3zCWk$@8LBY`b=2g9veWth| zov)?7iDaE~XX{V6RxN+f(8_sF7jNTDrrW#lR;v(Ht(6qj;^xKC&`PzPq3?4M!TYnf zjpe~ufeBdG&D+F8>_9I11~SPYh7uvL|M%Pek_Cz4zxSt!iRS8Q4(Bx%v$FNbKIkgz z>qs!6B9lo*a&{mn(rmTD3MshWI?jz%*+L!iWf;7O@Azth%VN92n)bIQ=*zHh?5rH; z&V@*=^~kFt^|FF|(JM&D2uYBOnK^A+`1Empf3XLeZ}XRV9K6F|7vnIkGP!1#bgEd; zC9iMedr>)^*BJ~81cTA*dD??NGAo1LYn%>)w6MFr2dS_1Mb7@LLH-WrL^Pro@KQe< z@cBCIvq;N$IKpDJ9oKn6D5n%T2!9KqtH(!=vOlrN<$Y@GVAyP~F@G?bC1h>8;#XFF z96I@R-fB^u-hl7!&hl+xC)fK_(5wB=pC_xV+>Oq*@?#snT>%wg871LdhWa5|Rj*>J zQ*xSKP8OLQmbBka1-N5!x288GZDA(N1m3dYa6F|ula`C}IDc8*ejAN@*$hXj*HdQP zskw>L%{6A$;_4Ph&2UisdiWu>N=-=bJaz~ zCC9~y&3`>G6z7XA0Jh+Q$0g|UeY7F2E5_&A@iK=3xjbZd;{-^c!>syZcpPLg?AHFK z_Xz(Xq-x7xP-mRyCUU$2MK(spFi+TqxiZ6`L=K6lWsdn@Ohl+GsKdVH?k}J&qzoK@ zvrpKR`MdB7MR0fPl4%pq^;aZBicZyti+4$i)JZNL^Y+-GsI1 z_sB%)hy}+tj+na6yE9wyD+U5;0x1MM!bUn@hJXsVkN?Gio!4L}47wH7b{Tjnk7N6F z5^YP-4fUULZrIx&bN!nQJwWNidSC&|59}zq?`Dbh1A=@xkrTdV#?>4Y%9+`Z-EqQ| zIS=H*b*ms|E@v!qhi%{@2s+*62gOyoOUkyy#CB%Nwu4HcF%b$JGb2r%?ZL9g+mZEx zA2K&}WF8WYGHA_DKj1?%v85E#?ZK%&ZLQK*|3t#yyS7_*MHeAN)(p299}=)C)AICn zzqz_X$A(j7Ubj8q8Qc#Ctd2kGr?%^AYEGLTm>8_?W$J6(0Z-LZBqqGc@J**t)g^QJ z!c=f47Ee3yM>GER+|9{JD8yn;&e>WH0tBVnef)1b-+e?Y=c}WbZ3n4FKk!oPy3n|^ zkMtnI)E4L~C8ud#N@w2Qjlg&@RI}`9nY`>d$)cZ!@5gRG2H~}n)SEbUCK?Wg%4sq` z+O^HQb|z_5#uuaP2lD%Eat&}Z2QrS{+7>6_L^T&u>TBhe``Bl;VfCwEopR4%B-#hq1YX4!W-MPey@ z?)4DaLjqitU#e!@4Rr{_ndvK;<=;B}BLHt;)3}VJWxssuoPVI48S)$QbDMdS4!{D($em2!n*vP zMGe6dw^E?Pna1<)*o2H$&2w^baZed2a7E6^7-)BvkI=L4LiPN5*C7*8qo)2_L1y$QI&D^UV}|x zw}7G5)S&mX(VDH1igtsIpf!*j3F5dPOu-Zdd-LxDhxZ!d_mD;|G@Eh9q^RzCLITDe zLp-g1>ofa$L7o55z6CZueyAv{KXSufxlo<!`WDHa> zc?uC*l@sZ#LY%-Ex}5~L`ucg(y2nLi&y!i+K6Ca`UWZbjDc;m(MZRht6o)BXT$4$j z$E&8%>ozyq#c+4U`pv`F=L<+{zS}CD>8@-c%l)jnY`2zUYy zvq`x^X*^8ty?58w6nOC(V_ToaHsfa$84EW1<)N_aA}B>A#SB74MtCK}*y(eGM~nkf zeFS+9>ki*z7n}diul(!Pqc8)mudg?42se9h%=$1u*KjhI_z0E9J+Wm6+2S+j;fBJk z%Pd_j3&!8lj2TiS)i9%1GDr8hAf6_(hsuk~GFfuZ7iHUkp71+Wo7Ed^hsad1lPxSr zDQ4_?E4JJ8w7yep7KQ9Hq$T%%mxn8r(WrpN?SA4d{I`ssN;73jMiKf=a7?^_zZRB% zSi(QEg4$^I#fh%$_2t!~J4$I*MXI$%uk`fd#jT(msh}8~L5S@AcWe;^y24E`M3Whd zk55@o^&mF0a(s!Zl0gFfsU!ED8MHw4uoe?$0{q5Gwx@T_3jqheXZM?Qth8~ctIbNp z^1@}(^QGkl2;lf@x0xQNLV_m`r++HM9MkPPIoNOfKyff4!@DaUQKLDC%ULkQEr!&g zbDWAL_BG1N^|5y4?))`Q^TbGV6|T#;rYe_veb#hOZ{HX^2(R%eSBOJG4FqRlGIDD^ z;ol$>kq~BbLJ@4{^6Yy^=qm+0jg@r_WvnZ8LT42m>Mf=Rv-CMq?kJM0mRD&0Fk4Z` zz@ps{YnlN_!6*L33v>JrQ=;m{1Z)X2E(;eSj-{?r*tafrjfztv{TPYsnbEBAA8+fs z;cyX7cz3ejFX7t6#_IrvEl7JcOUB2Jg%4{3tvCU#%@mM=Tiii*=pxz!F!V!Wze{(j zy7xb_pRNBz!a@q&L~NC)%^GF@(NEsP;%pNm`Z%YW$C=yIu|eg1GdO=)t|U+}yMSAHhE0>%p`DuR*Tujz}+gy)6Z z+LH$7<|!GriXyJ^I+o^MLP3SHw^@7hYG!XXU5vQ7(R4xFsr$~hIU)<#y^R>3uIBBo z#@N@5?v#+&h*1VSZ+i`0VpJSI|M~VVKh*HFs}Olqov|wBuGCBxRua77hz9ZG`3wp2 zf->d$#Ux6Blo%m8ZK@9+qYWQ;^LA+{=%+1lbsncpZWKaoT|Xk-#^e)|mrmY2S~J|< z(P3VHyDTs+_!P+{#s${>c@s)RzX35*n>eT-weG0u|9v_K)o_y<#htHCQ!v19wPMo- z1W5qHykB!oUXbU64pntP>~8?A)DgJ*o`~);tEUoO{QfVzw|v+8bp6XVdG~^d;m&m7 zaku>#@VXazx9fSrT=5KTQVfvh5c$F@?O!zsol#UkMZRb}vp6EP0Pp*xSZ`}*{_dW? z!*sm}@-Xydx0+RL9CoDFg8OtHzt)js^L%**t&IfR4OByBf?GO%&@lFrD$AWRdJtDe z)(Auo$pJg1MYYoTj_P^V*N>@vmDIG7J(+y+F{Al+R4VPp!7%Ph2PcXOU{!L=xHU(k z_r&Fw5vS$SOBXxP6xpcv>vpw%{U}O2JL~usZ-FVvR+czN^tUeaRQvTil4jfjEsIuB zMAd1JCEkTZLmha_p)DbCQV-^regV@p&Nbn4s$h$^<^EW z^+2iDc;-awA>nbKqERDfPg7Dp)W!*en4#NYQ>ek+5EDeZt%T+#?&tvKUkN{(fh4Qc zqFNjywsKOhGhKi^e4D}hGSc%5oYGG_Lhf8GDvV*D^#_7Ot2aJ}&AO7WiY)BzJ;fKa zoysC}Lg)WpKY6fPKQcKlN;VuTyYJmB@`!ji$mI z;?C7$^Ge(fK?0S zP=58sf>5JM>o_dIG@c}2RmB@}tOeLYpB?>?xklc=p~tiLUq>n!?lGMW9o8r#`fslK ziqH0fcM3k{8b_glJzYR$yqC$bq|(n)91tN036{sptiKy@J|FMb}v731x$`>1q zFDXF214%^13|L+c+c@Pt7R9+cD!&wmHtZ*zvZqoNZbnt#wJ5u#UpqrGw$u zKj`YCT(6@jSFT)XNW;NvJ^)X%c-n=IN23BgM>J|!IM`a;g0&t(YKLKAEZEy1H8gW- zRtp|X&LyD46g(8-Ph5H~P0TEvs+j+D;N^4ww3GkybAP1K$Ihb^wTATW_8>fPzSRwd zJ_KE#P`A)8->TN}gFH z6v@Z^ATufh<|Qq|O5zP_P2MXAgVK8ab@K}B@lBi|hMOZc{GPD?fg)r6O(NG)eF>M? zN>Y&hGOh~ua`R`anE=4+BJrSiwQ@$Spx5-Bou~$&83oqgo2uJ((YO=Y5xH1M#rJTS zr!aS3@~r~g{jZ5dy3(-?14jri4MX*iaUwB&Sy*wD{P*SLs)2fNGLsqFPJ=OxGei^v zI0Z!VE7oK|=t>L32YY_+w2Q zxmo|#cgXg6w8?E2WQVex(L!c-@Ts=peXDJ=UE_t)@8x|IX@^X1CqgBK4jR3d!o1o} zbxlAM3c+!yg;ZL3cz1?G*loF)5(g(%XJl|8;CyO zw00@?51|?*9z*IZCnhh51`G6^i`%?|Auq^ctobGed2Ci;_qipjvRe!AH@U0$f<(n_ z?GISKF1FKgZ*C2L=e*mLqU#}3Y)Tt4S7v3KG^9+tarN?|#1dpOaVcCXp1l;EsoFBb%udwsLO2$G18JtvaFnOMVYZCi|Mxo(|G0pt{&pWYEQzm2>{6 zKVckfYCl5TPLcMGBgOi%d4=|&XG}{xK96D)z@iI|=9IG{lRB8ZSu)BqhjWD9ZWgPR z1mDSX>&j+|3$1xO!rvwTn(Cfju`wwS88oL)#^U@*lzsn zS~WOnRyH%5NXchl+Twx)_c}ADHt)SO+70lqa6wpx0%Nua{=*EYcr4+n2^u`khup`r7d8lY9s3!VVyKI?o;!90S+?Hw z!C+rMrj2w@$2$j+^W+jFGbIc3)vJ@x$5t%Hd*s4a4dP7w!Y!xYxvyS5*?xQgS%cHs zFVSkL(zSf$moT<{2>F8NcxRmh~? z+Gt1Y7eUhvGlveI85fc4jGIEwQw$9^@=UxwxG97ejE<>tQ}#*vp{4dP?yr#XM|6== z%Xiq+nP2gi!s>ero(_8`uQaqS+L0@RfIYhX=>Y}Yk$y)S2_!-iFrs2Gm)lxBv=vaX zg!~(^V4XxM_A5!AZj+v~kRL(HBgs2d58a-N`@%=cl znadXU<4U<6%aDN2wND?g`d|3{(zYGyVH{V55MkZQ(5KuqrJb?VM(DFm^5?Cm0M!b3 zud=@(aIoADi>kj|_ci@|V4&n--$F0niF<}c9g@o#5wP0D-*1IV`R~6H%tiq(qosjY zcbgyQ^MS7&)9~~^7ifG$9j>%><#c4l2Fm2Gc_<{iPt~tt-p$xkNVdqkPZ9i44H#a6IfajL3LTSX;dF zR9y0uWvxg}c~Jzvh?+P&B)37O0j@phQHQxBt?!e*96P|vF+UQ3e0Zb9e1B->S-g@k-PCj@f7wc z$YNrJh~pTt$%bi#$ZU2eG9L%M3z*_%?Je*WMANo4)s@p=ss2{Qak!Bk1s+qqpb92v zECra0U7)r`+-lY|;$u=52gZLLfr#EEUGD5_b%obLOH9W<#R_kvMWgJ~fK9x+6N&TJ zbn!qQmZ<)w5Kn4hp`g9&Hk28j%evIaj)a5&><%^yIPY-p676T+^-@#Anx;iUqsi)D zJ1A05waR!n4PA7j|j-g3A* z->XRCgtyq4ZZyQH;+Cc>J|==$r&YAE+MYDH)eJaizG%-8eCtS2vikIK`cOj7)CyP;1;PklUzFyEFzc^?X_CzngN49m}TvZ7}W1eVcA5#Ko(iDrx(@jN%Q_ za~$voRUjL>smFzM3pAoH?u1>%rS-08a1T?~8YMkHRomn^aSKT5GL1wY_&=>RmHS@# z-Nz$i0!5&H2@1Ra^rmQrVHTbJ{HJ3F3j|+}nblkoCW6X7wYJd}M%??f$hwY{nq4E} zbmuTwi!pr78!xL|*d{XLiebkWJ=U3{G~_0y{ua;05@H+;%Rla-#UuD_TU*nFIGcKm zRbv)@@_wX?-pEH$G0I>&qZeH=bXXjljzzV8!1luCOy4%_y*Ya{zHX7OinJanRPaaB z4sOnF5%shr_voSB$QJ@`PVG|4Go{twxc7GYS1ZnfY+}x3LTN63X4d^Mn!sK7{U>r$ z3snnpzHjb>vewrgU%n`Yw+DX5j{WicOKORtWD6yDW(^>2lY*Lo7i3*kJYB3{#P1Mb znTio@0yPw3SK%qoXFJCm!DyWVPKo5P0049Z(|9M@_5T34!a@DK-0MW1} zI=UGoXTQX0n^OBTI9M*< zw5l#VA{m;E&YO?tVx4GEpQ zDi{IgaO`zn@ow8w-&sAV!S=YDV(jUV@SXl}nu3NE>&#R=x z(Ifl^E)0F~L6nFlKZ5PtG5p6atQ%omkq+WpvyoXPRXd%mD%R8#eNW|2q$*3ew^nf-rM?8uH)3CeR-f4$(cQddYX^Tg0wvBi;<`pLe)j zv&6kW8Ki&ta6%3Hz^eijQ|H~B73?_XTo7(0WqTwIe-@V`#GVw!a=9Z+8VNc*xJHGJ z3EjGelQWheeH9i?_a@B@@6(T29i0rz$v(%?g2yt)PL)vj_l+h&IlK7T`Eg-G3$j=Q zQHcVpO59!D4Gr_4mf!cU9EI|=yF0&IE8rZk*1K%cAK}y7u?RiMZAH8#GI)^N_2M~! z{qx6cY;rgfx1C7SePtyJ6koqawwqMpRzxRWJuF>Y`^N-p0Z!Cv0!a>6q4BEl3RO+XOJ1ENz4ixw>ER5kgs7b88lCZpqVqI~5G% z*j{q2J4y)^lPf5j2FUQH?QNvaWwQ}*JpP&(xt$RFijH2yM0(&EWO_qFZ5$WoTf_8- z7-Y)8OvFWbe13g1>Fq^T9(=lV>u2lgz*m0Xb#&q;F*Iwff885$^y{4U-zO*GX4L))-j$rQi(^EhkPnqhpSslF(nU{;5O=fW`)BL5;TZlD6^m=&y&_q+{4x@ zrEe)F$auu>!{ApsB@bR<^)vgCR%Xfe7=UQAqdnQ^X#KNnkq$dYT%+lza?Rid$V-DICFB;)Sh^CnvA{Z;25 zkUnK7>epB@AGfYNR3ZYP`qnYR3Y zfK?m;uc!bZ_X|8lVCQGR?d6x6+O>+SMtG>%>#_@RDD_Pv1CRZ$o5e8w(Jhygl7Z{< zP55n-Jt>${YEi)&j!AspMma&ACY%`pZZO+VbzK5J9fFX&OI^L{$cKeBfhI+(Vq`(S zP-!Q-Mbj|HHB-8Ftr-Fq*wB}PEx#FkX9xA$>ks$Ivul4WQ~{mVsonrLj*ZhB{#+B| z(s>({0ghPNsK7Tm^4B-7EFFLw@1U0rTEK)QkaY*4Gbo?woti1F?a-Ln5S1D6@otB6 zvOkDqde|4fV-GB1bB}hb`4+PQjw{4J+rUIP*LstOIGM9pVkA=+zS3th`xN^tuuTJ? zmzUKp(5UtYmqT2VAE4_2dXJ4YtL<`OU^knzRh!zUy|epmliWtf$6a@ewC@>q?J6rj`a59n>HC4L&+J8qp291$w86DRM%Z1lmsn4_-FozG;{S$@;0Y(p7mGqCH9w3-sqWUQT{p8X- z$iO6~daj@}^S*u~1eOxoRXYS_z;B7iERKyqt0nt4s-1!4V4Yp&d$I6;<$y;GKi*<%ix7LJ30x-3TZ*>q7H-q6Q!Y_^wF1? z6#+8y^l{FmYBGlVxD-^8=h(&SF!L}tB*~?#e1Fu_z4sQMw9&LW{U)HPY%4l{2Q;wt zUdzTlqF4UU|GIc!$9Bj$X3JvMmD+pI$v(#IX_AEa9oSIFhWYLJ=0KY%^(s*^!Q?k4q~1dxMyMp#`W6F5 z`HUij5wq+oqa1Hya)=4c9fU%NJ;x*3Wfr&x&~FcxJ-`yh>}zvLFuKn+DO}wk{G|-# z+f4HE2YxVWON4pYMMSEjHe#j zzzV!}szE}m0r%aaH|s$an)zVytZv}m5?3KN?peaYMue$s_R#zxY1XG_UvWkw(q_uYO1E%ivkyz)=y0d6}_eV8K&hmJxme!goc*$sHtNnw^q?3*_#@bZty z0O#rcV&iR!r*K;QX6oZ0V9WC+B|d(ZaG>v_b?nl-E)A~DG0>;u=I&&yX^frUGT|o< zopSG1Fb6MH3a#&@9g&@>tAYon)mShuQJ#xFysq6^2za)7$k72y9R+oyNhaL5#14o_ z>pstm)*5n%yfUQOJ&IJK7DT1BqZ6@9@0It}-`314Uu?kVb+Ub5mp(SmX*pwC8)*NAcZw&u2*w7KDJ=J8s>hPu%WnL)R|S!q=A%Jx#3!zbt2fa zGtv=TPu}HvZ?C_RX%7Aa@( z0-gUt3oj>X5XyXS?lNpQos34bX*^>|VuV4*Vs|T~zHrb)X5cG$ z6xILm;C_8q>dV;Pmabbx*@O9l*4ouX?Yuc_+9z3jR&3P=)+of3GD zQAhd}I2yKC8fJNzAgtUppnDtVnK2~?_^rtcWz^?oSR3dV5+ahX^{)FowhJTM40NNf+4_Dg?stsy5GmLe*X;H!dR zv+kl8ER$R15eDg^Nkxg}=m%M~y6gNknu?_w8TW;B+! zHn}G~crx1qKj5dA#K|G|Aj z?6n5~>vIt(v{b03-tF-oO``F(M>}Zv78e)n)hGxmr^Rft^>x?3iB8?83cdm*u3sEO zo)8W4V2#D8G=}=4NSUJwqqnKR%OwuP%$=4 z8(>CJuKBvXP#C^dWY?*?Plp8a*nj+q4QGL|WBDzoPpvvtU@LmSX8_Ns*y0u;48Drw zLu|wzHuzOnK2Lb4`z|kII^LBBr73Fed-oFlph4&5vqphN>McjT4XrF zxwwlEz)2QD!sTYGXZ?KvR~Wn?&&;UjL4@V3ckya;1#8dWhBv5<-G>;57&ntyShs{0 z^oR7V#QG%Deg^Zk(WiKy8_6uhT(J7;duf$Vi!leK#YZFbZfa`rG*={|8bY4I&tx@~ zna7k6Ea5I-0sv><`{`g7(tsBB`blRwxCRmyg&{mElcJ)}TQ4$b~g!mBAvpU#^{k z+(H(8c*+(l-0Vr8zV@Fp0dj5qjlfp#z%$k)gTgXZxBa~^7=y^^eJU$OjiX> z5qy&}lpXU7p8n=%2&UDi=Y_enO3R{F$_exMGsM;*#S89zCvGIir{CZ0Sp(FZ3(CrN ztb#@APK^6b6m))u9F-8cdGMg}<#KQ+BFvZt>CIv~i?};5s`fhrA)^4KL2{A zV<7)G+y%5-cl1BF}q_K z=?C>&L?r|}Yb54AM-N|6ejQz)=1>lcC?*I67ySawm1vw!d2woS>P@moE&<-C43U{8&)E_#`Cf&Eo6M2q zo!U1%t-ikP&y|*o5(nms0k99|?J3A%FqmC=QX`+X1sosHL&ixzLzS>ZaWY? zM!S6FxJeE8Td(8X=Q5)@n;Up~dHnz?18dd|R{9<;&OT8LQ8CeQiu34>$<7X)Hz)or&?^1|}Cm;iDK* z9F#xFSH1h!`ec#~2+Z5gjJ@)VvC?gfYwPs2_^?6`&$YH`qju*gVLW=YXP@eRXhEer z)$Xjy`nox3?BZK&@(pv$wLwBYef+k(hZB>I{9;7hca`mfX2S7y=68~i&0N;w<}&+t z7~`T`W@ViN_j`|uxOkT=iDGn^@?zsu(+Q-D3b?nXMB?=~E{TMr(dJ6xgewpiDptTb zuWfN9Oc(bF+YY1P`A#5}{!7N`fqf{`{9$!|qs03aJWvb?1aHN#Vy;_;#EwBW!>RwA zDf_sT)JyUEiFr^b%1wI`CeaA@;V%soleND>)0d`HO2i{xXg6f^}XKOYId?H zMp6=y8D}qpo2gm9V?j!^8wIgEKOD71QuD8Jp^<1{tOc_}WtMu!kub@Zk#qUWH!270 zfHd~288Hgc{V@n^O99KIVf7bD>wW_)yG|mIv5ZJX$w*aN8lT zVYZ}Gy-4(_tef5$mv1cm>+>oP9|JbERE}B(we4heW!VlJOB3+RakCP7GwES?<>h0Y zqvP0VvIx6YsqE6*EYk>RH4#v1?@<_^Z;3`7eM2}KpZmvxRF*Zvk}Ne(N~^#`%_$>L ztV%HiTY7Y+CQ;l!j@L3UC5}ni)r?hL0n9+O8CE4ZGe_?IzG+xmba_v_06+NI)MLmS zFJ)1yq|Gm>P>mCh;CG3+sYsH|MF83$C=PDn+|Am&hv{g6nYIaGgkUt6Baj_J)gA~y z+s>*8ZdO+*Z3d(q!P*7&CBo_pABFO|9x}W!f;<1Or~r$7z02*1;#X%k{q-??ZB{Xr zci6wquN;5}Kml7MW(|7`$tsKvJzYmPqw@!!7?JL@bWm08r5o-U8TN<+Zq**CUi8kycRT`RPCddiLE4f(1uG%xIh&;$I+?K;fZ>CC8| z3}|U5W)s@3K4p_d5>obKL+7)QzeDQ1pO_N{r1mohVmXVdkrBb zxao^tuGPHf)cg>ogL;)%RAYEf2MMqy(7FD9qN)s$633z6x@v2gU^jix67-J0A)r8{ z_ru7W-gPp*$A8Rd-DNB6SK_l-kKYB&oRG0P`jIs5$P?2j%lh>}q7oamT)`BB&q36zggBp58VudmNX zInK5fgn2QRuMS>X%g(+gfYFNqnN=6wgTW-{Exk*@TA$d01DCnpt6mH0E9*MTBY*{V zb`H%m@rja@9vqGbYtI$>O2*h#b{BYqAyUynA43$DEI!^#Q$`s)zJDrq{Rqf%LC<)y zyK~h@l_o5a|1dj{002L!A{wT`pK~%ubf}@Nq z*ng!eR>9JnpoGA>%DN>pfseU{{XbB-i!v`OKIVv010y$R?V}WnmK~#p5UrBEVoO?l zg+Yr#BAI;-HI%v^HDlg8F^VJu8Z^#Tq8QYn?U+Z8_HxFe-v6 zoNpZ#u>ZaYceYFH=@vyhG!dW#yCk#afiqdGX@mIqBS{0$fNrc=swj&JifS+Ngp37XvP%iKpx ziAgMtJ~|iTpJvlevs3-Rs#TCdkC?WUB2UgWp(_5_XUAiRo_YqnL3retL3_e7zbh?6 zePPMutdhOqbRMhvklb&05xei5xdnstGd8)2=ej8THdP2Xq(aEdHDK$*Gv(Im%lA2Y`7;rgjCSj(PS71`p z&RsAv1651^b_Y>CN%5K?f)`eE`VX3(y|gSP2pBW-3-eqBV}_aGwu1dt9y+nBEE9{PvDF6%g0k(5NT|c>L){<;`_K{`^CGz( z|1AQgbKWl<>39Zv^*oapZ5#=mO&wKqWPhd;!((~9BhJ(t5#V;IS{3w}?@&VR>0cKE zWwP3{hzx%d6q5~+T4RI4DuxRl)UO~nF#~VKTutq0(*44x1aBJ2b?51AwpOFN8bnzL znQYk^_s%Llp|u}3gcQ$IOjL~Aa;es}p{@r>zhW!K>W*j17N$NAQUD-8dNC99MuNwr zRSx8vrrCvugw#|Xo3e=_#4vF z-y=%JmMO&Jwah(wt?rZT@1xd4&;o?22E)!^1}f{y)d;2TM>t z?AtNO;2yw3^x1G$LY?OYHGrY@iC%gnOF%2w;OEOIX7VX}mO_YgN;t!Jsd15yB zz}pF^2hS9(?f!OCe(ag<7m492)8}72x%vZkiTEg@rMAM^TU)jYxFmGEgmz{72a6tM zcd1&O9h!)P6-H~lRB%d5MajwXH1I)EZ&=-4rag%pVbR^^ z$&Owx=!NK@!Z;?%HGc-;1O2w)RNy;S+Z<);t)wP_R)nE?qelC&D9wY^&^bRrS{3MI z0>2^ZPY(_J$@IqrG}G{VJ+tNR{n09rA_j+39v&dYqu;X1T(jEs{=V2`4N9arX5@z@ z@!5;ASa0dRn}Z#Jg<&$7Lx+BA4(PL`tkTufCP!>L-c=*Nw^o>H)P?)scZSiPw%Nn=0sAgf!fs6pVTc^Y>HAl&EnQh~o%bWgAl~@+i2lC~`MC3AMP@$CC zsg>eFh$h$2bdDv@tT=Dqf1n{OHEgmpI>*RGn<4??icsn#kR z%gKI2!DLX=ttyvvTgEGIBs0);!;NG<&PXG893V-Tg(ANHxw5||=fn5DHj z_c;->AGxoLS_1_?et{>P+c?umW&tlqf1A zBjL+i7SN9Xe*?4L;g{~2Eo7+)Vr+l~JFowdm$X2MPiQE}#ax`6x(im>$YYLnu$tur zcs+vx|pBnU`Q`q?7uQOF8)pKNYqk5QZTm+Q}@yt~6Y){IRKQf3M9#X~i zt|=JB*9zF<&Q+$lloHiQ%*N(sNQi0@tAAXy(|+%%L*;V}tQP~VrO)!bb2~n@!UCyp zndqF?ZSDFM9p1O!g+b%NnI`@gTXQ7`^2@UzKHzu$kPRM}9<~d&gL5`-K7?$I;;MXg zVXG;oFQZfm4Zxe?f8?1=R-qVA@wMl}Ug6Kc&%{5*ZCK@}H^p%SI${%w`>65t^xv3sb!_&z`tfpesMYr|y0^^} zmt+x?|9JWFu>~dec==A!n+<%0R=9d6sdXk~ZbxLk+Ug8F)Ga`h?lVDzGUp%Loh|$6 zQY|)jt(tewx|3I(_*5aIvC|eOFjB9nqut)GPIP5PVaG9WjaT{eSCoDf(u)gTROJqb zkmR7k&BlF{FFIw2JFARIUiGyNk7yE%x8xpHUcLtT&*aej^PyL?Fq%O_i;`%#5!$DR z7xu>T742AOk6S1xlVEsV$L?@B1zzRL^$Y|3pXzD@`m5S%YB%OnOGHnrx~6jl({e7? z7o$Ia0&=cnsa^BJPK{o#rIgu~k20xd4870o*QRehCWP`IH*O~5T*wjR<$X;XTWkO3 zybmATPFM3nk?m2R6~a)a_6;Dxd@wO==v?pr-$Yg#G`%SBb~rem&Nz7Of2_(Ps<-|k z=+d7Y+tqb*VUxiOppS$zQb0`nepl!{a{b1ccEp@f3yiZegRVMxG`tb>n#Br~oSkJ1 zg%}140E6_h*>9dwl99SGQ+q%b*Q&-8Mto(3&b8G3nKU`Ldwu<;G%;s#8~}EP!MEoQ z{}l0l%OBiy8joS-jy|TshMn=Q>9C4cH~SyKw)bBIuw*{^lmL ziXo2kexTCn^Gr{C=QVt&-RUUJZf@4gN8Ed>-h28ljA=*!&1@lpoT{O&{wpK&+iXR8 zwuHFYTq5|k{E0}__s8V?&&_Dg@lVU4{qgCbW}RkX!l}ca+-DPa@8<_>n=JWpBn@mi z+Uhb$gJF?^mSNFHj_$~MwRH_Zka1Ng4mDkk)4;f3OQ{&)R!q%xw}^<79b1LB(v2TS zMmAlwBrOd!VO)-v;Wf5vmtY9Kjard_S%Q=j{Mf&M58HSST2Rl~Dqbo>3iKjx-JK?u z5nu5yv#9ZZO*t-{s@oJ!M?B@3IsXXSFjAD&u#k-6z6{tFduzPNNBebM@hrS!Hl3*Q zXVG>L@`e5+G!*U#3&#PeCc)A|QZ$U;Qc$k9i&>!xhjpI@E|3h=i;YlXMv z-p`MGv$yxa_jgZ3V>Ng?>Qd(PUeY!g62T9Mf8a5d8C~B4kbRx}5;yZ6PhC{(6Tg`i z-W)m5Y;QPw`gM`rySNXt7fD}4Ecll*qOZ%_&n$2RiIN{?vud-pN4&}ykui|Lzp=ov z#x3&U`VUU}-%5`{#F~(9Sp#TWz=b6i_nJX!UDgW#C2M1#{R4MpCRI0vjQTfCsuVe5 zP>1H9wsRzE5)=8}d^gVMY4;&{m1H&Isac)@S$3E*A7nJ`O_8H5L$&wf+IG+j;~O}@ z3yrY=-jf!)_dAFm+E_<`-6?c!1hn)GbKNL6gDOTG$NR4sHiNgjZ`c03#3|veM}GM4 z7NZLVjYBG^o~D(hhYxOB(ZD8KRYgVgauJK6Xb{F!* z<>ZHl2jnaros-Z;HIOEDQ~SmDw(`tn;xkV?i?MpNGszrJ!aSJlSdx15i%QyiJeu}u zw;x3o&D)^WZa9ND1Z=qu3TGthe{ic~*h(N#CTBNu zr_`aY1ANK05s~oYZX!?0f$XAWj?6&|*5!Js3kzVJ&uLRz7$Q;kEhYW=bk zd|MR?TE??P7Wm=qXP7ju(UFYfalN8;UHzv8Fk}2R1#Tt|JMsD`6c|eL zMW9)`TekiCWH{>6U7GM{99n11SlpIyu05JP~|Kr~-lL61*586Bt2r z-1}o*^*=`gW%0c)ANfvii=I_MsJ-5fN8%%(IE`W=JQZ*v>!-3?^yaWjD`f9phDT$F z1mw{oM)yGkMIt<8r++2rG35))!z{sMk(^sFa9AuL@T=E1aEP7Oh{!>AV^NaJ&}gE7 zA`R)qy?EP_5zD|^8W?L-m3jCIPQ$#xgNkpm?O^JkG@$X}xCuJWvp&-c3O!zf;?r|J znt!`@DSzpxw}fO)eRgDX=k=vTQt&1Mc)SM@JSQy9DYOwi@w5W zvvbI?@q;8o^MW~c^jc@Chb2(di2BtknO1gXub#*O6UkE4U)_bx|qb&@2ToyT&#jTG1Ij=I}@a^R0II*svxXrHtQP;Gu z3XxwGmoN%L*Lp4FQS$e!ZyYDk?T1TC^SvL7+I`)2AYl022xD6Qk(=*@d#H%UeZiaKv-0^0#iT{Ku~> z4LqgjI)Sg)dnn2gA=4u$Dmv$fhh!NJ@-ziYBmU|YdOE2ua*QP;mC;ziYQMXz+x0U* z$NVW5cV4wI++3mg#1YwXR$+tSsFP_)PAhij!(Kz5)RPcYBCg1&7$+vYbM6n9#t=U` z(2c@tyyEq$)KjwkV3`q#VhkqiYdv%jTi$rIZT@St0xX{MGVlHL2=ts^%iG&MftIP> zTPfoZDuJdCd|EHpof(~1{V(vHqJ98AZ7=e70BpGUmvKd^rE&EM6J z-VS?qr+SoxVKR)c%PVTR&OOV|iS9915dv1(;C`r4(k=urg(@MdR3pIQ!;*p1BKgFN8u6tGMIc2( zuU<6cIztwHlRKjb=NUM}JQV5`Dn*SPSK@gWZPY~}2#kO8Ox0_xgBXS~{EQ1gQZMg; zVG#xBHjufWwrvvlaTcoy0*RfDN~ToU7M*%g--7_1yp4j`|G>|b0=sdVE{lsfrS^Xo zz3_hJvBz!?_(bmhT^FAA;yyEQck)aRLf1vcU+a1ETdKNy;^w;=u+dd#z)56+)+C18 z{J`3596Gjd(p(_9W+_C`h@ip z-OvatI_CIyDy`!FCrd2)ad}PE!cAM;qKWi#1VCw9!HWMf`7(4D8^>1|YGKc=;=#aCTCKOS07-1v&8R@_Hy#W063f8%}5(c~w4ht-nu%f)ew zLgGlzCY1Z#WtHL;YC(!Ak3TK`5p0s>GKQGft;esf5cu4?^Gt0vQ8bGsS_HmEkLN2h z^W=NVcr1iIFlwxmf=3{F20VKA1(KB&|HtR8O!)QOK7Ov}Urc_iKlXkaygLo~_c>ku zX?P@~5tp5M#Ove5@wug+E>W&+Cuc?;*JD_P$O+UD+LSqLJmvn1yjJN`!OXTcR-??m zL?3E#L_835Yzhgz18;iGow8ewc;(|C930H_PztIX=RKvMq&Bc6mQksyadriwHkbR5 zg~_4*Ug~@^>BdRH7N6JjD8h9GNn{D@N9vr;Wxog9z8kkG1rG3@3lzFPPqJ1Ezb)!n z2IdP{l6csdDfQ}9-ajTiuL0{&l?QTbfD^(SgrUzGPDg%%n%w8Hsx?z}{X0k*s?;wp zO&Y6p!cyV<;NG_e8s`YMe{SC&XOWcC&%*Dtd4>kN20MXPpn{BHTJ18@?u!&YFnGFV6QIxO)m{aZ37s2|F!tt21Se}iF~?)PM3~sL@v)h=5fX% zQICYPT-f>5)tX=QQ1pIwU4K#tlN2X6!Z8eWS<3i|dmgCN%sw&_`ROJ@q0QMc$=)B^ zU^%@sci(w^k0v2j=^u=XBh=*#@;rz9kmn_){7*!~DPULl1AqGh(AyYT`vsf{C|{?( z!NC^H1xDj76I~_jOFunLBMb%N7l^kx&7)%yfY)tj+cR} zg>tY<`pQbX9?Jm1jT0v#_jaH6ToX?0a;G-c5Yj3=Ae_63%f_36qNH)ucYw3deatB* zJJ_4faD9m_e7yKL_ryp;=NaSUlQ6%b9CQS)t{Q}LKwR{Bt4|I3K@rG+gMv3^0H#@lsl;pR2J5JsHlreJ zr{1MLXr?(PX|$kP#MiY4uV{1CdfcjVLwZ)94lVIkl{$R3lCp%yl*p82gZwAUe zH@Ia2p27iw?qPa`w7wjy{68R~X{llcS4DKXCy$7A9yRby;_C?nl2dmXY>oZ*S4+oD zz4jC9)R48s2p~S)YKWFQr*bT}@|!!CTw%j(PiJec;cw?nP37_8-x6Ct!uZPIIoXFQ zXQ*t6ylId_fb@Fuld!ddOP~!`_D=_oPZ#r8sG{~cj|nJOEkldSGOhd9OEq+)l^-2RA5OBNE*M|xJjRV{{{@{ELImfE%`7+v;7)uk& zeS93&>U<{{*(PIST5Ju2R%F$s99ba87RxP$a;CY=7rafzs&HZWId||DRNXjlgmXEs zK9z6k&-f%GRN5qb(V1{mJJKbvD831}Tu^s%_prTMe&_HrBJ4Tzkw3dy z*d7_UJJ->+%6%Y4+Uelac6HiJ>QTM5ZQS-VH(1%`_n|pw*5l?orQ>hxDQjhV{L#zZ zOFV9D0%hl5QM}z1ueWSP0?IP5Wa2*eWc@~46PNAIwA@^!+WU;K?-p?-;cF1EK!TJf zcJ|Yjb}UWJ%vf;GpkK*NCIP#SAWiWm2tEiPVoRXbMY$V`XRUJ?h;h;SR@C8RdMGP! zE14Wdfx}Rn_g!R!J>J1FoV2Ql$9J*z-<)dg<+|z&Hz|1e@2$2vm5UJ-BjvAW=%EX? z6g+k*6@U*}PX*Au(O*KcJE@u=E`E(bKBDE>`vfYn-J@rG$pcRBIRv8%UNzxC*zK423hF5yc|*iVt8uU%bXf z7RX?{&iuRlEd(qs5TBunm!E&&_G>oiL_2t<(e7WxmK^QCS^qBl5N~-`JtkTeq~`!m z7(vsJ{da_BCG2o*7UvXe<%K^Qg~0mvn*!%I{wAd1Z|eyzT7~O3h7>yJFm*TxE+l~$ zwc5Q&T({d1@6R@-A?bti%+oonfzBRZH(P?=-$P)SG+x1l-*R7rKGl?@zjWAEON}{$-7g(+SYdMn`o*0)8HDo7X-JRLZ=|wJ4~qj`~;jO9}RO z{AW+@gNLdC3$;hyW$IU$Z=W7vt338KGhu_^5#L{s(JKSp+=|HcTWm}XR`e$_2Mn^djL2u+Zikq+f*Q+b638{i z>|>m;SZ>1wpP*{@{%eDBrCtD|!=jORS#y6SDiL{FozKrlwPjfDJ>pXkiZYZmzbqFE z1@y8G`Y$s7fV0QAR2s}zSB0PPp*V$TBjdjZ{hM9}Cg?M?+0v88@=Uc4>F0&q?_}J+ z`tv~0ca=G|Pp)F%%q`9S-55(_dBer1%f>gR&w9VOC>S`F=F>~$KWt11`ttqTp55_H z3&8u>b&@oD%s%IV;GaC7^_m*QFSH+=oHW+Ya0h?CTKteLk#;boQ`Vy{9Y(VV6Jec% z&r8>4=YbDPh4#^o)dt}Y?=geMGwZev9K>cx*z`N_Tw^)pUAgLhZxlwF{jR`$Q!r_A zfrWLIx}F2PAKI3bM&YQZ7AC+(eXePv1EA#H_I{TG=e)f$^ueyF6xDE}* zWsuXkVt@pAzoc1v97NIBs}>gZVfjn@S7K6H8|q^faPx16L!IjG1nM+O^eKB#@Uebz zIye8>>GtDU9|MMQ+2UO0JsV<6-;%ZBV>|p0Em#6)IBZQo>;Dg&<$<72VQz)q8!P`# zVa2cHk=u>Q;Qe{7FYUMb{VrxCJ%D!}s+$-RNP=-vQu}L?C+WPWYt!->7RlJUlv+<> z4378#&W{wKgHfXsbuN)aq})o`;FjC$J?6^CbtRmlEJnJPfAAzM>|9%kJ^57s+4`5X zlh~R5VP_*j^BKCjWnKbZt|h-NF3qd`QWD>-*OK)#oGofj971Lr zM-B5rg@1jNnzJ(;jZzDAj5%Sapkm0lY+a~7(a8PU<)yn{$0fm>W`(QW(r(N8;O4jH z?irb3>D2D;FIz{sNg^#N8|OB;O@duP97c02#j|f)pSMDQR#PAFrU@OvlEX3I`-mjN)Dpus3vfq*dLtT8FSlIy27VRr z^88kM4tN;V67eqa)u5APXM-)xQXvXQ47!qfAC z$S`13w7i?N8iCIv8$b0sG+zCh@9vM0h@@bw6T!Syn1sIjB?8JW>+l1LN7c!rU-`EoaG*-xdP_Bb2M5est;}pqxffZAzM9%%S*@o6 zE(}EY0rp~&l6cv)^ckme;hicGmHi0RFaglo3g%vfLM)1%bNF@iFsdv+@bkUQ2pS@P z?nHMs$ot^SQ8AK-I+3MJS+Ie=*$HfJXr*^62?w;CbT|!VDF+*Kaw|MXc1{w3wY4ym zYFj<5Z!Id4c470yfN!vb@xJ&k8GS#+ii^(DHD~Vy#-qsKGZHuksz#xdb$1pVLzmdi z3&J$CG~FR&Cv#0mXO+y;lyV?vzP)oGMq855gMqac;ce0~Hps9B;cp(G1(m>Cm*Go* zf@&6m=nNMGKO>BT1NJw$F)$FEe>PH(cp(o6&%xT!qI?CaY&bpg8Uj;00Bar;J<_}9 zrUdVw-uxghyf^@zp{yLytaVSkM>ok$AkKc`l%N&ImO3)6yY*MK6G8ltbaNE#l&k>S ztngYAy;f7nZ%ASOhF`I@aYLo}TDJzr-g}7zoqV+@MaHO3=h7LR8Zp_)1hB8~%zApi z9aDS66j?7Ev5?5`#Qn+Sq!F?5*IdxBu6uRxD*_*_1A9^Fjlo#Rd4EFrhy@H8JNu;4 zErp&~w+#f7lpe^Xm+~0g^I9EA@-pfP2!b$-QSMIKa&A}DO>=pwAlpUkPQmwT%IT-8jdIg8+%b=Ezx(0F@a3#x7^ zi59u+5hgSnp0O8pht~YXsW0WgoIX9w2{~&f6_kO0!AC&+VSQkq`YZ`t_*kj5ei}fF zQ+nEpOK`FbK-QBrlElXq;maq@W|n`znEvMYXM}w5So%6YHhs=@=o_AQ@xArYmKydL zUT{s{?!wL58q=+GLihFyj2pEK+0<$RmM`wAFL#i%RZm2Kv)krn+}Cmj@kAwH=Uc*8 zrk$b)3mI+)*yeTyg;PAj{!M^jEvs}b;`I19J08s`L^Yd5e95zwnMQi|bHM8|0Wi25 z!gBhM9{nW`#+KeI^#+p+x}4MaXKrZpw)6N$34Lpo#9gbiQu2bHk-_<@Lf}_M2Mi*= zD0t4VSk~Hgqkk1AG>ksF4#{f6|0+U4DkhaDRK`||$P|?)UqW?`%dO@!AJX3z0&oY% zXT{9Ov~`3_{Cl?&H-2N>7|iw=KrU4@A?T&sr1kekR0y-F0axl|=R% zqOxWOd#b+^7pgEzyD3|6e0Q52(@Iv@F)+nY4v|#GrZ!w_^io^ja zqrEoLYxe1ylX$jt{lYrY|ISJDeF@sv(g@?>V*)oQ-f3j1oM zxo(jbM=_48P4#;=FW$XUInJuouN46XMlq}4j26Tm7jr^l&BEi^CUOmhyRCQvkb7aK zYCetupu0d~HmseY0>4EqR^NE`TE>+xn&b;~V|<$fhPDi`UAP{{oUDEdDv*z8z(m*n zP2O%Xw-^m|k*3B^v@-tZu6tOiF}fjOm6&p?znB7}6|h%4$E~ZE@8sZa_F)R4yonuw zH71R569NMU@OK;s&Fh)jw`4Moq%cXzr}VyJ`k`*tI7Z1<)of*9HM))$GyjV<5r=?r z_Il$^jh}X1W;(_q!*vUYUQ6XNn`+17;u`s>Jf?{0aa(;wm2ug{lTL5D zW4D}O&lp~LtujxMvQ+EAD%G4@ci8@W4oC1x&W=^JX0HFEZ+tjgBLWxdyK-(`*-e6~ z4bs(~=;z@1$c5g zy>5b9qEUn3d)=8j7f3tRhTI5vhmwuK1{nJgOHH~KHN-z@gmvX>dbMh{ z|Bt6{V5qL0kz-?JiDDfc3rzJDU`RJCbokv^b&it8sAKSGSTc3#uhI&jb(tRuwNS{=9 zi79$rhM3j8^ETjHGfh{aUJeHPo9V2I$Jr5Vq{mn(G#{iuN0p6%(Qq~3n?B58L5$Gy zuC;5TS9QHgN|lAKP{se6L=o-e4s(E6JG(1g0=)z2zgoKk-$lsSZVvdA0OA<_eb^ge z)Vm3CO24}m)K|b4bHU*b!zGRjoIq*@>gZASEYY>3m&kc~ z8cL0IVY09-v2H`T*8*#Px_7+7#F00W&Zjx#a&OB=SX-|~jCCZ!`ty40wW;FR&K}o$ zFO-yprIZppyqzE19M{p;ViOnlc7sbi98CQ^_zwEOB_TUU4@*f+y*AE}L^FN7=&$+B zjXB#$k6l1(&H3ZS#@$^&=-bURGL^$V-KZB5Ir5A7P5XNQE<=3!?l3;9dfa@xY__{a zF7J=M5jCw52-kf477=5F9rymthTYCsnQ}$q?Z$m#H1v(3kki#y0G9aGkW1sn?$} z!t%U3mDW?R3mao3hc<~vIQGhuqzc}})q_db`H8+Fg!praUG!etJD4xyb$69Y?w-Xq z82S`JGzN~o(EWf|z)R^99ARe(k6xnp7Y=l_({s&|9T#^`wQagjt1PCp-Vq_GREg{0 z4(kpE0n7Krb^aD{YiB$)JygxgCL`0PuPkP*L$fpWa9RxoI)3Z;WDV`jKF)qr`hu^2j^ij{z(TahH0z2%J7eS=;e zD&f0WPMl{elRsh7dXZ^IMogQW@({!W8O@I2-wQ=pM2M@1t@+oK^ZJj@G0;^XrXOp2 z@nIXnPQL)am%Pp^2?nt%v@2)53STF<+m4)RUxH4HIV0R^PhlAI>ivNJLl+sA*Q)Pr zuD$PvX?SnFi*mKm)&0tMel})v0~>xrK}l;12mrdq+(3sFX7jew%yU0gcl$=WeSW;II}o4n#QhUu*o{>E34O}+t! z*+g_Rg@3$POoBi+=IxUcEToOAM>!(m0|ysg8I15-;a~ct=jV~i4bo6JSM!XjfH%I3 z><|etFnamfPTs~mRHn0NZM=AN-Jim-{74OiB+Ld@NzYE%@w)-bE4l^-ek*=FBt0~6 z0C{Ck^WC{0BXOZN(!ySEr}K#T9{e6uy#N=_n%uyE6Qb8Yaxaco@-cFMTqxSU{ImR_ zz@N*EVqnUPh7Vz`V!32K>`)EL6xP^Esj(Q4vw)MSF%_SwYWq#J&izgRM^oz*{cHmyZ}s*hLm@oQ32Q#X%~ zH}K%Lo$GNHzV5n?ZzOA~13}B28cK;V&g}-UD5eHxCDtmmqVn{7$-5R;Zg9%dZnq7k zKgtd#iVzBzE*{JpWb1>-1v$#^k#tiAv?ByU9w?fT6n`$IOuC3;wCnF$pFI4}W7)s&bi#O_$12oI;<=))JME zo6DD=mW%6K!Z&lW&_RROhcw<*c))x)iQ`QFY~mm_X^%S)=nY^>XVSlcvbOqOG1<9R z-L@-X(6J{`PT;p2n8tJ@jtpBYZI0|OS{t)RebMj)>gD08e0BS~veqlss*7MGXw3J7 zCA{Ahjpn6vA4~N^+FDBdogPsgC-NrIDJGpk!5H(j-(Pp9LU>pr zD29xH5*0o8dYG3*3=%jJgJWVMZRL71SSMU5Au;m|+4VY<5$m^!21+-;#Y7JFet3KH z`+2%78u`r&v&ykOqRHtSj}a_p5O6>$zK(|X&Q8_F*?GeN+fCi7QT)!ZKg3k+PK&XV25)ipx#{?&p;RpvJTmC-B2k(G78P&Im7^HpH~P6n4);5CY}A_-Dt3kZ9z zwr55_C$1heM($a%eZ#}Z5l7zC!AmLCg;*2Oti|BcnMBDbD^3a9Qx|NlGd}(swp8kb z#SPEFh;m8+2O)Kc&Mv(y)rA=z#X%j9ub1v(sbQrk>$d8c|4>I!Gb;hJr|svtNX5e- z@!94aE6uZNJcnqq1$7oO@)43(gl}Y~#{_05vnlN%-TPi&Orh>iY)^h2he^PP96orR zBbKC+n5KZPZ}BOVOn6rgknK-lN?2Ep=a0!~!_?V@L%r7(e^&by7(kx?aUn^)ah9*I zZ}tV=*39hAo}fC32P8d*V?OY;0yyx7dmg$h6fg22`4hAKNzD3=pB$UX3ezP!FcPGU z%5oo#qeoGEfIfH9?>k7Gl^!}D9Vr+wNe%;u$A-O(e+pdBhRstWZWkAp%=;8_0zXX@ z@xGDBc*niyv6x4s*CWJDx5|0J^U%2Sgde zlg*O6VOPs)EE|3Z&=4D3)uc45t(vu&n(*;)6%!l$TfS3>TGqrx?e^17V+CK|Yh*FI z`MLUda;{r0T?ievboZRaX&JEW<0K;k`zenoT9cCC%5^?FJN>YskeOgY->> zikJOb2gY;8Yzq*pUY|DCX`|Z>_<P(?`jpz6)pScv)=u<@~rf;d)fGn?H})Edx5Tst$qB6^kurb zH$HF4?@UDS3fVU|2>XlI9dKw5q#t}86{>~|AWLDy0p!>Jz09OT?!X@&o+GxnjYRuT zT^CFulKm+hM(&s#59`j^nq4`38^^W}R>&({V-~(g*Fo^ayp^9~VF{T;y%hjLAR+pN zV>m^`Pvl9EslMNug_Pc6r|GMk!;J{C3`Mylwk0WI)Zokx%vZ2@ro-Tg)f6Nr8VQe@ zLBKK`?|R+1e?0q^*dLchCnv>&HxPGc2b^_(%msRDCVwLeCpM1>zf)qeF(UOX4|v}$ zY=>nPjFhCo;T)PWf|am_n%(>$0LZgmtT_esM&a;i zp}%4#hlXo%TmQgqH4r~OyZ6eb5?f@gn_n}gG~N!p-uZbG((pTz>T9VVQ z4G1=!O-nQIYSat@%ehEu5lTBuApnvmfgLt0c_kECTh z<4iDEDNf<1I%OpCIQ4f0=MruI{!`cphA(Mx!7F&Kzm%H8e+*_i%K4m_CocXB$4`xZ zN9%#!E0|bV5=BF6>`3)m`6l%G1+`-cLQzbR7T9y05*`v_{me#{j@N700{cpB_~*i^ zlM(!xc@`p;tj?=&Ibstj?3my28R*GtzAK7-XnE!$L_^J>7h}Bn9DbATB(vjQ@2LAE zJZD4xgJa9#=;0Ap5VE~A^Srdz@=j|8*0{f6yo3nwc0hyWODJMQ3X7#NFq|nG^;A1j zTsu%s6Gpt*7yEQ#s8;i|9#nj(UivXI{_mUfFSB#()@qSel%S)xA|T#0EJ0dmxCdo) z%R^vP3DPvvM}+c619I}`NA0`k1J;`rXoph{1}W7X;-gMGB%1YlrHp;0tgOs*Z0BmK zk<1Tz`@Nrz_?}RYMYMd-AwXpbh`>6Szs#eiDJCO|(0)GZ%%xIQIPz*j_lBz*(;=pm zi(yuanz0x>mZH0)QrVSnqM{2DsXS|3ZH+GUv01`^Vln+=@1Ix%gQw|p%yA~$O=r|3 zeWLC|pi`Qx&ev*Jn&jrgyFN6Zqsye3&@#2JywfGcmWl|N8b1L;8_Pkv+_@sav%`nj1{)!Xd{x3pvH6<$T*nfhCp|mY1>J(K4R7tODZJUpgyaFj7s7m2@^# zibPqT$re{|6u#EW`3=mb?1XaC`w{Adai(-cechCUK~F~)hK>D5Wi~`0?0ZZ1L7#;G z&Wd1weL3x87ndh@UU7$rR&22R#>p2;WN|p4*Hd5d{=TBXO*eHw`!4s!O1jDgc6B;i>2Qy;ysFr{$dh*yBn+vSF)tLuixPl(#1$T(O3;74#sgeq%p2JM$1 z3RxFy6Uv+80QYK?N-TF~r1vL)%S<44Bx^Wj(Fvab6a!wiv%3fbs1Xh;B=j=mochOa ziH_(u{jNocn#b)2jFnL<(3AD0%0Mz+FVS85zHNmrdmnOsLt4t)O&{jVzEu9;m0$OH zekc;6o74Tk!^p8mO?WG$Fo!C*_21u`swTgZnn$x4GZL&!r4kLLM?Llwxa^l3*Oc_?T@jWP`H znKYG+Y2fK +|kJ~#V|>dZd_e!_QM&*s6Nv4@fhUT@61=ze8+Q-IXBESkCfAPqav zPhHl3OcGR5Iv8z>H%`(*ZAI>L$T6YjdyGVr<_7ldYt=x%W#4Rb#;ytix&J-WoJ@ycsju_> zk4Ab{y3n`YQf+CBZh=M{0!Q3I!I(of4Ju#=1>xjRCyF)Y;4wpw!+7MG5b#Z=&7p_v zO?VRu7-{&!{Zt=~*X%LQ51WE|m~~4UpQEt9Q&Jcl?s@8!y~n`u3WO9pcOLC|Z5E&s zub=7Ekcy4f{m=;Pr(YxPC2%ZXw;ha`l$X0NP_xK+8mdt6dnVff>O1#2{D(o;1NHp2WiP%naB)n6JCG+n}kU}ypJe98xVj;W%2`l@fz zs^_JoDj&bT>|oa@TSypK!(q--vl5>ZbBi3n{qb@$apzbL$3}&J|i5ag_NfsThJwzyQoy|Hh?@~{m z`CVhnn9+dodoxr>POgee3z}P9x;tGmBGE$bZb>hcc=#%;V+!l;H6NSW!^16!?B_?u zFgjr`Cpk(2*mqWtzM3K(B_@Uw9bj#_{sWno0C;IPFmA;Qt0xpG)#8hXzCg3fAbX=- zGOQZu%fa*$iBU z!x{r^2lKlQ)}TzHW0L8r^Jt^lzP_yt0Lc zubM^+)jKzuuoY|SCkvQIj16#l@Mt$p#9>(6vodQvvf3I ze)HU_*qq{ELtaBZ&<_kQ8=wECyo3@FRo0*@Ina|#u7rAqe~l}o0oCWq5SC=L;L(S` zV@Ov%Vvz?N8{t%K4-d$WTH>{^O`*_q3D76&Bx@!g73svpY<6t?YFR}?>c}yhXuON0 zfdVje7n-Oe)km3YQ^G?q*{K0Tdg+kq+Z$vF9_3sclH7C;WRD0jt@Pv3hnZxW3o;S6 zs`$evTaq4k27f}SH;omf;%ng<6u8r?6NzJ9-18k6ltz@D{l?Ej;N3WJ!%5LetDRNC z?RnscMB&dtS7lApb&eSB^q%|yRT-B%HA^W9VVQ%4)LpIaRTLq|4%^~v0P3r2CqaOYN|e46Jv zHJut#&M#1YC#7Uq&mCzrG~VGp7-#4bASdOrc3?8#kd1&m^A~S_Li-d#wgL_`lLF+@ zpbE*`M?U+`Js^p|4e%gVBA(@rE&HMZj4)@i-;W~b3Fdn-YI2v%7K5Y&em{rW+;7eg ztA3rDUS92;ztY^ABeYiWHBlbPY;oj=B{@{7kPht; z`vP2XJyW#i+-qQ^Qlbk6$dxrJPE7@1H0P!ECACTFJ_sU~-qjPlr7G5kVO2gLo+RzM zqhX17d;9D?nqw}G?A5ZC*|M;G+&&#-uTE73w+-kkb=lkxVAT)Z|GY$j=q6M( z3?1v2Vl~p@<;!4>ftGDdhBGm>)`lWi=iS<+R~qw0AzN}&p`^J8W!&p+H*%AKB$u4=fXS64A|=hu)v$CpQy8Fs;jFl2`-wnzyloAThlcYtX2|U zka=CBaOPA}*WR_OQ>*Ff&78t&#+1Ifh~m?R{H;-e7&n^x?h-XAnxsc!z6u&D*d}e6#dXB*e8{!&M zJ@w0>6=W7puFNWB(k_{9NKXxS)2@CE_(lx(LScT5L!xGv^o~b(ZC}+C5NnuK+Kb%t9TPksDlF>h4Tv3&%HT_;7!6^Pdj3CP*zSv= zdwV$R?1)?k=HZ3l^}f6v%l+=~<~bW@_&zwFwgfYwWN{~H0`o_-Ce_>z0;^$H*E zF|cRpA#m{2Ni2@#M^LPElUe&?v~}H^+^$T%h{vbCeA=Jtp!A#utZk}4@z+wJB>Ur? z3}Q9mq2ijMq(<*}JIs!&tM7z#D*$_BYQotm0kmxG_vVhX;%B?l#$>G7)gy{ap59iU z#h1m%ew!6`cEC>H?+DkB4+{bmKMpm-lUH^*(}7P-c?sCsx;iRHNGGp;Jbn{n>Kf%L zGHPlj)*F*QA}`Hjr?RIkbSw;hBUd9MlzrC*3&4nzwWzWQ;gbcRPA!>^Jc4;mBiqBt zf^p|v$nU5-VTGJ#AP8LDAhlG5p4w5Zl7XW3TqUUHP`Xa`Z(R}Zs}8VY6AYI{dj=R{ z&I6|gX{!XhBg^%(~vJ@f-2OlKKg8EXz(%K75;QJHV!a;^g!j+^*CF( zI{Lg@seRGb67Fw63GIjMdHiAm{=8$fYJg?LOpn<;Z<_D&`H@(J=UrGT8o2UfrL${NV5!|cOzwPnK z@a5>Mc0S)y`vVK$o_C3R1KbH59uz@q!QJm|h@Vkr7XspL^hs>&V{BuiOzMV?t1v>^ z$#?;hs`#nT$mL^2V{zwRZnn)978n2q>IzqG+}O>D?Q?LjR0I>bUVkysWUWP+U;FR9x_Pg;7PRRD@-$_mqzK}1Dj zJu4VUx2A8!EMJuM`X@AIxKOU@;~8K^VtbDLf)n$R8?h z9+?m+swXe&Xs+Ml{D+!WykDpfI#j_0VwQ$+KEu!(quNiQx` zs;Uq}`4xhtmRf6_ibknfuYuBF4xP5{Y+7>#-M--X=vw1irHM=@2Bf0$+J$Uwo6fRL z`edrlf`ezJuTjmJcd8t+iW(k zHZv1HS=QS)fp7!Uk9up0fhd}=`iBEQk*Aip%y*u5_Bn25O7ptN274hHx7XCR+XAiSvP81}B+l1uOrf(z9;=!9F7?y`Q9;6*6o!6f0Pp=$G!|fl zxXn><1Z%xw6R4&J(G|c&=D^-&g!CviiYO-rKK#+3xT3%Q zoA@M(@Zm&AJ79kEp2)ZPvu>DZ5B!wO&xDoYBN$-Pi-I*BzkTkDi_u`gcXO{1MiLx+ z`Tc0WC~_RvE`R0T;7_AEgEe-7Js;w_7u44!s!z!~rg&FxuI$ebmJ$ib9Of0W;ea{X zVAw2N!Gt@Vb4iIFd93t%oucAO3JwEaAD+wBsWqN3T`c#Vw=&>EGuHj0QZF!{)=>Ny zdEJ{|LFs2j{EOGAkuY6Tb!`WiIJ#)YQiCXLp>ahB^ceSXq$=b0-vA>{B5()i*wZc= zbrKL5rhO(e$;NeXH@j_7PA}B2-eL;T7Os?)Z6~i*qzjB{LM}53UqYl*z3jp%7Bd_I zRisW8bE90laL9oy;KJ`p7d!%n+LBg-WsofA2wo1Z0lYmxfWJ4_pgxH67b9Ir(4*Oa zX=kTKDGN_ePWeRgC4;ast9re8If2Zv$oa}{uTDvFk$3QHg!oDI9jc|q)S7=8+SW|P zZU>BeMEozwREX_WQIzkL9^r<@=I01QC_?<=s1V@Dxirx{PB#mZIke05YsoLoz{*X^ zSD8EN$Cy~y*7Bk~CQL`#yuui7kxh)bfq$&wPw-|zV@bD*Y1{UVEW4%z{?#&qS827t97${bNQn3f4nFN8!AI0?~Oskh9=s^Ip znVkJ^+V!oJiGrqKxf4~5Ti&XYFdoFXuPPx}0}s?6*G?NI8zDM6yRzO%@KaUuk-i;_8U}6UK?$$N0-sy3XlN! z7oyuCiJ;||0+9dwYCsz~6CFs7clMBi(&JO%8aHX?9xSkZtas7MM= zX9j=SWCUm%U_=RBtYar8!r`gOUP)cCnVydyRrpMNCI8OPBd%ND=`~YpEd{ARaqrf} zS|55#Wh!-3)|x8b*B9!hZj&!lPAe6LmrJ=RPW^P(SNDZ!PmHiv>i~Nfe}lAxC2B`_ zrM3_PC7m;~6^=(*@Y%_s+1TF;52G5tgR4xyG;teV4}m>&8|EgFX^881C72Eb(zh3z z1DM-C2Pr>0TcJIFZfhcIRY=k-fm3z4C|v2iDSUBY=%6b3i}OjF_LxQ(`hqS}^98wi zBQaU(srhEyt?oH_Fr^~0R#Cn?0znaT5lIcKzvJmqMz#%CcMKBo6ANDUdmG=L=G6A$ z?tyo&#^-|&&y&Xd+e&aI^s{#5=lYCjq<+}Nt^pHLk^V&mj ziQ4+?b4f6ys~_nRLqfhWJMM~wZiMQD27_VA&+XwjiPVI1w6sBqYtlgKQEL@H9c5-L zyJ#t zTNZvY^k_ZC4`ux8`&xDFS}N(KBf-()=2oblC7Lr@H1ezD`<+gE+9QSl*b+B^2lO~> z@Xd>p0CK#z4^E$^wK839homtjQ%Xrs(Uj3|W9V!Lgt+@1&Xb|NNo7!#i&HNcG5YlBe68socO*x6ZU)A~zih9!u{7IS?QfpRmKO8@=DlNHL5M1mH1A;l^nd@V zcCpWQ;Q*%ef5IQ{;2h7P;pnrQ7&fyetzr4VfsMb8UczWX4@-{6ASrIa zrY~qb&TtkQ@(q3vDGGTEUGR%T8eO;Qclg<%%Kvojj1>1DltS7EgmrC)BR8i$#e z0fsQnMHx=E^~22kut=!pi&V+}TKI-A3<7wIMT`thoD(3Q>$62<7=MA#fnLafw z-s_dObi9;3Q&T<&bUHIgCtJMLCF-(Cb&Sg=Whv`E;L{%2wxx)NBM}?xAHP`o(ATYJ z^BRX1`*d{v`Dwba=$ERPzht3i#;quHNt?+^R)B7S;lKelj-{wR|8O+GpD;X5KQ@~% zCYj9nqoiGjNVLLb6;WV+ZU?#LN!C+;y4F-Q8V@%+_ukokH900b#tt^}``$N#e`hME zDxu#9im>l*{|CJC>fGdqipg!L3%`!O$dmfSR6o&Y<*$>n!%gn2)GuC@w^=tei0nC9 zQ!w0qU+_fXhO=u6$6#Rw>o_UfQs{Ib9Y^D#yva8py+*I-P6-xoO8Ie$o?G$miC^_D zx0W`%eHcUeA|D2KHK9P;$xUZd$qWQw5fnr!eK*Q$4*`SvwX(#*TwC|h+>>{;-tn-$aBH*x4=pJIbo{Kn)(#ay%YmJAd#__PB1NE;zyTk98_`g7H^`0d z&uhL}U&syMI@yCgXZ?0F!h3{?3U@wWJO8^`jou9bM*YoWt_7jBlM^1(2QQ-HgRgS3 z^inciKjgbbOSOz)T%Vv}LE&i(YvAWVg%#9hG!pX7i_rT9p)x$0h zqvAR@tD@yGY5mH|1(d*2NmIQ2L2E%L4chRR3jL~YkP0)!rX>qdn6%t_d9Odbm8(*n z6-t}(O#E7#NV1)W<}bl{Co99PEx7@0YLu#YYPft}cNUbn%F2gxGQwm5h^q5LUD&uN zePOJt@$$>;G1_AtF_n_0uI&5xV(I{+s?FG@kdsuWU)m=p6~-8tDArbAQ9;^o>P1AH zvbfB$N=!9kv7w!(zBHLMvibT0RL2vaHPZ4~(H+OzzN(X^kanvhk{e`c^d_c@=OBF} zN7=jqBV!{W%6}6>{ecZ|USD9QSLeGs7!C#tK8i74(8<=W#KF{Mb%|$m#~KX{sfbWk`^l`iD_wL`^$C zDM#GJkxcG$OjG$s!4)-+_ls~FGRlMX%Hcmg2<1dv7D#r!m0K`SdR76*S(y;PLSyuO zwKzKsg9UDw;_u#+CVST2DIuy6(kP{dE-Y|h@VdSrNEG;K#PaaUo@g+Ke5Qh2i+yLf zOKOw@$7iT71q3DUk(X$g?0w-xoZGw6x*;DwX78lkE{GL4p@Y-Stu(2B3DdQPK67^Y z!?&=^KyC`H#T&G?YfW2u1Q3;47K;t8iJ=NDULxne#lr4Pv=?c51DwR=0^<{X5}i-n z$QKsE^YZ?x(AD;G#2PQWeyLTg*}VanrrXY6uVGPOixKk=o70SI~@%M(re{3O(Fa%;?x21yeu5%4bwd|I#h#E zaJWXxf}tDCbT*C&rR)mJqlh*h)O9kZZ~*(Q?Oin?67geD9_vw@1dZvz%pVmxFs)yZ zxe;TayOl4qayq{T=Yju_j3zJY8yVw(hKRZatihr{DfgIRwX2vOvp7e)6(e*v8@sYM zCcsxic=l9UrU87#eT%ch!g;BfqRG#3KLB>L50H`XWrt&MqZ7Z8MjS{($$osAXt_8V zAb!4w;TMUavyBvC@}Aal%oIW@=bs-?zO2#7fBd4z1OpvmRihPGDsfVXe(rS`3P1^r zZxakFXuY{+D|C~~&*8h)q4UJ9nFTJqP-1ePDfB!OLBc%;zG&hxQW5*01) zJ*0%-fn$*o*M~Xghd}g^$|fEnX-gND2;W~RDQUwN#gP__^!U;fhTEu+ie;pm9d}@l z``3DEL8O6yg@1wI`)xXHY2PW^81~A_69l7q7(Vaa*#|i-ZY= z03T5EVOR@`{oZBDJiNj@P=Y~bTU(dN!4A}Pn*F`hU*+Js^8CQ_?yn+?Chz{=MxxXZnBDpatw_LI5+w%yDSMZYc`+?JD#%^aKC#r0|11-YNOZNoMHxmsP#WbYxz-f_-{*5Ju zCB^5A6wRa`p^J0SB674GMPe>1{T)vd;GA%pAQZ@Mo?t||I>xMF<4y#uNeEbhh!zOc z$De2_p}%Jz_QxN*5ITHaE>0RtO3}-C@>F9Mm2Z<7q2uf#wLYvAARmLbJ~k3=v~kk< zeJ=IJdNUiumJ=Y};7Su3_|u~6f4w*_Eo?w;ZJ6ev?wR}Svyt zpl(+DQc$XXPqkv4k8F}_0MmFPUs&IE!}7n1L_*vy%($4(IT4E;J_VeIooH`(;?(Zx z#!M;ds{GTJA0w4pY2;Jo;tI)@w@HpR);r}>jVJM9bzLR|7^`}zY0;&6xK{Mw6p{uf zawSnnk(+15vm}dZ_r|ETqHl7};gKV1pxCWpSGK~XjQ%GwCyv$2y zR~05vzS9x!`>S9Qu<9JMv12I5iyW-fDCJKzpE_t_7PaC9A3rg3a0x{=!T9q{Pz5*l zAYl^PLIbeTu7*^mOZbR-CoaV#_6awo4~y5qgJE?d309dUw%AS4TSIqr9crxj(He6m zr&3kigWqujoQ2|2F!U0xMUR3FzDR8b4uQ1*C|38&2YXHN+o#hmC4z>sy|6Wy$SHCVYHViT%I#l0tXIZ8o?wb)cX5?m~lgPs#sam zvXbo;YWJ<_w{fiEN0K(IpzjFF+bUxnP@beqY)p?}x3@M+OnM#_Aw?qRDg~0b)`8IC znetk1U3$TUS+y>USS@pxrWLoZPpL4Ns4paH^)6vai$R(FjYqCit}P;@;s2D&`1j&}pRdN7z|GX~9$S;;1!htbKO z-=jq~oMK$Ewi17}zG401HgvrnO+Zh3_8yq+>zVxt@AJQd#+P*2UXJRxT9f!wvjvYs z`cK^2NOttzTiQ|H&P%3D>}ZY~pNI1t+lk7#vEU7c%0q6k2+$Md^}z-dPkR74ZL6nG z6i9<64R!$87p2Yq_sz9%A^2k?MYD-USR?sHIUrLE4Zs6Ni0L{Y3t3mSBeiPB+QiFk z2@m*L{Dua3^k~@Zy!r;$Ie3-ty7Bi74W-Bd37aw}d1~`76h;uvEC>F*77@2mP@sTsfj&#oHN%I;Azl)5n163JLNdW@QAQ zOR89)HZLIx)xw)je`P6{1hZ*p;gMjhPY2fQeb z7G7ARRw+mvuBl2J>rYTH8>kEcPT$dgqJP86ibkf}X`_2i+>0QYv1f%wK2XpD{t4Nw zNFZSwMHguUcJLfo>5@2+OM3jvBK_+D7;zF&6NdZMk?YW}8+R3YGg!SF#wKDu5WWpm zB(2HZMC&2p<3L}`&6lA3TZI3sLd zNy6|IjgOK3#6?9M0wV{Z97!Uj+D(z5%|@cRf;(UC9df{J=OJo;N9Zqr8do?&>X-}9 z5#x#deJ4-uI@@eTH}aF(CjW zrqHy2!U5xTkuAV#ImixLRXwP=G0u{sMQY;}u!CXVMJ~;!?4+ zAggcvShQcOHg9VwdTf6Z`OXh|y zQA4mpvqYCdeOuKeMMJ`>h}rW|OP?CK3c&7ymxI1MDx*If>p8W6D*zP{ONFXV=-R0Z|;h>@TLy>KZwP0Qa_;_--UqDA5qUjf}+o_H4yX4gXnL# z#|qlWM0%`9a^5C*y-}Dfhj?$au1yeto<~Y~{O3TC8>AJb4$1tbWp=9zMMU5l1l`)2 zF}hZc8GY}AtBHGR z4Ph|w2E$+*S}hV$MuqiBH{o&f_5s5Lv_xv&_;!nco{nR!48-rhqkV%VSi{W$HJu;` z!H*H^lC&q_F_n3Yh2e%qt4^B+}Gw;A#xJ9)5pU-;}aYvfjY96Xr0dPHaAbmNq zpP9}SYu!RY&no>!!2OW* zRxSK0oHG|0ap`zM4^yS8wI3D4?3St9k=J|EGe4E<#z%b8Aix~nJ|59ih>j0 z;Ph^}YakoVM6IoG%A2EO>!B9tq*gemG*!$IG^Q64a0%Y%_WYLD*#4Yb71h>zsHb~V z@soW)fQ~r8(#*{LK5X7@V+)mx-onf+rJ6)i%50war3`Z#qOdh4CS|f5rf5?`9_1kl z9>O@16sD{yn54`o)+kYE@|NINx#v!JWzXlJ{ zft76A^PYF}`|VYI!LHro^|LE`KjX2{;aXpBJxFWG`ph1mhnp|?6fy-Rr9q7BAGMnN zmJQnXRp5XZ;JGRz+|(N3%c}}Lv*C7#OzYQJqGeKUU;*WUblJ0La{z)=F(<5Z$`l?cgDefGX_g1 z-!_-Y@%wRBp20?IQxARNm)Pg5bLA+{_QJ+KmkS1vW}3evvhJT{ZYSJuv63QXo%5Wd^^U9w21IB6m+YD1FJyQf`ju|1uOCf z(Z+(M0Zd>gpyA=+QL88=ODU>MCQzqYzA@`KEn^ihA?{C#q^>h%B7A@+)Y3$QhT3%e zORYRoJ=9G#-v5p=Tp;t~w`%9+YOjyZsH?I-MkmjozE-}D5_4IYTQ@i11;U)+;WzUo z<2U1#x8$O$N>n5sWt;A!v9pgo_9WqiK!YHO8PJh9PWf)vi#z01^p;qJ_rV}@l9*S( zM@Nq^<{^4(zM$Lxz_--2JH!|0z&D<^Q2Dvaju~dm-qKgE2Y4A7$1C5r<1Tyu9;oh% zy~AZ0=5sF&*P6BR%w1>R!J>8#)o+VXMfx@7aQseBcyVZB zVR>Pp@!`ZelwN~BWx`pkWnYW!w_iZQh5qjlM7zt|!;p!90pS50f4?E!-=_2P^Sxq> zgSdLEYjmMT!hMeRZW1F}jRqmnsBAa`wg!Rz+im`uLvT2&-~m)@*c=MOLFSHq1;J0z zGg{tMdR1wTL<(IQ$>^@VIhoFpU|L=~nU%S$_}qto^Q8A_&voyq+Y-Q_+N$I{fS@r} zP~*FI!$=gngEX$DTpp^Nu@*%}!3BnS6)uF3O5X{a8Uz`R)?_u4O(ip9L<6G-**&>&FJVvD0Ef$bmqTD|j0MAd&iXSHb9xsId{CNra zl1W+rep_<&rALR8RXXt~oo=y}X z={2a=^DuRl94P^)UUdTmQU~>Ou1yKt-ChvCaRt6*sMllfr&xG30xN@>Uns}!eF_7> z;}t7%cfXGPqaVj-tHk>E!C0f9uMhsa?P@iorY`5BU)2yq9V;x6CW2z7ukZBrQXUo^ zL411oZ||xlKaDY?Qprpmjrp*!6T|PHl0H7KOz`r9SM8pdSOJdM@|c&e7UqX_gZg3H z&F8OqhuLA4s7fLLt%Ts!@3NkkPJBz zi-y6L{!E+NuLc49Tb>75i7AZzwR*e_S%!mU2FY(NgITg>MWq3N=SiT*YKS&$u*Wi8 zLQi#`!}%NEuZ`(v_rD=DoMmno-xq2FK}5k7QW2~=zLBcUe<0^7p$1oB zqBDX!dqd%a{`zBsdtq9*025Rrc;2#%r{;A;=o3`E@MC0l?Wca=`&)vIOYIUN=z4>4 z;{8$Ffm}{Tap3=tr*H791njmxxv2>gXX0erwx^mVcd~68lU_9?4+tILwTcS>qy*7EehZgf8$az7+ZdfgsRn%sB&c(y(fS@>+@$uc1*cy25Cg}>EeH@}aA?|tgvUvDmS$=qTy0{b=f6G>{^8IRF z{v>DlPQUK--0RRf@rX(fGu=3cw;Err{dW{2%)jeYE8H!ImR75A2QM$Ehkl6Obv~WQ zCq(%d@cfe-8)qo#eQE9PWFT5YRapiaCFS>AFaF<4|CFQ)GILyhtAml$}PSQy_N=7FUMKgT(yyA^lLmiavpn`1Ee;|XS1Jg zaCzYP)_LGExsY09;ih&e$XN}a<;RNcN&oz6;x^vR^7mkj(^F8E=8AJzDAL%z{mW#b zT7P!{=I*2aBI~)2KkA>9{iF~=N)jc){4-~wDt7(^&PM5ugZx%xRg@t5*@)s$Y|QH9 zkXpH4;w>|^ys-a;)cnYxo$rim`*uP-d1_ElzK4;*Qw%{2nF``54#JTQYiV4~pS(r$-VD7<++WI5W$7qS{Z{_%^b!h+Bz*n;$c{4Yp72=c z7y6Uq#b8+wXn?Ofqb9d_19!CcUH2x%Mc>JH_{83wasdetm60u@?@0#Wv<1KGK%&>l zHO_aB_I<0U5FEN^zeP@ju=l#0!MT~j)_F%;dXbK>$WwiJLRc#GKDn2gkxhDtAHOvp zd#BIXB0qYITpo9P;u%0_1zKjb<8N(~bfD8@J8W#zPvMk=7JhKTW8X5{~Z$DJsviakE)BSr@lSjwh{QTYdohvS~ifV8G zzfK1gUS(Bfm339r(=YFF__7l)xau#yhBu$($UM&(c^>R!=#wmY@UW^D%1-TyA@eeL zH7$3Z(Fo!3ox#=3p!19N%vmfSg`!DUx%Fr zz#IV}F9A&;ru(In38jck?p|ywhpha1jC*TJ>hwC9ST9}|O_vio7|NH1^IDJ5^u`sB zJAy6g0^K-P-MK@;FmpC{F~E2|<|Gb*lPeA&7j>xulE=(AS?~0EK>#p@KdFz*#3&__ z1-R7GM)gCK-83)q@bmL?nl@-CTIJQ#rwrFKK`l@Uy{-Z~9Y`P;28%AVn3#=t~*4fwMG%7oyqfq*E`3 zi$B3$9zeGQsxSheOOgaLWtsjSfC8cUCQWbqZ!#AmW(ZOKM#7A2P%F3UR)96@BC5k1 zed7$EwG&>0i_v^n>}zq%^7b=dXTQbeSZG`jyU|5y>OpRReoD0=k7EYvwXdS(9Q01H zF-^bqVx#$JVCFwzmDEXt5Kh|qGnD93>(f^gwq88QJLtysvP7wAb>F^id(Q}T@DO}P z6rTlS5LpwCPcTn#NXZVC8uA8Fw5Znuj{E20PfhX52Q?B|{y*SB2!dB(RS3b&n3ilN-K-O+&KNvuO zS*R%YBZp z5_zS2vM{$trxZ}_9JbLK=o74{cq`*>fdIJM-y5JxPo>U!X0Aco-7x7RDPQM|PxrP6 zqg(Ic_gCEPXa5Zv(lP$mnrHFY?U&>yzzd`sL38|H4eWq=04NF3#At0m1l+A*g)-*Qh3q*}E%6_@Dffbi7Rh z7Ym^(wVH>gj>!ja_F7gO!+v=)sG?;uQYc$d9K~m#LMT5{bH4-5!W*UzIp5JTdU4B41y8e) z&Z`b*_W23+E>5j{4QBfWT7p+lrYKhOU>qwLerqppSZ6zwk>xh5g!a{Cpvu3dF^!`j zwpx6%=KhIA9R(9O#7>W9l;zIwEoO7XZ0Tq&jimGOxQ9IP< zQwnxJbOKd3JUrh`pXO|6p9(Uzoxo8T7;`fWV9%Dl&F|O8qLeQ`BPYpVFYH16ay!@4 z$V)j^A=#9z)7OBluzQn0I5LD9=l;Td_eHiWn{EEUeuV%^cu<>12m&Nk*zLsmtNz>k&yBA^K(6*qDA=sLE}7t zF$~*{u#CJC`qLvYE#a}x%!?Os7_&MB?6I4uxTfw+M2PlC4YcIW<5Jr;pu#?)ZD>}z z{LPS%0TOvo@DajJQw(7(eWWdO(LxOJbn%qv+|;d=;lqnNI=s;@#;WwOc6#x7K6pMe zqGVjQ;)f1?Ifs%JAI5lRdvQl6rA)M^{em0P`O5U|__+kjj7~*#rdslwyZBRk z!}P`N_+9s!@2eJn0#bpkcAWa90rHIuLY_+dbp{(<|TVK+7qQb(Y zx~?IN{LkhLi?C2&AeuZElgtk(x8^yzi*5Tl> zH|y=wXnOq};;gz@Z*gImKnsG!NM zELfD`uci2e;67&*0y}Qcm*Gr=X)u0E@vfUaEqHP~V7hjMX8EH&(&B49d&!d`$5hC~ z8Gwn{?i)RM;470qK7xTa+^Zh~(IbQ#J%+-z9|l-LGo1l;lloH+&dcybM-TbHlzGSm z9}d$v?3u3W)SdQ|@j_iWj*}`Az>L^a>%7lJS5hE!?wGXiQV>S8j70U{iAw=g7Ce{~ zyDaecsQgR`!$%I+14BowX(ZNM*P_+Ws`Fr?k`}VfssLj)VO*5NR!aoHf7Y{J0(lH zg|7+w{nI-x951;jh6!dtK|vR4&dNe`NeT^le61gF2{oYiTm4QtvJP=i$JVeW0hLS| z{N!}{aLmgrWJwhH%S)f5n&Wac=iWW^{H+1i;5mtdqFV_OE0F}6%Xm)xcq~mziVFSV$7k`ewd)8&7}DsgaRIT5_jj$BJi;__D?F#!1NP>CECJQonIS~ z#leB&PT|gTR+Sdk+H;AK$EE=lm~0drVE9eCq41nr7@63V1X^a8i#IcjUX#brGFvf55HYH}){8 z1Xfp5yU}@O0~#+&8`245_Y(oSHVtyNY5T710oU4))Zv}m#IkvQZhQ&Gxba(C3oENp z{p6H6_@RZ4AN9#y^_-_Ftj=lT>Uhnu@sQ!QI5^a0wK&u?G`JgqX{E5QivX6(Le_j% z&t&Bkm}tcBNU2TnDw)dUx5*#$CG<1DJ>@00(Rx#%H5jNGF-Dq#z&;!R3CN zXjZIkH+P>5RkT|#dY!^mns4Jzv!~`B-FdsW7AlZ%xjA}o!x}yWMrV>k{Go_}RDx<< z;#~qki^fX`8;vESloZZ-y3El1Ia+omn2IWY*It_2&2D2HtJXl<-RJ6b#L=GhGh&3Q zYE4aKi!^_pUj9($0f#u+9qCQr8<4i>)AS-(`omeW+m9^L27wY(={-k z7d&6~=P9sCPTZ{j&2Y#33C+Ibu}t4?P=CcHS(Pbzj{bd;EZ@y;UudSr&A=ynA7nh^ zOy$LN>>5-_W_1g@?lO2eYCYJe{`_!!O`JjnTt!9D!F+)zt8I2(j7FI3eA-Inz}`E< z8dST*#M(n0PdU_f)!X-n5zwf%RP4%!({t*%oO*ekn3S-Zbjd+k@@c}2d(TVBU5c7A ztHJH1#n3=iBVdFyId=en9a6YP$E|^-v%?XEOAg%+eVH(b_6z6gi|06)YXTot?{};+ ze8^bTUc8!N&cNuw{_4KfU_RQ))F-*fAxayng+cuVovOgY8H#gxLobclg(V@xoh6n~ z`4*!`aC>554l5vKjs$U5FoV;k$~A^0`PwA zNhsEDP?d~Y4tJ6<2mQO(?vDP8)pILB`S`W+$GlA{on1}CsLQ!D(8uuYIq|)@kW8~X z70YJR(QrMsUfE5 zh=BBqctd;Bi&_|yO--l9D{QV)`LJ4gp90P=h6Fr7SL2EF_0MBYZmt3FPM+hmAQgr5 z1+fs;{9qUT$Mfm@%ZKsZNu-bF+a0#f$MxyW{47}2r{g(Vr|RAP{X~F&%0ufXJ_pTV zY($z4>`<-??sLN+O=H}}h*+AG_^1TiOfaTShe0WwN04LE+j!aDpTRkynT6Wo&5he( z&l#qg=H&W0UU1Ys3MQgdJ$YUt2KL9H(4W~vr$1H!NoH2+uh7Sw&nT*r4+S^xM@3G+ zVbQ@roImPpAA^7H!xQowc13?sm32%DpD-70h8F6y$|GpXwun{|P;PqBxm^2XvKrEs zlCu4f?+^|H)^1fWC`tQ;$&BYe_HBAfM`boo(_Qz2!(IwJU~g1^?7$Cb4U1`~VD=y& zEi(#_-eYtKE7_g{piDp&yUHu$!E6Kfw0}va8$sWE3T!) zX3k6mA4)2EQJg3(I(z#(edZ>=OL3YI*|Ihlf-JCinr(|llbn*zzWIqisY z_+6xhYt=HDkuWGNZgC729B(X=*8&~n*26oUDsw7Y1=Uf8ym2A=4*56542XMQN=v+y zyv1;Mt+>lYkF9C$d&Vc$SEA4!L9{9OHa`_~@?E7>Y5&(nu~2{XU%U+jGiaXLDV z(tK>#S*PcbVP0rFCG+TfGF{8cWjTZ##A{N-AB^T-JZ#x_;JN`$cf#yxQgdQdC;htL|6wo<0hZ88{#Nnn#r!9*YRjVji!^=6j?KqiF6->3nJ9P zRP;KZK;D>cxp3W6D!;6PBH?I%IRe`_k}q3(&Dfw~Ummc#>Y1na;RNQYo-PY4pn9(J zPIEi_K!(k8XZc6(vp#F}k3kvE^;sYp@ z-aPC&PyPFXz_$-31r;f7ez&o&&raTL?f_d$Q}tV_;bz;mG)-4KZ=d?dlehf5`)vxz z^-!0#`Br9MXRQU6{PVsxqx=fjccHjgyOxifQklsZd1PO?_q`b<4vJhjj5HDoCB`xo za%6Xt*Dh_#zMo+WL|@y{tiQ4s6bc`p|JBY5% zD^Lj9Y>>O1|H2?x1l8~O=vjXsg?e|UGes|h$vCXnP^3$wCuNk}QX-+S(P(@h8fgJG z(U0-o+|;fVDV~=TRg>e7@P3BHa+N2ymDzUN56(L6PevbW>rm+%xG6DBcQ{0BVH3Z1 z+?U)iIewre6MLsg_GMHTcpOd?WfAli4&vYbg$A&jW5FS6+*EIojXgrVjZXG?1JVI}oi-x@$oy<}TA)4fgK4#zGE4LKmGYgEkioLlx@}pgQoVIic(QVvB&! zRyZ360xSdw8)c3Tf(^JJ`!#FMPIIupex~(On9l7(P`Pc+nW`Y`wAel9JN=s_-LdJ@ z5Gm#&J@GVD^d$*?zcO2XUPWz|#Z$1@)gIz{e!>1aPWEna-2F*jHH_N^O=PT=Qs;-LBPPHk9#Avkxm z?{}js!LhXnfUvnejklAtKtSUQLh~+&cC*b}s)8=F;aYi#V3sPIt> zI{Y1b1&RN++Xvkrb#TH?qO@8|E%)dnr?KS9Hhj^Kf`mgJcAi} zvnIyy)TQ-hbnmE}c*-9$?VCm*{X)oMcfSh*k3A`v|8?DZnonXPWqnai8qLSvdLm^X z=mYYe8mlMl;8S^!kXZYkY+8QU?mxE_w@!K!72?)IVJ5z@XV)N~uo{4@oklsqeuXS# zPCda0uAxNODlXlZS-*NSj5}l8CQfrJFAbjwQDC6wjJ*>iC{QF1j zy!h0V^?g61>$NklQdU^Tsk}00-jr9)dvlMb3cdFV!Bc!e)GOknu=V<`9G@OWTe^J? zwc@brX<$iBCpIu=xV^qAr(t-=r&kphv9!8}l>)Qqd#M3q>P=c1G;64ZW_hYyngz@K zyxbC=xeSonliVktY$Vv-+~Sl>mIS@N2kU~~+TwIe6H5dUj2j%5m;NuS10|n_UCtV= zU0Jmxm>Z?$3Zr?pr7=SuxQ z^?Z?h4UuF$ge!DU>?<(^-7zIM2HO0w{aj=f$R)5qH>LmJb(r*F2D{ZZ;Zv=G<|B>! ztR=?YH|5)OOXa>B{e$6cRNW()nrYJ%OL|HkR1-<)n#Oc_mND^Z%TbV#(3U8D%D->hv`BXs`U+Y3<&vsFEgEF z^p7=#_C)|8-=T{hEEupKWc;O51~R8`8{;1tc2{H0zq`i<$*7mit{0$eK1;!hC@5|M}@d{)H2_S9SHwA zXTvI$ae&d`h%=otrf}f(q)VykU{LJ=?iS;aBLNsIrPcQ(opp$GJaV>=VEZ7X%-auiOOlbSWH+ zwy}P`AM2s!b`KADRGVLwq$S-n`be08F_BW_-8q$^{GGVOH~v2Z!=p6}uXm|~Ae4+Km>kc{P77`?r3*HcM)-O#+0LMH|6(-^OudnEl z{d+k_z3BS5)r%VnKp_J6b74fP_uF-6D%`?cd~9tZtE3IK__ah6xd9+ULCk_YvL;#d zn|EuPCf{?cbIopiVE%4=t=HZRg%3X|L4_32eQ0g}p1Dj)iss4VP%-|aml&ylQ z%CE5>pD@Ew7Eh4kI#gb2^o7tVJ|grcKB#qbl4RKkWic*7o_Zk+GfPg!Pe%1H7K(zN zfhb%@6a1Hx2h3r&$hBwUt$U2|>{CNgJD~%d&h9fHib}0>Xxvz~(UGedS^F!bW;dM< z?%7xG8uCx)d!t2hHH1d|yKxL>>EcO)fFq;8Jj>E3q#sDR?P`;>K+n^7c921M)Tu+u zICw`a>#@-F5X@u4+F-HX-K+eEt)h5XuBecC1&=jbWb>o4Ja?$d1L{_kQw zjG13WrC*w(+}|HL?(Wc}zB_z*k||^Q$Y=`Fq2R^7C$1R={tSzhMX#RN>;6N8#ct<=G?JLOY?J9b)if=7@weYrY^1BCf0q48|?%Po9pR7mX;jsr7_=d+J}nz@aU? zWeW8%$isz$J9Tp zW>h-Jj?Lyqn=I4Vx(*}jn`LaB^&p~n>*aLGj(A5e-Qyav|68MSfI7+}MK=>%HiUC={E3-S2E6gkE;J0%>K+Zom2 zzNnv6mp&w}F#>XUW2GZG8ObU#e<{5zv||0GxiJWfg(-RUYoG4WenDy~4w}^{r)aGM z%P+&+{nEYC4h<0v3yalIB9bJMWs1xgPHlT1LQK0C8`4}s^y{bT%@pFbh z)$Zk6EUJXH*TVQtL`3oM=^k6ju}awJu61s7xV|s{YPC2fT;EPqXUByS0flWQ~zv^N#9cmJf1_wA;(ps-<8DpgfoSw~{@3_LxK(9!=Xr%Z@P@gC| zQU0^8H(+kxmUP15?k;lEQzU}!i4L9FlUOd*w8V!3i^Nl=LtarGAJylLV!pb=F_xI3u53QGm2se8dEyIgS4q zYt{6=h=VY1`ES*d`~%XhV@Lxl@M6^KY~)$lC;4vkpd|_T-FN;dv!|l&0Q()>=!uET zc%=H~Pk!`&+pSAQQ18+|=l=Tw5*Z0JA+?96W-Vai=f;9H!e(h%=U&W~Vy^4auW}{WVnaRyzT=oDeG5^^-w75b+ z%99VkaqlayM54`O=PL6o)_~*s{=0#+^@i?J? z$l!?0`lhRWWu`W40T`5IuZRukyRKbEHeA!7p-4VKq(7x&3A4ylS#tni;L$*p_4KM= z3BsaMOE?Ma3i%fUtKxtA5%{VIi<9p*b?5uCUqRQP%AS|b^ajOE*Qp}z*5q|{hRF)m zfD5VT|83A^c12jXL4Rj@lCzLjeS|NYz@wY#NLwZKBoK~};qwofwygWPuJsF}@8ikJnb8EC(@(RqXt zqM~|L0szN7U+^wW*-R9yKRbaXJ==``{24P430g`@FHFkF$HtRD}ceTWXPubM@Z zao}uU8`AGg;v~ZL=Ac54AF8^`e?odZ(xo_@#D?AelT04O-IA#F5nu`hjjLUvVxd= zNk4L!-ADGAZK~rB$M{xIhC2b{C=(>a*`pd?=2m&;-#v)!(K2VmwI3<0#`_6R|8RSP zRX5#FC)bUiEhYV8HN0tf0<~R@>K5RO58VLP2Tnnvll{BkYuSr8ak?+ET5+;4v? zd^b9gs<4t=0BRzcj(=;&ou{zByw=FcV{?WblfFuldDkRdkfd8RTb+n$TdvwsTD|ch zaGr;9rcM+L@Ew}8m>uoc!|?wG$q6zZ{MC~oT}bWLjJ<{UFH^sc@Ey@^3lzY|P6`e4 zno#x8!ZB-%&xn<&V*}Y&9A~kbcxc?wvj#RJzh+zcWk{fgfrB>Gkadh@!YUL1>HMiW zBk^f^CI>tgWL5e#LBXsow-MRc*qGatHgGrzVxjNHin+lvQt9!C80M~;1@Krv=cNiS zsSlHdmh4u`eIq4Kg1oXs5XX_&;>wWw#(3^uVuzUpbyNp(*waIo)8n7w#HzT5ipNww z3;zp^ZMtVSRo|#B)7P(GSgG|-I0MSsjaE-lu3kl#R7GZx2S$0%R-=;wtP1C3I3&NM zSp5Ns*p8!5i_*=ZFH1v^V|=rac~=MT>bBn!K=reqrwrjyiRUagT-L0dPNvx-EP z=4W(TATIM9k<9M@rPU1J2S!zGa&DGL2b+qSGt#dd%8QFhT-_rP{mR03x=I!2Hq96> z1BCH8|Lz#XkF^k=*zTC^6lBqVXYf^ZfKQwW=RGvE3gKN^i;>SMvfzI;bV%rc)<${+ znpGNz5J1|(gt*nK4N{#^ACMn~ zdT`CyyD2}_b@+~1#UngLW-2ONUhRum*;e_5#H@`UDD88#yHlksbkk?9;x~aNbkCo!|XE%E`X&k6%qw;lX~$XXnI z9?a};BuFJZARQJ$hxJo*`h839T<%yS=ckj91w(#^JV-sbt$!`&2sfei&i`SGA zVAmW;rLMHehapa9EUt08Z2%n{56k$e02tx56If>naj=xvO2dQ9!Xi{IrjWU()gHdB z>rv*+`p@rDIWcg(5w_p`hQD~N*8wPT*iY5?hDmdK1zyc8 zVpBVxuR>d`tLfW1D=8}I5al6s`Bwc$xB?*4Qmi1l`e!*X+jrX+T*a{dIh{cTR2^YL zX+hyUig%Z6oXS+4F2=^N!tT(`)3ps^-nKKhAg+a@Jm~xg3s-^Ac3Be_{b)uEqy{h0$t@T$IcU5BT0E4l#+#zhKy^IU?4_#Av9S~*3+=9x1kO{Re++c$D$SmWDysuFh0_Da!TPDj zd-z=g!`N(<2y`=O8rkP$I*AUNw9Jp@If9lW43dIQxUA?SGJT0zeXAAh$V9 zZGhu*E{AQcXnBFvU8K=?{~a&nQh=YDHi{KzO-)~gRJe^rT(62P3H6)j$WLS0Zq?Gb z-w<7rC;`$m!jrSABy`JDA zg>bJ_7Q-QAyYThQ5lK(fP-8ZkIxE>?$&Yi+}b^HkUmk2i25Kh&i=Y3f#=_uX! z_LzV@!CPdph1)hU=_dRm63X{85f_My^9%$q0652Tv!Om9M}4=3*_t3Fj!E%?O#Nyx zFd0uaPf1Gj+a=kNs*aRkjs7lvSBdXwl!5wIAU_9j)<7h|wH`NCK4U%VOBt2h*q|{D zjb!TN0_pKKwqYsD>ACLag{BBHxMDW^DzLLLxduAnr&ZdI$hJ;UB%u#&fDv7%;}q6b z*4NOUNrTBIK9*zlGsn@d*Eh~_-KXsuoUu;LUS(~!Ym-^w{76|~kJ z2OksA&?oiSkfT`CIp>dlvnJG`NXWg*Ljitkudg6NV|bGv^I&JYgYc6*98qjLGae; zq0@`&E6yF>G|$<}ccpk6HF*d&!Ud$0!&jQi{nqeG&!fPJBo?DE4eaZPx@*qGckb`) zuAL@uHpL^fQpP7Zre=F#_W8%|paEWcGBTbHMoM6#Yvir71qwq=^1PIdUrpD*=q2eM z>kG(cUO>q?i~N@w@xZuJ>@8xiCfzD%Mc9ZklZ;d9pgSDzu}Yd{U`Y44KjXgqIB{Z% zrODLnI(a2e&w4p{0!#2_IZ0Jb2X$Y^t#6T!<&UR?>k!U z)GuUVIyD6C?&)Aw?jy@`TRX60!xi10Rr=P$6~iKn7usXWp|t;U^gW0kN97w0i`0%6 zmTlDhkYGGrNsDP!)3X27S|_X%@UHU;qG!k?28I1rpd^x8 zQX|^alBe*x6AdJj>=3K@D}=QW<8{?&61S5gT2qm82{RF+pc0#5ofczG=;#~zFDwVO z^O8g95maY0!i?F8%al-9?y}x~K$6PP$qBT{IOS9;+cw$=SgGCW^#>EG! zkkwmH#A2JGjr$GS57*sd-=~jo^JjrgPH8gT2v&F0_%;Qt1z;gmp*7c5lIofvZOfoY zI@%8_cMGTHho<}BhC|@|exEdzhE~%;R=X%0(uLBQiz_!Is$zn^O3glv?|S(FeLZ2^ z`zS!H{)SdI$@Mc0;>04!%l054P*Jhzuv4}9EUwt)W4^xGZnc)g%wg81NR@!gV^foV zVp(0*`qRtvtqe{yE#3_@91Cr0?@8gSPH+_zTi`xN_w2_6KT2PkYvVPMh&{7G%lmOq z0~4$V1NnU~`)IX(|12GBGBL^3brKMFC~#^I<@+M?6MA}sS_>#kVN>n!Hq7QafpRMr ze;diB2LC*e%3$gTbZ%Lz#jUcogx_;H^)#@oODw!^ak48J!G$F=wvlsn5!r2BOP~uV zp{K%BSt-ZLb|{inq6<(-_!+M#gUN{v01T4EhJ@>_{D5c(hcyHCUCJh0j4bjnv)hrp z%^Ui6)KOgUf|S2ueS9756>oCeZ*-kP-O}%BpV^TyEiIKqBnE{6vNua`bm!zHzQ`8`X z+FJbsYO~95xh0{^xk9JQeDtQNdd7Z-x+5W_rPOw|u)dz8trBN?!#wIf`Q*HUtox++ z%iLB%oUN0WVtr>Tzs8K>CMO$yc{HrFy9O{omXB}RSwt$EO;<&jj}KO@m?7`urw5as zRJS2e8}yx~E%zF^3eX2LezwB~U|8@uXdp&h*o73vUUnVNJ!^iUNG8(nr@ixgb1`;~ z&?AojXXlaz_eX&&+{(p-dM&%{ypeDtgDS=?b1^@vjpee`)ISK_k1^wn(F8XaJ(!1l zY&keO73p9nO5PmVL_V2fj14{V<*4l-^b2@9@@3n)=k-sMTW(%q;T~Bt%VKhyOs#1! zX-9*VmY#;jN+n@OtU66iB8dL%iV}B|=iz3Quw0<_X03L=z0}SbQ3l#sH0;iPShFaP)$s zDV^%qYVG^^P}s(FyPsuiR~Ebo)ELu<*BgG}#d2^aWTGc&t@xG8R??@(ZX6w<1Tmz! zY!gy^%)nm9(a1SX&zhDJNVxRq;ohTHKZ`grA@df+fzm~y0oD=ma9FSp*x#pV>g;hzRnjBna9K9PCe z&nQo0_^`c{=W^mmLXc7LhrB;3piJ2P?!CVwi@=Vk-vJjH^~W!vh*tl&8?>qC>EBc& zu!_o95BrrNWn3hgW9UN2*2T{)Ly<|#n##Z0hnCJ?PQkI0tY03T%^tUBJ zQ3%o^tc-06fdPu60_RfyEy*1@>Grz@QqX`(pMa-L4tQtI=k7y_9b%?ZtM(!QhRcCt zzLzSXFbQY6*^{l)d3eoXG||YqOlY|a6su#aoED0`o_lMk#JO~ zP+}2SLtI>_yE9^K4bJ=Rl+4JeMP|hQ1K8c!==H)(;0mzzd5Oamr<@-VH?N{ItkY_` ziwY_a+X^~-Kzc~?&J8n|2q8lWC+2YT zXtKY!kD;Npm%?)|vwgpThu>l%!?>2N#T-hbR+9jiFSK_H8F~Kx@waW_TCSOTch`2a zgfbvej*R&NUp_)ET}6(ndiaWgi%}3xHyqV;(K$oYF^waxIX=%_K@;+rrE2l3G9)*rBO5aAq@4 zv-%N8#?00Jr;kBDs+nwUGXO1_FdzYIED(KHT#OOYm+8eqNh*Pqc-doW_>8&%9cvt} zO{>lT1nMM1S`cX<%O`K-7MxYnNc1j$=UQ#tOswHy|PkIA5NR%}sOT--L*ZZIfd zRKMMP3)lc@i4O#}9+M<#c zeb5oqqC<>P?u?}$zp73@X0MZhnNdy+K@5Lz(wNRZK0*4Do`$zP-O;>)$Ct8BzxnJ8 z6$(n-?%ZstB{-$u23N*ozeiGuzel!CGV3JlZK*qtYO3Khay?D6e&{pOn1xwR^2WMf6y=w#MQrF^YcE_GV z*9fW63D3XN+qG(X<94fuaf9T4?|2pEqsYM#7cwRe^i^3u^b7`}_)XubaM3S2qt&2% zh_9CnePp=NGm+byB0Fem zhLtrF$k?AOOK91iLL>0d6%=6gM$PMNwJ6^B#{bU(qXV!&qnBVU_|}F`qsN5q$b)4Y zr%=>?myhfAQ;9Y6h>wvyJ}LlAKX@l$CL+Ka;T8-lnyA?;2`%rGggmgFO%^)RjChSs zT}w7&a)+1MCNuU<8}vC_w`%>Qe)$)(2obNXID|Wxtncd`V)Piq=#S7yNXOPa@cnB+ zQnm1YsF`Fl?O_2qUXzO0BvPEvkB4JLS4*P<8~aHkW1<=yM91UscF9|cBZZdGaZ;~> z5HaC_w=+K2AY$UOu5ZM|K@lj-Z!}VsS<}5xjhzt9Tk{J|O*WU>Y2!FJpP4tyQKEc! zaQ8i*u2WY23z%09n}~{(^ZTkv8LwItC)Js-9V1vke8rE5gC7lv>&0cXiGmK zlQf@6FJ>*C%1N6F$`Bo5s(-2^i4Dsv`2SZp@>3wesp^{knBX4n&`V<=WJ>9VX}ZBJ0$age^t!-$MN#GMT_9V{3Kd`h``=$Jhu zSz8-a8VC;FuToFof}=Y)Hn`O$B^yQa?f&t@XJkbHAH23vYJ7|lYzM7mXLzjW6}V$O zxjwG$tA*@iBAXqwH2WT*LvJ`z5z+Vuq~eUAwFQZVQHgYJ9a4|Aw&FcUt}Dh$+(F!&7R zhd95K)%;jEylN9XmO);C@!zci7>Z&Th+=u-9`B|eDd5MCSeU$T&0bxavww{ciXe)- z8~$OPhakA_}ngqZ`_5j1T;eZcnGnSxZbqRC^>GPktG zlno0-JZ`Q>5Twb$goXD%R4FySp`&z<>HX4xcCj2I5qy*n272cJARR$2j0Z%n=T0*) zcUu6-)JoAk7f0uHv9u>xzO4lwILvU+y}8f(Mf`vh@Sou2>Oog+$!yzqLN5A z+_}Hz+C$Z(00~P(4_hMn9o**FVz8{CoAlj^HiSX0CiVC9PxhmWNf(yZ2W@CO#KT52 zLK`!%rdP}=bu%9M>r+B{%~4L`23EK?_R*mkZ@!w43~(rRevaB4QEGSEkPFr=9?#0A zJ4}}++WnGT$Lx0O)VM*ic07_$D&$5gSJq{gm!RFuYv{)RrkQA;Xi+BxqU@VUIdm>| zJ%5`Tau-WwVFET^3oMhG1OL3Rmj30#!g@|*d|Zlpav|9Oo1qluryqF%{yt0qPj{|j zaUq~oyz!;6L;(XhI=5mytpcST#}9|$iP7kKj_FY2Qyf1t!7}K9dQ6Fb_#sAVOoS3^ zd$L6kJE7}q0wMx?uxPmsBcnE5_P&ezb^rW9)(K#^KhKpi{A0OeCn+vK-DJfrgA>?} zxe~i~5oD#rSou{v-z{qxCA#z6!8&p+t)T@jgEg1wM?H7hM>=w_aq#mNeIuaETyOy~ zSd4fNga!$>-O)q7P;xiE;C+Rg=R+tvMrGu)!`)9e{8u_`}I@bSURHDWqa7 z0`n;?{z8>zO#Z-fBB4YeJ@!N>H3TyF0&k6%!5)$O_P2Tib-9^ViELMzwDpAQFYgET z^N&HN95wlkdI&B@l>C3lcTdE!rsm^=&vNzkBN@vJp9Fk9i7W|q_Sl{LJ4u|;;QVbvLU|_PDXDiWCK8s_{mJC7uoEN^ zLa$1js7~z4%;e){el-B8uxB}Zu-5|jOK$@&P@Y36ZqS+fJlIh*!A*78r2t#qZ^*P^nxrCtB_jkmkqGL+8MQMeaTvyD8Fc0n)dQ{cBeD zw{S+xkIA}ecPmj?w$w?GZ8t#@2S#X^@~k7)HL{P{!Iav7?ElaG?;}L8`TBh9*lrk< zx04?XzH~!cWTA#Lc=8vTUJI8~*vu|bWkT#FsBqy##87F%G0gvO|a zjsIIf^mmlJUro%{;K^bSop&3n8aSwqC=V^;*NifJD4>c21)tbKQ{= zK7>E?`5fn436>El(uGNx%LJPs4VoJ}qNI=0ZkBt8dUWjd?3~R7`#tfOU~U za<9nxR?C2)3{F01K(FARuJ`BMieNiec89_6?{)iizMvY4NMdO=hM+rK{7fW#0dS{M zw^+FNN@cEsVUwiaRKFc#9Kpl!!)9}*!s?+T7Gt+AGa!>$T|!-c32qWFB0zBOwyvr? zj(1Y&MHQ-R*FjA|rDjr}sKf;A1s)K3$IgLIie~(f&?!{^l?$bq{-Ln1Ul15FNcE#X zLuuT~Ah|;PP(j!8b=N(gs}>AZfa0A396W;#&Y6Od7|gd_$T92Lg=1-7sRe=t>~Qiv zMnTu$#+loB_?)4@wa(@6Zzs0>?FWeBp{G&@l^hY8Rdy7MfHI+ zI5$tPBAAb&U+bMq+5BH$Vp#r0SDKeVZA)rp2pC;tVq>VH;dm@cUuvjzkJzFHkNM~{epO`~-f;r!lNUEDK{*rdMoX#Fd{6oY`QF*OG^Vn zsEgqRu{vVCuGYw8TtA*o8{37242Q=>O#}UC9|9r38@&9hj!JGB5q23{d}cvevf$4D zAnu9?j>Pda{4zhlez%x-;%gbHEx!6GU=Ak6sGDIO`+#1{k^HiNd^i*K$P7f7cziLY z*KwwG1Y;BQo$>IF>U6;0%QIooF@@adC&kG4)~{`#+CN+;ENyL#xbhU|$PdvbczKGn zLKfSfzu6rvJ%uqbYTV6GJDI*Eh-hQPc$u#@Rl7D7OBqbHM~|#PXo#V+x!hw%n8;V@ zjMQi(3`7NL5j7+40WXk{8e^#6Ny=}OtjoDD&!FU+GJlg>x~8$3b+H-A@l!Ow8Dzll zg_>K^vrkQ92Ua^83^eTl!O+vi=Y7swF|qA=T6Z@3-ZN5>#N>SV738flkK-7$>Ye)= zb2d+0zN(3Asd8WiK0Bn66+Ri691iOIK#KYe>Ghn_Mq9^542iRNlfm`H56uDy&d$yc zdK_mR6_Ntiv|9m=hZ{NS>kr+|ut!5{pJ#@O;gi3aM(xR70!6ykvEt&XCuuL7oN-&j z7`0+jL`j&FkFLuxe@^Mj>PuFq^t&jOpvXzu_%{FZSpIjy05hBNIOzT?i}usDfGq(_ z&L#+4<41`lSvbYiya%DBPrDFe6z-iy?+X>Up%fK+V_um|n0c9O$8Tv+R)W9b$nxdoUDAnOUpJ2t z+TM)&Y4b7f9G++ZxXkMnHeYICdAt(~D>L(S%m{A~SZv7tiMaaxxT=XsMk<2GweX_+ z*$Qr=9N)cQrxv&lOwD#7@cC%^8y8;JI&4r6%DFD}$6si?K}y+MdY4AeWpaT#2lE?y zg+Fc1DaF4vBBj^}q#L>vLCo~kLU<8PP)h}<3ZhZno@a$=s%(+*`m1-MyOqaB)0?eV z{W+5@q>*L|eNHUgk1J_zx=b^oskltcb&TXJaNrgk2;Fc$C?w2|wT zeQBUb)3`dS?Z~zT^>;E13;QNaGh**)(6sgW+UBT8(VZYJYuEWnrs>&IN(yc(Gai4k z?bG8^u@UakdOGhjzNaldYHxBroPmLL78XxQ{zStHb=-WN7yr9Pa}j1F2^Rk*QH$>ANcIVq~c*i%y`+NGoh1wM?R?NgUFH=uE#l<=|aP)78V?@SNsggn>>FH zoYJ`0A&t24S$qF>Y;XVd(1gf3SbfYn-tIlEt?liq6oNmgs@)!OD>=3^bmM>beW#RR z*X@WIT5E+MA)X0wdb=z+*}pOxPB+Kx*A zr$m4rC5y_mxUcL3`CJhQpTzikG;mYqLM;|MLLkqmyb(5}2HWUa=1W)Y{h@t=%)(XXT> zHp++9x&Hmq4fUiiB-r*+l)9Qv?M*l%nX=X#r|y$b9J{5ko~PQZAOZLwXeQfOuMhZ~ z{g~nNBDo%Xd<3(&AEQBz7%>ko$c@7Uf(l<`=f?jb-CJ1!&K=6oz{$`ThpQT!?&6pt zo}2Hz0zu=0fI1H;p58b=q_Eu-k+Cp_6>0*pNwZ`}h!X@*^y3aR;E9(P;!zp7{Rib3 z;-^eXAtZeqIHC${=Sl|SKoU31gI=2L5E@Z=y%&N2d&afZUqJ5;W z?+RO6HJzQil8bsH<*>rJuZHjW3$S-*ZTWTEY!?1&E&EkprHb7tQ^w`%XWP?!2|UNs zg_CXZ79^-{EZEby$XMOih*Y}*bCRzpj#>f4qGR)cWw+hI~rGe+CxoG8eB@JHOe)na2J zI9u~-*_C^{XpMg{Rx3i^-W*r#`K2d%Qotx(hRY2bg%v%fX38P2Q zNP2L2^wYWPixTphS-DiSMqXd5C1HSw%hIR&yYc1@5mygP<4mo5HXA1#O7YbCb@Med zn^;q1_RX!6f|rqB%3^s9UvKLW^~V(X_f8a>UlW~L(LgH^F7oKBxGh{OdUb|wcpYac zq$c>a40BN6K)o1=aGjHWxWw$Yvm{%ObK$_COYq8<;$&%OhVrIwUIJV{iFL&RK!n03 zdrY#!G{2;6vCDpJnG~^ZvkYqXi~UsB%tvH`!sS!*woQGgSVh;0xz>dlC4s@evhRTV z(scxhPh%%1INuDu0EW+p&*Yg(jiVaYK8`+@OWSu|*+McT!Gt`E>39p`03YHUS0H2- zU?oajOYonh^;XWpe+1r__3@o-4o0u_;_esph1auUbui^OWTQ=wEq-Q(Zo}O44rJ{j zN}6-Vyt+K;i+~-KX=MqX!8D~w+-JHv5$83C1%YbXL>Ge$fc1F})-K0+{9n~V6;um| zp%gj$mNr^*V@&~0_L#JQoVQzCb_!p#z01K3Et!Mg%eG{N5&?zz(sKh4&NdJ`eh{)s zozh|GzPECkNNGP-kn%>x8Jh;KnJ_yf; zAa%>Z!5&#cpThfP?N|8MR5>{dWM6ZIqq~)##k5x!@n;tPWIq1N>?kGFhGGB%b0T?I zr%-bmqZ>hBb{lH%saX@aj{CwdVr<}U21p`{7EI*0hTd?F1Tx*r!xQOFrW`Kf(cp6#X3LaJJ(yaf@ z%wHx88`w1iJ#1o88ssa$_Vf4GT3t_?*COp-9o<~%+22zF(v!K8*$8IVd*Se|lXk&; zwf3!3Sui)Qv+;EDW{3Eh!+!2k{o*fyLa!?456i)R7@%$zWrWhhkV7c;y}G8|=>NHF zeq+j>NxBlWrND&?_h{;Z5w;Xu7#`7}>A@S4y>fBxC&N}F)1;efP7$HrOG-3;I%Oe{ zJ8;(*`6vl?iYDO;4QPLVTNPj%ars!9{PLY--HJavRI%Od^WZ4{0|z(|HX|du7fP7o z?J&_A86iJK`!pA1d+lV(Icb@#o+bC3bxzu3-j(G$PG3PpyQz$v3Eb?aZqs*Wd+y{S z#S4vTiA-ccr7~1~zNWz}t6`^X_o$wTCcMjf;ir|nmPFv$RA}Gr^e^1Td>tQ^ZJAR{ zy*u8jx8L;#1oZ{sL`hfL6jyD+RLsKw5%?x3ZSU2)Y0u z_+2VZg`BhI$2sweGz#{9az7-z>&bVCd}Z4#(fOm`mq4_$9#E8o11i}vs8HD%orAi; z6@eI<-F;!J=1I_}hVqjW!-KU|QJWr&xG$qn?rv3w4&Ghg48cyW^vIk8oIhG_=VY>n ze#>~jjBCa(=Gcya%QpW$mxs!4Q90Ejh^wS7=l*ZX$F9oawKDpOkwhXUiL5d&Va03G z|7hD^tC^I5k8=o=l{pmL9UKf0sO=}%IhDV%03CI@yA|D%QAJeZ!x3Loo>6~EY6~bZ zAHLu-uo9Xdg7&eMgj89^c@#;RLIW_^HAFo5zSaSm8Ua~eT`mWeOiet+b6pSPA;%+? zrM20=w50UAx*)0|@_RMp=Vcg$;^#DZKv@YzP|lt;cXc9qgn6m2*IIg+n@Mv#v;~x- zc>&S9d6miw#xb=2KZC%jw{p?Qy=2p&*(nM-nIiNRmheBj#5abrJ}A)(tc2(8-hjYI z&OF7>Df)t%K2M2Q6SC_vqH_!N)7t5=+5jPFzy^<{emH5jZ9O8`la0=-lx?dDj2APv zO#C0XulEFhyma!;W%vs(zJACf@I9Qbm(2of77A3;AJqvB=Ion4YCMafxeXoXR(k(D zpmX}Sxh^XJb_SzfVELa&(LrMIz%a)%-v?VW5xB10&NO-|E>5jk+fgYaUZw&3T?@~;0#Y{_4 zf|F}DT2De`I--KJgvnxYHG$?1T|tm$Alm?si>C6z)Jdt6QUJ&0vo*nb)pC*79u)L( zEHv$wd*6A0q_agjXdG)PEK_7H)sn#&ut(5MHUt|ncHN#XUB7U5G=vh;iZGDbW`5nK z^jj=@E3oHF$m6jQyh~p!B#C6wVKZT97OM@xD0V!HPqvr-GR}N~g%f&1bxFoQbb@-P z101hj>vK4=i%s{#eDH==CA+z1TrT@P*Tt#|3HMqx_>*u+8!l*%xk8S*G6plvx&0ki zL9)X_$e4&m>A4}iVq1uaeW}@Bo|Fu{>n8*TktFQj-mP^FkZNyKWS^cD-VGPz=o$%f zvMMR!YyGAmzaIZa2tqedaK(f~_|5GeG4v(^y)y;%L1`LC5enT3IC;a%KS=%~(rZin zfs2rsIh~ka7li0^t&Sn<{>5inu+1(93PDyjZ$srH<ZNwFK1%oecDGU%S1Np@%H5;#rh)3RSQ~^ax!ZJ3m^W z4$M&?(oQdwT?;N;1RK~b#nKc%vxcL@O$(A{g8Ewq5jcB|v{{6zcDM>1k!cu*o~yhdtrvRyXBoc*>W$tPuAKGXqA_F{`RE4CcAoj2EKzK76aK8|ScM zAThdU!14FD0HC{4mU|Gp9Nb#?*Tr!Ci2NKfDfoQW#Fd)-9JPumCT2H08Jm-_*3BLG z37GH>i1{#Sj8DeK4(TD8zNFLzW+UEWN#q5WFgW@NiT8c1b{m>LI1 zpnjU=|0+Eu%=iYn(D0k4BMe+NGt9&~HP_^ts=~LJYR$@;AvS>_2{=fseppYwsJq0n z{eiTu41w4#Ni=45QJ<5a%8}pGLh+cGTgLLu+mo?Ne?ZG0+oU7vWax})5ZqOLNka8y zT+BUG#QL~|_9VF&$Epj&fbLpde+E$+eSrhOwQ5|Eikkb`*BRFVB>KsbW|r8Ewa2@} zdk1P=4aby#j?vz-T&Hrk4vm8J!`%-@diP`u)aAMEa9clEn-Vwe>9D=hYgKwcP;8`h z@@;;9@Qgl4FG5&N>ALQDo3b7FB$4ZMA1F=cxW#hTHB(y2m2Y@7+j*dxY zDzN-mzcaO3E*rUUA}U%pqWl;3{1weR5J=K9ivbO|+Cab&2LeHdoNmwAFy^0Qwub6e z!0k%U9hDbbfWM0k1K@h#5sSh(?x#)Q@B9whk_p>RC`fl+K2;s%_kl%gYk8iW8aSHD zdbU75NiX7+>fgbe;rfBiV3lE%oE6RwRZ7~LC`SSM0`E=h-WUT(Y&6;mY5D>+kk4z z@A}$~->&>Os_Qi=>V7qPcxGhFWlT>=yBIQUeXwrsZ%+ObHfeLoa=1u<{0qSW(hA|6 zOynO}H#tAnumYrb%@KnV&MsIGKEp7Pz)&Y-J%foT&isI7DkOLH1fUI?lPfU|8MrE=m=_PnH)Qgz=WQpSOWG$AS?&``trl}4)u3?_$Or*6WA#N}QUeRy> z+qp7(J@wV`qgEFd6up88xbAh&F}NFViMOBP_0((?l7Xjs`TBW05-#jph3A3yp*Nb4 z{;P4(AsVU>^8Z&iMtkzVGbd4Cko@W#GF(kyBxJVwY`*x$+ zpCiA%Iv`LY2o;xymBtyMMFum>2(;}-Du^Px|MUbn!tg^(2klaCI=B`7*>`jj4kRj~ zrr`npRS^I6!}E{`RKDA<97o=$l%!&H;zV(s?wu^{II*y?gVF3nCD~-61+}?@A3QXh zU}IVC20INEu17PSlC5ANYeCnOYn4f#6RL~SbE%M0d4Q7LWSWoJiW~~VZw`z9n&ovj z@AyQR{-I<%cq}fl2hdacoD0fy*vYBM6W3KY&KsM9;;i6fp3(2uQr>w zvH+QrT&KA|WqFL#;D!%Nm#IGRY@WGfj#wBCycw3-k+FU6Y4u;cz^FVtRs3tJx(R45 z+P@fM&~&J?^ZB`%3l8nuWo)<48CZlbF>baWCRhLZlc+i~L+5*4|K3T*MdrYIHINLH z>fc|M9QN(n5b-k!r+(QbB&D7iMlVJ}Ys2A@_!~0)KvH>3)SVW}jYYc&+Ike4YJ->z zBKEd$7~K}Q?Y9bK$eq*g^vc6pEkD(DPQ;`MGYU6;2T3q#M2v}iN;Bwo#h1YIg6wMx zO&chXHc^_?P8VnJS2Zi@^L@V2S&0C8n-D@ED;#-QGkMc%tTMBMyd?_z8V=J)dB<@*~k_rGpwQz7HOpM{X z(nzol$SQO$4(8pI(Wa;d8xa^xO^%W-ZdAE;3z7E=h*eEuC1+s%&4p;z*ea6 zDL7;s&0|^zh#g~F{~*;`E+iBq4^qvwqe@NQ+&rXaQvQi6>rwuP-1%8q8KAxIu&tM$ zQMaw*Dyn7z3o@G!gn0@xgwZfsW%BIXg3&v1TKM*)Q-QYf#e^ZZnVOoDjfxgG_DYnMp>$2w96OJ4nECU-*x%az51lBwA!t{^5B$gBwR8yHtJ< zA-6Q)ibH)1697PPriZ;Cxp$|nxg*eCM?0`7Hp1*EnE%5JxBxt3c=-q0dCj6dd`iF7 z`#Z1QnZY3(+;Ejy>R``!yiB5L0LSMxN>FvPaq(1aD;g44otqHZXE#1sR_lLe&GrED z=7I)zZ#>BYzC>`Y1iX-5qjxDPd0@Nuo39RmCX+_-p)M1{vB-3v-n*rZw*w(qdpc?v z0V+4K)DMeT<6(F!<3u;`{xWMuEc<(4p|zf988qK9=qKnFDjl`n$Fb#?t&sC+22C&8 z{*6KEBj3##;}k~hxV3zyzjxTOQI&aJ{n>ydHIh$a>9&|?8Y`Nh26~#b=m4w?g>JEU zyH~4AD07WP1!ZWp*CcNP6EE%V+)tGJXxOacZ-8~RMR$thqJPa!oSeO7{^vt4`BhFx zfE5m{R@d`v9!;Fsrgb0ZE$Z=V6$-%4a!yFdsGpaECt&rbnQH-Q>U zkE)CQthDg*H1gxJ`7TqDt`se##&U3VWb#?UizmMjHG(FP<7II%YTZ^R%-Pq~`Hc}p zBtAYi37#T5OIIb%7EjpJHzu`u$YQmfxKIvZNE}g>0Z(tA~M=Ys7 z<=^J#3il(?I~y?WqTFdqD~h!81!6(b(-xXlg}RbVy>*qt;i+C0pN9`mZ#-5GM`mdcHiXbvPU;E<-fM3+>n=;j@87#* zBk7o$#QwTiuY1>WAj4jeAls1PvTDFw5Klhv@)J{0(i4pe%_)qcwT9PdS?k55jzaj0 z+^@W!N&mhQ)}db~1BWgK8|4*xEPk32uNr2-t)N&E;<`RNyF%!hbN|6YgkP@4D~YJL zO!NJ+u??PbC{Mt6o-?GoM@u>Nb@oA5ax%t_iu33!tr%Bqm~eL@<61hn%{}bL|8hTAgjjE?fQ-KIN%1(Y=6z)r9$)dOnyJ-c zgjf7kaAyr#Ux#F1W1ZDQtWrWFX8D%onBJNZsxK*(h&X^vkUDfweopo&BGVgp6q>~F z(@R%QDUIHKI#32htjx4NY!Y|Fn?T6`Qq>gnt#9Gz+n*Q-wSyCcz;k4G6B(DT$KZ7M z0tu!wd31=<2SZ!afl0@P`4GV&m4CdFUz@ElcU-1{ZV03uy6CFGwz6p7kr^0aE9D*# zPTFuC&rUk2Pmud|44=Lz^9yuA2HE`da4DmY+a{cJ_zfIfL3#C~2(QJvk=27s3@-_v znD!yv<3V1_g`I1jGZkM;mDH>+Tgv}1pj_bBh9um#g*`E#^v7?RJV5;loqI`xt#BlZ zncmEv+kLED-c)k1Mm4)B|NTEM7I)JIFJ@9cVtU}vh=6K20B2xNn(C5WJ1F;?a0*P_`nngOTS9=D^EW0y~rgYsvbIBnTi?gx`zkYRx@`Y=&Ut| z2$!8mXb>}^fpeInSXWysnAdwhk7jHw9_+(4H8w3L!#N!b z_H2-?n%iiYc_KcjhXMdDQENhok2*`>{B3ZtM+6O{Nx4qiT*|&U@0yZa_XOHXB`SQx zEdaK&E?#tAF!2#(f;Gwjuh2dc`yaNaR07ywvHh+B5;ZJC>zGq9D4fjlt~r4~{3mV0 z2IeTX8;qme-k@ zm-Qw0{wvwwuT*?ZAy)5sE0jYj`vSA z{coA$i^DL7wq=4ixnzf926ycEF)Lo;zV&hu7r*6O0~c z$T(F@OpGRLV4`?R)~ZQE=Lf7)g>}0Y8PhJ97pW2Hi8Yb)+|SuuYF?V_3zi56%qC~! z^K0h13H%-RejlIjA1?Y&-cCc!wpkiSdvEJ{UlfVNcfyhH)z~61!*oQODZOqpFF&Nz zC8XYB`?Y`XG*0(SOfv{1rn!*%<<`n(h3d=(u*uVEsln?@N@%ri3pnNzsQel^Eq762 zV?GKVi&J999`V`!(UtLTG%|kwmrz~YUQh1fW_<2!GN%Tnm00T~K<>>Jk*N6%juW_L{8%qgiQz%b5AD_OKLjO0L&;GGh*WQXgL*25nWLn-|h z)&pg)%gl&R<;G*GM2xH63JmB#so=sk!aMw|`V9IMG6<`v{H4~T+H(u4wBbR>)0kbK zW40?*b29Loj#$NEn-`SGHk*qrnOO-ob$hBN4?S$){3}gsMDah9=||#h@YT032Z+!K zObnvd9Q#hLdiEc~&ReG-i=ikpqq%?IL`k+PkMpuU9y(}$i$1z&mxd^g}H> zeuAvH_~rCe%N8q4O!i;m_mEZfy)(nTeI6n53cM*9z=iEL34ls5#hS!j~@wR{$ zZud2Ib#`?|CnjX*V{36Ne47X}WNp2c)5`y93#wGcG3jW8!svH~y~JpTgjVPCF-34d zI1(kqPOQ^PSO~V`SZAyhyEZ8ZmCF0s;H>o zQ)Ndc($R80LA8UJ5JMojNJ1oIwDa0a^~hhLq=D>xONfd_(tj6P>gl@MoUz8@T`>qX z_|w1V1q1-4<`KpS|LY$5GQDMfkz4?3AUHEc@Mq>`A!Z45eaU^>Qlg|Q_kfWCTUBBr z&3D-6XaafYm0kv}07|xx62pgSuwp0RXB|9;-z1!qd)8!Pzy2 zvl}$eS8uH@X>JF<08mxRjtgiqv$lvRZ9t%r{qBI~W}J~>)9A*+UJdX>q3TI-?w z^M$lzXR!TDjmm=qMz~6vscIYwET==pnwr)wa?7>YTC-=hwF{)xm$a6z4*L52y$t$( zP(K*D+%JP8JUC!N@_@@Qt-XKdwAtK7+XlGDbnloIw|r--C!8RNfd(LL7SCV&c!F4c`6$kVk0G^uW`lKQ#V=h% z;oFxT7w%m`js#C+uQ3zE>ATl>1`)fdOjX`B+ko;R7s}jaAzg8Q1FE{naeBT#`n9)EK3w8O|4=j{sfB(*tu7~~k62rzh zKa#cxc+s*xLS2DjR?hg?AGKDKObh}8k^zrS`v{}ctG*7N!oRp1<>n^WXq~m;B{0E( zB3-Kmw3~Tb<#MR)zn2gZG#WnOpXyT2>Sk+jhAIHP`Zb$5?_YJPRguV)rW1^!S5LNY zu~UqJ8uFS(Q^nnHd6^t}EiJr`(;T96FX0+qpi^$=s-FH+TSugh9Z`gIRd>nU!Q<&? z3i4?deNDHv+SBijCN$xIH=cNDdR=pd^L|vp6gYhx zf<1QSB0PkV2=Oa)5GL%hvsafLvq#o!N6(pVrET90YfPCBA?c-Wws2ru225EuA| zL5)Y^n`JzG(r4Z7^_e6!W_Qf4om%;CeI*1P^pFGYm|GG+GuQ9TUs83+8zuSU9oKpw zhr}4mS)uP8gdgq2MarSYa)RAK9tR;Mgm^c+dt@Kw0pzuEDtf^s7etZVK(@Mr#}of2 zR5oBXce%Oort#YMo6{l3?Q`LSmLwu0q5jsLwU!oY;^&+sk|B(!p$YWl!& z>ydz9gH^nL*Y3Ig{R1+xk4w;AuebYrqQ(H+iO>Kx=CE3yU=Sy!v5CX6saI)CD<(Zt zCE8)u6PR?LzaO@!J}k7ty8KL%A4yh{txc?~PKTKQN$Ic_xLqdErm1Oy<7w6eY;R0t zR0dD}ll$U8o1Pu?g?8gYxO7T>pS)Ir#m4&($ zPiVjzUMZ{waR^=S|7K?nD|nY2U=r;2=h4_H&aV%CVg|Y*Xh^TFT`TL7T$rDSaCpqp z>AcwqMh{{CW8$O^vTgPv)LIhvypq_mQNq{2@p@Yw;^3qY>|4l0KwObC2*wTO3>4^+ zL8rsDM!^37KFUN?>k?X0pAa}f;1~Me$q)zI4|0;nd;T%>)pq_|pAmvHhUN7Z8=lB={vTX;i@Q%a^Dob9N!2N(GyY^zj!X460G+L4jO^2R%&Jm?7MQ^`IoR zm}?u}1|1sRxNYOfl~@DACXuU8i2bzJJE8Tv>0fHbR!7*^{q*Krp}a9hC@s z>Bd1>m6ZQ`POk7uv6}@pB2T(JhMLir7|{LWDs<#kTiU}-aZ)K~ZvZXSdbL*{zdpWc zdW`pZK13DuZfzo;bs@r6slrBiXiD&cQhoLIQtwAq~Zl% zLc&t5cZSFee{_GGKw#nFvM~5u|0|%A z_bE>?G@p|{J_2zal$!!R?98Cm%&TjGv~VljfGoPK&`s1T70NAH zs+;ImmGpT(MhO-di!2?McP6+Z?TvE!LvX7-Yk+#s4{{<-N?2(-v2AYJWR@_wuaJENVW$edm3F+smZpW zKG`4qW!cs}c{fJ?dGq~Kadm)cCwtT_k`Hmj;U~OQFZgzmUNdOQNU5R`zZ3pw%CAn zY3P!$rzgNaJfcDrzoaQ#Oj!_(2-M+UsTLxjd#bg`&AKZ3S58rUl!L)39w#1x+b|r9 zsHGtg%E44_Ah6Fz$k54p=ol7+1F!SfLu^107@;UhWLc~&9bAJkH%IP-ea54H2;}~M zMmW(&t1%Q#24uIimUK%)zwjWAf^HV5`va4|w7CC7SsyUm&4dB75Ffq>g_?{pFwMl! z&|x$3eQS9+H3N!fX3VBLsuFH+L{E}PY4mnnY5f44H)~^Ka6@Bfqy9%`%AOnE+3hfr zw!G41v%g;cpe=;dkE@=LnV5#Rg}Go0ya^Qq*~Qw5FeY%cUYA{}Yj&(TBVnDcv?4E(FCIAJtJn3tfq!j{poc~heG*t!+ScKR@?k7v$({8-|_f3xQ&Ap z7B?FCAJ@Ofnp)`;7L0nI?*0Pvy}HbKH)WD}R~;|OUa{Np|QPxipD(i6Zj51q_YTDp$bioB+ayXC;U&ZUT z18Js2$O&A9vpG@3*unTBNOs*YeK-C&=&GF!EpShNp_pJKsx=;Dg>}VxF4Lz7nbQl| zyA2>MAQ{^X3pvTPanR(AA|{AGWnkLC9%Q&Iu>o2hI38rHLtf)>CRpr(1ZNUt;6AR6 z0oM_hnuy*6-D^6O;7l(9TKRT!L2@cJCzsIRLl|Yor8Z}$>3+Jfw4uSu2ZhO9QNZs7$GZ6|9Ppu{Kg<`e0!J1&s zcBhtCs>=#K!CLQ+XGP?z(V5L}Z_OJ_87hSD8J~-uA8p%$fs;gl_Pt~rd^#N8w*U=+ z09Pyfc^|u*u87Gz3gk&y0Cl0%$Imjd!T3OjUErx>f<3zyXk}WAlgKjcV(%R43Iou(1q(o6G%>LV6>OEmheJ|j%9@9vwsETQZo20 z55oe?XEbt7!_W|%-4BYY7Z(M_uoM9!6c{6xl@kZ+$%{T0W?{1WAZnDtH5+UejB5;R0^ z6*fsa|E2PLwF(80JA(vvX9&Vo^xUL_r)VvKeZgx_9+?uE5&%SU`~IN4Iz2AMv%OeY9ZXHB*t$FpS;~z=(D1Ul;$`t!{S&$HV76MWgd5gMTil-~ub8;!DVc)D5t5UC$SWa_Q`c zjk$N4_~TZ9j@69i0k z2BNs!WPWB#hMCr>vcI=zyVuYW5+dr|WB5ZM;82WmVE^r>2qk&`Uc@0)HSU|AevR@X zaZGmfir&lh06r4v@@W`MZiGtM;Ex#Uqj8xTT%4SYc6i>5-&ImRRL(R8bg!OfTnOa zlC+_wTtES=rV&=d1-gOlNe@kWL24GsI=$}5?UzFAr$ z-<3R>?tGaj)iVCi)!fFiqvW)zG}za**n0k|3B<+~oBfGEb)>iPKKHW8;}XSrUs>Go z6H19WKeOjuWlO3HELZ}7yNt3bcJ_1PiX7P&0`EF^6wf;-glm|1{sVit@?|BdZ6`53 zuExBMT4<<(avZFQ38Ci_%J^;dW_dQMZ0A}Oi`Z}W6A_#lbR_H~47=h*{G=CJWr_+w z5#+nqu>YvTTmScV2LM?;<8d%Gl~qiny~Hzr5GpBg+7zUpOK(5z?Jig#mo`+*)cJhu zJ3nZhO)tQt#cUYP{eL`tRa6|&wr%6??j8v4?h+h=J2Vc#g9LX;a3?@;_r~2VxI;HC z!QCAm_ndd{cYW0uReP^B)z_ZCoNgLyDXX~inoX|i3C8*|qoB$!jCqHOaf6DwNsOj| zlEh)^N$E!H+AFfPMNaSoA-o=+3<`XJZVbup$`h<=^L{-WZ(x*(N+L_Fe(7klIS#*N z?{vQ(9N&jELIC)m7B{+{muX1syf?nK-(GWG!H9l$LjO$&nu6@toVsq`3j;uNOpyRQ zgh*Da_q%2aD{IyOQuf3Ta08IWXIZn_x%F^q2e}nXk~STFRZp&``wTfZ3}Hh3=|0lPaL3@MeM7&t25c#ptNZ z;y>NtANU=G%M;9)J%0}zdDBerdNoqM;#P*h{9^esE1LucuRkga7mN`XYh^ zZ|Ji33!|&_>+^^^rXRe~Wbz`Fjw<)e43nD%uE6wMx$WN{wp&XVsV0wRACQiNziZ5N z+NAsq_M(UVUvJC%OPuB{@anooXL%_(KPVP&uiW2ka#725n5eytem`b>d|wN8)5IO! zf8Fb7%Dwt$&E&`4y8i6ivko1HYFOc5Q8*|eJtpfQSG!-&R;{02U*~T*yh6ZLF)!U& z{q~kJu0^6r|&&yxoHIqDVhdKVnB!sHc2dML|l1p?a@b2ZD1*E&G&#P6%tey^Q$d{eJ0AN@i5T?y8%h)&rD%(=67luf z)SZEnyVg)5%w6f75lUB}$z-|>j|vlW9-e<=45*5Dti88eWI3sq?6G^|BEC7;fqx8h z`Fe!GmQ^!lnCwA)?t7<>C;G{o%9PAa!6<5eMOJUKkVO5zm`@7SN0<+r1!!|5oTU4l{8P-Mvfi=uZ|dp9$8fuf^(Ow&T;16k)R{t_;8Xaywj=r+7&h`E1sFq(PYOKE-)M<;W<-Mm;*>Y05}Q zj8JmUI^00)Wj0O9egMp%nlTsNQWyz_@Iu4C!!*WJQ4I6mEP9OM@`^M!bPVZ;g8st0 z=&Uxr5+kCPIBa1lrV&#*e=F@`t-A45Q2bvMl(|9Ohh>^eno2JjqqoLepR=nSe<6n- zYJx=pjV)KUYO?5j#@U8hO`Qx?1Vs!RuKH>29&cXnIbvcw4b7F~>!gqRcn!^zk({KW z%~fnN9?r-o*tg41Q5C!vlifUmZ&?CNYe#P9H0rQJ#vylj&^FO zVrrk1j%Dxnw7Q$WR3H5<+wpbX(&y0%``$nkH8`;^c`??Twp;DRFVC4={!efu&qra= zqtQ#`mgW`1j($!%b~q;$OUBPTUEPnFQYNHNGXxj#+Nw&G)EN(>DSt zq0n}h6wKF|$n_kQa>BqDF~_p)i3$p`VRr_ezJS?k@#^HqtCXGW1Qinm=gDK zFO?W5n6Ah3kj1Hwoj2>LW3CO=wddYeg2L9N+4E1`RN8jD#@8^IYL%R+{32_osjhEb z(|=;4&dnU+H_U8~Ir;2Ol09<;{m22%k0_4_CX<#scGpZyTULK!Sc7C_Y%M>wHCC5@ zSRTht*BDl$e}HsEMMXsxK@A??l9kDrWe~b!R4P5{C{G~Mk@18j7Qan_Jxa|H_n%CE z>tEq-@XIqC-nW#kE2y+k5gG2M3!#p-urnKeNxbU8SNnl;nDXL>KHC%N8F&cO%uB>m zX?*cPd`>X%eRECtgnxonLnf9S<&TPj!S}G#b4uJT#Z~N48l-6Da(dUrtyB&9tZckWYRwV~2CH&QnTgeLJW{U@h#l-_C<;1L0k z31U1of-_Kz6Ihd9<(cZh%D^JBX3T`BuyHs$$77vMRDlNwNO;eGr#y`WL>vDq#k#Wb zTCC91i&&ZQZy}pVH?~qNg=WfI`4j&u_L9|@JU~12Ejx&vE}$Q#-!u-v$wwIG7cP5@ z=>rl*|347Iu7dZbXmtGR>W8)9C1hqZ0N>t7%ykv~5}WUZ?EcA5d%o6s(N|>#kGXFd zEP&WzXLRSazuqfx7Jl<#MU;%2`V}6E*aiMc`%LP1n{?9rV=CQ0PloKcRj`49<@MrJ z!1eqSIXK?<88Pz$-*M7m#EfSp+qJG)PLJ28<^X3?%Uo+r1?S|3jFDk9kGz(7gP zY&q!DMxZNnoc`EiwP^(J+wYY2RM143A~-L+@6kSHdH~-Fl<2snrMof0$jCLMw?uO? zO~g+y-v96aKw+Td48_-2ORo0*dbDoveDBJ_sn3=N)cM40(0@uO~V?3m59`G5ezTx zHfDSVHMEe|#Da)$rZOjYOD3$bFfwBBr;D8*GlosRZqU`cyEr&FNuUXbfrzWinURs2 zvs?)bpK0c9^;-O8F{Kn;^4#X2uNC>4?X7b)R1dh%P$wNl&Kxbi%V z@7{QSlk*s;w@-N&mV&k{mGJx;*xnKIH&7lX>Y{ma>xSrv3DVBBKgE7@GVb7_q#M~7 zz@L4Wna&sQ@nSZ-+zZw6Q&i`3!%;Q28TK z2|vxmVp8JIWC*eRWFdd0-3JZA>r;&+BMc>4`F^jK{Osj&sFJKjV=OD__vD8C`>3`9 z@vIaj>x$o?J>>TDXb5viXD(tj9bS-Bv;#hR9r2b#D&sr=W*zC6z4qMW7gz4T)By_U zzLP%c-cP6CWuD{e-HEr5uDdN2SfEru$I}Bd(CXIf{D9g6P{7OgCOOSKd*n=;0{Unh z{PwtmH2wpv+O@ZB1; zT4_oR4lXWtm^jU`uWy7!u{W@XJBNV6TeY^NwWm)w!&5D}kvx!UL92}wA61i2E?TaJ z4E${qO;sboPJq(3#t7teEiTxq8E-?LO}~?Gwye%5LECr5<>htw(|A@KcO%C`+T)80p15y^JFJ?Su3YWEhF>Q z2zqern<3G7d$Ai{6^C~QVb8`klh!*L%oOaIYXUprmeu0W@jU@*T>Te7U$Aq#S{Nig zN`#OYJy9%lfM(v6@1 zAjN?saRMpEy{~vzh8f#C%?9Y)c{W;U#^TO_M%!<6cG*H*zIWXd6zl7_!*kIOO-Cm9 z9|k42JMpSB8a+-~vZ1^xbo=Qh-v1k&8hc%PFbo-to1!Zu=n0(%pSNdE>w`RAPJ-Mu z1MM|)#5nA_4rYskbs2pW7K#`$;MI4S^D&L&rENjn8-bCZ&9|=7Usy-kCJB7D9tbzW*m~w z+uAttpJ!Gm4%R6UPcXQFea&Li8*3OSzfo`6+YaHa+Ma1%S+T3NzuKw`_aUp0t$G7f z@1ObEfy}*;cIO`BW<&Per`wDPgw7D){w9!U6xi!hAJM_3pgX5OosEkd0-sIyj2W;s zw9)?AXO}sDj8n|_M`-?lGN7lP5Ihf2t@yIvzVb~Sg-KUiXE%w31j3)0DJCE~dDbA( z7YG%Fy;|6IU5~s}H_;RwGI2`S_qQDQ1JXB(kxB{kiKmpI30fl!GtkrkvxxGx`YTDK zd=$%G6+u#qg$eA}{Wrer+l!ZYk0=y(ZUj@Tnp&3Sdwc)e3B{8_|n>6r6sBq&z%-47 zi?l0IwTkw6f zb4Q(xv)g2vfJ8+pxSv(-o0!=ru4-H>)GSD1} zZ;P-a5}(xrDTut?NBUYC5GZ06M3Cz(cZSi}^L!q4hrd}h$CY17PE?UgvzlbeujGiE zy+uBLIm^R6?%K&6=`zG+AE6~={Ix@0%7nGmp1;!45~Yrvp06O6!lE>NQ0rzCl$N+jU5Ri~(}12H zIix@}9_$3|5;N-#3{rkGYIaVuZrLw563qzNF)$#=(m+k(doVq#i?R()FxDL!$5~e+ zZ(2$d?j4e99jXKxb1NCD8`Oa)D&Pgz4l6tGHp|{s=UdtZx4{Y~7UTZ;ENL^wV+ZJ$ z0qTk8L+g%L{o!$nNryCo)|$uVLpB7Jzh)U4wFNzaz>jbm9V{3HMgO4-`ycb$Jv2MV zW@a%7yTnBq0fa2`;%pHTm~d^?8H3=SX0<;tistlJ$nH)5qTV;4q3l{kA*7k8HTw?eF@&o zhmx{@`V;i$uzk%xpdfsB)Kl~b8Hryo{Kxa}iZ42IEl*lZoIvK#*aQh^UMzzC^|y<_ zQh4FOjx}vr*md6@MjV8~V2`g2fT zDFZp|F(~hcCJ&d=l^v?Z{DDs-o*n)__SE3W)_JCW#hx5G-Cv48WTwi%2)?cmO8DHZ zB`E$EW&LShr@Y}v1=0iA16O@ZCB*gxcgTu0)ak?MpOPI02y^7ZlJ>;Y1etE>>40R=f#ZZ#q*gcX?$43Z=I8B!|R)%`g+NU z=Br3zylS{C4+jqk>DS92$%vySrbwwFp6o80^M&|s|ECf1&a;lcXm({2n1+TiKEQ9P zda-%rhU;o{zgL99&5Qhe%z2%vs5~{dx+Zx|$gQbEV;7mzP8v8_&u?3$}3#3*6;jVciLJ z+an{Bp0E~aAJQDB6uB@C4)Xcx((E$whPR)lhsm61_aND^`J`&F@Gs2lo0fq+mLV2M z_T4~ms;ILGI{$)3gyr-F3kE-P!Cm*sEXCAh7cWlh-&LbdUHW4Qcdxq-t1+}F+v{bB zJ>xBh{kvt#7jtFC++*F5!|!*g%ewJeedtC*qCo9OOo!T`l{YgGc2MgTCezd?V^w-S zHFM9xUwJofT65#56KBs3E9>|i{bV=3Pv6T*kxyainEhfsXkdn@nPFeRj($N^}a;_p^llj(P>|B%ZTKl&;U8|Uj@3AA~?peO!Sj%ty4ok zUsV>d(!LTIYk~>VdBt>92FLj=XMM820e7tf zQlbLvH5!%4ypUkYj~^WTk~M!rnV?&!PO*&&eVDY%-e0UyC6Xi;K+#ut)TRlPh>She zCIDv->US-+rpgxt z{T++TY^6}Y)eT6TuT_-M+<0xu0Y6K40aaQ~iR~CxzB8P)rh!Vhc$TS(n-gu3dFHAIc6&X&iHz~J zl?rI=!>*Dbn=#mnA5NJ=l8;Qg)i0(=PgUvZTHr8To%?{Z)~g|sTOAIN50CZnpun+a zmgMx<=pAc4x(6!^DfxgXaK+ERhXv51QttQVq)5DBZl7n~s~h6Sf|cLWCi2XcQo&um z63MGXb5ZqUmJg}b{$|oay}PZ`VRP00Tz z+4Cba2IYfF%0oZ`HAZ(JrlDo1Cu;?Oz5O4xUi`D?E~8HRUWd2kXm=DA@=rQ$hW)uj z-!hM`y-1c-7pfkto4)?j_9HLJcf*Kk$y>iIsSbXJkRL7YY6rceUw9a#%nQ@1$a094 z<9F$7E~2RL$seWrO4*Ev=rT1VFCyyu_#}ajJMZ-K&Yjx}ty1vIjf#qL5S5D_d8v*& zzsNIr*2rJ%k=tXdi%tGODH9@w6WKA(++0t<3i5gERCtpLqd8mkU6Ipq?BZ9ir!k4q zIrEfsu6b;cx0!SbFya4WKskVNg%XDGoo_ibgA9SrROd`WtLo)#E?BK?uXOs4+Ec^V zhjs<2iM1sL6%yV7D=&=j!SBB#E6}puiOSCo0w0f#s>lfT$LFNw3qG2%`>3Bjyrm))$llQY zw!A;;5vH5bN#g(EA}EOc)vjT<)h2koLN2k4@_*b?EH9I`WjLRFyx>Tac2M$cQo)N-9GHq81t9l8WJE_-C$$qp%V_$y=TPxH)2hpFNr_c!) znLL~!)Q(pO$&s<|56J~X8mtJ>*=0%ww6+81n3Hqz%eKu*-cqc40Qxpk&ayR)DtKsXY&Q{UySFR!+UL%x8rY z=pg|2AJUOz7)Nia^#4gE{|LC^gJOSzN=rE{qU6Tj>?{qvHOkCqQWg*(GvJ#q@w>4a z9(=cZukGOoTfx${G=4cKKqJw1H*9O@^gCa#vlO$4LUp53Hv<vB_Q zgZI(L0V^hIw0z04>A5cJUM-7B^L+$4??qkx2x}%3Vl>S1Rg%kkISY}*H?Kjg3Ei4O_Y|Hh4Sg-Qx-wDLVHN8+tLE)CHGqAC+PbEK9u9(v^UDY9ig{BC zA;j9MOb#CHJCwJYXD9;v zF_okDThmvqtdnaf0LkV3+@70#&3e6cZ+NpSul$qQnTFlZ5Buo{=TgYRuhx0Ad{y4^ zL_|XNzSxUyTYiDqu0xyQmg@usH-uLnJS54$*K`2A+=y%5UNgvUIXc4uqZeMHyE?BRs2VjpGDn=D0#MOXaLxQt$|`!Z&>ijy zUFo?+&FG4oc3|6_6D-Wc?$Z9 z-2d84Cr}^Md|K?;2D8)Xmg5~EutplInSvfp=Lepyetyqy=Fh5RQf(ze=8~tge`5Ir z>x3pn@8tu!nTntYFW7Hi283b$2J*m`E$QuU&CcFmkpzqr3;7sABT0R4l%*cCTGV`u zI6r%A4M={Cy719{!`?h*0c?J-ANWl+WfzRp`}(}y$oMFs#5Wu-BGfnUKvy4!6YY!( z)sv{S(6q5`A6z~{j$&Yi5n^#B#R=Ll>d`C7c z0<2l%Q%OqzB+h;u4oKgCeI`9x>(dsa>+n8aqyhEzxxZ8RoWm^5r|&;MZ<q^HXUZB!|!*VTDQyQAuN$qGOSjpJwn5{(AR@s%6k{Z(9gCLnjk7Z;Xap@m^?( zK3!{H*l;?QvtC?=7!6%czHPNBuf$a78tV!gd7j-r3)4fbOs;O6ub(;Xy9an(y$b|T zB8Z${KfX0~r@Y0U|GP@z@@cKoLq}5T9$TGc=Bfv@dJ476y5As*Zs0V8p@w(%jxN;a z28pQ7@Du&(TGb%#W^foOh*Kem??&y_yAJHp!g%phS6}XvEqR824gCBuw#*54(Dn^; zR)!81W-J;2x54Uzt*&KdY$YuE`i!-?v{k~%>bx+;7|ez( zXDx*4BOc1P=mF$j`6qbo(BX=uQ{7J{s&tH-$C9!LQdL9`W0B4_BjWic zbKOfaSS`MU1!)o^)b0{c{ZVs$fD;K;L5>8ZUp~6uJrJ?AH>Z0$4${z{Io1$!M*-2~ zMqE05;^wOS@EO;}o63p!(xavvoG97hSc2Ng?An^R8p-TTruO#QSi)!H#O++X9*Lo-wMvjz)!}@ZTcgV;HXnXEw#%* z`Yc7oHE+tp5OV12Se9|v7`VI`y-Jpl8Nz#AZVZ0Gd_Zh0TdbTI5Vt$x_nQphou_j* z+68uT~i?$DLV7;=KAnoV5#6t1o4of5Q)vkyRM^Ve9=a-ht6rnezh1nuQRiQ zC*u??rnW4>oHk+on3^s(>Gd61Aq}b}alITqw&qAp_RD^c{#Z?K+~gUp)0}N5fsKF-VS&RQQ_-n2zm$y!8dP8o$JPc6RP?Wp-i%!W-yT6DJ3LAPnp|bDuSe91 zJ#U+y6YOC7v+hf+UC|R}eSailT2VQ5sCLLRGMUMi2N*?&Z>4A@UQ zYNIn{Adr%&0c3|MzV>t*5B=$0CYy_QG?M84gdeUBo7dIl56s=1&eIi3^SP5Ce;5Oj zCf4HLC|KfP|4u18YCDq6dI_Pvj@A10OUV1_;0)S$vb;6=FP7&e!PV@w6CH{R1Zg-q z`Ja!XRBOeoUzVzc>NT;y+c|08)oY`UU=ABmW0U2F=aB*&A1|Nn`>xVR?|QoY7JKqr z$x_EdvdYa(OVYOVQ}GwM&nh`Mh8o{htG;%47Eitpl#g#Fi5a$Ma?{f%CuZE7WFL=k z@N_;?M2*n3lN%gs5v2Kcce4t4q02uywo$cMNy$ewaC%uf?Z;s^F|C-_xsKf3Csm}3 zZliVjsixSc5&B&EfDXzeQf*H-GC)ZExtDWzVyw#vel&W^jfS!>Co7lIrOMW)Z%)4J zU%2hf6IjAd#e4W0%KzXLcS7}2)QwU3{CpOXy2Bes5I&#gOvU#wT@U-Cy-#o*xZ)em z7_X=6>WQM!ql-QkJU;`2iz|PG#zASzcY<80;PD$H{DnL>Vvdx6fX{-EQ#jok?DUh% zcM2r-k@Ov4_-CuABekWaW3i3bGdS)6*V-lwivR&-JKM1;q%3t&JC2b9jx-{^QXezk zGt;mzuN=%7#U=R5o6w@N5H>{NtNV5ZLiG`}|ATB1ESd9TIEBc?VjgS}kR2DbPcU+r zy7#FUNC`ltM@B*hh5frkz-y1d3=j`S`Yaa;@TK|+-lCrF_>_uF+!A!_Iz8Xw4Yob0 zv^#KZ;CZPpsF~WbKR6yx^`l=|78Ke#9c&8cB@rgg^5dVGnSo4uV2l3X<#szF{`0;% zUHp_jrehW$9%Py(6ofVCO*N2syqRmZ@;PGWz{A?oRD}6cV9cHk%fZ1$qsUNrq~WXBjZ6N|8;|(Xe$@yUxQ=ukil(I2dqT!NlsN zozubynQoifIQ>R9?Gd2Xr(&wpm!&>zUXkeF9(8UX zpUupeQEfG}s=+wkmb5l^r`tEao~(z|s9-j}`|W*u7t+;q;-m9KVtzKSAm-<(bvU?> zqu?95)XVY@6RN}C@$@yWh52f>{ zIT9>%<|H|;_#FhVeS_kv9?GyuOx1+j<^J58JRA-g{PNoF*W+LlJj6H+Mg+$+f;Ru0 zFG45AV|G|qX;*GLx5#}5^BteC)9_kYo*Q?3z&c6PII5M{v>x?2m@?LCfuYDyRFR*T zQ#)ZI%ubo(e4NBR3@jjy+O_2MvVZN=U`Nb}0pg>HLp~!B0{>)|LV7kfr_EI@$R{et zm6(0`YOMy?hhmqcci`zs{|yOO-<1H#Ho$aZ>odF^ciG zQE}DR?WK>7kD{s0+cU7T8f&yNdc_2GnMt6K{sM{Z703S;ivhh*5MI8oBt z!9!GnO{e)ab`p2nan>*ZxyVw1j>T5TdM5oYjiJ*@H7_Uav0HJ;_>iQ)6;?N|wdi*& zuQ78zUE4WsuO>}VYb?D@Tkku5)}iO2hM=r+9!=vYj+;Z7rlg%)O!J|K`_e?hngWON zJ@R0~5W#&-1N(O4Vi%xd`SOd?CR%0b;}C|wqg)q{;Ggwiz}`0kCKprki{ASCjhD-X z3N0;VEtI;9j5;M{J$ih@i4jP$>)i>Sz2-@C#0j!6ly5>`X`soA4UsGxuT;h`vP@Gd7n2q9r^nYX z6AaO{-`N*2JJ(B^Q_#@Rw1%~GFd8-a&PE+b%fr?9G<7<=FZm{7VnE}&<<)jI*@FI1 z%}063%Nz4=#g)W-PC+AibyqwsjZi-jl6Z5Bv0wX4)hfaV+4#g^oR*`fXIW`+ zXJVL>CzJSJGL}pOvBs^+b|@=-r(=jlgJIC6vL`RYWdm!Ltno?x0B5|YH{ZGWA2=)k z_^sDEo6=T8e%0aqIzs51H5@1o(>5Qu1fXeHvRf!wS=^o(m!)ankB?8cNeQQ?l6vv} zfIe4Cia{R%ijoSoT(bUpyKbCxuCrfza!z{pF^%cueue9;aF{QF&<{6F)>h6D&^qpuWG*2x<_NB)B#=M15)y z!k>ezCsVg+DCFIzBFWnRQoP4EDqD=1(SKLGNur`k`gF|dPr&~)dwwQ@?rXG?UqSlV zg;wk#XzabO?XLLA$nv04x`BSqu5E9|0RA}Rqd*KEg1PhpS27swPE!&7l1MG-nRB;{{> za_+Uiw+xoBhXiQHRYbH_rI(!QuRiuNRGT5pM;?1i@Ee_#6^wts+H@xLB-<_&ANOyi z-+lv5j+lL4N=8GnMNHXqF&1Y)WqAb!6DQoqn|s_s?pF1X3E`4&{SpnC<>KnOtX6nP z)BwUL!A!UphQ`Lb1HoGPgc+NEJ|{4ejZ}eT<(s;>3O?3q-p}>5D`QaXG9HePXp_Z! zn@y54236Xfv~V+NOyom+5}$>oAO6C>6I$GVD56@pS;Nwq2t4b*8wjqS3aMRSe0xJb(OI>!aKNFtd_tuh2A`= zl(eCV5J5wawwU``5roesebEvoc7;7ZUe^;JCD3CqEdmVhU&Ota*8J~Rbh&{1P^OHM z>i6?u&?EGEkwOygWU$nzc! zTsIh<)9-RAIa7|+EjRWrR%>stFbqJ>MnWxV$;7X#)i)l!`j1@;){5C1HN4e=tWO@$ zq@DHF-V3RN!_p?#%WH|}YZf)mb$ieG^XlqUzb5F4f^XMSM4p-;uD;*Kl)%N6R}E7- z{PnU<6|IXkixcG74l!Jv`TqL~{K`v)$L=p?R%Hha2DS^&qQ7aL?1>sXWADZi8$o$&Tm>7}EaNFREL@6od9{T`vz!5V6ELyVqW?@MP%XDr z?YlTd{HOxMwBBrpXP7lGnsotb> z5iCZ8Z0mkj82;D`RNV#j)t=1=wJS6E;CYEAR{JWK0(&+$Z4R7EV*`hwrpk8&MR$zi z>^!(ZjRPvoAF|*x!1sayEg8)oN|dcKw1eO}M6$vJN7#njz)W@&uHl1^)I)UT;(E}H%Ar5EH8}$^TGJ^>4h;s0h zFKdPN6;rAf08&9q)fO9 z#{9KVAdO}Z3y72P>zToVb9VD3>ghJOm5V?|$HT=X{S4e?c+XfbNTO@c(o(ew(ivY8 z;%|hfX%AkTQ)wsQZCq#vq_9XB8tCnz2e*itFECecd9_3)8MsuV0~XK!EzNvJ5Tpb%Z^oWmdMZPl@7D zg;$Bks(+psoL2LxK4RXX^ptJ_BGn5tjfs*=PdBa$xU}mmbg?Rmb$$vD`0;YPaDLIT zDUlwZJu%1EeWlMr_2Ppb4(BYVmXqH)Kw(y^Lm6T^7oXKgjT#0|6i{pEUIQG4HU(3T zbOnnh@x)y>14Zu4|JuGLVt{vTPNR5QYj=efLwMV2_Y(DRJ>9BJE}nzx(MuqPyL%}q ztx~vDQ`fFq-D|BnNcr^O`X#AgWHn}}7hD63q##ym6nr>qDRsH;8D=ank-=1IKJ7m( z#Xl)jN?~$f5aNPLYQGO=;4ax_u+*afx~0FF&qk^L8~`D8NW^*vH`VK7>juiPMd-l|6vz0%?wPB70zilzLa8KicCYh6}z15u( z3#vK?M*QlnZma%9x1D=-P)I8F~{i5LppFP?wFh(S82a6Q(=4NQ3d2IpCI1IoR>SfQu+(0N#Hbtq7Z5T&aH&X7_ zdO%lcOB0Z)USA<+OZ3VUez~XN1_$PwQ)uU$bSu3IqI{!5)i#wP~fR(KV z-B=&h%LUvbz&2@R$3eKQzkRg~^r9F4vSG#Bv^S{Ltl3|fw_79}9eankBtfpQr`LRB zII;9?tdfP>K!Ew-7w!$j+hKuK^5^=;zX}uy{@slb_|yi~xkg{bKb*o&&3Bb8a#623 zRmfoywWBlTXb+~P*7vhXJWHWvedjTEmilN@xN?_p=0#26*-zmSwIx)Lx3wSeaWz*^ zAX*)}D=8!d)}fZ%rSb3%4f61%6>*aQtMc}e^M;c7b+L!{H%f6*LKuv)rq*t*f5Ho_;uS& zvxoH;SQRJ+r#(bHTO)2~too1I+v!|>{K7$c`Sqv&HeGiC*I$3{W4%Pl^Uri*h4*)u z%(YmuID3FRCsU+~oAqgB?SpSE&=uAxiG*$V9v@EHz&$y*6Zqow;6_+vJ2X?y3)MsV zxTHbutkRnyr9Xn`C!Jw-MrR9iwJE>F4WTrUivF1jRxK&WE}BALa;VFv<%H)1#HA^r zpDJDiPcwfx^m-}99{S_KVMi#H0L8pSlZOJ>ths=?H)XLY7_pa>Ef|TW_u;GK zonImE=3#NL3+v_F^cZSu{6i!zH`OShxIaMAzG%gfVSa7(D)yoiOegr|AkEcM15vv# z5q*-lib*LuORd^T0*;j3BAJb~vYPz676HDo`Kk=jICv#yGmHdTx7aJa{FVbMdMvO) zX(j*W)ar;}=?fWYaWxtXm^d5KP~mK8s&{*sw|1_bs=($tLU%?13uTfE8>f`HT22oZm|>)UDwsp=Lzxhrpj-|mO{tI zG6WXv+%s)rAegnUBARl0;e*tZbC37_vH9LE@R|6r^0<4mnT5lBiLiM8QwUQtmG%6z zx{t2OKpA`*piu9_gL7kSjD&K~z%+BQT%?%Bd%WzwJTq_=NKf+D6PmjhM7( zPL3X~Ympj-Y*cvp(aH2U%0=cIXLy|T(kV8H{!UF6Gugik)8%0fy!i9dfRJWy zRCmyuv+H!)D~cC4O{RP;`bP)kl1s(ze9+IP)wkW4i{^Lm;NDM^(+K+oQwR==-RJY? z_tmj7_HB2H_BDJK>M=Hl^)`3gmoC|~Vq?yMHdTj`D7(n|sHplawQ*ysZX;oml5gv* z)sT2U^M_gpkJC~I8p?V^5oD0$n^nK}Md|1D3y&d#8wS(f{ynk+cMk3#<7%$y;kNSX zLIR^=KJ7u&VO-v&DKkfVDK|(=Q@# zfq-O24&CzVrs^(WIoOq@%0zNBd zVypl_&HMSyB3|zB%L||4j&-$ByW3esSsZf5c@JgJt@^C$_Kx+WuF(5LD+2jx3J2nG zY+U0(O0CXj6QkI4`!PZe53s#iC^pUUtvRlm(G)7${*%jw-^o@)efRUBvwTcVqCptb z*JM$2=pXtRHj~(9Bvu+ZEq_@B%}L|i6Fp_cawbbS58Bo@e?Tp>79KerSh6WiASy(e zlJIIp1vkPE)DXfDrz)q+*&5d+P9B7nAo1Fu#%IH+?YvpDEI)a8{BDL`A!MG?PK}!WQBbwRNX#9p|7aotj1DE5b z?P)S{?_c!kg5bvdKfrorjW#OfJt*_|DT$KSZ&64LsC8o}_yh55w^?aAH7jlI#~+8G z^6|lUljsivvqDr335KAf`%6K)IiF+qTG$3P@Wd<)`3#I{I%0*-OeE+zDk4~6w?e4~ z4TCSF*49J@;bs4;O<0=7vSQIfDj10jrb!noh+S(O9vd@2y-`KC+*MPOATHvzvPL31 zo_9rHpZ*SQtip)_GOnlGd3IFBbgif}Hn(q1sQ?zT`HY<{!whiND-}>cba<7LP`D19 zQOPD)gqS^;H_@o18$@(idYS>7D|LPt5H8B37!o8%OGM9oc@6z71rD`SWkdjq?5{et zPj!RTICTyf0*wi%2qd1ZBp3Q3!A0S$lVX&5 z+Wl7YtTRreOp$%)`H>ncHXG?-lc)G^BvXueypp-{#lPLyr1Q$t$?1{Q$vJ=TcXrEL zm6@>aos;Fx_8)iF?bqfkk%1;Zn~rARUCeZ_*SJC@5#DR>kwD3CNV`rd{NR-&lS@^{ zB89L>iM?-!S8S9L?&N)9Ku_anSAZd@m}rRzznZa&s0~xiLY&Tye&g_R$dlc0$AFgZ z3=VUq(W210=Q!S<(#}1!w%F4%40JzsZr0bG$-CT^z27_subVBR2cxBA=VUdkPRw@p z>+j$a!M>f`cHY~g@2OdT1ulnj#O7+h-z4-4?W!lDtP;wwM!YS@cr@?hvrHTR}IeFKg2InoowPEyZsRB|}Kc|hw8rz zOQ8rP#w4?d!urX9#g1OM_{b)HwAhMbGZP)XYr>@{EGtiWrh;vCFN@AsmV#D7CJwwX zLAA6zOtQ9y&PM7*J(X(FHXdzwJd5A!ih9{@1nBBj*bSs*ZEDh!XB6@?v>LStz_g`S zs(;P!g{>kiZ2K9UhKG2#tMAVP1bz&OJn$*V`S{J$FUF_(;zpWq-iz>xC6d1@=$GXS zMjMFVWvmW?S*oyYx!O3;KL0O2mNqm2f}SLP0H5A)+e1Qr$&JG*FBf;dDYPsc?i-k> zI_!%A^Tz_tAkN*8ts;I5Wd60CDI|v9;e{Xt-S0NNVy{3M!?VUd{CyZcWAmy+T!~&G z?1!S2_L-#R4Yru5aYfJdy{pJ|q*}j&j?<2H%Y}RJTdz=FjW#Iq@xU-uYeq(~DIf96WZ1^V4gP0sHFC`;PADDBr!Ph+RszOz9W7fCh+P|5WZ zQpJ=Y)JGHr9`8vI-;+NRAkPF>=J>Jy$-hP3Y$~*rz%Lrd8{9yVwnJen1?(XjH?(Xg$8h3YhyX;;>b$rYousbRyt~th z$}Vwb_s`kf4X&WGOLAC+8!lrjcu!Z6F<)BXvNzm`2Rd*^C&iAg#-y5+$_U&Ct4RDQ zgY{(}CagDod7z6-Nm_6&h3xc~pMZO7s2<$=^_dBvJX0=S-8)#bO-C)c^bH+K_Scts z@iT>CA?+1+*Bkq!Owf%;)>uPF?aXnhK)V7ZlA+dE*6IA-bD(*p8|!|m~{()yh7 z_U4nTY(8j(hQ@3~?t|hzn&+6eMjS^Ar~S1cjF2He28`afH>1I^Fw^RMYV>m)N~=~k zd~nwR0kv-E$`+Av<#qGqD5maUH2^ylj8r0EYNhV{p82Q}`Q$9L$*B5`1AMBmvRYG4 zsQCZ2^TujDUu+kKNUVQBARl>4LIBS^U%w9K={9L=;$4M52sp+d+` zkAlG3YDZ?*fHI-?o<2A3cmrc&Vs~#V>e}!DD%F4W;V{|ONf@HoBo`2Z$3A{Gxq@iF z`b~)VHNw0F%9;o>-O!V?7oZEXWLVg#q{#g%mA#08HxSO$u2kqvxeWyW5^$600?!gI zQJoN9{0hLH9TSMo_s61^YG|jxDC9tu-@9l6AB$BBB(N3_0Ns`ByPfN=qJ1LooI-$C= zq%C`^$M|tK2&PZii;vGdB%}>IP5Y=R| zMQ>wVC9`abdT5R3)JF0+?1Z%5FNvbtdo*3!sybbh2O%0U4Y9GR%^Kr!){01&*EC@P zI53b$1eZkVRh4#<1ZamW6>+rtFgms^(4i426Q~!U7Va$F>jLT?Oz>( z@~QzxTxsw^hP`Fa?iq^1)Q>Q~ZJ3J{8|W5&&FrDPo%*rnY6e8@k-KcHFe+BTHKA7D zCT<-mJ9eO9G({8-RSj7?bS1KvmTZ1~y%nSEm?`9W{v)o!KC#xs>@d1vweg+M+Ku54 zgSv-5Nq6{=NL0IGtw}6v;-f5927g6di6S$*6WAJzp^xh9TfQR4Q>>p1rFj zBja^keKc|)7S3gva?Rr1k=0)g{9xl7vYTh#4Ocuhaxp1)ICsM-aEK@DZ}j3vRHLan z?3pTfv>(n>{zy~TTojd6S(XuHx4{Q7jnygGK1gCjdW4kFm%s6)f0yoaEgYGPq(xnz z!qTUS{GjaGrOwqp9vW3%U09ibN@=rnmHhR@$0W4_Bvfit`r^e~(!gS3Dco;h&jJl9#wW9ph#^Hk z(l)lU`7+>>SVhrb9~{le!D@6h_&m9lySyjgTco*NtT2-E70?!Py;S>w4U$(VJSL-fA)sMg~lp}nUDf<&5vE{+skU(XNwa?W?V=dE;!N@asYOQNnY_UMWgF;d2OE%(qJT+s6N4Y3ZM6L0Eu z>YsZVjNL@?4qa-71{%eL8Mh~Y$YdFBW*zDh-e1-U<#}8F)MvNTl!IQ;+HI@D!aORX z(Qj{FbOC?gT zM*aY@(r9U-rr}UcGw|xAR4Y)SFE7qZVb*4h^%4^GQlOl}Ml9{!;*SnyF$=u~Y0r{- z%_JVRJ$08as0d#Qr!wXQ#}Zk=g=GaPA@zUV5F)++`7d3lMzSsMQtBfX&%;Y%Inub) zQS$U@>v?SNBZ$oGEXOU!=Gx2v8itE#co51u{IeAW)GeS)! z$z-_Gn=Mhyu*#qBp*yMxe>LlCAB~9TPv?9yw&oXi;)0Z9h4oEZ~&b;NnFYMkHSJX#{^#ca9I zPY#3QPT^oQrRjsr^i6g$f@I}lWltbi{^2d-*e5GHtfX#FFf*h)Zy2474XNS*hZ7oI zk6Sq2CiDe7ofuZbH5&0!upIS;Ho?@n|E(R|ZC7`x4!IMxHWO%&R2fYGHa~x;UO&H< z06bY5uvRWdj_ZV697o;XPr{akA&QXR%ZdyV;lks&3>{Der+j?n87T}F5Or!=Bd+!P z&JqfQJ0|9*Y6v0njSzAAxO8Db(H)(hf)kH4W|sjzxm>lx1ffe$nk#UK<`k8gyzWnx zRLSl}NN%5D(6~=igAq%fDT;%fDgVwFm>`->3BhQBOr4x&)atxavWKI3_rt^2E8Nzr zovgJvPEr*ZqKzsUobS5SM>D<}E)s zd`sG;d$O4>4&R(Ob-erwCXTZhpa@mIMuDP31*5-wKAQV3X|C`!-M;|)tj~7k>MU7( z_?>aLMIIp=hW@DPjL$TyNZ%g0c|yqq1@^wSIWBsa5UF+85f&8gD|m<@XPM1-@xC^? zi@ajmy2vD9R~r}fC3Vbr0hpvI=U4+W+;0;_;vmRI%flexs7}DG*V6@V(GkjQI+~aC zt_k*66fb0tIWQxQZ9~kR-W;W{juc6cjiu`A5tId$a>6k1dft`kG)P#=hY?xkbVqJG zEnT2(-~v{SlU`swY@R^tb16TvPG_-LB01kR&@LS4>$aYEK*%2X(h3o!twqlFw?W#O zpDP0vfQME(o7s5C1n6Shpl(^K(Ww4{Nq&j*rOaRXDWc|oTXFQ*Hj}k3xL|Xr$w$I2 z@uU;i9UZOjcUj|hXbF&3KmBG~g9?3Jmea0Oe*8Q=EHOTVe;_z3wt>^H6MVgkA|xby z=<8@{ad#e?V_IY>&%bb8&oQmZ|EX;N9x&;pyBtx1*euiYtRQT?jC9l&2Q9II zdqH4M+is~Emm8bHz4NbjtA?%(JNtXuu>`3lrxV5M{gYdm>0T-TF$ zg_@bfgV&wVds%ef+QQbAn)#>BvTz=cP@dM{7RA+xA&bUMB1vF#;RI5E)<}7 zFT_M>^M8P`PQ>nUxN-UWlLeBWkbaPz3#24o=Lxi(BlX-_^CN!A4X&p@Ua=?>xE^9f zJVPomcT3qFmjs)eLKC8hUu~2?RgzSy7l@hFoHNl z-5(!0g6+lB?dY5p%1Yh3i}zs%cNlH#8y;Q5N}4Ro_%2gRK0Hn z=sQStb(jtM;ByxN*uCo5f`wHzUvkj{$MWi2bnYSGwoAh$K%h$;yHgx+WKT}~epfVy zsA*Awa*(skB{*o-N-oxAKR096MtU$(z~*T>&Am^!-M(e!q9DXC#a^hzy=`<`y14>T z>T@DBWi?}xAn#&=><-r6g%!s)?~`V<#ieh>E48K?4*PBREnqA_wW3s403xC1FBgmq zhgfOlG9w)$i0N5f$2zkCY7Y$aE@i*+s2A6iAA^?+tQNuGaPXIBs|w;E`O(wZ{%G78x z)IT7&F~gQtpP$MD8_()hX>y|;`NnFKz^>@Dx{L)lBpEjJ^{SJ&x6x*6=zbqFY&i7cYtSnqh zCYfhlK`kr7{cpPrXSiJ)WWLFyKqO7@gLpp+k|!85C^-Z_XUulFDyv>PY;~3)G_@^h zZ2M-la;*=)@<8K0kLP@=8TA6uuV%O{DFld{>cf@qAW+M_XQ4NXYg8Z%Mn-rl8}3zV zsyr=eyfp@$S22E}g^( z%{SA^CH=gVmF2`a)@QvW9ieAFWq77ShtLWLK)8g*I5Q0M94t}^G~i$srM4If#vKu0 zAz^y5h;5O-gxDBEM-uh~dO5wWT_X8cN@GslJ2R>0->SwLle?dIEHq4L@ zt9P!jXT*TPwn}hPGmD~1h;lZYitt@!@&x{`(o4C(-f6>cM?7VR9oSa4qt1%B$mfQa zSa(nD6}!onmN)}q#gP!VJj9^mx`GHOY2aeqXT7bY;`?`xqPtn;v9!M~NvKFuajNnbUAd zZ66bTgv6>qS{353xz|>p@QUn0!5MOYbCsc%=8#zgcTg9l19+m#^K^f6`YoTq?mQF- zD;GcTMi5`I#lj%Bjv%{dHn{8g8>$LNYC=%8!h63j&P8%O*mB<9wrd}2uzt@riC*!G zdRU;*#^m4aayi`w>a(rDFy(A7HFj8{8bTam)#gN^=B);}*;wMC;Y)>KJKecDIAR$+ zu>gPkGGV}&=L`95N})@Pt&9edN?a_KA1h$|g~M3i zT!*h|tcNah@$ko@jU+kJj$LB4Ow6Rjh^vi(ZBH`uZ$Bx~YE4q+E z!<6^xV|M02$gZN;8C?Theu^|SDQaTXxp_+tAx0xhPFg$(PWD%!Tu<3^af^5|lA21% z$%})CwuhJ}6vpB~Evz?B<5>DCcd6L;;wl^x$$@`#BvI1hfYuot9Mp!G+KAFu`xjxm zh!hs@BgkEwn*w;%fJFSPTJLV1EXd9qW3Q{TkLfF1uY0xIdi?+JFBOQ+!e62u)Pyb+ z@VdW?-ZQDc9lthw!wZ~K>1uiQA&2s;7hW+`Q9NEPNcs}EA(_njFdvl3gr@-LMy((D zduQHz&=c)(`9~=s_es)FvPZ5a<9m?&)j$I|qZW{r%;jZ>)igdF>a7`C?9Mf5MP;WZ zff~wmOVLTx{7zoVU{GxW!d;sL*rNUiCv10nMiaPCb-u7&jpw@bzF0zxlQC3^G3$J3 z<7~b-e*E{T)$6y$I)fv4V1UyaZo;88~=+9ce*8i0-`7{NAjI1;=RAa{1x_3%&ry;F|FW)ZrBc#L^MqcM{f)U}$K`ut4)lE|d>wkp4#=6NU~ z?5&}-m-sKMgU#uDwP32_`@_rvVx+;@l6>8i^YqP%J$6G@h(?YuijKe*@7@)3tDG8Y z>X)#vIrgw2qceBp{@%7TE&vPrMW`TsFs<#V?*sq^bS!^AH-J3q zxk?a}rYIFe*iUGMZfHIL98_YZr4~zAhtF20iUMR2)~p0coj$D;=jHa|;o;)t;bKNj zji#vbTRD=hRs~YDgsTNthe@5;yEZT}{O$s~hJwS~clV~om9SG{pE)Ynh>~|2XKihQ zIhciOxl~21I1vYJ&9b4EBsVMCSJ7Gl0d~uq?H$of#N1BDql6^p9KiGl5V%ftPI z4!51wz{$a^M>+cENuVs4`O&*7&2BuN_4y9hljb5q$OtU!^>*`&Pfq@X_0meH_U`h! zo7nq^p$^}&epim~{*MB*Q0kpEYN|*5a(9CW&Re+}ez01-CKGN?!YL$nb~s-RILQ?J zqfov62{%;ZfuA1hp-ihT+^l8_+I`7`YL9htIamI&AW2%8=|Ojf0uO~#kb!%e9jSH> zU#gFW!d9wgFvBO7gpWGxN-bp|ps1#xyd;~GA%i!A&kgDBtjsywt^-7BdVd35Z9{Pe z^Vi{R8$k3EwG(=UMMnGqYkkiWr`RTXBy~FShj*1XmxM%u$dE_~=1KR)zu4cz|2=rPtpiw`P8z%g-}p3rN9*?FMr zKf^q7e96=HDfappEhn+{hB82mhc2nVw;|but*^5YTuVP$I-5S6dSUCHwzPy?j#iis zg4q4^F`d`j# zU0u)RELyjCKv@eY(6a*2@F4KMlY!{FY6whYQf;}s6a5Zht|qpH+S3_~(-`=|ZhwOrJNkXTrK(6)^Wm89WGxmGZCxnqJxr|dIEzL zI#p-B7?M^iseU&=^eQa2bIO&2ry4P6$;60NRZTUpFBx0qwc*iQ=;glY<5cK9{mOXb z{r>teh5bLR>*wYs>8MO7&S#Z3gK?&)v%uiLMMoj97f3C!7Uzv*b(x&Bqw>K}lm$qNA;3rhstNo~suKkfnA^7-1lxLRmlX7OK_mb_9y#AD}zdzl%7OREhIo zU;cCBzq=b>BU0>r-zYN{X#W$G`yRcIiPc^^d*f_+v?J&;ebJPMq*}w!W^}m81 z44pW$nfKcg$?3sf4BzrC^s)ufjxs-bYgA)`aq7|PFQHvhz_=+`<_C40(@<`53w0W4v_w?OtGWxgWn0-0cQ&Ge)3{ zA*T}-m1S2!@Znr~XyAp)zKv^Og9EF}=^=~wIMw;4;)P5d(ewW5XcbXgn zU;c~=)MbSuM@BBC8V2P3b3~BL7?Y;z;P^OVlo1fx?XA1fSLB9?VdWl^k!o~3UFi^R z@;f;oTUO=7B?ggE4TxHsTmZ_?duty490S&n9jJ4UhsG8_IMajSz(*;JCrXDFrzfb% zwUSrBrp9?z9`()Puk`s}@J;ZE1UfJZrvh7BgZ#}O$$)vkEcZR2XtNnO+IRegTqiGX zAYQbSlKD13E6=;jc+wSK+8sE2M>1=~AdesG3}M>Lg+M2Tp82XwohnnKMT|zQ)U2tC zvWxv9q>B!ImVgKIfzj!Cx`l>q75o4HbOO3LAExG(&7(@yKVk!XG<%$ymum6wS9Glg}zsV;}h&tF#ztvo`CMQe2c)LLAu0S=Yi!(PlwN$28PFdXP zOU)?HjZ*gJh$H`u99THLp~`z@sWgr`V246q2xH|Ch z%~rk+Jx+Q0q4=2LVjtm5`F6bhW(g;C-)y7M*XjAGHf9@NdB|q!bR7ya!S!mi<>iVa z9V72R@#u@W<661qzw{fEZ*n)*$hNi)jF!F>b*1sn%|F9Cc_z~Z1_-~cFhbnC-I}^} ze<{8|w9mM<@0ozQXubc=s4|s##Zu=0Z|5uWElk7{aEbVQBa#Y}Isg&{@HddyWH}nm~rkZsi%#==>uT zHi$;p_&Vl3ax z-Ii!7{%N>0{&wQ2G?OYZF5?_uvw;d6hKy(*M?hW)#h?vWX7q@w)JyY($Fe!&#DTr* z?2LJD&TNtdd@A3g5zng@6rlxS&N7HK$mlOPU6>lo7iWm-48ITtVGWw`u7?~)ewNP? zo>0q0AtUkEAX@2jufXI945yU2{t?sT4|L@jr>kQ)d`d61#Rr62Z7?z*C5!6e%LZ17 zLwv+6dM0_jto(OHG|+CoaA&|LX>CKluftmk=YJxV@bSV_t8!XvCs&JbCo|>ka1*0` zjvPuWj2{_PkJEQ)N@&?cyERkBa;o?0unaYm9gC8V7dham*f?toRhc6TcdSGgOQ4(- z?56E!3llpPx3jk8R{bvqQU_+&*BDMp33I8~D#2L#ubIK|iC~MFKT>}6uPro2Ws{kDYbS+&BfDd~mmvQ$b+iL_$|qobv*t((V%b;eWQF=j}ARb@foscx#kW^D!V)T1*% zUlQt+!Vm?SN?0Lx{S@J7A7e|4kP|l84zEe23`Tq4X zMqnpS+w#P_K(LXRfB8p0k^N=0&LeU*w!%bpX+Kr3$N&F3Eqgy}#1lsHl;?Fds# zCzA6i>+wa66GDA9tH&({57{6%I_i8l-9uS`eGGib&IViaeSAy*CEKxPXPBbzM#tR*R^*`Rm{#q@AJjlFMyqS=~|?MA*$|DoZX$-+QSx2?yWOC{^RRv4(R9=oIqtdJCS%!` zZz;388I?C*yItR$`=Kj@d4_k3&ni)Ubc*{~8*J)5rBX(T&oTG8On=jVS*vQm{MX+7 zC3SE<@$ZpE28W`#`eG<$+Tc))BWoxKf#W+`TBEww{9axYn8>Tkz;IvSLA&hM?5>(c zFhZw#cr@j!JUlaKSIM{v@jgtS9Cm=o`P4CLO$Uv;ITB;jF02w)$wy5E6bSlOBS1lO ze{d95j^Kv_JAr*U`swL9Lt;dgP^pAgUQ?Dz6!+au_|^WOy?1 zkj^|PFlHa1lO|N~NA$P)hMZ`l%|LPSge6rNZ;TY7rG;#$@p{K^x&C2dQPa}}(AZrr zRg-zDrJk0FSc_F-Qo-72xWL7!rO-wrou;TEJ<;oM_wr$is#1)}$N9SAgXP_=ng_zW z_G9)yn;i7cGDg3BxJGqL%-1;EhCgj`>hg#{osOA9E7}!n371XDK83s<3!I4azI{Pq z&a^kVyigP6GA2Z%^dAPV-w-{{`uBJp=?VJx5J^9kg@#AY~p&ectdwVA9w)dGJaWO%~>ro8r~o+&jRt zIdiH(Tm1C>IpXhsA^0b;FCXK7ff611O9(6B1@IrfqFP2`)gK=uP!(|)A8uv2sp?Zy zKqqPo9Vvr@PV{OPzj3JbO^MXqy3kK2DO>b%P@r_L!dYN%IrR_MWUHPuATFBp66+-z zgD(;M$|iTy^?oEm8CUf>;dTl;*q~$cQuOGJFlT!a-S``RtMV`4JN4c`HvtI|TYSpL zd!!XSOIoH9U2SDJ_U72Y91emy8I4udD5x|x_}t-;vaI7`g8>@OxRPO9QubRqfa*K| z*}x%qfruy@Zh)&Ud%-+b4e;rG5&vnZ*1^Ee&u%<+Rd4&%vvhz_mR{MK*xcR@#t~VE zY=Rb2_uZP)C$1ir5*EL9b7{vmH{%#M8uMA57?tUrNVq!qIO=?PzYvl zXuab~gd6{Pm;kCGL%@}-P^r7#00OK_ zNNfsrDII8*&Of~W8cV}aU-w--5C7Syq5^DFlt)y@;z%*CR)N4!Fa?Gyl!n*S;}D zC|ZN2O7dKEJ0ODFD+r+-s>oUO;`_+}SoC{#i`5ZA)ifqYP;sNR{FHi}Q3?So=ND>! zv0UaiuFZ#bFruV^QLYn@_4S?nf{bV+&qBeQ5evyq3Q8k`$td(ut;?2pRQ4TpPUFpo zenX}Hp#cdfOGJtL$OaCVY9C=^*Hlg(*YhVP@FKb7J<+4grm)P9He%j;)it-EVy}c@{WxgHX#6Q}YgIFTQ&DweE{ZqsAg8e}$FkV< z(f@+@+-2-v+vqln0Np3d<;<#Goq(yQF+g{defe|^1Cn-<`~V)g8vQ>1uy*i}${HDn zS#v6+1F%Ve1BEg+x%*F_bd*Xv4633=OBs$4KB+l=Fg`xM{|r1ByR=ZM1zh>n4>xY- zO%DG)$~OH>nFv{K=rK=rXV#O0bixc00%Zo;s}S3W zC*YS^8{~A%Mf_H!%8L`%kYp1R9*aevRN1>%L}S7ISA+Fa{Sc;XVtID6n%6yps5Oo& zs8V@h>FC&`Zpp%uC?kU_W6G?~VfkxgWME`xpqz7aoM-Rpau;#fuT4}++IT3dPQk$mQJ zhz=ySwfUvxS^S0Nqfm2)`3A>-4TBB@>LL`zu zbp_aogAM;0I1H5WC&a>rw(1b1SS&11UuNGzH|w5!5z(CNKw(B;gb)FCY8zFEk1lYR zGlkV=%p=t1jjul=?hCD!B&Jau9>{{TVEah-+1eYtl8 zFQxGm#&^#Yw1Z%;LyG*$d%YEeo2d0T%D)*1n+Th32n&-wfEg2RwGRNc4;=`-92V?o zi*7e6o>yRD<<#ery)W7`gAd^MBj3*_ReSLW>#D=&%Rkk8T_X-s-P6g#>$b^`rcN^D z#%8&nT_vB!wf5<_9a!V|#-tYWx;DT@>?4~aFfxEVwJ#av;MuWmm_h8I+AB%f>AW%V zwdkcYW$Uk@`%UM^?Z?AMrVYg-6&>K6&LVue*Q17(D zHP&dURbvd9rYE0a7FIUd!Ed+s!tT`Pb(&0i;y*FEf-lJrYp(h4bb2Q}B8Yr--m8Xh zD<1&fP|n{ux6ozukPI(Apq%QJ z9l!;&Z0M{u?>8tF@gL$n{DXrmg1qcb#Ik`uw&S`REoTdI72>3MkG@s+ob{oU#$l2f z%irl%LW+2}Wcbr!7V9`qhu94V;K z&01f_OKvBtH-W_O z)Z|kJSTNU>ktZBJgRlo9i*Q7NUvn5p4RTCcM zecB7Ex?s*K>!@{tk`CMSo)+rMe&%yun7Td=XaBir_n0sud*Q^dJ)tqC+Pd(Nx~!GKU1yy&Nc#!F0IIqa zY<724>+Cj%b3_)yd!7dPLE<9VwcL(jeBgS@FegfTBthZikI5F?#?B_|4Uv*3B(){I zNRXkO;_(OQ!m>N{`%S$q8u53VN4npgXmljJgFXy_C0~7lhki-)BS>-}48Zj08fdb| zNnMqB*<=Gt@77chsxLNB`Si`#a4b&BDjMXBtB$JM&Ttx~&+LQL9Sf}*aZUMh2!@b? z91*8Jo&=^w;1(U<7pxAJJMKrx{XZoXRGV|V56_2-&Yi@e3VPSFTs=d-Z-(DKV7s#1 z1GS)WMlrO?-=M-*9PR8~?8~$OH5ey)T1?=F9?AI<)LTHGFE*u7cf+#d#4kZ};f)y0 z$(jb`xjD)!_EscG>jRUJdzVRC@u$G}Kec<<5PLruNSk#{KQ4{ExC}R4%%Q!Z0Q`3e zfOZ^mN+=FoI~5^gmwz@XE-(?g-FvTWKg3Dn3+1J@FJWg{z*~IQ`b-)^P0_?Gb}3Kk zETC2c*zgO`qQTZH1|Sk(WAGM&Z?j{wH9U#YAidUFS8eLt{6Q2yim2Ci{UjX~E7V=w ze2|b3%OUsDbv7zJRY7Sy^BY@8dGl%q){_8XRO{V7M^p827O(9w(kmvjTkG&@b5?AP)?sYY5 z(9F1=Ri&_Wfi^OIbq9mzL++3DJZoa;uzOr4#J}j|x87A!dMS!Ek%broLxNSRe+Kb9 zoLl-M`?D&D({lOjZ^o*WrF`o#EMJRh(V#9#A2y?p7g8X|Bd4qa?z|_~M9dVP4N8JW zHAZL@Az(q1kAvpc#4Bmf%NdWNA=Y$2S2enS4$_ZzJ7CMOtWKxjr#1T4Cip15Jbbb{ zF|VFaNS$O*Hf()0_FUz4RIVF>Au&85@28sS3L7Q_{m98@6|5~$fAZvHUzeN2VUVO^ zRl!g4;C=g`pL)U9&7b|ZNb zZJyHi5Zioz$CvNyHTjX8fCI4!4-f}unT=>qGoH9T3jtG-*Ol?SZ>|wp0crhpB|}M7 z2^SAR2|_K`P@7#lVlyeNyiC~<;TsL2K21V?wYsNb{I$Mh7coUA5j#8IqzQteo;~R1 zB|QF0jzqp8Y{-sQg+wZE^K^bT5HkeNK(%!?04}g~pJ`$$RWlQne?m zYA}1|rFo^UDe3w3u|$%R9pT*MMT{ht*sM^Eb^B1oTxVifp$81b|D^lp%R|!cdYu(W z{$w9jTPxUN2dm;m7x^|o4529c5Zm~NRSyFhTfV~QQ)7_HM&vc9Ls2{92Mc0BUmoeL zu4~sTuW+*3PH)ZUaf&sK?vDK|7%7;q`eR%jn15VTOr$2LF}b|`wOxNag7YFh{;NS& zypaXJmhbdzDUtFouvU8w$D>p1hH||o{v(yG^bCGTXbxqVUJF^Z0OxrHViO41qsb*m z6beK`@DusW?^UL{@_k1OCk?poSAp1o2_hx>0+tjrDkDJEXM~-k$nNy4B>kb+#A?1r z%u*kUu&UR}7jn^n^4yU_e0jU9Bl-!thNawoE;|5E?R!76^ZavWW=xFI>2wtWfLp+s ze14>!o{19X;;_oujuM$v7qVQ1zl*W?t>GYyE*#K}ih4oks(_;*#)3!Nv~@UY23}i*F&GP;_BxMOhTb>cR%`yfE`~Ltx}=?{Yu2YozXS2f7t_lqq&Ph&`s8Enk}lm z0Aygi>>K$^<2CplEeMwlGz-N=LZDb?QLzTOU>OF){(+*dHJQ2QR-k8b>I9*{(-~H@ z)iApqzgKhR<9C(Y%)hIV8OV7V2`A*8C+7j?;A#Ux%#KB}oOdqkV46C+j#}_yie!QvrfN zCLLj?0A9L&ViR7rF<>w{IDi9%Vs{Tg@9f7kei;AcH}gjj2oXw%rdz*$HD$nXDr0NW zs3E1oMQgM*=9b)_>zjQmevZ6#9=?j;pbGR%NCcxAqa$K>#{_}{5khebdk)jbAx#qS_q8!+N?Q!Kx9x&z9r3iZ_h{u$$RWv3hOPekFtWG2178qW^?3^zPnLK zY>vZbGGrde?wC933ka{1wY$Cw62aOk2Lod-Qh&^Mb}7raM53rP)HQZ4QClE~9yC|x zq9O(uZ~5hQ9rlW~{{EFXv|D~*ZhG_P?*8WP?h&f$hFtA9F((~qqTt9iqA2k{AwkCW4xw7|KO z^924=)mJLXvos6unlWP;P;6@T2uheLjD+#B;Z{;al{OGec$+wG(nji-9^Es{r0rgE z|1p1ls=`Y3hsY#+CI^|I7oJ1kO$4=&;^s% zw^;_6F@9-tViwH1``$C{cT%m&PaHOxYsvEZ6RZh=;%MeK*QINu`WHPX5tu8CXes+4 z^l5u}-G6vv1X&PO!1!=X*)_FrCw2ccp4DyPvM{n2ag` zX5XU(o*zxy4<&9?micTSY?iB&_tSgj5;j&=e=qL0no&bc1d4PC83aP~jODV&iELZ) z<;6Je)%XSW+A1&qa8eIpwC1yE1&FVkmW>$O&?pP6Gaa#PM6MZxHP%P&^^h60-?;?s z#jxAldwKl;-d7L{8yQ-&tXy?@yz5z7tLb9>YBXwC1h3L*M8Bo$a?iu#>twh}4UrEa zWWwv3a=!yWF=uCuHyM~Wi#>Z`S!u~%D0~dz;;e{&5E6TEjLclo|B-pBQX&lH+TK&3 zcsl;!jn4-~nEvV}`7T7k3k&Ic1Yr}mFCsR({DYE!d6NAsYL=IZn#0_fZN2U*o>fC1AWc~2=c?22qd}?*9w9U5MS4`0b(fs|j`s->N)r>dI%=u6X zwVTGIcft+YiKs&_Y_H#%SD_s@*b^v$#PZ0jn;Wu4G&|k>v)r9L?q2KdF@N{^Hy<~$ zy-rQdj!j4DU#p{&g{w?VPqe3@Dmfjv#q@6*ATCQa<|*Q)BOx9~%}LWcGMX1ig=M^} zbT5nyZG)%62V^<=p#VY#rDZ2_Vw6Aa{<^Tmv*?$aAP@kOUxT{hI6Xl5-TjBGw2iqW zlIdwBq6ji|t5A+*YK0Hu=e28E?cL66iukRfI%FLl2y|T2+jU_4(R&n=Y{T<0K0l-Q z$sgC*iD(0)F;^7d%dv{}`3&0wrMUJzl+WNWJjd84e8q3@^n>L$x!%mqR9hEVGt8+e zP5!8hzKf3#--^ssW{Sb+asCvFmry0A-=&bXiZ`Jac&P~9c;1Juo)_OMd?D4gq#u@=ocIxe)HNP{{zISJ&*H^CH>_|~k9f~@*_sf4qla9#SngK2oM$~I)YANq-5|}$Zwy+Za!$CEE(Rg06atkAiz3l z%bEbiv!jCe7i%P)`|F~y#`z0PxJx)PTUwDHx;%VnM zYnD%^aXf@G+;Yy+Bl^40LGY|3$DD~Hk$R|WN56m~1%Q8^^+_vyl*UV_b8)#n#}+De zG+`>akqOw&iRPU(ANI@7LHMff3E4SgrGQEn^nZAI$Hqw8C~LH$iqWxc+qOFC*zVZ2 z)#=!_jgD>Gwr%6&nR(~@g8H)Sy4POVE1)|C7|*-C{#Al@AiN#k|3mygI2;PXNUlV) z_ymV&)T<)7o)enBDWp)L>|RJb4#oaBu}o_b)WB@)zWi95-L4P_(wsJM-h}U{&nQ^c z(tLEn_ndDsm1Vg^uiK{juehk_=*TPpm)y7M0nnKNj#hsyrg=2R`voDMu;bVX>s9+4 z?+FFFv4C<5nb~%#u0S3EgNU`%FN>Osn_)YIjS# zi$>fyLaHCqGNtfZB%rx`8O(#l45UTG#V8K z%ifj<55EO=5msy;EBwf2Ci)^6xnuVRTP3D%*e<$9_pbPqZa6LlEn& zx5Gz9z@JE-xt(m#jNq(nf;kmRfyO<{=t2n0>l_g8Yy)1iJ?#3!A2WY#Y84sE;?#BP zkiO^PwkY1F(Tl3iMz~s5-gQ6UD#Tf>P%CbiE$b)OqSQ|oTRY^Je~y9(0x%{o+<~9! z^^ack-GNMJ15fJ>gimfvrvt_0?dipE&q}a-JVbmqlM!p7 ze`jX3TN3PY_-?{#@M{Dv{{|BA=?Ctb?(l72XtBFrKu||?Awfp`!2Aki3|TF!4hH$U zXzF^|+R3?@u>G>$AI1XN9)88fy3X3!LA=X3ghq9HZb|`ZV#51-a3-u%o-njUNdets zn0#AI5g-vKmagX$i#CE=qkwur6NS_@YLBiMI1<1s5<{`FM*G5qG7(CbBoyf5kmtWw z3H#?l#|-x`$mQPWaUMeayLL@f#X+Bw1_%V&l%v6≫W@uP09MuH5y;$VyjhS&Su4F>iFz4NBm zct|OLZSQ0VEzGp=##iL)ITrUv*b4)+5uuUf4)rl6r4ULL8ax7SWk1r`xdS=%CQPE3 zQqy^*bF81f`AXv7ny$CMiN+pz0XAFFH!fh*22W}SPME25icsl zS5%M2?%4=A;CS%B=}vaD!1dukS>sL5 z?hBQOjV+HrT2Yn)!;5j%<;Zaf|I%Gw=YXfI=Qxj@1cCQ)xxoaYD^CMy_6}t6&}FJg zp_q;ZBMLRLjT#nnuOizl$A#BsPp|U5W_U>rTO(W_K#cfX@q+PVN|OIcDo-m-$e5?D zX2g4yAmo;%;Jv8$cPwN%&{hzjy!}%Sj4mK{SL64jEeLqL@=={i$$_+@0faKc^_-4_ zMsza?w3;4T9)o->G=1%K^$G0}d|M-9Nld~0NX{(PIVb@}K-oA~nDpCi>A6741$rrY z8y_F3922ba<+ZvwNiR>Fbv3c<-Q?q128--+NO;lS=X?KBFFFn_xpLX|_e zVxct*FN`c9ubw)G{vR_sFOp`#qO&xE2N##N8<(3azN`l~>h4{IMU)A~`Wprbat}=v zN)i44zbnn&K^cxkM34edzn5Zx0&-N&RTGoQ#8D0-Fbc`f zyo5l0!~UHl1U)WvjQ75+w{>O)rrqmg<-P-DFC7Ot9VRQP)Eg8uCj=j(71yF7>AQ)8 zvN9^=G=^4<8x{wo z!l^Ud2Y_vmtRULq9=O{~$@Kt7eZSp0C7L$%I9ow@I#Z??cT!F%6rcf&I#PR{8uIu- zOG$l8J#{JfTA7eM)`p06XT_Sr2v11+p?Imwke+I?O+D5E*FZM;GQ{xTUbvJfqK#aE z^i(_*EYT0`%ox0Po)dMi14WDNbWdLoV-yj*#=^c)8L=J@3^4+qRA<=)Q#&}@n+JspggXQ7IWgS=#|fpL&6 z{5kI|!1cM?>4ULd9ov%Dd{As}Rl&#nAn19y>XjzCdX&O3TleZlL;Mj3~&}{vN%M>Lo?VY#So^q zxqN)ydqD@#)eUZPV?y-FaB8*#j97b=*48iolt!L7x0w&;2=*i$=Zeij;TLZ`lRias z+3W2L$1@02FDG%MXJfZrHalQ#vxy%^!@fCIQ7#r*;mGJ{DcE}{Km?(D;&_xn<}^X; z38J`t{7vrEN5J&xPVM&x16S`)s#~Ya_^G_vAv zCky&85M;M{m0cvKZU)u~^N1S+VpMjx7uH74 zIdaX}Le$}*d4o+{Z-T1F+7u)}?1SKg=f(}CT6Ym3dv91 z1=yIFEd<=Gj=5g0Q5mWa*#0s2vxE9slS4iDPVXb+$i}>I=;U(9qN>cTs5G7H&Z;w4 z_)op!6&e=pJM(H|2EkdG!4Ab{%z{GoF=(A zyy;B`-pR=Xo=7Um#Ifp|kwiAv>bf=znHd_yc4jfAXA5a2HAbPCDzzO`@o28@&Omm= zUi4=sD+@eTn7ne9dK~K8phNI1HSz;`=u}5LMS_4vC!e|XdEHUguT!jVzD5DKzFHOl z3UTju*M$$1MSAY?5xeI2Z#Wv5w+H!t`PrNj5m)St7rENx^yLwTg}PFqfUuy3Nj#xF z-Y1BVA}1sxUMXs?IGj*C5ePhjDcrZD3{9(^kOp1vtesZl<#x-2F?NtgvM?R%56ODX z-sc6Xq|o8kfA*Ha3u+O3p!Tk|pvt`+#u`eB5^@OY#x*hY`$E{bsOG$ywl{oV0)URO zXh1p$ClEiOrDKJ(sy%%ErRNrv?Km2df#@#dxWjhdT{3S>XdSXjAw>CBZY?D-wx4VS8!Vp(X9v9F0|CML{JBS1y?!qoTI1TH&26|A25&9Ch6|AahjKqkO(hY zIflG@imhFwT;+2a`ImxPRTErQTH>=>y`*eq=2N$Ak1v#jf`ZHar^A~k7eXir*HG-a z--7n{^dI^u zhqDIdTAq`3?17Yd7HPQ?pTMk2?`3OXe9|o@Mt1Op6-nc^dNtINoIiQ~>}VS#H6}`k zjrr9iVBo9MD;`Ns0^)lvzno&vO(GH>6O-$H5DivC$(2l%)lvUGd-{gbg!88XdZpGz zh%^6JXN&RJDF<2@_YYg9Qo>|v6iU1DpJKayYR7(9Lv0FI@s_cC!!sWIEF76PnC!X1KtyKxV|Vmvi4K&PiYh&)Td zAL7EOCfQC{3)nfS`QXt3 zrv9&o$zI&{$9_6CE_Y_tN?s zXW)Hwbf66fDCRDw&dV0z%DtKOwmUkyA)tSA0yic-*p)OCQv!qSTgA!hi|~xH3(*0C zLYqjZ^b-skcK%eB#jldJ+4Er2dCgTt7YW>zl7Dl8Ih01NN*haU<>21lhI~)pZS5bE zW~9BO4nErIJ>H-bs~z7@y~w!rRY5hia-Hp=AJf8+P)s%Y)=+U_*DF$^lebRD<3yS9 zZNs;HaOdE{3u(stR(1D$KNCU>(wRzpZ1)D|-caH~yP;(m89t^u=P<*bq!vdnC>pD^ z4-Fz%H-5O#eWKz_DqC&gwAF=^wJ#@_)BN%WA^S{*#?y!E`BGpw9{&5Enmc9M%?Ppn% zq=xz@jxuD;AX3HwTaj_tHVHB40j5W0$7UU#IA>cbJtf6#aLEK7QbKRR*C$5!@%$}6 zA3Ku#!#b0ZvD+Ty24$Kv7Wxw4U5xD0!O~3y-I3lOrnwW!xg^riBQIoH$wmOVgRZw zACr7||Afp6osZqD8~Ro0ZZYxnxU@hPv3vGxh^p7OMb@r0`PkB?GI$ubdma}Thet-H zWu$Ed)|v>^O{di1h@9mttILDeMIJ)ZZ(rSZs-gWChgD1K$bUp?tq(9MSD{g>rE=qW zA(X@E{$pg(YmY)JDvdX%ZwpcEQ|uw0Lzc(hW~qxYezpH@_fvQ>tu-T~l}%vWy^P)z z{_vh_#4_vE071vu*%JA5v0`MThhvZ78AiL$HnZXbv2=~INhgkTa|Ak0hrgHz{`YjU z4E^K@x@ZqHe})MqZ&Ml5qao7Zk%V8*m%;x(FIOO4Z4}j}AJrqIj9ljeZhIz>Vu;D% z;Eb3WZ!fn2#R9!KH-Dz&M50b3T`(CPRwDPJb9vw~`C+QC$i|(qR$@s2or4mC{@2c= z6xmf4n|ez~N@@GYH5TxuFFDYQ2i0aEN_>mjX;DO}e!qMci>7X>Puo!oO{L^=O%-LR zSHMzkE#Ob`QwXP`i10 zLNn?(tc^i#*@tm)4e_mWX&J2<`$K7&0rCanxXd4He^KQ?40ht&KjPO~#7Tbqh88CY zQBQ_7gwf%@8HU9$(1q=*ni0bY(I0tEc0g<{4T}P;&Mpop5~xRTb^Qs#q(g1iP|ApG z1g@Hz%OZ6;;TB7T69+LKH<3^aT?23H(0Vf>;?C9gCxU794@02?Ngw9e5SD@!%}}w* zwr&VVc*Mv1(A(qAgzPaGzVffAY?l(C=yt`8@|4`Jz^>E3tbNVU{0;8hf2S3+{8PjW zzjp_BGGNDXZ@>%?)HNv{+!53be)J=Va&khtMPG6|CBTO`db#C+nWN#j1r8ZZn>)2u zDx74M;Fi6ZER^T%^n-zYix8(~;_FXLN?r25A2SU};U-9~eQrGIC~P4Zir!I;aDPO) zVI&CjW(W*KB+Jx961DlW8Bs?*Z9v{z0bOY1;TjLTElhP15aW^Sski%Q{`xWpfe!Hs zV%hEcp=f;TAQf$x*JXTXo~o6Q1W{SMhW$*=H~>tM>M5u&_dRgw2y2=uoi#^$c_9-M z`EP_Jd6+dG&CFu?sIB!ib-ejc@R?q>d?@svebJ|;e^dq%fy17y@~j*wPqD(_4R5tj$L@*=26n2&cO@FKn!os4gHCz{C)ii9<_G-z_j zA4W=o<}T(taxwz<5Tg?jSZ}~UAnD2i8a?1DLXF`oM7MB?b%h>-R)ONUr$me1iWA20 zEnH}wt7b0M%u1Nn=1%G3k)h+fotXno=^?T<&PiI8K=-CLt;nl=Qd@N$qgTOATil!K z{;SkZt(SOa!*>H!;{Y}+PWxXZw3s3uevf`6aGZ6--z#gbGf7T>uKZc1!;jZYoZ~X6 z=CeB~`X0(yTzy%KmBzbA4^MBtPu%Kij>WcZ>dpHug?1%WCJp*!5itKVCdIwz;%dH* zV)B2%=3GG_&uZb0MT<7xZx?kRpXo+Aj+%YzYK`7U5HxOl>1O_EUOcWsM#n4#?(IT5 z%(^G|M64n675+3Hp&TialSIU~#_-5~YeFX_W!Y=nE(RT%HU zWsiZ|JrzVuxd>Lki$&HW4n{v3sU3ud=D+PN!%844Q>zc_&zYrw=4bv2c*2d4ijD^R zj7z&YbF+P81WN)*DXUo&=87lx6KdfChsG^ztBEZ( z8~W)lLLH@G>8GQ=Iw*3XzU|qOjw6KRiRG$@aqHc{w9Z0ue@YIG!RvF zyu^-g8UJi24i{$sX@0YG3oq-^r<_kksRQA|dF zpSO5k6EkQWrkIB6{%z#kc87gz5g=?T=QLhi)0wW>L_0-Hy_%k(Mut)8lx0mrDv80K zF@$uSq|^IuVVWo(!GPGCyp2t^E0CRqqNWE_Nd z>lavwbCwdvtul7%zaiHA*|5}aHB){x@!I>33fJ z-5|DksLsAJP!(22ed2y%)`SBp%$QxO&nyZHB7VSFeY81ywiPV~KuEo3V;KmsV8eL9 zd4dkEmh=;8pSyh9!MGF#X5IzlZx!t(JyZaefM5;BqL*OWn9Do0##I^E-C*l8{FBOA z6FFWZeV8A5b7r*0-dJcEg1fa(jlbIWhl7Vz|mp~dJmP@QQY|ei3ARs=5NeRv`@)5|bs!VF(|g`CM_o z`I64bP^rQ}u}%UETX3w+mthN9Dkg_qGOS+|gdJpLns7{|J6dYMc{7`p_gIdJ>f_Am zWgU$FDsD_(YKFM2$MoZL4o~Y$ng*;O)UfI(n2k!~k%q;K3$~r(LiIx<1Pum+$zgB( z0F424phc1c8y5ysH}%$Y?HCK3%C0AcrDE(Vkf0omjhgN#S)S1jz=g{#7r83irYXt! zS+RP^>g3V*->=4sTL2wlzdilB4aE77q((RLv{B?bo96bfvTL zqXPw8Z#Q6*&?zhps~iJ9qrm7BpWb;iU9cy{3F{xf#3-F-K?_HM|8*)Odne!h%h}lX z@7Y`d7*u7}!#HM$2*_M7=cM8;km@`kW0y-2EXc}PRCF6lA#!f>zQ|*GG$hlVIM&C} zMu74Siel?EaY7+Ga?224z>yc6^vuh`T1-1SG$Y$?SH@d14f~ZFF{QjVvG5xP(aq`2 zn4t~;z>-GQGQK^poxwiZhzCI-VOylTXj;(TM%go_2^T!FiJmBlVPRBbRmcv!pMX`N z?xxb3ufC$4haRSa|M<-`&|wng9|M(XDGI%~HH&n07}VJj>6CkMKS(Xn=KTn@3r&iiCvxsZ4bALj->TD#n;$ zEK_L-p~%oGI^jcMtIT4Ny`ymF|GU-}xp=$(Y*)I(v*d#7CVQ0_fmP+o`^5}~c6_^D zVS^OBkg`#>6x@jSsU>5|{{359X{k51lv$~|tsvT*#l=_aw_EpHX||V~&Nv(5$LvMr zAcGz}WlKjUWPO(uYWy0dj-cRkFko<4rQ%Wh1lldkHoep_b3Yu5G{sE(h$3nh#M8P# zzL!`KivPi$u1woW4=HcoT=!RF4VCT3>rSuh^aX8-jkR8ZGOn-B3wp3&tpcfr38m0YENJ8`E5Sd!9(wYZX&akH9|Ywk0yJ_HEoie&qMtr&Bov zm4#9tuI+*k(-FKHKSZ~BV9SYdNk>X8wjskg4#T8l(dmfxq59q`ZC=?rfJ=Y!72mru>~MupcdSy+L64u8Ie=sQ zCaWq!!qrhn=K_18C~%@(l4f#`J`b(CLE2lt-K}Vjir!N*pWvBEt8U6Mq0RFAPxpEmSq+y3jes?P@Sd2GW zS&aMnM;59m7r76T}am6wBPyjM20r0!5l^Zv?8%qmF8Pl zlhR+=;rd1f1E!{!_t+Jx(N#%=l{ne-8e4OjGg#o0RFIIC2g^XZVlAGei<7^9@#D4E)y5A>hP(OrhHlNssHs}JQ$xWZNJA}; z8hI@-J-Sl6?)#`yhA@@{mfa(vk+yxL=uG&YXBC#1g$NZ%EUc(Rjv^a`V~`1#C6Zq7 z3IyjmhOnVWveXpqQn8G@<2bTl2S6NW)k#|Yrf)?0~x=C5fFD? zc>;S@?)$LSD{_ZWV@i0mtL7^lzr2@l+UaCgV_B{&%pNO+L1HiPCi2=?gSh^(||pu?WM`hx)}O6(71QF|*r zQ_HcdN+3{Gf~s9V9w89a=ZRLH&EsO_yk5J|W+?u6@EwHtVoeboW1q%(zsITjtRWhl z4^J*#n&&D|ginRPbewc7+H_=MFi5lJFR&3Oi%5@eVOwhvo&W+P8#-EpG#O0U%tkPg ziP~!5P%V4Z<5cs_s~Ac-vi^W$dOUT3pO&TXng7ar_4;J=xsQ@0kq!_kJ4^fbNCmuu<7+OSDE)S`sA;>QWa z`UKGG{qK7Ikn9Gb{SQOJpx?b^p|N$h(-|%BX?H{t9NY)!R!RY3xd^BKaDwLlkoat% zN=Hj1Mtglt@j6HvwQkzkQ8-(q!jR#=VRAaEplqqqVV!*r<|{v!B@F%bNi7*Mf);Ny z?7*xWUI?P3be0@V^gsutw@pFUKmGDrLMTYL99MNfaai7CPn4U#uKJCzgxG))a@o$H6nVNRbKoT9p|T^P9gc}*)YP{g3b?`?t+#^^ zG(+$9t`%T)i)#SkO{otUw86s`VqFD#-jwF4&}#b|Zp7aoC&EVioTkUf*!#)RD}$Mj zBTFu{P{Un}z&HPV?iLocZ$(AiSDTHjbHzcE9bdM2bSHe*DoP};<@H1{W8cvy^*xtA zOKG30pEfRch^b9Vf^gMe)#RDEi&=SjovK@{-|Dv@5$JIvT4i$=)5rP}r@Ot3#E+gxC0kwNJq- zSH00OHH2{GKL@gOf5Vdr1UgzJU%-aJHuVij!#Z3hB#dI{b$PxUSbQ@C7F2ykeLhh? zi{+@@^+jG!QlDEPk)$)5^{2VJxWTF3)1?H}CM~fFw=~Hc95pB2Hn;8QP5yb%h%1~G zMbLw_&$xxBW9sAf{6oAw>~1_~e7NRkU@z@u2&=GIp6EyegsEWmww z&`_79Y+pN7W1whelaX{#=i2Mp4E|0mQbNjjYr;pKVq0v+LiF&^OZz2DFtY~@qOV?fxS5xU1e&1j}DK*l%|D0p0A6Q;F6?17Wpc}s zazWQ`MPno|Ej+Wc(xy6i&-CNVtkWry zL@RAji3xbp)p)-gCW2zxBM~5I-T#5FHrs{3Gx&eYH!|@3x-1$7RzS6ZN#u%OF(sK} z{p%9mDbZZ*^Ir5<7ITN(4~gH?am$5XK2q1vgY0^xzf(-7@hFa?PSsMp3!Z7wcsq&@ zSLfK|_1Z!NEUvrSeI*hRy20!B+c5p+=vnO9ps<=|2p__I`eXxy<=i;+}F9p;H*j{AXT>2G@=*vI+eyb-iN$S{L2L($~a~|YeqEH#7ipS^qP(r<0 zG^uRFNpIR=OUXeYCqFio{Cpm-407@4OqDdWiSz8=`M6$N4(NW$rH&`zGMV_PoR*!j z{z2XP@k`+4rnkjbW73wY2H>H<9;PB^K!?71ceg3Pr0< zfJpV0turUDX8Ax_;f7{Jo7^UsX^kd)Op?L0q8>u(*Qh<5O{JsXvI~d0bJm&8g$FF# zSe+9a7!{C$HmCcV(=H_GZ8QW{wKG>}+QZ2iA$&iW<1EgaX??@wEoQ_tkL-9|glo#_ zO7OTer8OvO4vLI)DKiPHroK8zd!%Yg!VKv9;ip28OMnA!hrPF$^SEHkhvN}H#qSvq zMB8@pkoZ?7H;_tPzx;PyLzzmWtd@z>JrPH^FZnc>4_mJv3C({l0%Nk{@!rp9t+nOB zw9Jn#-B^w1%Sapz+1C#=mRwJAe%*aksdC3uVtOai7OXdiJQS8~Ws0-Dao2$#!hS;r zugOKXJ%uyItgW(H``kZ0H5`|69&!%#`*4*JjSFuu=!mqD=#JTRuPTyf%mo{Ghp^Z+ zQl+SSW`Qs(@eSTNld~Qo78apK?0)qivJVAQLK~WIuvZ}9bdd$8{!V&RUBVwad`gd@Fk`OejDN6!E z8hIp4Wc>94dTSNDl&yZu@|26gznhiZ-f-e>wx(x#AKX89-h90t&KcA$taKQ(6eh>O zLRd-HBxU#=Uj}k-&1wp0Yf`=7sceh-A@z=N{$8jOoXodU|5fcoM+2gV$LB&uI9!|0 zObnK-0pY|~n6kwVh()=3%uZ(X@Y$p^mET*ru&l=g8-x+0%_N*RO6K{0A29;P`1F@F zm0gch*YhW`s0jxGpU1%mip9jZ=(kZ2XzEuR>TXvo@VfUG^6(fjg{344MrmcTZggmq zV6QxRm-x_OPe6F4%rnv9I-*#(H?YRTaZ0i@tAu#qGZ4P7kvwyT7lh{izeyqk zyvLQ9@9$-j%*^n(qF3o9sy$Ce!WZ>ioXG`k%yoG^82lJC(WbcE!gnE*^5#8YWZW*# znPwi<=oa-SQ*;GgvtuB8>6Xy+*W+c~OE8)UR9k7_M{FWx@ zL4e~ej9~2Ph|W)kGU&?0wcpeN^^hj3&KM-JKQugW)q+ufpUq691tth8JAc6p7D;CV zYvWtvbdQonL{x8ey7DKe2fNcR^FcVE`u5Vq`JlAxCdkG6&8Ftik$!f=HP>o0&fP_= zTfuc_a@-wY4iX#^CdA5C@v{=|J`L8aP~upxo13mWXyX-4&p^en(j4(1Fmo-*eyN(|G{hjoi1&gZqFTjjJy9(yxHjq`+8yo%R z%0Ih>=-&Ntm80Bt)_(^JaN`)Sl0JtPvwE&p9M!^00by_!wurD__`&VNYJ-bGK>fL& zCC}dx{AK(UV3|Nu^i;c#snfabRDVV|`e3yM`bgtN1q!=3qwvwAkZHwQnmQeU0OjE8 z0y+!D7LN`Zm#>mGaz7W34c57Ec6|@QS+S0ZPK)4R{5VCyQ5cOs-^C45mC&Fifw%Ns zhLWaA7#7&G9vsXv0zS?J(86=}2w$9A&)8Bpv;QYfFz1OfY4V4e&R=qBRhN@W@g0rq zWSxS8=jmhYuC3RlT|n#xC=2=)VS1^D;UkS&zRt$^X=`Srq^mn+`$pgn9%yGk4s9g) zwg?JbSO0eU1tbj~o7MP-xa&8~Kb&hB85tyo=g~t!IpE-Ac@s17i|!TCxaj<8^|x=F zOt9w`SjvtMe4l#;H<0)&=VHnU6L*c$oiNqGlTl#uX%!F9Z1QZ9>+s>naW2~k0tvq! zCpSXoMxE>I>d>(is&*>`!gb6sil$#;i7Ws$EXCF-ap3$ifi#kJz~5J<#9rk2VyxLc z02E2?h$imn1!vx_W!~7P6ILvp?R$V9u1q{O%QQmdtG|1eNA( zKNz5lAj@R3lqh?@tRAWFMMKCEsj{ENmmlYi)-vh;{q6s;>Ib%#mw$q(81%m! zwEWY)xBBwdmL8ODLTWIk-%5|M7COK#^%$D~xrxifF z_iNe|Z2C9y#vmnV91$KSMD}8tr8&2m^*)04%a6c)2kM~fsOMtkW8`A++i$=0GxTE0 zS&jOnTTx9xdin8$_+Yf>rb`IN^ETuzMB-IobLDG?v499qF!Dxtp( zL2wIe)yQ5dbJL&4lS|@#x(Uq;du}PIfp?bNWK@zGbr3QUoz=0i1hQ5 z;zcyendGoShtWAXZx@Wm;q0G600~~=Z~2a>>Os`yjW`5rV|7O(qlwtlwNP&MLTigf zk6)$z4qPV}&gLhrE*%58EP@c1m$p{_}OQ5NaSnKWBoeFn1P`1HUrA>5n0h`P;8v?ChW&PQK_Me=>O@LP<}*+ZhWLn zsJ#-py5yMl%4-9o{dW42+MTaulI`KiWHyLv_-)3vV{ULjs~M<3NfR?qWccf6*JK1{ zaaBVm&I3l|x$rFBKZA>MTb@V+0F0kzVQ6GuLw~102(#M8C*-N`Ct;X1h2IH32WgPz zsH>Zz)6s;L+IJ9=3`E2*n{EQZxx9L4?xDTC1ID}ikUTp@BOFeEl?#E3%!gxqw6rCU%TQ&Pp1g+T&LD2F9gacSJ59Snz??E`$u-(3_1_> zVV*6c8$22QcnYE0;au3e){SF5npwS)!Fpz*1%XRRq$+h2xuHHT`lBd!7!t0wtCXngI`xn*Us8Aq{gb`xtuJv>-b3mo{c- zdV{L8pzi%b$6XRf(i{BS4@_3E@&>8$p&M8 z*B9}hHco|0m+k7wdeLN@Tz;RgF>BLV?WaKQYqb5+XkDrbfpG#M@6;a<0`(`M{$Goo zHy4<0gK4wGBykXH$Tv+Wx`I`1_%K>yG%3GHNim6Sm|90%&-eNH_Ccqu&-5z* zs77i2?u*CSMbg${Bw-52-M2lIY1y=|rC|!z=RS(y$q>(4z$km6bqv63Y;Uc<9~l|B zuRjysofm|^*eIgfbeIxI|{}QQOPxC#z|pbied`Q4Rbtr+&zk;Cnw;=zC+H_?$^aA@a^43Vk|7>}K3{b<;Jk7w_QZ z_zU-8^>B~M)PO^3FV)s+6CHf~B%!|_h-C2bPJ$f5$_sa$9*R}d;weQ5FLepRfvyh@ z+zrRFqv=#$8xOc!G2QF^<1)Zq9-ShFP$jF8h23gktgXRg{y=_2c)cU&%(PI*^ui&x zCSA^L;s=m-ZA_I%kC2THGjZi$$RP0(? zju|&*T&wa$axkQ$sQrD5@raM(ClU6MsmLS#> zcsS8a(;ood6{X&I9QMognIl;dJ^i;@o0zd@XEf6PsLJ_V* z`?@AQkNBNbP^-!Dx7ul7q7;nU8gYGZ^1b!h{A(BDN=iyF`yd+xA_}eCUj|}}dLb2f zO}ddwa)|N~P5k9Q9-8>QPminL=Vay)eRlP|=u7kIi>v6l417f{RvS*x>9!cJ6E|`0 zek}8xJ-|d{jiWu>1c-ncToLZ3HOM|P0Xw?YIm{t8J$0_&VM?C;gO%EuK|^&80*}Y& zuDjAWd`R`mGxLdQWyBT3HkF)LV>573=BoI8Pu~Ndc%7Z*R!inTE+IQT9R_|JUmCun z5nT*ZE_S_*T-fXl4_y4EOE(%SDpoS$P$Rtz$l?;;&iqM|_#G8oJAT~TqHMK79sI(! ze*d!%!l8i8OB+q(&2Ed(+%^+}c-s#azRPgfYg5g_cC!o(!}ZxQl;BI>CR{s9e{d^Z zmVNg5XTPCQz3jZ}N(ZSf%ax`fVm-WDL z67Vq^lDvTNT22czx!pLFFX8^FFZmVoPOLF`@$0Zyn6<4FeQd+C&tU49cX_2>L zg!nhd9C4ZdcicYmeR8$QJN^Rw)69F1o{RL%Mh8SOrz6Q3H&?%Ok!~23&`Y57z^VGE z^IkMx+b}DoJU0_fHEwvK>tk3pHD2DD^7Lw1qYwx-ZtZ-T>i5c!7KI=Q>SB*4|2e;EUOp)HcN*Q3o51bv(#fh*LX z;hqG;Ex-?>UI?)fekBFjCqNPJST8hN_v@i!qOxdoI?)WNd8g?GLGXf*!q`fSp8A2FK3?vuJi^ zMf%m|ctgBCb&9ODj^^8%?mrr*@vhUwqDP4=_9z=n;|kMwIie}ZYL(~hJ#(AYxIZeK z4KW9QQIDTYszb=t$hmPMYnquiV!Cn6$ZNsf4l`mAFWv$t{eLxx1a3wNW8wRNeqUp1 z3)~5h2~jqRtNLUDL>aUnt&tuMFOY1&De+Hc*czQmkQTMW_m-29;5(f{t0cONgQfgul_|!zc#lur}SM9!w*Ll`b3QqEs*8VZnhNe2_x_h z1$Ipg(@oe5Bg+1+^(gWtA0bBfA_VvP;vRbvIm?=iUd-VBCcM$H^~ZsAJoxwYmq4oIbd|=ydqt5a{IHgWv4IXI6%KA+tiMwo~CPEq@~laGfNd!5XY9!Lloj zeG9e~j76VwJRYAhA;%wL4S?v2R8FgjulA#<)$9!dinIW3nNCNyRJorI-ZX zO+!A_S8_Gg7m>4(tC5jw1VvHp+pnsDy^*0WTBeH@ycY?AyZx$_X7LL!9+*k%?I~ql zJ#F&?xD64u4gZiwpASV;=SeIi+1S-P0FyVrDcON(%MV%S?;?UA_|~)5KK#r9i&`f( zoIh)ccQuptcp{8H?770U)AlL-QO5xGK~j*(J!fQ@jhZu2-sRXoW2RtjaYWTmm%P=! zFdx=$)Ey?%p5o&5yhdj(hezy5kJ^*}6}503N_msxo}JO%Oxz8!H-DO_x>yjAO9qqjkz<))1RZ{_nff1*$vE3}!pM+ACYrWZSki z*|sO!u9a<0m|EFxs>z;g+qV6+-*@lt*ZRGV<9;rjy67}(R^2K)%zhSf+%9^3#_i;g zcDB_?FeDO_Zw=c&{0evmGe8nNA1*1NsPUYzwl>Q1kE-06YQM(RngXRK?EZBNeMje=RZWr<4 znfiB-rQI_u6`Vv}w==)~G@hotjGHWVuUV`9?bNV^vQ?;cc^KPIaC%8eL%Xitxf#8b zr4d-9+7}usFHh98m%Y@)T3sP>XT0?Ex#aU&%Q?ZPzZ4t}IfxCBF{ycFjG6oq4tQ;dsEXqFYzrHWe|kRIu=OLCqO$hzvp zVOMlMt%)Nbn#>q?0TQ3%4Q!^s?(jb^vq7Z>_6jGMZ0 zs~}B8+tqMG^PyIq#D|EufY-aTw1Y^WNB@f4r_9CE9&X9wk-eO*^_vPh#-TYwLV+AY zE`7q#e2sB@oA|bR$qcUhdERifj*9XGJkXZ%IEI?4k?_{3xh9{4;bJQg5&QL678_aP39fbZ^p|&wn|t>O^$ga}JIjRW)$~(wET2h= z$e@jhQ}9EL4T)Ck2RyF%yzDSjwoF|7x`!S#9juA6Rv8SIk*R5>vf>-8E@AW@kc{k$ zj&KTqek*!A@1q5nW}g!(RQNccLmSzkzS$k$5-O@%HG_;_LlKbJr?{tiG54PReG5yh zD(1C!&j>v62Shs1E~|*wYf#Gw(P^R_3_fD}!Y6n6UJ#%o4yM1!Kbiu<{^IPwjD3K3 z>D{Mk(m~UHF2+6k17PN#qM9?LvBN&Jd3`(6#!&j$ zq6gSThM?~X+pUBO-)X+3m6WdRV*?+F3ZQ4auE|OR{zS2l^RW$ypWGDJ6aLl|Nd8fm z8+1zii-yJf)lt8hWJOzS*3;0`0Jnk5{!E(#rm`3c5Xh!`zD&YZsD!)}iBoIfFc*vt z+JH4j%y2|IImE!Re7ue{2ttcV#s+T?l-Pr86*Fli?ukF3*SxQrKIuP+87glm@A5jU zd-r*`jxteN0amQmdw8+MJb` zqdtRxD|I`sGSrW>o)914Xly9yq)4D(JG)OirLQ9+htl#B45Z+ls@J0!jVt$36iuRd zsPiMyM%G9mKia2^(k%2_vgO?5UgY0)wtSsADSG{q(;%wO)AQ;4bSW=;(^S6CpR^jA z>_WVX{uFMbWr2HG=|Z_|d1HA)BP1m%;BRWrrVoO8@;_O=nG2sNu9nmHdKk|SSJCu8 z2cdw()j5 zkC{1TK|6Q3rP)c{$y{(w*erB~6C3ju#}Ks`@22!!O@AI6?3?D^rC45Orfsq*)?nUMS+bk72-(D;on2#vzr1Qvn#17-6Xc~K>Hfx&aWFk$>kUCEo zFoKID;|U3Pm|0mR=40?0U1_WH%Z;dnd6LaE`9sX z{|a@YDQHuF=6)*y;w9xfvP(v$z%oi<0K5Ckmb4M!ssSJ9o z=(>@lbHiwueOXeiuFj9{S@sk09e@4+aI*@AgAuL$E}#h9uKnyfAq+=tgm2HM)uIoY zD)eigwI;aL8LI3z0K4$4LQVW2S>X@_80ls52p850BfMOv2K;K;T@>P3OVnK#^NRm) zVE+{*9BDFd9g%SR`!in6 z+fOea`}@f(VN^sDzyeC(=g#(P%h@q>j2d+Che{@xJuPGGZX(ZzX#s8&GB`8%Pwx)F zng|@nQlv5kc}P=0=ifpU?!|@ug;P3^W+~baB4U_IF7QiLt4nYtW?IDL{!-NeV`rq4 zSr{zc3Zz-ntkp20mUB<}zi2|>cCur&ey&-aqBYGdg6$OJ(-({@7h#8{LC-piJ#SH& zh$&h^+vWBX|XzskDa z!_nql6zM)HGb_C3mZt{nHnm`p%(B|ol^Dd22y#~k*Hz~F`ky)O*JZO(=IL+@q5FtG zh-|k2i0V#L2#9yh%7$pSTK`ucicAdBF+-gE}$pKhjhxwFwn-)9VG@J$a^^#`iiHKE~4 z-2oF;6|cPxT~_mts-$HeX(iD3q`y66=6$%8lbp3cw_Gk9fZM2*#476y;I#Y>gU)s4%{R{Apj~8I#=xdNcHT>&v*Vwpu~~ zwKCc<6j$M**|q`I)++}^Vn4&s34T=ZJHG|^9*1tVHoMFil&HAY7z|CZbn@_Bah!fO zgt?R|^C;smd_y$xoRn5fL->W&Lh3UDTpe zy&jbW3tkbF?3X!F$gJq6E+5y~>E%KOR!~ZurH_2eVd(qXG;b?jSa+k z1AzhO%ev(jhgx*onAJR%jp>Y@A?=NksuVOMpevxJPR>|ww<_f61a$+`nDcrdqawfW zFRBCL@EuA2Gi#!JeJsEOF@4-)(Z6th-DVkJ@m^Jh8kR9AK_7$I!)G`7T&1Eg@eVwR z9vaxs7R-R?uxniE0KzAKJivJP%USO@vgSzh_`|qILpOQ)&`?|X9W9D@lPl~yJ{`hZ z7YTr1BWMp-{lKhFLIC(TWwf^}gWKjeqPmD;Oi~WKLsAgK=MHYg^M?_qo>4)(S#NAW zpIbpXwR5Rv(iRpt^0RN(&|w)=AOh-#_kl)rgW06D>V<5)-w-1q`_8W|8&<`>$Y^zX zzjMQ49qMnRRMc{MMR_pNh;eAk3d*s}T7lrRTT@r`-cs{lp~0TqR1Fnnr-WSORY-7b z42Y>eBE$@(rvjCoFhxr%B^Iz_Z_B0RpijYcVwzEH8jOpO*o-ovoc|f+QyaY?2(U}^ z0`I-4K+{If4uy6YA!pB)RA)NU!jlBLt*rAuX+;N2vxPtEi&0tqYN0XUGpAf~b(|?i znZO)ntea9L0$v+SS?4s|Ab$#tLfU7TDYQ)YmV0drLhsQ)pfffEWBiO%A7-7t1#%X0 z^&nZn>z7&VZCZ%LrgR_#z*F~GH}KKf>SYmbR{Uf}3u8kt>J)a!!8%9$AWwhK)04(i zba8z+{;)kFFu$^fCaaZ?UBz2ZojqAAb*%$CaZ{xv9W+Hdz8!lA54?8Du1&#CdFKPaLLh*Sf;H*pW9bh9{=v4|d&{YDx2bMh79{VcQ1V??@vr#Yb^n_#$UnlTAz+!x59*27 zJ-Ra(vFfLS-yoKJ7*i5Q2v8Cy1zerz8dWq7VT8I%Puc!xPsrPDmN^x2b}iMH?3FEN zbTyP>&OFa>bgVSu%!1J#rl@G-Mor+qqL2zU5APmXj0{OD-z9NGhc#Ox_UkTHawmql zgWX1lco750jRENxXH%yeo9iQOSZAWvCwO8NYS4N|p3>aim$|Rl53a`Q9`0Pft~ca1 z&s+@Tes`EOCO*J6ZT!few)gO^Vy^m0d3-h1Kuv4Xg+YmT8O0vPu_Gb_iY>>RF+~~s zA^P9ep~c@Qxb?_XDl_HQ=eEuz5&^L;O~q})*X(ea=y#gFSpMb_GsRhoBj7>HBlx^c z(4>TU%JGKMm^s+EQq`qn!!tV-dgR5Sdvj;F)z;yuz}?{%~ZN_c^@gA=z%@a z5o(aSwoYtCbBQO!Y%}WZ-Y|u!Tt?F{Q{R+u;td%oo?;}R*1u(;uAq5s+4pUgD?@&8Gl*0JBx$%QXWt4u>Q9*=OEY!I)>^yZ7p@hv)awZ)1D!dP&`!% zW)+GEng+o!qH1z?jTu)F(=b@Gr_MTR;GocStV9bmG-91GV%5wx0bg1=bGuA9+$4qD zB;imi0iTQ(&`8G_qe{nWxO@Slm8 z>j29!e0yOl37io-_2`qDOc3G5DeJN5w>iDq1)`W`MruL6y$8G-w|~zv)}|_X1o_j% zGL*wg1)!XV&5uul>dg89cTs6Z};{_%ymQ@pkmWx;~z;;(g6`|la^;&2^{%&aaZ^~*%b2nqB@APD+?ikf^w0eF}4tKVp1~o)12b`ClppJsv zT&5w?#4zH;=}yyuxNq^Lp?P>cv8d=<68RF+<$1Z$|67%O?P0xJ01_ULIbRBkFxlWvn%#DCv`g#WSsYaT-0&+&Do7G$z&JaJ zm=Zyomlq^n#52{UvYJ3CfdSQix*=Bwx#ZKssfQVDhN&soaAx9CNC9^0RXJFyM7L=f zP$7gGF>L+Y(tV0lQ6TtX_3L_O=fc86w{;fB?8M@pA*q0l?{U1MYC4yEld_)Dnbzmc z#rmpympAL>;<3^?bdIj62$Oo-<$3#4GF5WeMjR7bm8%jYpjwrIRLrki)}`Cfx^AEa zFA^RG|0p&Ap?XdeoI0ZElKilTTWv?ZEHm?b-#0wIpNeXTD#zL)Snw+Eb9YcinHbDY z;aol#5(>~pDrM*{l}$QFn*t67AyU!uty;{ch97nZ4>`3PKC^L9);bjv0dmn6`5$7Z z8xR%qj+STa0PlddHU5tBez=?xllT^2O=Ne`NPuu+`rDD!2hdf}#$1ZXB*_MntME?f z<#R9Gg4V}n)9YzJT@e|{jw3o7H+b-ngOGojZYP}6R!YYEDVr%m(ZkjnEsX^!fFb0A z(^^I=_eXi&f55N0@4&C-=i}kgBlY+zhz&|9CKQZ&V$j9+wLbTq+UvaY{xo?feB;`r z8;}l#SfxE0)|u7rFu$=E9vCw&YBinl0%jdzD7&-8N9?sMB(bZ#eP>jP>3f+-#YcTY_T$MfAJCGXiW$gYG z#%Sa==(#l&LA%|YC3Sn=Evrb;q>ofw`D0>uR(?;%Ie4gFRH;FVbAX|H^-IqAY@?&Z z-QnLTUEtf5=@G~tl`=R{wIq{;emdwwL+%UwD?n4?!ga((#ED5|KSf75+|TiJ8yF1d zLLMN(Y|7V1#5CAm6vNYKuixn(ltiie3U`crLRDax1|my~U>TlS=ZMJe)ATWwMpUb; zMoUwqGpISp2h$P%_7zv=Mny&_@(u*s{RJgpAyKWuQ7a5oaf33)O5uT}FxN6hKEq@_ zL(ZgHSsf1q>U`2m5pt%8UIf!xDr{fTIi*B={yp-td{auzzdJtHL&>!7SkjqaSy@1z zrEP8+Y&09XYaIA#Xj@@DdQtvYFP7C--BVd{HT^nCgR66PWkpqeepYpUg~D$+J*Xb# z$EB42(>(gBLgmtv^9Hh6Cl0ov`%Tz7l|rR%-NiHL{x|U+kc1kf7<@}wsvItQlXk=8 zhySHU_@5P~g$Uwfq37Jqjf@KgpWE?ZZ2X+Z&4O?UNUOr&C8XnFjqAYC#KlR2LRN+G zRFg{U<#@EM<@OwwYl4jEey8Xv$|aw0iBAL|53?^Ejhxq>Pdhm=oxf-AuR3R8U}QP!LUWKuM=Ex1+TM0d-l#d>C9XGv;xfo)WFO$?~ zU3u6meYT^=?1S=Yo}P3q&LGo|G;HS7GzO*9sYgV1zZBHyr1fcN@U|j`Vz=>@Pj~&A zvw+}k<4ZV3-rqug;P6{TKsr}Xyq zMVx~)Ao{RmMji@wZ5`Yv>WbT7W=n*Z|Q0Bq$Yekl$&FSC+MUUBiN5%BXs02UT{YI~#r4FsCom{TmNb5v zt6?s46B2-UZIOu10x;a~I1MM<$RA%VULr#55R+-F%x`h0evbO%%lj~GR>zKl*a9HC z`UL@l>+qYVg{S?UqnS-$TTp#UVyiRbP2=P~H80HUXaCAm`XWV#y!+$oQu-~lI0Mm% zeqy72)`=v4)7ccry<8`Fz6Gb(^?Iki?D+UsTXP_CL4M+0MTPP6xo!o5Cd6I-uN|E6 zI!Ei1i*uS3P;rJpW4w(IufTehHE?RJE=5hX+r$Z$t9yp4FhrcYS`SJ`v6o1C^Kmcbs|j zuvr>UF711fxm6F+F>87pylEUkh2TSD`X96S3!2IO7tP+Ee)Bc=VMb6-pH_ zN*}TJpgq~=(1W>&!wL#)3s=|(aCEd7(<;C(WYnVO^fGfS8zu|g(Gvmo^y-wXO?{%7 zJ6Of=HF$X;pcAX#TEl_AzTZYJLd~V%ADkkGpJ~#8c*e;*e-oQ>FR1aFW1*&J)pV(- z^D@gcAdKMM;uyM@VHjt~X<*Yc!Mej%+6snErI~8(u)60T=ahzU&2ebB61ID}wD4_O zjSm4TS&jU+hDt=_W4hj)w0S9psLtQt-`Xjt4s&3{$mvi(iFLXmS9GD}BcSYF&++qZz|+?nhHWtAD4CY304nIwhw z*Vm~ivsL$Y1pqe2^H^kS*;96234ZX|@(Yz|W{G{@&0zH+0@~8I!G8W<>ro`!9Cf@- z6vPi7-tGH2x}{R&sonGv`M=L75xYY^X_bH560c>_^(I2|5G3$w7wXw4^7E?5 z{QAv>!);Z3zXQCsyUb79N_-7e;28+x1KhTaGF^8f=vQca;I$03m$B_?`VS>iW4-+@ zT+nDn{ z1fPh{V`&r=QTzobvJ}f}6RS>wpc-ps3WHi#6v-i9-nQp8 zqX%fQjx`uNwZ9c&LQ4Fq!aXbD7ge`bw+jz{EOyJ~ne{Agdp&T3vKznreya{(e6LGP z(J_Yh<;rmolHPeZp>A__UUuHV4T<{Gz8C5xk(G3_fmRhDR-Sk2&o(2YT=l%p<-)3) zb1eG~^t1OU+AwO#Q1IAx!S4Wrt<8~D^!DF8KMqANA!C(f?S8k}CDM0?0)$pZ=wHX0 zgLlshu&IV#2pm;T@^h$jHvFv|Dgt+D1W_OZJkzPH%jxN`QitRU>R+5g%=?jDUy;qb z#Z!t|k;*Y)P*$W30v!$F2qvL}sN84?$zm7aQ{ThEsHl$?2 z2d2wY9d-a3O!nhZLJ9h&)oeG){I5wGTie>IFUC~8Gu<~U@dyVITgsjS#dW4ogBCQ^ zIRECzWVNA*PGx{`LGdO1Hsow@41jrlG_LCm=nPkoiZRxs#nqOkBuNN2M%Az62fivK5nz*qCI*DnF7GC3g#W03@F)KL>?AaZWaP~e8hAP!PbBjKa7fXdJp}_b}J_IjgTzv&Q zTX|R|0BUpUt3Q4Ul^6f8(R6b-p$h%yckRvsZA5er#v2XB9rlfFs^N&`cfK#(Ig4uB z)IkaTyc+Mw(lgUJ6=&Gzs_ohoqiCM)nG`SDm-Fa-S!V(c2Mksu{zx}<`7ZiJ#!r0A z<^TA=w7At<^(ih%Wc=6#qL$^V17KGIV|4&~3|K)k7a^}4V5#}?C%4hs#-EGh5|b%H znY}7tx6!sy%N9Af4zSyFf<1T^9+BJJ%*4&jq_Mi@ zp_e%jk0BmTqTYHDBw9Hw%>Y*!L#UaDjQN`sUFo6$wmY^}8bRD0QZOw0?N@)Oh5K@- zrg1uS0oF|4S%=$lP&i8s?aFRBs~_7J%yIBbFL#N1ZCzh!%CCX1q?a$v0gD7ik5-iI zTM7?M*(lMbG||)0B_SNl%3fiUuM$2&6knK0U&geW@5akVU6+U=*4+MF&hvQSQ6d{z z-#X7!*j-T(&sMbkJjBw);3DdM<=krj1ITbtUl*{&Aw0tT!}(94A*JE83cTliD#oET zT#x?p&A~_iLJK0+h*W4Ms;keRf1v|6OqDsI?02ets$q`A|{>0R)4S8HWAKO zq5PX{yA`%)K{3=SJml8U8a3ZLgG}9po+pXzPF^a3%p^jQMvTbWRw&#w+C)iWW-c#> z`kmVsCilXjs{it&F{jf~b!7_AM@g-hUFTPnGmWfME6u7U2WZGo4*|f8LSjjf86|qO zoLc(3yelo~rBJ_2GICmBBrDKFkj~)a1auXURmG$zT$qL7vKxRo7&D!@u4|Rayfwo9 zX4lB$mp2Sr^!WcnPdHe>Xh+AEc~9UbKKE4?8 z*I6my6Xy=ls^^0FA{1b!UTUTfuo?^WZu|8-dXk2%C4|5^1~8H53T=1g!vU&m-$d5+iM4pFL!e6z)_QE=6TD919d^)lhr#vL)aYn_FTis*1eW^vp1cd6h)X=G z3;^6USW=dSwdc7Uk%?QL#71 z8K!ViB9Tw44TMw5gzP+pmnxUQTtdr)xqim=5n%pTj*Q%o1ZT2T2%l+8t!xQ`io}e( zMBf#(mLQCxucWdNLpPlLGwxiNwTKnrEi8;3%}1?=n#( z|BsA*4b9u!+=xZ{O8qzeqpr00^@iS8J*uM)lae082z32xs}bH3+jmxyC3{6@Z4?C8 zKIcA#ZG_>Xn+=Ze$=11Yu&ncjp}!=KFn=VnGYK^Gc)J49 zmR%qmnCawe6A+OfdEtw)-lJuE()xSndr58(ljPEtnhU3oTbd@%TK^obhALP5aaAH) zWqRuq`gve9qazY;mbMd};m~NV5u`#zgP+^FD|maSNYwdl(3NYiNem6sVO(ATS=XP! z>I)fLdYl>w+Rpxakp(4*kjF^Cww2i*k40zvK6U7hH`@)ty%JHQ&S06P#d=7Mu^FDU(;Dr!)gEML4OP=Zi2d3;NxA$>0uLJA_*@V5U07v-BW-$G%o!EM)v&5 z4H)Z?E8NckIVo!-Ak|;P{A{KsWlj(%IA5!j^v@+vVg>A8Gvi$*7&%;6=C7KV=$E!k zc)TsBhQ?8(P#TWiqQcX#<^_z81>!<huid&SUAcmNu{+qzheYYd0l5fEVjWZK9 z>K3`2An(Kj8W`HMq7-vAMt6+@qNtMHspRiX`!(rQ0^SzJ3YXc~&WZTUR2^^DPjz>T zZHq4KRv%U5lsKu=)6+&n3A*3^7YlmA2Ta&@hra~bzd?-1T0vbph!Xe?g-M!XWvI>c z+2Cbw#r0?1cH*T$DtsI}qlIu=UZEUxAVG6H*mlDrDhQeS)=VGaL!1(omn`glT`^WR z2*?4M|MH@d5gH0ZQ;KzT-u`9OLmG^{Uuoj(gy^x}n?c!{zy*QuysgCl%xm0zQwWIG z5_&9-&Ky|X!P+WRHf9-YcqD5f`KPafirI-ARXbNq9Xf3CBXh@RHth3IsQu$p?;i=` zSMibh{=z{f9>NC);eQU~dzO4XICQagaORH)kBu}fNlwN*@S+tIyrgw_|D2i>!mY-G zM%<{*WNFlC5HhHQdhaX7Ztlr|#$OVKj9`IUSPgEHmNvFMpBVH*4wVv%yd<~NEgs0d z=59LI1Af;v6JcR5N8U2SDPp58mNM-&T>KQ1#!nFwnsyJh)zWJUC@zJ$9Xig(rVjcL zklE5!Y9UWiCh({b{|7FcJx3}H28UgXUr!227eQL zvPO}viuA7*BJ-i3r7Es#hC{}xLnBNCW+O5EoQoF_j7~(bEKFwQ zbe}d53}#mOn)bWcGM%pp8toXbJC+&Wa}G9e0DBC0Y^1Th*q(fZ1J7;8^D?)SDN?33 z9$or-QaHEpI`BxOS{v9BYNP4j6Y}?Z`4W1)EOHM_zpMN+k^cs5 zr0^^}H1>iKKEQs05?F2W$MNIYpFA9HQ?oi<3^`*!__&2KWAweyO)FE)Ccp0m_)DBo z^41}&111q`+E{wa93zySl1?yjhi1B!0OE=pdMhZ~_j2j$S0O_5bCU6`t_skdZgJ6W zIMu;#Fa`FeG5A z!H7EA0ZPcnqF5laAP#`LVPaEy_z@bCxx{rh6E^$xyV+~X{#9!xtX#`hx}s{vb0@vO z=-8AEn|!`J-X;Fd$}AdBLGrKH;knW=e^lo^bbV6O>c@5PlJ=7^(ZHeBM&vz%t%)QZ zKF9|%olY4=#rc$9_{8ETh}bXNot-hPs*ANZ`0q|c#ryeAZ_0n*eaJ+}HgqOotE2Jt z9)7v_S-&EoaULzYH%Hb4*J6h?6!b+V9_;19SO8!C+?T|5q&m&wX*+g;*Y)H}Uo})D zfbBkCm_qfcWd1K7(}0)JKGJY7Zqs&Ea`njx-{2L$pV&mT3*0u9ih-AJ8ME4d>yOS( z=1z9>$0OU!HGbKEP&}Owm|uDFVCG*A5jJ*h zM+?nAPBra+o~3*T>MJZre_X{;r6E1)8l`7KGN}NOZ^_6B*aP$Dm3cL;Ozmyi1=NKZTg1SUl-&)JL&BmZid^%-rG4MaBimm zhN*fD`#g3E2>6*fINz*FA66NR0YB?}Hc&DEwX5a1}9duq-#dvA-K3 zUsG15a%g&5a=;Lwum-~!7s+f(UH|MF3f zd$IEwC5=$%_ZG^G9wvg2S`@*z*`$@+>d22oaM{z15ZzIEP~yv1z+TPtu$lCk@)$Ig ztT|R=4DgR92IcU9=(H0i{qVY1w3*lX?5u;)g2nZ7X|FBvuB*Pbx}iD6t81K@HIn=7 zHIfY&-vySxT!6tuwd)oxkA=+!YAOkrRc2I%^K%x(i&Z{KnA#jm^5>&`XfI#Q!`$8^aoWbl z#;#u-O_g1RfILRc0x8`3{UDWj?*;w8;u&{Sh&|6GWD%ZmXVApVjCVXA6rA~ zhf@J%LGzO&Z0a(ev|2D4Qwvcl%JVzimXMF|QzH-W2+&)JY%s~mU0=?Y1wRy_>}-#{ zcI=R*g@Qh}lE-}t3J30bB1KpQmhhZZi^{&re0wf z31W1~HF%0nl*&b?5+DWvF*voF(!v7hukjS-`+t?4OvM)+roZ=i&HliT0>`8iZp8kP z8+pS9rpHVZQp;X2>{6SF3q!ZrLK0}iPRv**435lCWyrPJ9RQ#}#@WJp1HKXiV!<*R zh#M(vsM-zGI3#vsAlAo^PRZ;ZMpSYgutqTMm7w&c=I?0br=zrVWRy8Hs%I-AQhLfF zOk9;fWB(un5kub~X-=p+(Q=CT_xp8GBIYbg!+EnGN9{@$wp3G>+=P6l#6xWZgAYx^ z6)FvHkLT_-#DxCoQg~b8sTJVGSPc$JbbyVq-a-4Fnxb(P{s&p~MTYS20wX$YlOAEA zLUQiTH3IyB9*C>*x|Wuf9;Qn6XEm5w@91EMWtnH`+*O(xCVJm0p;ENh+hFnzR-@B# z_a|toRe5h5sve==0rwIzcuNaVmIgTiVumiz>J@N5_0DLm`EIo4<1lsC4E(|-C zR7HIj3=1BW3G?wDR~AV3SN`(upRkTBF*3-3_kopcG_Bw|bTHPxItBkMto3NDCur}? z0}NBxv0+mn$5<1mZW090&?y$2>?j!>85tG0Vg(~b2dat|yzjJJHQeRye{V5 zztdH1t!h=TYVC>`9!K6YKOEdbSlby=6uOPZM5nce<4?x>=LcO4-m18>nX%Ttwst^u zdYU_C=LNANLNP3MS*=xPzsnS!ma5dh8D!q`ymNnl&E%j5W`H1S(u)0xYk6Bg<8SR42> z6d&1sdG#l}`Q38;#ud#03h@bn@Pu8$2+caLsyh$_&{6GGQSBienEuXn8OA;;)vJPI z`OqnYPw$F5-0;KKd9L@FCz>L`Nq-tQG^NMpTl3YKcl3aXx2i>=Xf%DCwt9xjl;0m! zE}qs|#N&OQu=`0m(eMhB=e{-AzAf%-BH7+{yrdc(wNP%gT~dB8q>VaXykn6d1UQjs zlkr_Mk9CeBh>4O+8F$;YzjgyR$cc}=WikI2ZHYc$C%qoZI;87{>13DteF-vlKEnm^#llcfSRE*gP&~m^*bI@cLklD><4dNqD!5UN<{+ zA~L=`S{&XOekSAmQ^2}33LRhh9O4x*N%s`;*gP~dK&;F)b?i=8U1J^6b8IgNiuFgQgLrNB>!JhY{}7cfcZ|4{2f?@x}QU!asIn9Ng! zqV-Fio|4v)Auoh;U7P4z=pZvs#Z#+x_%KmGF4Jszy=0nuC^9h{l+Bh@LShPC~HfdyT>V=$VS!nCUyUUfrCK4 zgz$%ks8y~BM`XV1NT6=qkeba%bK+m!#@NZ*wPyx&34rn6BDx&Q)BVd_x{mq~3WE-LU8M`kksC)VVU` z1Xn5^UX13^ewF+PoVin-7AFSN%yuL zZA7aQ*%bWmA4MQ$=FN**xS5@X)!T}*B+Lg4@nF2WAG@a-&K>m85Adh?(=U757s)OG z3H(giWg>iTAPl&^gxT5@xT;#jb%q7s?R#gI*xG)y-|QF()~!m<3rj`N;i*_WVgHHj zsH6dz+VSJ(bcGfVvgnjy_YhG`chQt)-|fP6V_;?h2SmqHbE9isb8|EMUmH#1>6nXF zU5|xg(z|0Gk%S_Ovvk+x&WR1YpfBbC-jkk-&l>{bEW|1e{*5*dm+c87-D=@$t*7Cl zyHWVIjvSgd|A%t9f9vptCOYnx>7RbxV+KpzBdqvj=umNFbJeMA^K|viFQ$&`)Lwy2 zIZIG}IKo6W&zFF{mrfKV$q!L<${lw2mP3fJS-`Ow#*{Ioz-xfT_x!F`-`8pcpDTqo z#{gOFPlxB!6RF_6z}+qC3-|}}p`|(ESAw)&FA(kySNNp|_Dii{UI^}qBHHmcU85?n zn>E38{K@wz^vVkZ&GBJ6ThsM#tO0VcVB;lktUSJ?q3w=kO$YmtZ46-~BLPn21MQ!Y z8MF>`Z(EjHXdl{`3rmND+m-Y3PbT%46DrF18hH$BWs*jcNYa53cpK}0 zidtukK3Hp>1~qZEK)?qfzm5pIE0oyqyc_k#NrF_zZT1;}$ta0gwrXS<|C5uAHhp&twVG}Q zLG1o+U=5gT|8=mu2Au?|LoC+TF3rmEz!8aHu=_m(BOVJ3w4!KdF$e_82Q_S~^m&Sl z4N$z5z7l7;g1$`C8WhBLP;!!?E3E@BSZ97alaSBc#wBtzYn7y@kTJj0PPDteEtzOU z05GRaL$8@&HARUWiAs9tptrOaYRc8V4GQqFl+$DOnOuq(rL}6J*??dxG!n)FVuirJ zn+O1>wC5CJ5s5l@oWDbS=`P)8;B6bs-M={{5n0d*I*K`S7UIkxGSAH58u>HE#K(U= zZ2|D-uSqr#h_N97gV^u%FKwZ;NBH?6W(}YBJAzvlnI>!Aj-o+fs^C2ds0(9HTJ!NJ z37B`8^D#w=9Ch;m$l6)=S_DoYQP@L^ou^rPPVp~Svh!9;+Ym~Pf_Q~Ryn77JB_xFY z=i}lXIB6mTCfyh`J>MmQ(Ha9BeghmN^ZSYEHq)nV-DcdDYol5G4b!OPG5~4%U zW`u3MWxOk{Rc&S)$^V%^N=!cOSbDfX=Ir9~#QVo2Jcfe_TW%WI9{YC-nq|@Fz zv_y9W65cmJf&a5QibA{01 zY|`!Q8b8sovGb<*3dNIiKKuM!=?y_$ju8i2=JoY3Wo+5l()a zqy#QY3VR_(jD^9|re$h5H`sa?>9r9MTI*jxobd#VmnqZwjBT~YekMe=qi@wdLm0-v zh2gC)3iMZEtJxi|Ahd2ZlsQfuPLt7%?5_g7A3sKGGF&}D-^$BPmY2(iy=21#lY{^H zGRw^GRqo{Oe^0kb(=QZlReLITDAO_X!!!6mHVfc*U3}Sx|}qsJqwS!UKG0y z=*|H1&>4~)`f?;k67A;v+GW32%o_2wX2j0QgwB?iSMXieU13*RQCnGFmX0PTjGeSl zdpW(|8TLQXZfph48CjuO8g<)+M!R&k%G);wDjA^)hKLC=8v)fBc*|R7Di}Lr;E8B; zEV<=;kPW`xqF>(*2WRs;g)q_Eohz9sn}ntjIT+xgZ0hu$)6MW{r&DM3g=E8KQ9QFd zAwECDg$}vPSx<>Nv8ZhK3B|@+eT}L*j>A&NWUkZT8yMd z#^EVQtOsr!6MOOx&sKLjU{1KAGb~6)3`yu7Hq}GU_SYIuveNfjTTrUe=yJF2IR(Y& zxZZoivBBHm>K!{0AVx?gOPK?15Y?ul*0`mgiXf(8{D|y(Iz{rHlO}j_m7|HLhVcrQ z19Q8hWDcTp8oCb3Y!sN5L-&ylP=j10IJI~gP2xXFo+m~2k6E&S&%<}<&yP)ypge+6 z!%_Td)oUzb?y9YKU5}a@Y>$qqr_+HWJaXL0ttzEm{8Fa{Pn)kr=?x)tqC=iTF@K(L z1OAU>&M%0!8IhZwe9=3u(l2+E&ScQSAij?SMVj>wSZ$-wrn5QuOu1xa#Dh% zL#IQz*<6E)OzSW^@4ryuj0)VGn(C8=f3%5%y4v7@z}>$Sl_ARnbzhcp9|ttdHfpn& z_>TqOt?rTrL-~?YhDOz9&g5!kLfE%OJlBBjWJ3lZ5f6#zJ*myj zQ{zg5vz;V8*V5F<*S4+$2=!m&W|qC$7Fnv8pWZXlIF7u-T0cC_Sew*OcI)-mJ}Z1F2HnzwFaT6l{XiR^Vs3yaw@UE?kik+dnm6i_G077n@V^cvHbgF{EZ6#t9?AI;W0+HA#`cjIZ zqBIRGX{anzxRN_mGP0-4-19=y8#ws*wJUQTJ+y$M*E&uJp8NlG-oUCLLFfPrYOC%4 zwSvePzNy9_Wlkw!gp=Lo1VO5!XkG|9hQL2U88v_$F@T$#ofq-+*A$EIi>({82@p6c-=kM7 z8y%%dW@-Dl*;SveSBaS_ZGC5sePd{09)Zb2Y^zz9v*>{*nc_fktF=%D1-ZG^=z@b{ zJ{kdaCLl zI@DwD^X?6{NoQe0PCPI}pGKTd@y#Em>sJU-&MP<*nzovg7TB_LBep#^7phto=rvI6 zWxR*f0<17u{`JsAu&i-oJJeUuoU?VYek_SD&~8^LHas{Po6A}cV^j(6^I=SmMW#n^ z^a9T=y6J(mYgQ`29He91do2>>w;-SMnO_E{Ht-G&Ow$IGPehiYRpcLc`Y++tvHCn3 z3GA4MW3VOja|T`stN>TqO7!h@`CnyA{lVV$?n#6=Xr1qN>zw;jUw}5)OM>zW?G0#K zP*a3nv;HG$W3_iWzcsD&QSK=^%pDk}8lbCm-^*vZh#Fm5t~%xluNx8Nl&(lD?>q&q znFP(ySiDx{98kzuFR!pa0>CiXYal8M#Pg|=*M_B{2M^yMqg~{gjOAC2YxsNN-~uKE zk`9at75b}7#Dcx#U!o`{ai^PH=HC+7eX}!exrEr}MLD{>6~`dwqC}V4dKI)R&({(? zrv?49W;Y&>IqSZpgP5niIK5Re8obd6DS-?)lORtWY@wYItk!l0<%eL1Q4Q+MMBpQ9QP4W7cyIB(qLuVinN;oW;I$u=Uh zKJAfF_T(c-xX?KMx3YUu?@h~>F^6%3lOX}|#!~ktGz^Tbxk1L ze2^FB5>pL%-KA_e0*-RsDF^2bbkdD9(=g5H#D*%PabT+Y*8EkI_1P%P+Gu*t=oO*M z73J>(bl5B4QwY^?S{&-zV%in8Lzhy5?#6!WLJ>&5hzLctwfP?LJ7e}FY18!|6iQIK zueUiaThjVR!?Dfv;t00uj_85V@#KW0OEX;>?*jl*ak)#XdLx|42zGsOKXIwLvnDJT zxg$YdG(-Bo!0R0wDPq6)mn)$SBz_PS9I=HQniN87nnVFgK_6X&$orp?;-aGNVSW$@ zDcjYOyT!%DyT!X-9Zoq6k2Y5A2#i#W|8jIQI#6moEKH4_j#QMb*n9LcJk`=7IeD`> zAnlt=@!~#L1!pr#%F&uw*o!~b58Ib4qE3weXq}Z0@Fkm4M;Z}BOjTS#TZy9x>Ql|2 ztn~2DXOSVQA;(^v-ZKT6Wf&d^&ZF3*Eqc}K15gxdG#oQp?DbTW8+xJQe!b_(Qm@5{D_UGI{-vV%>u*9t-h|$C@|B4<6^=xH1q?Iu6Bl&?1M> zze_2?#{KCh{m*QDBX*JR2q$oCIy&fLX=lIT!&-wqH8(Xq zJb3Y;S#vbR`M-#}k%ZFqjz}An{zDBIvM3 z1cp~j+f2}|X=iyG&&851r(u1A<_`u*(Z4Ud?AZAzger0gxkdZFNa3W%|C#dwAma+e@Z;yae@KP^DTa=pGT2VbSiLr8j%vLbm?Hz(=0SVja6%Xu*xS1Wa1NyDk+i*J8gPPx3HtGkd{~I8l&(5 z#vmAQ4bk3%0Dea%Ca5z!A;>lsE)bTvdayhpZ(8RKI$!cwVdc`4CLrzn4?Ocgb@Pt&0^mi}Pi8T#haU+6uCC$Hc3hRyP|7Pi{*p%g^0>b<@5W zg>RYUx_K4)lZ^ri!v9FoUj*>B=oZb_y1UUbGZtlgu4ZM=fFkIdlfm4Hv@JnYax<%n z@t|MiPEs{;GskJtu=TTc3}N^Rur@zDQG48nA9*|?J$x0>wno@od);4hzMrG?KjgPx zTb=r@IpHu5Tu`}(v$OKSeXP$a#%{?G8F<^hKHq$3-6#()`)+U-2a3rj?u_=IFQYb} zf{Fn6>5aF{7O^?ORR zWs9>vZ5H=%oAfV4--0lIkQ$o*Rhq0a8kiAe+gx zl?l;`#M|JXi@(fmH>@T> zZ%ww4qx%$eV$D?_@UT5y_Ip-*-U+tiF~8xrCIq2yKK##bFqQn}qg#^jZg8V2@(IVD zT-yPwAu8`>pM5DKQcMIF5`Vos_D9?~`Sa4;0Tw#*#Jp@`p`#A5DMT+pIck35 zJf_S$V?S}fuV)nc@yD;P^q&8AsOxRs*hQ3ucr=B!flW|!nf;3{QsU!3e1H-dRcVk`Zw4fNvd8UiASs%c~plhvY0LjV`o(5vM3~g zH&5{h4U%Gv;_vM$5xV&D4!-|VcLd0rP3o<2^r#udu&7~M$fq_H?9IhL*(9?Mw60*5 za|-2IG-Y1NmiA-(uV==e_KI(Ki0p0u-PRqrF>Y6TLI}>HPI{8<`inW&_Zk_%x^n%x z+wo;Skl$$FPu&;Z8WOJ$Zt!Vqk0%Og-3#obzXy)<4zsU~47^C3;5gfd5e!#oz{uIu z=Mm>jjSQbxOYz}a#r~akup~nS?YYpk`e-Po@sxeOj0T2xU`hlo4bIE}OUN8@J%Rw| z`7v5ALPwm&chz2lgO+jBw&9)fk#QrPbL|l8;6q4pc3QGvV-(2&5N^=nVR=o(+|XOq zQ2GWI2i0A7Mk#IdEVV4~l@KDzt;k>dftUCF=`;fW*M}j5UtRV%gu(W3sUxgG zrHeH4^^%>>vfsIMeq4-SU1Lk$_{nv4M`&mt_t-Ll&Mn6Wgf1;Uu9Adx^dm8GS23Yd zBw^rmD;8xB^?RImcY6FNxVX(n5_c0XLlJ0(0T&R?78cJDK3>mPF~1t#Uxi0Xa}mn< zwlVz)aiePRcG{!Z(M*35MZ;T^R1|n)P$d6qP}oVZP2E%~h}!)+x2#`PyiK3U=&_QH zWZ21Mnn2~jBt?2qm5nqx9gTEh;$Y*$}v- z<2Mj-Lx48$Q3-xF9_gGQSJ0I}8`i0vlyUyJqEn^r#m^Kyv|X<>byJUVtQtFP`%^On zKDM*1ZM)yYTFVODy1b2yKepQ1y2DyNS$aekS^D@L9ZojYla{MA8=uEU#FMsmxz=L) zIb+EDB=LCYWov80S5e3R2iZx1Um{^zz?_*w5tPiLJpQ7mBnGxKvGfuYlLu3GIawi* zEGQxYaz)gYcAi*WV>&1+Fo0H=%RzWUPOtNYbxnPJU}U=)fd8rPVyJ-_$%h^1VQ%fZ z_q+`EQqjIgG5X%}`f)*KZ_jS({+JQ%e<)&QNWjUnK+n3+T)oG+QM2 z^YA?Z_8LwxL$8nN^Gu>sHD7SP$Cjtz$9!>Uq;wiw8Vv(B&ip(-i$5|7Hu`2Q;Bi|d z?*mq-vR_Oh3|n@49)#+C;Jv$^4ZSMWC`OLz-e3$FVluQ&g-P%ak4mriQz!-SWy7SE zNh<8giYDfkpgxpR^UedwqqJK+D2g#Z9wp!eC`y3nu@lqj6;&RCwboZbP~@DNDvDWazz~545aP%|ycOkXeP=Xo5;*eS|jRH`IUG5#}JkwYd&C ztYO|bU~PI$s=`peq2pIz2gRYH&K@l!E*dv-7DgA21lW^yrM2<4>XN(9MvIGTBN|pa zIfW3TJlYM63WJM-5q-;Qyy` zP z=OJ)7(1yOV6lHJIdcw}OT0q@pz1UrQ!uGmd_v^VueS=^vw_9|=5A*x=5oH~MwgysK zd-qjf+nfSvvBhiJ{@ML0H;K}aB|}EfOz4O;?|S0+9zO4euty%OzUTSV?dB;GCZgsOU2){4_(E%V}Ilx&YZ>3Fq~Xc z&nR<|8Qtnh+(J(lqM-DjIc$1F#>mz(M5;ZFv|hr^MI;1`$mg@X??V#hRrhn0ras1( zHa(zs7E-1w05OVaC_#{&tlG=-4hk=6Ek|WI%d$Q%Em2AN8kUhzS~lmFY3ajx4A_2L z;Lh^CG|#THtGE>M=S%MzMqHUcg($Dk^{CJHEc-Wl_Q(TCI(^~mi;AN-M<&UdrA9If zD9K)au0hyGZB8(Jc#M9`EHDLgQ*Tl4%#|8cKx_SYgTk4R8{d*j6-bQDR&G*cu@ywhaB*Z>NBbq1ma_o|Q5Phn}g7Cid_>_m{s6vv)l zO@jV=BFM$IHup%aKxEEpm&Go>+L4+%iV&!-TCar*e%aTAo*(gVm7ZFlg6rX4t)f=; zM9QadbRjkM1V$}+f~Ap-PHLcgvEvh9b@$24<$0bJR;2h`LZ{G!-P~y(mSb7fk;4LR zBIu!(;i-%iLuht6RJ_2aZw?uJrTET& zE=l}A^6OTl;_%hIMklT?)>`dRR76I}eDa{1*g0Haw%f{X=x({wENTdmtCI3t;-10h z_G;oZErReyc;P3lVr&GCi$nLiukAcMWCSz6k7HV?)WhB6PXD07OjSADg($+hBkvj) zpMW?*-{se1cgCXy)(rVu;%MSJXZ~w4evq@)Ms|Y`IT*bb&h5P%d0dH!-ET& z6AH2tqGWiu7wQF#fxA$!WLqqJP0b#Z6h1M*cK-Qwv03P$F-u=jFUj zR#vZ@xShIPAqW2b;lwQ~yHs0;60JugqM!bSq%eJcxETf;k|*kq4}C1{jZ(jwZ@v|D5r_w$o`K z6)u{GU^BU&B_l#b z&ZwKh7`M7R)ernMK=P$&>c%EXU>RHVsq54I?mfMS$`>rGra`vW8AFBM*}w~xC&ZPU zbJgDb8yoIgeLA+CqZwm<lbn<;;%mn86FuqWBS1IMk9A7X_O( zVvh2g7lEX_XsQQ5mU@gh4Ev(_pM~geoq#GKY9)AcE+3!#X@A429_r?&03^hP2-1n@ zETK~mAXMd1X4Wqc8`%13=4S%&6S+pCqQ&-l^G7oJ;aBX2@H8+6E@kqEcMZuSjAIy9 z+iJI(jfxE~bKRyXTQIk%u)hipMovyvg5G_?Y>hxewWu2Z%FsnCPdm+O82w~RbVAuq z4Z*z}4yWU62N8xxY04Ey{u7@Iig0_0z_%`E5FB+Q(E8(g#{0G~e;g$OB^Z{egeeBZ zDs`sUH}}&K5e3|~U=$Eqq@z11JcsAtA_DwU3)43unIZ}osf(q9x=7B96+;}&M}|8H zG#P(-A{)|&knl$R_seiH40>#=Dx6u-o=RK+6}{g-DaD_iX-Dx=A^knE9QGc^)a{M( z)~LJ z`<^hpG2nX+FH7PqZ%R!mta*&$u7~y?E5GK=&*YTEE*?&X($LvkW#nQ{lWwI>BPf8pnt*_h?Sf8p>rdg0AZ+P zL8Ky?gj~3d0e5Z?2T=lSIHj;^(R1hovDn;JJ0T7cW^4GWr4$2EAR$@kqWe7f@J9>Xwx{D~Rt-)7Q3)5Hsfr84FZ*{UX z5}5AkU&o}F#Qb_$G!X{Z;tNzVBUnRz_0v*!$o>No#jE^p8{I?a7wfwC`2s!yl<@Nz zPmm5JSrF#GUUbv{{Z^h(o-B}6_)14m&hW?nF@`|7lhEriWE0kzFmj~mL!8u%!m@|{ z;#kEf(o?{d8)-7wg9jH6@)D7mp}oaWv=@*%3vMRsE%I?^o~?(+=8t&o4%<>_z24ktxNUZ&_(p$_ELdkn z!H;$1Z78$8BdJ8t>A&Ai?X9hCm~17^rA1Vf&V9pVkX_Q|w@oK_Jl$IXwHR|6&w6qq zWnMLAF;JNi*_3*Pt89TPP-3j9HI_8N8OCzzN5-aQdkHCL zh$$x$zb8-?nxSnis$jDYC&&X&&O-OvhF_1z1(2@#L8HQ)b zi+iSz{JAbjBIGr&Llz1x6Y=s6ieUaxY%}tpJAqSh@F>YVD1mlG z^gNI~?@^e98SLjcUuOl7({3FoU!ztL` zC5KHJCwz9DeWd1`>r*hD$f8F5!g_pY39G)EnIs&~3vwIKx@jy}R+xnHP1`9Sh1QFP zd}Qt=C-+bEhV#b#(!PjLPy!swsZ)mf^rqP>?s)KERPgEAVv;i|3N4tBNayS~>A;j~pHE&U;sS*fIq?H(()xe;gY(FYh9rZ2? z9@&~cbNfo`!WB>r+KBlxWC*T^@gNTM(vAEiesOAD?ZLtM#LyT1cy(LIl?$5pd$}=B zKNaL?{@>Tk2CC3MN5--^Ls>1}!^jiRRBVf*?ugsx3nb+8a3BMsE{2i(kkN#5x>L|t zKu42S@n|}aHIoYUtwqSwh(e9WQzNwdTd=@;*tOsHcCT*u{@*G}h6CUEEWd-X7Sf_~ z7wNAM+Omk+`6jzu9-|`u=Lg#LuALr-{P$unl6k$EoK8ZZ7qBwWux3swg(4*C27jg0 zKpEs=XJk8xM2DzzB8YL~!~4)5NiIK5vMk-)0g({ifb9Iu#7pziZ@ZwhOsXs^Dcemx@ILTONrEk#r_A>s zJCiaXboXU3n*tg11~kuxxO?@57PwMk3>Z`H8gzPu3M$sUQ=+_D4^p>}C#&@=T8x!t zyjd)@1V^%Co-%jB!#Qa!B>0;Hvud0Ia5TyajmR)Mag^6nFMymg!|X8j0!ge zp*(q|4-&fgE&veli;zy=V-h`|(iUsCWq8;5eG-0gC=C}4NQ~--_+Vj6ReG+J{Q>YHtQSS#nNN%KRZ%b8=-I2{n&F(R z>Bu8Ip2o%iVo6N3fk*;Q63)qdKY zk&$sVa<-W=8q+CKS|wFZL(M;;4}f#J;za}EM~e2SGn$V^Ib=I*LwXBqHEnHvDo3Q# z!4KGHU0al4^30{(FO|h-yR)R%ZaIgkeYdWx4oj!k^RV2HA`gK~ufU%N=IWP*cip9d z{q0rPR!}#i{d&wOhqvXCIR*F@=aGC_?rlvOQ`c1a0~Cul@^gKhC4OGnU60)b`Uts0~if_GF5#z2(J zr}R`Q3*N_W64+YUqtnUsN5lY5Tp{SqWm|g9>=Z z*IiN)!p~}IB#k2`*u(C8y-^fd<%3p0dv>!!^49{koafP{K&0T0EKA$dlL=%{9mGyz z-I~>IA<*su4Eux+5;aiLJ?+1qhw`ogzsPM(KE`|xiVh5 z$_cC|#U&J^kpe&lr5lL@h%AJJwm7l^?+;xQG4LdcEFFmhc)f*W%^Q6}$6YoB&U~(* z*8@7e1B!n@y%9JeO?Id~S)y$xb{`yJTtqx!;vZutsm zAfvp1pBlpTl?kF%o@xEFrO37dF03IF&zcfQiWXuQZz4=`PnWdaCWo0v;iU&E0BbZyV)Jih&qp+#) zD)AZ_>}tLHM>I57_{RGD;ExYDY{9FmZe+!v$#Xxw4@Wg5U?ZE;QI&hfMn4Hlg6T-{ z)SXlu#^*kFE9<|KJ!gk4yH8L`W)k4zixh*YtyG;gOHD^;nvf}+eoJ4EINtZ(Qw}X< z`r=`JVlx0*t_%$u%8ySrcs-%<7Lw?*siuV>Z;W&%vIM25n3ZM8UjN;vIky)7xAS1( zMNl$=6BIhvU{!LRY^OW^BjvI$P<22?X%r@&_5EhOT`C30*$AW|s;7>VvE)F_fgqTq zD%|h2er%hxyrn`dn2Vwjs1?>cg_Hbq!fW^AGcbqSjlAl5A4|3$&^h?hS=X6dN>2uo zQ@ReWq=8UpGML)#9fJLW8M8BH^s`>-Nfd5U*S5_OweF}pb>lZq|hDZc0ZKz`_>@; z3-hhR!CrqLrk?hMvs2&F3(c0P08EDF3Yd3*9A%|_tDqU#5_n9EZtntusu>!ByqYhT zc}XG$ax|#V6j%v#gotz6aUaaT5^{uFsjhg|pm!Sys=*6lbeDaM)*UERUhzOXvPvT~ zr(l$BqHbXt4o#v4#bm)LI#n1dr7Pe{FW@UrUT%#ll860%H;nL07Dg4iTAWCzeNzcq z@x;hp7M98|8EY&Fw-wM zcOxeYb`|I&?3RCBhc~dd%I2j+IArIXTz$`mm9hFxOt0JL3WD z5+#{{MoD&PqvI|=AR#HU33yhUTjUohqOzYW{Ls-1%{^q!_vDtj?Z#HyY~h=Hwu~(N zsjO*IbJCNG7QUxFl`Itg0i-q}4|mA`CTGE2KH-M`8g}sC4^j$ERLrm~()cfkg*A#G zt|tpc+>%6e8VZZGKvm>*e?dwGmFf=-FP+kSX1A8mh(tAjmh+KhmHI)f3EvE=KVKpd z|HbClD<+R2Z%);{7p(6#YIV_X6SHBPZ++wUqLMxe%?~)=lKz`J*~s}$1SQuP+8P*j zC+~ju=Htfpd0V>r!+6|y8u5WHrq8E18GpA|U?=fk4s_?`AK}M^{X6K_1?2bJG3$<3 zYaSTx0KMUJ=Lc+K4abmVI_UMua#Kr7Nl)%u*5IqH?ddN$WSxhX0@cjr<6MuU_846E zT%gHI5qA%_@B4lSn6^9}zt}yhg!{;Tu7d(0J@cpEu91pXG)BQb5J`R6=)Mz7t-^I$ z81!{X6mU!sQo3&5FXYoO{bvVpWSXfmppi7G6J!!7_2%XoJLI6y`0{06;ySZP`RT-7 z@$hTXt3;Rw>40s=glbXbc7rE3V|vngZvq+%aAO(3`rAvRly&vbHdf!Lt@&gDG+a*8BnWzVkk_WEC7w=e)(6R+zVSPRBt^HhJ&83U+mUI`?y_@01@IM#G@~O+KWj;T<$20fN zq*zGHVQ6ToI!gA^pS$F-8l%k8@h9!Xfw9{G50k@~;?PN=3Av~O}2FlH>} zL)Y(^NAlK&E%@atPo(dvYulk^OS+YWJ%WZDRYAnTu`S3+mV*>RLwY$^?I7-;0-;%4qqWs^d1UVAef>3B~BS&0B}K9n2~M1uCVS%l(kAw0`+FB zX<%ByADah9{VlJNLWX$W$J_e9vLpE^8C}m4^<%YK%{Ee3|2!$SC@0-mGoQ^w;jpco zTVt&UW{$n!B1)X(-~It0qx9;@b^pH<>KlFRBYy4wXKY3hzp9q?$ss?6tl2f6pMgMH zk?%X{+n-ZR1QG+eZz6Jdm0;DDrhM;GS~4Hrul185V=9k)w^*GY=Us6Tr@S=|gmuEV z2Mz(vcR?z4_JnPFGgvznsYIR~IC?B_-v9I!R@nrwqg; zrbCH{9R1{fc+$7sYVI95POyA@k4`)UpDF}rgC9zh+L+zdn-II?lMTB9MXIWy}ndH_Q4^ATH6N`-q zG0KgA6Ut;DSGL(lGpH&wK?kVEzp(V*sSzx*ra+>1MHd{wv??K9qLqMe`0+UqM9=iA zv?CPz;{*e+V@WC1WE38hlGjiUl`HeB6~OVWKBoW7xmPP7x&^~>{Il$U-IF$r3^z<_ zHSi{BG-KUb+T_kcRLDl$i0_L)%JyHt??eM?;Sj<8FQv)I)$`Gh_;qXl4z>&FmkMds zhWPT8>%z6wN`2M11DXA!EyNBQDvz!}C1_l|c@f9{&TTA{my$t~88^MiYuIb_DEnXXhI76)aLRAuh%QUqY z?3L`7EEbMX_KpjTWHdx-h`|4HxMk&6NE+l2&J6Z9T0KMvtbOwD#{2%vY0x6_C#;86 zW~NwskU=zz*_^V=PMac<=<>1hdhkuiW2DO* zu(2XKWE&k0?D3D%=tmPda^X{0=fIeovC!JeRHBfcVy5!2!)b!8B2yJ)(6AICLDvy6%f!;jJ(P1Cif0<4e$`*m`aLE$ z>Ca5T52VelrlF>x(Sq4xhhVdr-Tg3RsGhi4sV%UMIAl*WJmrGu9( zMBf`ifp^?b!IX~+0pFXTYk&Zze{ZJiwKZiU+DizYgEpdyVC!#pc(YDEM@$t6Mjj?e zirhXkkS0KU10O<)X5U)su__GS+84~{;g)_8))lp@Cc)?4a7(85^W)*D!Y+F7UYfC6 zGf=_ELSyd+{W5IA$}yyD*zFEia4|DQ&><0LM5N#};??y5`3Q9)otjTVI30OW6yOb} z78HKq%K^w!3f>wfrWBW%sTJ8|FLVfINnxc2`1;hV){=Abb(nIwMZER{llnk&mo{6O zwqjO$!w>n*e~LXuy$>E5WLl4vSsbAsz2NoeU4Hq2z}09mf(h2y-^`uYEkQf`o#;Er;8rmcwHpItS|JRO}M?y zQ*X@T3#Ap!5J__>MrapeokCuc!}pdSG46fkO6aG@mp6YjMDe2@Wzlu(tJo}>+$C9F z5F1QlVi`ykBPmKX18FqJE0#0@XW3TBTveHcQs#CVSdG%JlbnMF(}CBqeCRG0cu(NE zd3%}orN^Ea^7`2|JGEn#L_}-J?QeKXR$?GCKiIM z_lHHJ^qxGq;UZpiAoG?DjPUN}iSOm-qFyzB{j!qNgBKKF(}l$mn(c5Q`3b zqc;_R(xj>c5K&ZWe_5%sfPhceJ}(B$MwW0-xOGycF~lXuM7Lcy&!rEjGsg$MkkO_XLy_;o zBn~`6DW!m21^vk=vaptjf6F0SOLF5y_P#Q>bW^x8$e`);nHA24(=>v<2;d;Y6uLKA zkT~s1pEOZ6+g2{<03Cw|y5Ze|>vH7DQnxSe_WX6+_?E2(`*mXnE3REtXBDNl`e!1k zbj#h#64z|%kB~FATJ4N2sjDu`0gX9cl8+qO^Cj%H6{UwVE;ESSs4~7uz(REqJat7d zI=&*%S5z$S_e-r`<;i>PH`klF-Ow>i#^3JmFCDnPz5rs_jZokhpDkE_AQgJD&`FZl zdtW*p>v{L$>$Bl~DjB!pe;SxMAKPUYXbPr{iQmKO*K>cruO}eX2gb%WD!#>f0c}X~ zxS;SX?m|#b0ie2qiJ-Yw*mtZ8NNG8-quE`@C2kfH+Gj>10&kAom>G#VMr95COhrow zIfzJz+YxoM2L~yJx&f9CoCP4(nfupGN*CI!^GJba!Txi?&`QEa!X6$iq6cNAvq@3s zxJng`r+G8w?D}+9>daU(+LP=#jZmP|of=)8SYkFdw}PXB(HUWgJka!4kVn=}^LpvC z3gF!~(ip+y4f)VqQ9m*3UCg?$Z{=%T?zz)|Q97)k8-`z#rw{&!lP07HP{w__QN!kn zl)o)={$v6gWeOxle1Eyzq5K~IBP&m9cP|yf3ULJogbY*x*P67$Mlld$1<2|U$=v5Z8Wix*C9 zo;Xm;CGCqF8(Laee){GnZ-#u~2K)yd23yTrF)ugT?{`skBKx8?sLRx?@{$K|%qxO< zTZlISaMn6Z$sJ6#G=xKlU^>W?=`lm|441C~0l-NuXn43hCB(In^~cSqtz7uBGu(}> zC1LiGAV~rMVJ$-l} z44OZ}EtC^zWm`L$C0b6#>sD7{&N%o=>X!qH1gY0+Xo+{Hf%9Mey zR`R77E!k%$=GHe`w4%@DTn($M!D9wq^+8xnV)M~O^ihz|amq|Zha)ZcVTX{@*>D8q znMlX^p$va4^2$+SteAuYQnPz70C*$=up*UBpm&Rs+n&ZlJH)@Rsu&DkHJt4g{0~Z;yoBQ2pw=!u#Cse2w!xqF z>^@7@U@D{?cy||MkVZ(?g5Ut*7Gwe+m2)L~M@}N6h0@MsQPbRHg%SF;oq&n%mU87d zYX7s7kdb5^gTFt*j-C_=MkC)hzdHEl74>fh#Y=}1LdL*+kmnyIjAcR1h^?6iIyV29 z_o(ixM-COcC@K#$xlRY!kgS5=j_@~j^W04l5F)k~x?vJJ(zX(*gzy-{Irogq>tad zCdrscPgbZ+4uP@tT9UcAoylrVS1clh4?oF8mA;Ck0XL9lh}cDfB^aG-9#*38Zy0L+`j8n2lneADG9DZQIFOp=P-kus@!A`!QE#j3o!uo4xcY-Km|r7ecFF6v z*=`F${yI)jiumYZbAV(sZL!;gJi>CMII%F?xkj(9^agg|NS0e~Vs!{QPjV)M!4T@k zA1v+9Nwi;P_SF3y3&(~_B+O-j7)5WKHx$1Ey|6AniT{>#Eq=}Pc5!%LZZTfvgdC+q z1O0p2uN?5Ve$sDGxYe?wzaZ(_&)} zFHrz0b3O8noBYko#eI)l5=0FI!kR}T z%VrR$Tef2WcPz{vBR`kmA`6%p5eiO&$N?ERlJC=tN~3;UWO0QK8ys8}&88|93zQ)+ z*!q$v2w?uk#xlErs$We(wW=q*AdV%G;53 zE8d7zKI8r-n9(=mg-7}C(OpXYpJk8aQku8{tv|@JR`V8e!O2|EGs5khmEn#rU0d;G zbfo~8HNfDcJ7%cz-Pv||FNcp`^$hQV8)*WJXoPwO`?EwFK|$%lJ2gRhk@9R z=ViRIz(l%66wVM73kI*LL~`k6G>^WV{)umdVdINK3Dm@~XW>rxnQ!-}8FP>?voy|^ zKe|&-CdPwn9+tRQ%pGD^T8^h+w3{e_M?JtVH^RWxzjQQ*b#W58LL0N-AO=1Dfr;tw z^QWf-!9naeQmr%?Q%uUZ;0xGe#otD`sV1$Nb`GfojBf@Tv~s2d5s;8VGJsc*bjA+w zXe4>3cgGZgJ|{-6C7cV$X|@|3-t{yzGs|M}x_ZrJziQ{{eie3W?^FHONAbH7kOY}y z&v}mNekwzKk{Xfe+F!nC+F8H_=^-Cky0`qW8Er zUt(PqC7HVaZ#qfXJP3J%uJi|R z+M19HA`1r{7#H?c(5K(+YYuG0tB{>I5Qh{uplT`25_;Gbbsuoaea_k8$SRjYB!*7Y z4P^`GF6ROzk8$|Y(tItH%*?mmMg{%;_NZ~iyIE}Bk}`vhmUTq3S)rIXD6}`5#%oPO zkWGL3wfLHFX(TY4)h%ew62X~^ih{74*JM{$WkHgq_EGV0RetmK;TdBxQw%{>+5aKa z0>}S>n6a_;27SFV-Grz$Ep-@bzE^aMMDutl^`w-?OKHo^xe*VG=!Jm@9(LmBQrVL&tJx6zUu`+#4@BJwNNra z+`FaIEO+#_5?|}UTpRglRI1oaW`j$`SkW;tSf_+K9HOu%>$d%xOhHt4#?`R>)~hRp7ZWFq@UFelMl1-=4x=XKAJ_ zZdT8c?S4i)qa94%BCy}@-M(D0)|Of&ChFyjGET7z1QU#@uf?N*WH(#%Hi|Zr!X5kj zX|C_cL4t)skcAOQ0r0{6H52$1@=t5l69d5u5^^ZVFpVeF%->2uC7V{&QZ^M z&wC4RcnSPCX5d57>?*b87xbdm$6uY8*N-xs*0y%)*ELT-Yd}^dns>u31f(P5(MJ>z zEldQpG1;8t0 zGGTa$U%9ryX^;9|?!&SFearh%0?&=AR%^0&Ed{PtLdu2rgpbr9{c?Wfi4kiwmPG|N zAsI@@y^{C`3cHL7frt4B8XHRmBtD7{jOEnV-u{aWs9Ti#;#f~mmSl=^YRuB-bmLc+ zIit;`USYDKApzcAV-m;L#05{+$I|0<&F!6D58fuI;h91kyd;}D!SuVwc$DQ0!DEho zS9;1ZyihRf^#1;Ul!hwm27WfC-8eX{tVDp47t@EowFE-LakCTBL4A=y{^B7aqLeU$ zUp$lk@_y?+WM>n4U>^J=YdxOkB$hPje!~+Vuiat?$jF(rYV`l{^o`+lgx%UZ){eE~ zMvZMZwr#tyZQE#U8;#kZv5m&I`Q^Olyx*_+HP_5FGtV>kTISinO2h$NdnP+f4>a`WT0dmN>!(_Heg-Q^d@ zrN(c$B&Q1uWPH$NHH!T1ewdlvCX<)piLM_nv1i-gTyO}rV#*Yfs#Hr`iKXtZY#7Ux z9t2+4{OVCKEBtK{gjJb-BB%CT28}M?-HZz`?W#>wImKCP){Sy$eJ%az>=&V-nKb2T zh&a{G-)yKyv5GSFA{(mpedM-y!+D>@L){Yz$T zVn%lCw(Y|Hq$1$!mcyf4H5NmgjV2-^f(7wYVrsDCT z0O2B#;!ak2tO5QJTUK(|({=nYB0F%JhRN&s@*8{%y)w$XW#( z=fXa2(`wDhKfYA*B%GAdd?2uaSV-1r@_gve_`InMnK~qMiQsRB1KsXa1mepI3Z4!v zUSvVwPxwZIrE8#EIPM)Me```*x{+Xo!T-<3!o#vn(Q^2(zLg{|HkDd6_KXsU^&E|} zfpAGIULqT&H=8v8h^kHhG&`))PX~^PUur%j9&n`KV}@Pii`Xyirtp(}9EGH5`?~IL zVIh;(YQ$f^YL2-^b#gd(tp05p9{U?j#l%!BMj`=HGRTi0^?w_8+^zYwpZ>ULd_<_R7Gk(M-Iv}( zAo%$^7ZnJBe>fc1o(?;upZc7d)zqJGo!=w%Dt6O-(u{|Oj_&vTGm~P_%cpL?IqK%> zAeYzj;Q6np9IVI^3bc2__1|WoViAX1tu_J6&HdHUT&1?tq{F5!ELE_`#W2^Y`Y_Os zpSi)~p2coy#%xlih!V{GwhsswS;uY7LYP$prK`JkX9-!88{QL2dlXkYy0SqOCW}F9jB)?a z{BX37MRJ)W^^7U`t28u~U+5DHtSACuF`HyF2vW0(p2w0y>9nc+46V;tl0MA<(|yNs z9}3bHkiT~VWnqGWqalp*cP}3t;a1=Z&~Qgf3C6R2h!68@b8=RWWR}Ok+1VHi=?P`S#FW{*W*X(NO~mjEHUt6hy&B8 zCR3uS)AU<@DP+LzDPvPrZ{_vuA|x7Fn}H$9!_)uPw3CY>Mfqn>`8Vld7h=5Tkbd=^ z|1gADtOHn6Ch%!g@HL*5aC()P+0`@eeC6a8&R+?jZL1-6PD9J1lMz|L5ZMy#2JLaaT01g* zWI8#CCc?R@@x%M{>LZ$8?I3KNa?pf5P9>=qADj*Dwe}F98_z}GORGR*HNM>ASW`AW z6WaVdLIm-?nvU5$1og20_OZ$y=Ey|TGLo-oW;0U+` zE<|p=>$S7t?PUX3Rw*G38t~mzBN9JV?hz)NzT&^=#;Eu4;NU^W_LQ&TT;d~vPTR9# zm0pKxG!NHNi9?>CNKL@$LZt_Ef_!~1IaU3eyUknov@NOQ(HQznm8}loJMnI2ep~xx z9a!?-;JI=v=bQz9?OZaNlA&p%^=)nJ<)U7g?b;-E$!{3V0`pG8Y`yFcF#Vq85D~-} zwzoa#0W6Isg0NR$2Qe|H8Q&lPK|f*N!Op)O;xcFG&@XlWN~g~qrd(G&xpC6fLT9O; z`mqiIjRLCw=r)WFikJml=5;!ZReh5giSP-rHWAM3Q>`bS+a`^$t9PHFalf^$0{Q)N zvbLzlS&h${6i3dq#_hqi&0|hnJWnrD_bKPPHosnx8X5OW+}vQo0o!nvNHRv95P*U9 z=0cc^pidI25`DGC+fo2s9U4Oa1cR=k_zsMusT;^|eICr_va^~eeLtl1HPkIsrt+(q zwOE{b($Rcl8+wZtNp6_H#t474$vod?PNtj{L>Ho23nDYv2wN3SRS(ZxQKL}R)%eHv zv#^|RAnLv?O5SwIH9z-ah|%WjDob-&)pKyO%6jzAQRB=iEyP0xom^9p#Cwv?DP*of z4&Rai0epGNRAmtcXtqNJcpyl+%f9dNJ&C<``NHwPz;z$!r!NfV-)dJYA!GU<(z`wO z?6Hy2C2tyi10Ky?6+OQ*-jM-Qi<4Nq;DuBawxEF!JxW^J%kD3h; zXxXfVu41@>AN=j%_m&By75C&Ae6_^DbFy8%YZnfz#@`W z4C3?8)2}a;PGd9lWk6a0SPyMZ6jz&;R?GR&yO^X;nC#2v!&-@k-g}rw6S>(DY7zM{1=8Rhnl)Wn(#89C^G=( zZrybcHwf`Cn{;yO`93B-?Q%CP%#te-m*G>usN_iN042qmmOn+O0>D(uOCcHIF$A<| zI{z6Rh_D=`Oz?!r2ZrS|kltxD78e(bHWd<`yD~Qw-x6dl@L2RrM1uYPBj$7`zQ01x zBl~~>Q{73Z%54m;6*GcQ>OYc_XW|Y=k~B%uC;ZePGLAsrEGlWR-&aF#K~r<`ZHIus zs+RE>HVM=to~XMZG(f2CqZI-pmCW?n97<~&hMi>SQ=^=m{CO`n@E4ORN?^*@YCrPN z*!1FWj@gP)2+~KA+Q{x1lb|Mz1bg#zFH zU8c?c`3lS`9vQWUDtSyCiz-3I`?mAyX%7Tg2t4(qpA|Sno!<}bSgm zbl9U~Jq&a&^XAoQP!%9^2&Dbofbh5Y3LoPfm=(-Hnu*!;jitEX`tzAJtZYWpwrpV*TH_S~-mBg6lWX>^oZgiq+=14S=W!|%bJX9Q@8V|@ z_Z_!x6=BWvV}aXIc78?Cp;LFJXJJt>10~k|=0YZm-J`6J-RYERTuC^8ERL?6;<<$$ z53Vq#O5V5|{KWMvtt?B((#DI%`#p?Dq}b?w86-he^*$QP-vi6ikRbrC06Ro`oE2BQ z;*^KYMI4ttg@vi&oh5EGL+=lW_4sfiv#B0MW3PL8f~$6NYe7GpO24dkac zSioNX>-E!wA5n|g_=kOSsd_gTP5TUV?|;m(`Fp&)WGDVaVOw7{4Q1*DG34^LJ6@*g zV@J{MS4-qYA;_smrHNF0rL{%1Vch-;~x4AkMdq#F<8l&E>Q+ z2*QWfr?LpHDaxy20|$)l0y!pen3xEscZ`{H9vi0zS^e9bU+@V< zg6h$*OFBO!CMtP2S%Vky1-*~M%1l1$8H^6>bjxK|>V7|M_wm*VvnRdT?UNA5$e)N* zaHWkn?78@=&QjL+es}DN89W?6h**B;zULu%Jd7sbZ4cc`0YuUL!TeD0i`r1 zdwLu%zp_U@nOmKOenoXF+D#0!B7IrhH0vnN=C}Dk`j1|B+ueib8u{Mkd@r|yKNe4` z8KWNr(5mSYjIojzzVMZGUWKL=o}iX=&?ch|=S_BMSog<7jz5^_t@-az z9yMUb996H%#XdM=v7iJ#Xgg*b=>B-+1;JWIaFJ8G2K#pq6m3RgY$o(mhio=P?i7V_ zLZOEs?r4N3XrzMqr_9pj3txa!Rh0mW}Ynd`c6= zX;xO%yB?e^%yk#Cz(@eKI*V4^)%R8`9?>Qx!KW1P+*FnLwETBM5%>0S+Ypoo_uhc6 zf4yg6x7*GQGvFI2V4E)^L~^D zn*l2-nad5eya)Wly4!+W(Sky;-|EeZQ!eX$wjzAv+0|+ip#VE~*4-SdNK9?h_Cn9- z%ZGzc`zFr2J(tT=b{NAwVeMf%W@a+U#*3^KyO5V-iGEZZ^i;2Gh@615MXbI5Kz)e3uj>i z^rXcjFUgZpg24ZZdtDY{>7LZev~`ZhXM`c2!N-xRH*}@Tk#aYrj7^N@)>GeY($}oibLFB4Rrt$mI zR)j%<#UIx77=aY|Ql}mH6K8Zl_vUQ6Qnn*OaZ{0Hu1@IV;NQp>YpJ~qr__XOGztdk z6_!Bih9xUyB{4J_1t}6uy>_#Q#F1QC-2epc1n;+iqD28wLiG+e`>!B3UUBa4J+E9f z2_Tj;KlaT3>nLRdKuP82Y-wHs?@gR7jgJz(YTAqDZI2r^`LV5&7g0}X9v5BENmoQ2Syd~r#AeyKt( z8XL@y#)Rc+uWN@AXQzW*zjaV@FupfYuw-4cR28{A1$XMW7@m?u zY@u6C_ufbd^+f`rAH0@l2ljS2znqV|N72idPC@7wY1IhczOA>CcIOsb3yJ(q_pQ~Q zfq|sL$aNz3FE> zRpgFSVKJC3hg3skj?hjjFrO`kv`W?ua_x{Iqr~(}D-slO!EgkEI9P_A{24>HpSIkYsU$agPvNzht@3y#t;IQCiNO_ZL-OgY^JL6 zs|}fIQgUC=y7{f^M0@z&)xmt$BNech;lSKxCGpeJ$?h^?jE|2Gdwr4-0_o77=%<@= zAed4Pq0r1fYKz)KnLaN!S%TxVoJu5WsE)>tE!j-Z+^0ix4xL)YIYDHt75Ru#wY;DC ze1`7)QpWs097u#YPK-l&=A!7-$K0tYzZY6XDTJfN5kv`E5(&pNEe9tGQm!AixWhrT z_|vjN^Kozzqi$MI3)7^uS0EMRX%yE$hV%5-h#7uVO7Wui)25;8(k{YK6A&C+1jjA^6A z7Uw1W_QC)>Py@XA=rgJk5|xlIa)_rT~4+lcRLd}h$J)X7>S!P<6ya? z9svy~nhJpJLL~7Hek{Q6{S{5)|5c-Na+k!}BXPD;e2$?0FenS0{7Yd5ybE+;kR=hG zt<0oo4PdETzT{hKw+(53yDd6Q<@ZQt5Wki8P`!h?BA<`|`HyCSNDd^NhZy`c6F_N7 zQ|=YICDgGA6y5ok7B5PwQN~%j-%9cH!h(u&M*%Y?0>cgpSWpI&F}q%53TKDhMR2L) zQ-{lNriMTIkzw=hky&WPoIR#%YKj&OeOO*XMY(&2mkBLUem_7T6U33nVolh0D+=Fn z$Wf0!GHzdv2Dx{qGj7vxFh8wMRJ$apaC~HRm?;y_oFQ_3+RHW4M~@F&Pj$WzD;wR$ zO-C63;q?C|(0!F@M6UdI3r*BV6ohwd?O?9=+~S0Wz1xv{dGgiAzHGjc76R%N9uZ7+ z8p+BEjFNq|^wl)X`NN__U#F&{o*xnC6zW)TsSuEZe|@J$p&OnIK|`HQl!aVI@fBiP zk$*)TFotr5b|{ztEUa)(%${9oEt2K62>VZYeBviB0 zN!5K)@EV#0l*a$cyP|$0R;aX%(I+W12HQau1EORiwDS@2O?JU4&&5K9h|q6*HRM?! zgKeIa+X#$08YbdsyacMri#;81+7lY8Jn1rr{A-DnJv%slS1LEavD>Mx#aFoT`dL(v zTpzpb3P)}h|IT}zC=arn%)r?%KrG4=3?BG*r1}!?=%Pq>^q;ca8y%wC&C7NwwPh+6 zpDQspH&-;dP62|!tjf#hJ+}K*Z2GY9nxUCKX5*Yqmp8PW#n) zY0iBC%6h0=MEux>8}LZw!n+{I49&2gntC2^!?+|(owjiYV4>`N-=3f@kwmRXI^!73 z9Yru&HC^}5M-)~aO*38%-TQ3Cw!4u$`gF+|KMkXDolWrk-5QjpSn7%(W1MMNr==e0J6&DY3P7ZsZDRa{E%n6O$HsrWP%H(`i{QelYjiII-ZY zYEhi#bnU!1ibsxSPqSssl+xd<{Vb8%pBzPiEN`h{G+y&!_QU-ntG`>ZX;E5eT2DVJ zC{)Nozh)CJu}1E-l!#6ReA4vfcv_-EVpvAI(B$Xj-Ik=V;-r`4KlKPdmrzAATVRzt ziFpO8`%nj$0MZLB_a9t{fiG~43P8d(6h-Fz&yOb^saFIJ;jWhP#kU0teLLq3;mhgh zRFvPeT*#bhkQ?yxV1N$1vwAcG7e!VEUAkA6K4noMVSZMG~$xULl1<9;GpO zt6{cRmK6QpE6=gvpx8WP7+=hHn}C&L_TY*~q2DO9Z&Fo$R$%jCqVP^|LaG4e(l*ON z(!xHHkXNIlg za@@XNhNkvqg2Kt&9RVg#-&JzRJYD_fjq+)?<_NYPFGRA1v9;0uu@F+*Vl`>AmAbWv z;Fy%Y6QRrFsHDAA>vz!R!s64pB>gA9gRe6@L;us{Ty;>T4OO(9Pq-k1I+BTyF*Ys; z4T~e&CUz?|=3ZP)q+YrDN0!4#UYBM35Gfap*O<<-l6_#dGgl_Ko(Ate^!O&4vsq~? zxjap9>UWKrzb@sGH?aHiqbmzIrOEh=TVHy*t1o&*EEMfzNO;q^38`7H_s>Oh`4%fB zZGAi4rOc#N$l2AWskJ%RJqa@6p z!JYPI@$H?}lxAUX9WZl2!G`=DDVSg??@)v&lV3?|*bz9}E`8G-3Ex!Fm(NP!!Og89 znjS={>N#(~f?!4}TdbTaotPb2Y4K$sCUh|VN&4bP}`k8jvxi{}vj)n}}- z`#_~_dG3brS9Z6ZnAPvf)Os9V37g#OM7g6zwLp2ImHInl!TQUs$aU(ej(X4drw0;2 zcOVkh_kK?T6~SRX=Sy`(=>Hvf9vd^mWTkw-xfAcB3k!{anJb&wh1c?Rw|{HSyEvv0 z;F?X%%{|-~-N~nTF{{x|(W>)2c*P&uLm>*Y)u2556SdzRPm?PSU+eD*G^{qf+Fi7)FWcQTId9X@ck zB+YXHB+{RYt~rJb2fR2>N|!K>GVD~jhk z&XrE?o~p8z@GEI7i>H!rkFE=uYC3{vZe0#P)ik>M=tcR$`-%RQ9z#6;*%o#OmPA`i z(#o`AK_>HK+avOY+P}*EomzEjFi0UG@Pg6~mo}|~4A=*zS?+^1&)YByBf}&U&+{ju zD(n`VQ3!U`$~Y^=bKKu&bM?>GH4SCkHG!E#nO@PKk_8vsWe=V+i~zmR-^BIqr9*B> z40hWp;mfFKbW(hwTe`=QxXzyIHytd%B#0~Yv5 zLh`|+Gp*mA&Lh7i(Slgqro@MV3yufkD-QB2L~$%hiXLd`cDJL>%&J#QeZo51jQ7|7 zqx{-_N^kbLPJ+p_=-xVo@-ww7d-`ahv$4s&C$!~Mm{%CP)dT)Dx|J7u=-TNKI`G3oeD}ve$Oor zrZa`?{ykhDrEmiw>Jt&txA8~UY@nuow_Lw!HvPl?OSaa@k^0Ved^-tdXf3{_p-xCn z+q(8^1{P?}Y)}Pj9nWko89)C)0&GX8J$@jk7bhT;42&(LzcTr@qftaN%1?=mwr}gf zoGbJ3t;lEH`Ns*f+Njt-q*Vt@MN)M<1i#el9Xo?ruih^ge%x*cnN&7Om6aaL&D1hqojZDqZsrYDugnB^g-Aq%e%cBntx#jilmW$YYR; zrm;PUE;<}X#BlR(3o_L7mz;bw$hiamSOE!n%KsuVR z&Ir&)ywif+D_h+7QouuDPf|Mp1Yh1iMci+*JH3HJ(Mn?r%-_jWx2k$lQcg;H{A_%@ zP?XJn{;0#_AXs0Ak6dR52mi{dpbenbmK~(SKyx4`&h&5Uv%tY0ZlVIFouEYqm1r&D zlLy}u9@v-Yozzcj#pcu#oL8|Cd|1fu-Zh`so)#^#%{gh%)n~is4~Gn7VdXqN^G{7e z4Nhh~zH`Xe{Ol*^iJ$uL?#aD8oCAMk-Y%^53sp%f`Uh$L+7K8W(kK>~ZIlE*a>Z|TkFJ65uZXjwYF z%JinA9sU_ADyBF48A3%?PkNY`%e2|HL2mX#^7#~r2EXKqz!#Qeu%mU~TU!6l;1?26 z>-ITP*g#x9j)+EH;1I)5jVu=#^0FCIn3v!uGUGPkFSHx~38}jG;UWb6@!oL_gj0K1 z{!#h(KvEOgA%ij`Y3@Y15!2O|*XF1BW#rcH-W&Q`pPqiv6YR`Jr!&^gbvToILbgql z7c$B+J*fP%J+_MFDq@X#b?KurNR@8K_nyYzfoC#e#473>As5!=6D$k#%JN9jjg8aK z3nM=@26_mu_WaNK7_9o9aCXn#>1Jev9qUT2qoVx#o4a^jb^tj)nH|6|o%c;9X3LLH z(r5~(8NuVyq0+z){A058uE|T4>fYa52yOgi9wmB8HWxPvU3_s1L(JD28-DROU)a99 zF?Sfh{Oil~rPvH)$k^a}*Xjy7V|rS{hQg-f-`&mX<-=+jt2<)`|H@KBT+ht+7wH!Y zA}OI|hQZfF1;kc~Gj7Wx4BPr-gFPW!KKp?DnG66gQoh-H(*ZiL3~JdQ`W(*3AW*N0ABd0_q%krsKq zGc*1JX5Q7{T4Kxerwu6S0A)#kZLZ!_Kqw)AWsZ^ZD3thB9fWn22nm-9Rj7nhtx`b{ z=(j8Y)OO+bhDb96vtz}rN}K{ievo#&)Ub0}jZTNE{259ZBwG(dER|hpS0h}U{3=wP zu}yP5GYuR?4Q7P~?P=7mg_-!SYscvW=Qt&a$&PzEe|nf!umxZin^7u^eMhsZLCbfe zY3-f*^-_Axo&2|so&wrn+?xp&0%E8qP1unV8me5@Fo9O8*iqrCm1;GVfV(fi&L^-J zzC8&Zru!PXG6l&{!xY2Y23~M>H>QI9&DpeUpY{f6@MvswnAKT-?U+=3YP>K z(hQlKvCz>;Qsu2i=rd#{e=$R}0eAAudVKU-?u-K;%j4m=@?5TSnk=RXvc zznp9A@5|*~H2|mzqInCrA3j>>X4>xYAd9xAz3gnXDPo<62wkaPx?>ETk96Qz#gBPr za1O$x4r~=HBd-snSE3?+^kA1*i-zZ;d1SH_#e8CdW(X20W-QyY>rYgHX8r@I&56)U zyI`XkE#^^pZT{1&wfA9pmGQpih=oG>SHZN&`g_x-POB|AcZZ0+D5QpP(LoiQKV^!t zrHKf+S<0%`xV6WeXtj?TLJQtB#`hKATh*uu3H>x=D_nJpb(4;$isgzsoX`@gr|T;Q z_!??y!m1)JEC7KTVp%y;Q_u8iHrrBx68OZSj)^So=Zc7)^%^#F_}hN7Oiku$YK{;i4`ld!Z7|1B$jgfSlNf0A+3ApJ?L1))35 zmA5qX3BMv!Nn?53IzT_bfxZ5)ARMy1eg*%UFxv}zJZcR5k% zjs+=~d}|WE0UZmZb!B(!B<4*hDE#bCBp$!aKj<@1;x0TVZf{p&B(0@I;N52Cr=>M2 za{tJ|W!th>3|9@vt&z_Dwm6-?$;x962RE{~y4A8ly* zcF@?VGf&@|R1Cj59grkuPXqc?-XrUb-lw7(U<^2BkZ+wqW_rs6tE5tLVh#m#-x+xK zKS_5(U{^JQ&&Lk~_RLntJ-cSkn(jeu42FgIb;Fjf~NGs7w5Q*mJqDEZh$M1o4IwWq3s}Zr8@GT}wNOae!2kV*e zbBE0?m3w193TN5zZ{&w;cmE69?R>zrdM)<$|v-_ZDElO`Olqxe&s414ds z`j#aB+Mxt?q@bE8WhzGJIE`-x2{0$t=KG|$9t>!-p%5VNdE!e8gfq`C^ad$Atq%3p zs*sSN|FHc3UopAQy`fUxG!F16ZTD4g$XcNoW@>>VC&Sze%sD zWa+6|Snu9JL+}kMDB4DG)n%ln*-(2U7NxoD@BxPO?CbBtz-psZ;J{&Mb(Vb*&$O{b zG!&vNCPoyfv@p#e22sUSrvI~ndtyMe*!+cHx}cwh8d4vGLolX2_(|fc3{`RZD1?cd z2a#*gk!vdHfRn^w(97*_bnn6D9N4ot?^s@3yssn{1+Jn&heH<{-Q7B!@g0LBW?Fgs zD0elAE9TY4FaVde$ABb{hb+=nU_J|RBh=@IpsF^wi+NIShq?4@Q#Vfc-YY!O_W^YD z=0I()?=}TW=qgej1C=Xr_+kCLXW!3wxVhWAao=B;IDi~lw$p!|kjm=BMjgU2MXVS5 z@sJKG*?y^`Wu+Vz8R|#4$345iryRi~;N4#a+mjJUi)i$mjwPK=?cpBy?-SY^0FRqn zKzR1FN1tLesugN1%S!EgX0_X;q+E`#Y5Pn#eueZt$M7#Xj~@96#wk3zh*OQwEglG?T&At$)@g&Ikn3IHBUB zBo8855rMw{K5=5Gh=`Ue8WOJv!dx=T99L0Pv%U_bjoL_eqEYL+OFBg8M-#H=GC$F% zkkLxgG{n$R1!F%5t+L@5^nLZOyQ*AQq#<+^cjhmiDzw7eqYgv4+O_+ZW&1r`7 zYN0dbqK;gFJsM5IJ!!+W(faXj)cCFOEKr7{L}fB~hVY=>+Q^1&;1Rf+z~{2@)=nDz zO(^<*fZR0vIGEjwXY^GyNnkHTh#we@RJL#;yGpjjmYT~5y^!#-^b?K=4JWl))yv%G zvM_DaSB~J4KVC@UcI>?4rj%Kn!5b_DYgcI_KCgyfT|+_ng^tZmdokvr`vjL^>|-b+ z_VGc&cD(2!INBFmS}Yw7t6FGk-nLE6%VzBG>6A4^ySq2K>P8pXyY!ur-rCGoEltMR zYMojAz)vAq)KB1>S!aps&ddGZp~R-YcXVsWse7kY_6>pHG26A77WtBxT5jEc7$QjB z6!_;6ul~u1V(RG*6imwF7p0g*4mQ;dLz2X@B>1S~rK0armspLNW+Lc&47PmDWRSy{}dd1sW# zuhK0k_B#QeJ!|>#ZBbAzkqoy)3&lStB{be|J#brL4DM|tJ>}&c!<0Uwg5=mF2|D_Y zf%Vg8fQhv2iX-L)D>mJdRv!~2PL%d?qxFpwEgm@ng9$i>m7*xTX zHa>m2rmCr)eb-CrsM^>Q*lnd~R^*ieJU(E6d56!=0YU0{FlUhgr5K*6>7Qs=>tVUC z7R23`e1343pwm)7Z=k-3lUtyjl3@QN{Yb=(SJ#Z$tg1j03-R;7USQyZFk0DUwSZX9 z$(NTHjonguRbUI^!<)A)GUw>dAW%ba)?5+|Z9b)N^hbOxN6ULmaB{Y4r$|)EU1UmA zlzR21CZRSaOPQMHnd0Z?hx<+@*>(@ePn8rJ=#Jw3?YB;MkOQnJo6KO!JbhPAMe)Xl zW)3vU4Th>Dkz06D8@=ELamMOjxg=pg-+Yr&VHc-w{UYS9Br7n&z!lIyv#853lRmlG z*;ZUKsIoK|gx!RbRR@`-9OEaDCTxQs5-BtM?&n>>lqkJ}mDZ~7vAZ1ENb9hKgs}&; z^=G*YFK#z`Rl@uC9sIaAOD`nCu3e>4z6F~B02;kf0-3Xc1c0xJkeufPbl!s!W|Xk| z)OiA(7~#u&6a-f8SIW^wOvurfkyOxRAN@&t3no~pujf%u(cftCtf%A}6v)FR2zq81 zA{n(G;MVuszyGzsJu{=4yHzxCdGn0h9Mcbk(VOlckO<3ncI`$OCWRa|%%siu(=J>< zJG+7@LvGpJUE)T=G(kWu*)ihKY)Our`yjLGzCZY3ZOJj54}(uK5%-awzg43+u)C#a z0LtCFeB@c)PJm{S__A%Bq# zb#LI7mXa$j-K9HDDr;|iQ870kZGM_mCeL2l_J$`6kYAduB`+`s?V5|hH2I}e)uW)e z$7!OR1xyFhr4%0pu!Dppfb}MWh^C)N*U9i>b7F$ToCI6CUiA2S%t=|zaI@aB zx0Zd+=wa;#mf7%}h0fi5s-N?jqr*cza_t$bWD&7k@bqk3m%8iEHP^E{JRbgbDo!2x z!oO94U5v=H8ZI>dF z`xA*x4jiRak}MhDp!iXCQEY|yT5rGVzlmSeQiMO{Y@V*$-Ev1y&g?X} zq$mngZZPVUZlbV)luVp^{r=3{7V1~GSq{+z24V}}}1Qe;yt zYrPT0$;;8{Umq+!stMLUVdn)BlFH#5cUZuA&OZ&V6WS}`eIdqKJVeO!27|_o{dYS* zg)77B&1{O)CcitwS7<6m&H>3Ngw2u74(H=U^2#UyEmPi~LbBT}La!Z(iVHK|zlCK3 zfBA?Ub>p`cu`_cOHwNwzIJrb&#tt~|8B`&dvR(F-oub{bH}^gmKw^!v7wUg4y8Num zMbUiIfb>4%5z?&U#$I7C{M6#9yIq5C5cPwB7Yr1S{$323-%#P!>t&|-pqGa@@@8fO zQHK#Yq(}6f?wehns0;z@&?(dDU`{q0kA7FV+u8_)JVu6~%9Oq-2Ne_0{WsrhZjqTC zRPyH7XTm>>cxuCXa(XxOiR5^G+MSK+1xKfjl0Eu9rs58-%JOvblv}CZ5=NSZ@RatI zBtaH=h1$f?#Aa^)Efqf!5B&wKM@i*0k^zVBIG(-H7sY#(`=Cw}Z@wbwy@%%vEu6Ydg~?$QCp?22z8Skj zjgo~ijf<;Ux%b^70O$pf?TNUWF#6|yX;XXTmY7I~0355D&bN%g&s?nqQ(c^l3WUlw zlyIB}cZjS29oTidz2A%~s>F_Zh-2%ZZ3wsCE(tzG9y9HbuPa1j{WY==`sy9)Gge2p;%g`tMmO83s~KA@e9doDEZItuFRdoj??!SD_r z{Fwm5%NPM%2GN6zp+&468oEFG7H#DFe!X}7PM*WVdv`?DYOURNe^Bxt>aZ9+Uf>|m z!VsQr`*i8jWnL{>xQ>zC{3aK#BdXNFvZ*zF~I zfo1S4CRj?8pUkw9ZDb_&o>4*Gl}sjG(+}%}jw!d^c|E^(SsH8k#@cM!AVXp)5f4SH z@lyhl$k)^zBD+kT1&EHp0 z=)o>+*^(&T30V8VhyvSrB=6sgA`aW7Z(12BM-l)_GYb)01q%>gB*nSPku^5<5fv4M z5H)Uqf7u+CvFTq>6+A&v@7@g-!N>UX7JTN?XNS^S{R9!V9AjnisqO)B<%TjiZGR(W z!Z~WKh`TD{Bjc-HyEwn!c)8_=-uP>1C2UX4yY8MR?Y8~UQ+Vo~n*WFwM=$!jHsh@C z7AwTYmXs~@?e^cuL^_b?#%e?pgLg?2YmD8Smj!YV9{E%VP2O|Zo_-$=#rQg&z*a+X zAdkiphW^sk&R7PwRc!#VI++Wg9_JEpaD@mFK{@!k^Um|@UdFFKwoA}$zf=v|oAvBI zim-67h2kgh;rmiohE5&@@ORu%ZaL~AXbJJv?O7dSXd0C89ATA{nre(GVUQ_;qD4kC9$&OF2L;p; z9D2vdGQGo`8su?s!g$XDNhN;zgI!Ke$ZC20S|8j+Zgg~#|0iFi@7lAKug+Eaj~Ef{ z&2lT2$ixwq+W4M5T*auR@Os%8JMh){*$&|=^76w}cQ&7EU&3=niZAasI{o+~KbwKf9qEL^iT%@qc+_>O)&* z>>-1Enba!!!7-aI-VhnSc4nZNkISJi(1|kt&GV?&R8mN=@aPdKldgGmEeGDVr{`9q zj~|+4JNGUC(sL>IpZ`(ZuOawsEOQVL3DQ9ZuuDD5-~6KDTP1f)CazVTdCRu(!BuO8`HlVbcf3 zCAM(Z4ZZR;gFDzLUFuE-|75A)oCLN~GYuY87v<9HUq@&}2)Rh{#2I@%VGn5v!FEW@ z1Ib|DaOw1|D1LW8pNwat0&Em(w1UKSW_!fYYJO*zP}b&LR4eOygQYv~AnJ?v0NN-i zh6waH(~n?N954!67C0(3H}t)ZwIuBppZ$^di-ZQNH7)1i>8m~41{(H91Xm~i%vIe7 zfDd7at6iKhUl%0}VfB(BG;hH$@JZo$f!y#DVOaSL95#>O;Q={Gc#UZ5L9x1sLzrH* zsX$v2*shIN_8p9FkFF%h4LM$&DP zh#mhb?d%>UDqFC^9uD_z_C%vZM^BkL9w`OhQ=6C`DO0IQ(u8wYP)W zj2tG-dqtoSHGwlT)R~cxjiNEejz51F{GIA_h$+qGPz*E=e z`(=0=NBqP;;E*c4;v}o|`81(H5Oj2=9gg^DI1mRAqY}8(Jq=0MMZI-b@u6bxNAxYr=YA^Kn#0YUMh|~Kkw_o zDGd+P+~t#PMuFG|OU@bg-OMv3;hdL>?n`gfirq%XqxwOvl$G*t9csQLjdlk1SG^;< zkIgVROtdEd;>`t~{w?V=GW7_07BPb#dKPdZ;xxTlv4uA{xkj+ro5P&$@&cj1>@9fR(+tEk&p3$=zdv)iJ6dd2rk{KaB zU;x_z0~3Vujir}ZWqH|g6N-WY(9{QCe~87bQv}ezm-Z^2>CQw&U=T+=+y?8$tiOTSsq352?fgpIgF_l)zBj=Hs1@# z{cLz0PZU$-1T+_e7PX_r76>Usm=xT;cmmut^nBHG$zF~BkEnBCuPo}a^@(k}qKa)N z6;y27RwWhNwr$%^PHfvwDzO*4<+?zrrXSIN^@*h(3 z&3BdhL9AFUf%cDJ??gC{%qE9z*G}07r8pKykj@_{*h;{nA62$||F-4$xONk;p3%r3 z_ROC^SSw|K`6E(jQ^w`D^yZSt2mNcFegKGTP5W|BNEq0wuy79+pVe*HPwmRTapZ%z5SS&SwfBmEssnUu010^v0;0|Nn{@TAVw)?{Oh zrcuM_li3cjwJPKQq(Ye*B2{0AXl3K)Jv~=4KIXyO^9gl+fTjDlI{Sk8-@= zQ~`f+U5%UaQ4yC`5bxm?Gw_tU+NgUXC^#nASirmk-+}C`<{U(n)old1X&^tN%s`jE`*Be33f>?>c~@ z@gOP#wN+mNV|3UX{j>Ykpc0tQbf1oq3NRwE9#BgKaS?U@AAeI5*|!&lrr=7|u_F8A ztI|z>xw=~bYpZQ}P&sg5%9YN?@d{F*B;kGQqbCxCSu8mR~u|dATUr zTz_PQqnmuPP-5K>mGg5g85I$%7N+^G@AztIbTklzf%Z1fqk8`k8A}o^_y$`@OKo{1 z_4Q2e@=MtJCk+(SSeW?0m!!~xnmz69q?t5)`VxzyLAdB9o4Rd3DE%Znr*UEoh?A`lwH_gJrPx)sEY-B`gSR(nTQ_94qBjO!nM1k-t!%G{J zlXebFPL#{DSM{xhk_-F4OeVOLt3);O$LE~qEZ_!6Pztf!!2}GY4!K#Y$Px6S=XBK@ z9)Gk#n);Ukq^873RMo&sB~ardj$y!pQT|ImzxS7EG!?(Z?B{3;iy_oU#IAwu23KLB zw;V74mta2uX>m%py>WRl85dlb+4QZUyssul>)Ylgc>L$t*!^bSH6Uy2%=lpb>YTZ# z6`*{|;1-ar@ip3QGu-!OvzG7_QCQPW{NnKJVbP0c1`em34dPdTAzNEy`#mJ^-v;P^ zX(H1IbS<}#=}>f}Rgr*pK9+J+LV>Ds9HR|i1rs_8BA4y1S11O12 zCCJZqcwzZZ)EM%S{FQ|00om%_@%{&>pd_>)V717n-xn1g-mj|5EA4%89PcpL^y2{Z z*5>-9i{i3?q_x#x$*7Fs%GUV#Vja?$)WadYSM6Xuer;L4V;4VZgB4y@DZ<>@RxlFU zvYd_QQ6(}ii~uglxVr2w&3LGIkt?9@>YU?~P>On7Ez`Mg@rP?4*FO-X@Gcmt-ixOh zr5bc=0K-4En{h__=L{6D3`2c2qPqM*!s~QKhJO=;c+Uti>Z#IrKQ*b5zpy_Z6FC&O z;Lbp>a-5KT%y$E5Qc?nAz1{vKT@yh~(C3g>pWBBhk}u|O(yNh3mW!}`;Fic-?Ih=U z506rkF`}MTfKi}89UD?Bz@u@Ds^w}&_UA|Jt9LAdnLoRd6O+kTa#BzV z!_6;_H<@-tvN~YWe?unvrGr2OYV46pfVsnF^AO)l2H%J6Z`B0yMr)38$3Zd6gOOBw zHd7W(mB=v5M3x`O-Vp_xA`H1R$)pTsrWL`}z+`EI+P>Y81-K3sCdvxjL-N2!d^@Z#!W9 zlce(hHyj>9$CN{_ypxmJNBx4nZ{kSm3t2DZ1b9JC9}YJ)8A1W%646M`1N<1A$=j)2 z?g0alxlkTI=q(x<(|7FPI86yujR_Upx^xNHf}0OalZw8$U7o&6zQdjBd2Czb=wHi12Nd(Z7NZc+~+ zO9t{s@V1tc%f%qQhtk}*3=`7}A0mOP<}StQLwPTp`@JVzT@jgIpjQWEI$tx-6H@rb zP-2xIQ|{>5FdRR?PxC&PvZ`H?c6{<`v*XkBHs0Xmx+k9^!r6uz_xY%{#b_lzVeL^g<_A(I%(!+4^`ynwd5Dt`WT)j4@@F}ewv7xzu=rxMnOt_+l1b8%(oly z6W>JmYLsPrLi=(&0+PFW2R9Mls+m$9FPF$m#4N-c!w`4h8paiiNvYvgP*>hpdRIvf zYAH&HvbTv=DP$KfPo65XKXiqPi7f$Z#sgm}JPkVJ@f`}}|4~%an%&(hf30%c+S~vW zDdFflf#ht-SCsTIV4@cXN-26Tz?t*waNQogbD33l>*IxkgNxC!!2MAy^%`}bryFUp zcu1J9MJfbrA5p0@GaI6>%9;olfWa5R!pOEHO zA9}7(-ou0Mtz1x#bvQ4Rc-0kXEAOOU6aNlr?`-+;7;trf<$YY&>{!G6*iB0X(S~locba*m{cpgm0X*pk0mJ z#4AzjW_PyjbMvsDo9*Sa`#pQg3_8(v+JW-h+kB3TWE!=+P{g{zS1?C)HuU>EZJXxI z0I~@e13RXtD{XE}G>@|h&wf5YS~lS5pU^)jFtF%@|0p6LfFbzjhP##@-p=~^xupzO zs$1246qm;=h;~;?db&E=i=PWhcDkQ39Sv^4e9~RuUhu)9UGmjtTZ7lb4b5;cc@H$T z`D_dq(Y2l^91f)F-_i~rXAv`kCiTkavGSUV((P`N7US{Y!q&3V4D|O;vB%2|P*#)C z&bPdf_G5j=T7`2$?z_w6##1^A3yVbyv}bqFYN?;sGB6r%HME>9zY5A<4{QmAt1JomJm2XF+M$(qq)LuUDlr#iL94jN%Ka<7UJzg{xoV8fb=WA zCJuIXz2#6{OeXJF^5hk@+MQoiwUGeG=t8O^a0^38 zP6-#5OHXncbNmw&QOqSn2>Mse!0LHTWAHN)&D4`$C|10cBuuZd%p5nq_k0NrWeJIN zyM#&ZO)Yuw6*xa#X#dnDE24Pn<+Fqt;l!WHW#?2#hap+%3GXJT+y!C5zHD(`#blY}T2F;Jpju2H|E` zhC0r*Kv;4Cg-^Tzy-p5}veeIxdG{RQcuWdyiPd%+BZpr?eUQ+K$?rIp&`|st4)3my z8LO*!HDt;X@jo;U}%6{r0l6 z2-GSt5<5uyAOZ7`asd78FEF_9@YbHd*Nqm2Snrs)cR3EBBu8{uin5Kog;s>XH5~tnbtZ}s@E==H-Y|f zx_w@<^n5iJsxKuM znq)3B&onTCb4G7r;Ho>l#fwly;5oR~t8Yl~(c1V__PDWwLuHMR0NZV-$Kb7n25+H8 z4_XK%?eit20R_gfnL&5}z1%X`AL3lzx;q6fsXfoVQ%djNMBnmO5@QtC1UO&W1pT0f zVmp1YtA#ycN-DQ9KJbH4dN-b^+Rc^^@o%I+SR@UHgc5so8E(pA@x8^SPdd)44FLMV zf4~48$8yh#t!RW7zHB|L7f1cp>20-CWG|8|a847ec^V1H%a&(7jA^H5GI9x4N?vrz zC2aUas?FJGgN!xJ2wZ{q9EEj`EFe^A0c1Gh#P1KNUlqNXHKQV|&*Ir?^@d;RQ0}83 zzv=5LYP6}u#k*%He`Wg>@^3?$lDm3HN;*h7^lc%;>mA1;CNLH1`~?ZU8vE01LVpk# zl*fU)hb@kYn#lx!oeM^T8NDFF$k7dYsgW#V90N5O?auf5-UU;_(LC&2RxyZZzGof;T*^@}GzWC>IikIT!=-fk?Mh;mr`Ojpp_$1Bd&je;q zt>pImO{aeZaR|~xO(vR@QKmZG;RAD{Cu5CHIWZ+&iR^Gr$AIZ1$C%O=c7g+h`hDWn zJW@*g=5OhVQMu4$8o_cO#25bBnqtfn!7g3AYT;gWK{dIm#tOH_K92JjcQC7=aTH|A z%+d$PCtN=2@?xb&i7B6Um(pDy4;$O_QI^wHB`Hx&O_~TszVO;|_Vv(jJMFgm2LC^? z`1p%ZWu4ilJBcz^H( zVcw~+tz|Qsf&E2WP)=J{`B${R-GzFeh&PnG0tWj}D;8PPI}%pW@h;=^bjD_q!ir3H z52G+6!BEt$shB++=*CXWHJ^(h_#|ItFRV*pVj7n~1XWfui<5_msHeNI@Oy8u=SS%x zC`E(jhIk4xh6*(zEG!DYR%;i7;bzaE!(5*ihUi*6~Xt?tywNH!_=rJqy1p7 z5X6U55rVTPxJdy~Id6gy!yl$IT$?uKFYqgSWX>V54a}NlpmMZDpprA#;AD9%<(7lt z4YDSz-ftY(Cy~fkw^C6UAyb6h9QCdW(%NXTwQTIvbe4})c z(t~sKb{o)Fo{B8;-0xFcRQcb)4ct)+dN&QA!^x`=J{FBcaCBA^=lIvNHU^%QG~!kx z<~?9=%sx<}tI%kRAiztFPY=MQ2cb4@)k=Q`U2Tg!&3>4qhHVYCJdGy5`9LvbU8XS3 z-QpptWR(e;fIE{kmE$FK01pLaoDRQGB2LF{$UEg8d)cc7X{8rnh4Ov* z!F6=}%nK#KjIkXY^97k&AQ}@dywI-_Q&J1h0oA_DEz*>S%1anqr0w}$2 zivIE&zICupp2(S=1e0}$TG8x5Wkf%oi4~EMU4Gevr^1nE^lIdR)N^qW*i70sI-S0%<{13zvP<{zL1QHS;LeEFz?Vna%3N-V0Mv@4C&o`9 zbqNT7=sX}C=DII%b8@cna)!$V6ktjP_mUU@be&P}r*XJcB^JsY#Vll&9Jd-IoNno2 za0ONjCy3-MODhR#8kS3{wcKxPy8mPkE`l1h3dihq+ft9g{+8lLS01@@w4C)6$D9m; zowQF+65_1%!GE_U=H}xG$?aeF{%C3~V|h41J2@%SvUI%r?W8I`F&HuN>$p@z()Z?6 z|JvK=b(uDRuvUD#lnG_&7bjFKb8>PQyC@`k8{Yi9)*ixuBN}phCNz{kAg8`LB%Vx)I$s=5mXs9d zSxf4cl6fZn^aE=p!Cr4`F%X0X7$gkhod}ELGb!)?iAlsGx@AxDU-kVPo&V9lO!<}{HrT){T$b=|2=8u>xNjE$a<4YC zOeO(;`m16J)kYqz`I!8cCJcsU@A)Ise)~mv`GX^Iw*G)Cl6U$`_1)7-B0JU6-jSGt zH$=$!Hg{zzgs?AU4#sT`HaQ18W1v@wVhgI>zcg9|f z%ysys{O^jSY|`LN((52>?_Ex)c_Znj+g=9mb2AS{v2;G<^g(f!Z^oCkV)sAwWk_Xjgm1o6z20v@p1Mg>)1lC2N=?N znk7erCn&Pq6fImYh)6Y;kzMFBe_Bz1_3cni!f4J9!rBD0P?ExAx62x^L8^Dlx=lt-XK#KT- z3)}r8wLz#Kb*zvZifsw#yQ{ye301^#HhsxIBgHL>Sek9}8FAy15H0e^6uHbCN>mba zVrMzWvB=D?WJLPJZZ;RV!vZwf6yS_F&>ewyuU2>CPYtox82TsgU=N+~a;*&I(n<{V zZrV42OjP{+-$MMuPxNmj80XP~0aATdZtPYhVsJ)~tcFZ;+6c5Vn7T{$yys1AM0$=& z^K~H`u}LusNr&E~5k(a5T#|r}edll({rjgYPcz0lmq_8YgCDf`g1x}hf9Lz#8dfFv zmqm2+5H@@pd^tRZ#fTz1WJG{R=GMu%0tk2o^icZbGosizA!l!r=TzXCG$$UF=hMnP z;;(n;*D?6mLzBk1G>1nh12wC5~>IdEEz)@#j1(@=ItGd3Z| z$~*u^^Z3zh192MbLn%0xxuLxT)+ZM{1tWiNNEp}ta8K_Wd&Bx+;h(@XKtU=*2fCQ2 z)HNm;qr@o$XYrX-Z%__X1vM?JBY2euI=(k6q!L&}4+_rSp0+i>WR>BhlckOTCKJ?! zlk{4bMX*cplL=B(jSPY6f0#^AM#dc(9A!r>k*!OYQTUaJI;=Z(7|R*%8Z1ZFxt;;R z{U;vAz31!WD$6E^b2IaoT5tn#-N+uxwMpgU6?b=cLtPJ>L#v!-TSX@K#ztJ3ceG#Y z#6fITOdH?DxUPDWxf@r70j%H*ta7~N+CS*f2YiPRWDWoe@BuWT4HsD zD6k7>Q0?_1yDGu@YlK63fUmT#1lQYu_oG7$ZaPxO`Pgh%8KggfurvC85XouqBviEc zQW1sKKd1_t<^ZJ55UWg9d5o4I=1t%~c%ZjZCD!h-Z7%3bS?}ciAsC%+3a{ZqC&qt~ ztwM1N!b1p*Lu+m=2=p^{`{rs~-jCUj&3XveQzh$wAXCo}7gNY?M^UUhs7+}r` zr`P%lGwxwO!u0zOF!~F6WBjNhU4X;IwlD4zwO=r&Oa$Td?fi?Q>{~`)jDvnP&5Iu(02=px);LrG^xa83;M+Zn zCnd)5z8i9|w&5#;^5m(6+F${N#~x6__Q(T7ZJ+CiU@0@FtJ$UOK{quA8mJ3hY%Rkm|;u zFp+h+2)tHED*0u*EZ8P-c?LXOvi0M;fvgq86P2Xk-6HWpdMS?2x9r1g?3v6KLUNAnz);f^69U? z)bY-}(~%gJbbLNzuK@Ro+X=`P(lw=|T-b7iN8%hS{2SvY%7P`;fyCbo0>ko)^hD0-a;5J!Wuit5uN;x01o zckZ5p2ag++D8v!_qr8R?M7H<~#8FU3;4}G)wGzO8+6dr10t4p`1oYG+uEFO8V)jXp z`&n5xI>v8f{EhqpeIARyCWb)4Negs4yBjt#G_*7tvbwW6vobOqffCt{w6n~JK01!+ z(Vo3`P?~pDvhUJn(*0wv{pF6;eHA~-o@w$7LR2}hZt)ClW!awJ3@JJbc||MnBe08N zU1kbWfmJ>}SwLtw_<}V_p8a3#JVUOdgzy4+Iw`>(F@hS?gO0nM=w5PI>lbAiQOy~a zHu4Z~ZHt23-0M5@2j>GSBbr@>j6lb2$9&$epk@^vc0F{`6b}c7DH6LK318i9M{v%s zKmy7;X(2H&B1hd;QAr6^8eAI9|z1^&6JuO@6KgmFj5jSNX0{45d;W|%?G+i^Ym(F+?_A9_Vfv-g9j z@v7C6?d>+Gyg<~aJINqQh>c@`U)r+@meFY7zQ#V$?Xz0v)UC&6z;VY`RZ0wRR<91^ z1(l`W;s}r7uJPyOG{55CK?YW0-jYZ@4m3`6Dd*|BHT544BYel}^2QYZ&H{L$e0PZH z7*cXWT7e1I%L()xLs~~jr3upfQWHJ&4M4uLmEt<4>z}>$kvR58%djDow(3c-o<;f( zLl{wvvQ+_lEP%R|RuY^V8Y%wg)Y&>j7|9toH=K?wZX&==CQ6_0Rb?7{5it&Nq#va% zh*yCMwI@3m8MLC^;#A_}qe{q>!~j@?gWeR$O~{m|eCHn(l@w7MRTlxm&k*}BpF0;8 zJ_ID6I8G8rS~}73L-XhX6xqG2EX^kvYVyrBji{fooyh7AYN^q)?CcDOp{-Uz6826ICtBKmj<3!CXk+u9beyLg0!@nGHh zW9l#bPEDIdmOcvkBxJ^4s&kr#QE)G97{9rLoxe-(%KK5=77Aab7YUq!3`Qp>DghyL z37{aiV>aMidbB!wYa_fiUkD>jsHv`e87wo?<9nZeV#WdNbk>pR0~w9JzjhOk#7fFd zTJi2o0xeIr4*glkFhhpjo}|&?mTnxpjtf^IA&h+&XaLZwV+fRPr>?W^1wJ*jmJyJl z@?03H3JRK_S_`2h@BGK%_H@O_u2Ocjm3U+s2vgyrGPbm0G>E5`Q_Acf%}IemvJ3x2 z#gZ{TU0hx<{v!k|$2P%=bJU0J_QD;edOA2(~sZos~TgEKK76keY*PM!%;w68}IW+Z2`a$($d$%L|hIyRzWY$#5M41^mn zy4m)x$J6EJ;`G%}2}Om=l{Y^>pY|HRC+H${)#; zW9DmL5GbkxFf{+e3K;{Nlk0S_87M)9c%Nfpp=eLB$n|ubKG@rN(o(&++yw3eyS^K- zhw*PRqRSgeM)u?6wEH|j6lY5yH(kn-vQrb5&iK(In8vq)8_U{ z1A1f|>WS?8(e4#%E?%g9iSs%`TxHr!;>4oaO^`QPG=D~c+dizR`O4pQcSR#rUa=oT z{b}X+v(XLd>F{C=oKJt0;bD8T6Kdan5pUg4jV>o$(}kGFZI=IgUe1iECuddfTJmM? zOzBTpMKpPj8aWEUn=K}icoxx~kZmt@8H^njQ0xdaCF$$ax8B9?uY;+GQK`~wH@>P{ zq{8#;MZqZ};UZ^mejh0B8a$+;i6q#J+0ODj_;n^4MkDHnWY>=aR_6(obLkTTf=yce zCq`x(GD$ZVamtIrWt_*NEvb0z0!qdhsD_6BROD|qhj`Q$OKZix180LIMZXZZ!2^Bn zFSHcP8*fZhKd;%S!{go1(8Bys6n{9M3N0r{5;zY%FAQo0fPCj)Z-%0~bFYkCWMO2S z*}aKfVDPNLvEAJWL&P7#OXnlN99ko0R$R{&xm4$iFI{3{$P-}1;uxZzlGUhZ!R&FS za;B1Bb;-1{>v@$NizlZdGQpxa@8=L2?K1EJyiLp8#-R9=I*T32_%O!G^1oD!Pl?^vfdY0naF6;zKg&AvN7gs^@e^x03 zZEF~eeR`4TXuJ2Yq$T%=#*Cm}^(W)x?(QrXJk1qH3HnU^Je5iXrsWZmwT^(iYPW4209vSQq*M1>7yx|3pq8ZuaEsfq)n{GdT;-37N=4gL)*pd(%8q`c z;Lu73Np?$T;2!8g+U})4Dd6W35?Zc&T=2kZV=X+SeCl}weNQ@T$;_LgI_1747ch** zVA6JKO8j*&O;dN7IidhZvD=5(^9YmW;Pd=47*-X_St#=ZMsk^g41>TS*ln(=QCk7* ze!-UH2>==eEu|2g7#_6=ajKAssv9ITBoicu3nlO5HY<`Vx{q>cdIu9=f74|k!Qk;k z?9~lLU}dqU&zfDc{x?sm@`4ZjVPDX}*Uu!sN25_54I#qO+Y9N|_H;7P?M*kg-~JK~ zIC)gtuw5WQiUz8U)M037zFF_6U z4vjtsx;sH1oWI<(Jr7D6``Qhz8=jf_P<__N%cBvO(BXQXr;PvyQ(?|It+78oW_O6j zavPKL!WvpOY-J^68fg%9GD*9Q$X`4A3s2HwYjT`&A|%6VLPdY_A^#_=xwIEVc`vHz zhHbpt?;iOGi*}eh9)i#M@*AR3V+kppbSK{7-YTq^L*JpUIiCJYOabuf z7mZD*4=k~IV=asTsV=o>0=T~}SL8L-B#sjFQ@ximZM9_Aj;PT|KAGV19v<8unr6ZX z>78%9-RU9>tc9eoKv1imXy5anLpi6OSf^8qHwZ=8VY7d!Y7GMG3#Bs*r`uv|99D#Z zxRSA+l|TpAm`UIb?1Nu36ztgFEthPLB0k0vGPEsyP-3J(i|cjhSCd&{gLvdHyC$;e zSd>76oC7m5c~3M*_%Lxu=HLT)mjcCtUj%3zO>WHNOZYiS4}EKKM@=0rUu0fIzh}#_ zM}9-K@3Y%w^Is<`g$_^CY#Bxf&(9~AU&M(d77YWmJ@Vdv{kmr3_9_CUtUYs5-B7dt z-XT5v`S-TmU`c$qPZQ=NN);J{l}hOMe{e&0Xx}ijB|1Y9D&gxKxGQ}Ce?~nU{rw2} zx++JwE>v*jhZci$P_vy!^%&JqEMe_G3?~4Pj+@C{Nq1IGms8m#-|GZQhY3m7#?}HY z>?;ZRTM4%(7HlNexDv7IUhBc|K~LV=K^&g7_kWlFImcUak_$`27|y!A1lB&6dIw5Q z@yq<35GhMvva)F{%{NgxUk*w{UGL*?bVF|MlCN9mgZ9<+nXbpxRm8^P!r5>B+mB!V zeoC!tQ{=Cih10-5F@-)JLONy-S~SMT z(s7}Qbgx{lfxalGa_$^_Js@5g+p#J-Jp_3V(Wt(=5{duna5TCahDp?NsNg%Wd+9CC zUfj{XC5LqRVunb(Rf`0*%SQ);D1+!3tth_OWn^g@@K0+Z*uOy`;;O{c3W$}&e*!zb z#QKJ%9+x%ZB`TRwG0zoKxs39H1_8WP^yed@N@se4EtBIj^^~j^W!VEhn^5Um7_ifl ze;d)duC4Jktz-s%|6nt3siK7wn0|n=lE=}E0eRkO9yF+#&7sfnb8dkU*nFH{&AWgY zg~0PnHKWne!pN0YlP{Tx{9jk?dm?JuCRj%Fd)!6v4#3n;LT!FD5q(=L{5Z;?MubY9 zC48H+f{FJ?kgV5r&4h;b59GV?jARq0XgYd$NLx+SyYjefLx{MbKU|g!Nlo-9Z*L%O zs;r=5dq`;4=olsR=Z*Z{@Nt(Od$`XV5(T&ohWL36Cz0poEt~hUE40J-`(K-pxWN`d z;4SD0IkP$AJ}?Cb!Hq1mcF56j_$?vbQ1`Mr=A>TzuWAVCe3G|$f43K&yY|aBB|(|~ zJJ<_y{SDj4F_G`PZZOltkM|>LSC^pUqlQ(jOz!t&!e1O6;=w%zz`ic#^Kv1jD(6kd zs9VSIu@f8xKB&jn9kZbNga4c{Mu%Z2$h8y5iu}c}5x>&lz$>hBTQ@Acj#U+X5f0`_ z*9Mcx0MjL(+(RfMz!g-?40BoSQdbKFuP9OeJEr`ORWQ zEM$j4u;DnN-p-#Ywk$g*FIY~iF3qlxa6jQ$pE{uHw8hdi@~MaX{7e)+Fl-6g;rcO6 z(oE>7|08Uf-SV@cI)Ay4DT_{G{S%7r%&~4Glqoip%(qSj&lK34P>@BbcF&#*HlBku zxH&R&UN`j7it}CzsVgjDrNEjHvv)V!FqxkidW%DK%0AAT2WiSPM_aY3mibXIV}+%b zIY-m`Uem)t&O>~jL;NC1P@vXi2w4e)=hTE@iYt$d{NMfpQ{9CMa78sidCST{#J|BS zxCZp;4B$_m(xyl9IOtlLk05RuK4aK!r?!6c>8Wpp!>)~I)VInLZ3G3IIvZ~YpV)(o zz+&*0HRL@`lAab=@`|wh44;|9eK(PkSsPldMJFRN$-vMw$WC`77Nb3;Z*{ZH&Zf>p zxZ~{+gi6b)=-(4oO%(!@Z27U>3c(E>>BCei{MN|oAkl9%%!K6G2`>=!C6pks-JPzs zQZF&dsMF(p*>;S$$PzgPLP8rfs2GY4aA)M-x%WI& zyPwH+q4vnEYABl4Qeh5Y$Pa{M_;*4v(!ps8Y{|2`HpKg;aB0v7U~oxmVSBdEinbod z<+`vS?*~;t$xDem7d~~NPqx?bI{X$g_ z$SxDSf!E?bG~~YdV@`i6IjM<{_u1pSrbJCfLQ_LI-Hp}Ew;RRc%@?On#RQ*FFG52g z9R43Ql5WB`r`D$Zkn23`5uPyk=}kve-XF7qK7>X8@9qk5jqJTgQ8@um51h^C?Bd`w z2v|3hWM@8HRX(|JNyJpggHy;~eF#(FSBZk*U(1Sr&%%oRbB*o6@ms~MqlY1_+gANY zUT$b~f&v$a@`_K|_J?3LJ1^O424eAk2ZH>(e#FlYojeoo;hr=c(*lY+K>`SLJ2*mw zkilT#`nAh3DA+wYS%su5jE7No7Zb5+JwKQjeuwjiTkZ>{x9A9dZM8=?R%20# zR#Ki~Du`R}9f&(n?8^~Pjv}xL5z`C(tT=pAr6Qpw1n|5yw6gW!Te|Kg17(CebNPOv zM7xkQ-pJMnPB#jOJbiOaxGg~D7e21xWC_pWD#q89-jkTcOo5MS$oAgZR5r8f4S(i~Lu~X>+VjdzW9D zcgml(Ow$S9hsv|USp)n!`&1AH7VpX$(w>D1)zCPRGmLEWdrwD5;66|iy$6$hOD`=b zbJo2MQzhaTI^+&2dOulS>OwtS-QeyQI|V;CS+7BeavXs!!Y>%L$5&d$Bm{*((}p#p z0Ut2xfIb)l`2VF%Ljc&Bwal-O-4<*}85o7oGEy@ks%8vGZwaIH{Na9sH11e-n|SU- zzaic**9UFUog@(cfHMXgTg*yi*LCNEEq*=p)_mOyJqBl=(x;AtUBkwkf@GyTFSX2E$wnamptxnIR7Q zup<0dgfYs~|G0i|8t4^^L+-|tpmb!-P-+Mb00Xg|k|($k)Z-tvh;pMH@wI@_ylONl z6|`6{VE$c!4)mK8^D%nEgCGWUcl^7Dg~}`LE9X!R0l8i{sVa5>=*?R$S7nHq7k!#1 zBu3BJ8j)Zam}uO)|BAC)F7CQR{0zTQ7F2~_D@Bu>d7^*;bVRa3g(YMF=~KGg2|l^z z75*&WE-x02;$uMuo0fHnsZ*mu?)Z|V!*TOLP4oWF%z;yc^hsuH2kTsU=@Ohyj`|*wm}f6wNk;32Ed6VkkNkGhbkBTqQBi zJ8WS^*ElvmWyIs0-BjF9^uU_c-K^u7z3|6riHp$8pI!Nnx;nSlgLlo@77X}B=2NB9 z=VX?#&&C_+Do^b8M+d(*mPubCp5x&%h2$C%iXvM`>{$MTX|$N&{|8D^)JsS_x%FV9pwH`35c zla1^GRACPy?X$`VI~2}o+%l;gjwqt|QxL7OV9zLY=LH$%P`oP9u?q6rG$SzH#dqsp z$sA9+{SXn{KJEFh)irfRa9(?JQRMNIELl%S8mY_k^maMjck6O`AD~dI`2rMfQpR6) zcgvyCI*A}p4^f<4GEV!@j60SdM+pzUH3m$O*)E!(X#sWS0l{HOPDHL|-h1~?$?qDX zfC>z%Ju9^qGC7_+tjw+1+*jXq`=;=mmUv}$z^7^)GT_aX9~?M>Gd%Lb$!Vp8MysNa zyhO>YA2oM!-YkD>Rl*qK$!SkhQ}z$DWS(`y9epOP&Q^i4g)-9$96s55-&N`@4qzp3 zb^9l86w=pwjlM9S^j10^RW7cCX-zdSN zo4>Q5wT$7G!3ZDSE?*;~d)1ABL0${sbT*!clAg~Tq+eqVUq`p3`p|Q8+dnH2pC}k~ zJ*Cn2#HAnpR1Pnz@CEYg&n~O4JPSn7!TCHJSa;f7uXDJMT`FJk_SD?VEBx6zTmQMt zQ2G`?Pdo7E5(Z+V41Wg)S9N}9UmiV)KC(nkGy#nAK4z{62bPR_9c zIT6;jHXj+?LoK?6C2iCyMNVOUfX2egf^8?)_<8)O$pDBi=jrUtOQX*eoQ?8KB9`eq zemT^)u?uQuW%mah3{g}FY<-T0F482HSs%W?9?81Xo!lGNmm;}jF*F<(BCC_!yLTZN z%%Wy^_FyY06;WEXiMY!~!0zHF50aezG`|tFFHzx8sYTy6Y;RUyq}(n!wD zKFQnkn!7xHv+@y>6?RDA+%|P|@5;D}i6FnV(0vOos35iN%?huoE5=>E!y*SM;d;`e z{^TN1Fi>Plh?s469U#@vE_RUh#$b3x({;qxf_WGI_W5x`q`Nu}VL^EPXCXI{VJ(PW z_Yu#*1J{Qw+r@IXFUV#oa~01$9nMjF)2;p^C2(R;4_L>h{&JKPX8q4}=X8E(wGH>Z*iZ8B&m3&$>prP(h`>?IMDH^6xDJ4iHd{`VlSx=8q zZ0hT31?_4PlZwm`N6&PJ!V0IhKGp#q1nmYh)r`lLfvNmTYR@^)iQA#g#p~jzLIBO* zTLPZ@GMn>b%rhxH`lqco`&VfxrqPIv_4(QDAgqF zqD6M+mfw!HM{`qnv4^CPwE&fka|Ha{S6`9jW^rnQq1^;wJ!?MQXumIe#}}LNgkB!+ z(@06(BR*MSCNLZ&{k0A~Ps}WQ8P zf6r+r|2^E&rgVjyXua5IRGdr0oNRVjFJ)f~Or9d$HQ=c1%rAF4-?ZCfFJ;oGO@p(l zD*Hhq4>dA&cp#g)d%g8cWq;_KD8tbFPq6`Ij4eB5u9|jwy3~pEx3xaEC>+El+udxO zB>Gv&gVy7`84{6l@0NFB+eWDiQOG9>g$lqtYdyhdQ3p;ZMk@qSrsjZoIYN@dY2WjOg z3}nO23tYSa-#E0X3usm^bWo4=qc%7!>2mmq;&Xxa<>20(p`@TdK{&40{5-(|{eX7U zGt~o;Xpf%s{l*-&oT48Qquq}aZfTa&E53}*9L1t8aq^0n)vXzxAI!e2*S!TGT8W1W zFQnqxZkDqxpAsT~6IMWY_GjzD=QvdKO@Ca@IKq0rmFRP3!k=Fbhnl5^7_gYQ?k*C`ey5J54a!(D{BdB8y+%^e-18gnn6L>BHt{9a3^Y}ey?Xw zZMp^kadgCTrsoIimiFT*8F>M<{iXJ*89#6@CVm%Yuil;S@hx~W#nnD#wc*o&Pw39S zEm?D=2?~=BC1B;qF6E-C!i@!3+SIYvOk!GD&#F}@%zURW*eC#^n~98odMd}>N-G?o z0@6W2ZKVA{5DmZgYpvg>AFaFVUy=q>80=mO`{&jEJ&DG9UH!U1YMVgQvqs&pUzPb&azfHHy@pcx%XJW`7_fD4M>74w)<(>JCy6$8W_s zZyk}LOEe7;ltWLmnH^-0i!YQEJM5V0vKq&Baa}KZ=1Zw3W8E9aVnL1$C8cQ-3#GDUHY>Q9z#GbeSj-X~zV-UL^b4 zowVj|8DPA7h+Yf(hWPuJD(+geyFJ~ej}FY15X3A0x%yeR23P>MW{qV|03*I*fI0nR4p?3SbaOUwT4!& z#$q-+$)*mVfC|OLdWR(otVv_tCf1$A0pc7f8=ZTJ!CbGcYTn!V>TbduHTXtLf@`lP z%Zq&Tn4m@VXde1JR7^($i`&uZuX>})A-0t2AxBFIlO!vOq&v24+g68PY}>Z& zWHR@jGi%L1*n91&+HXDl-?frPUkK6J?pavtP*_`AbB+7_@9M?W{?VN?V09AHw2Jro zyaw@)qajw^3MEM19cgK6jIL(3y~*NcFo-ZpfC!Yvhab{?-y#wiN8~<7mpx;9OT(T# z{!(--hi2fWft%2sw0C!`+B(vY>0cE?$hw=K7FChhO4w~b6rzTY76J?L*p&C3VSbl@ zsA9@tE}n>JCLR^PG+k;JKa{SnV}WMz%0w`~D^*!Q!MUHW+4V`O2V-a=NpAVC{JIvxt!zC6 zE>x(^&2DPEwaNAWpwsNYD7EODeV$rk(Chkhm#?XaOuPLSYSH{H&-tQ;IXpS#$~BlxpOjjpVmZmCfB zV7ZzJm!_cs?jgt>l{mHua0UZn+x*P|vZHqePVoL;5NSDz2`Q6){18AN9HM8_zVZXM ztG1@3gy{((nJ2%D)xVSt&q{$y2px#E^hE;8g?v)?`yy8fFB+5Bsl8H>+yxA99|UY2X0HK8wMzFeK0JW+Bj$SS z@dQjg9^m>_S8=enJDt6OW0J>H#&CPn&>|ui^Gtyq<8o5Bk|88W^C^E9udO@@%J3SZK=LMrG+s=nQ{XgdeA(;L+SQi%yT%c8!A+%;$5h z;Z%&w@pNZxN<{Ds$SZxuv;U^D=ywHuZnl_Hzu*4(l`Mru&OkIub32=oA*I@5w(WmS zK~-4VztFe}imYyGUa6xtY$T`flL~ zr=(mSC=Sw^`_K%DwCqXCSbZ4NBKO`QDmc7{ej9+#jn6G-qb-Z4?TDxCuC1+&Ah+t| zxcc>j6VmkI!Grt4!ChydiO&dU^{c>L0=^n z>aU(^vHnj`6Y+lm6TwMeJsNWcD&+`d64b@-K4T#OhRF&dxLR*{)36=+RMehM{MJ>< zI}1i$3O-koW-=Un`~_HOcQpA1K-?3c@2sES*qDRd_6pMuC3hVO)~bt0|EzHQ`f|>( zqb5H750QzXz+_{bt?<{cY?>;h!?CtuvcfW_6Ox<1JZjW`#{W?dXFC#w zxHEn(SA?X=;!I2}kCanCi$Bsz1A6l**FDplf=$69CJm6W>*)l3F1m%E@+Xi9uD9my z$DXX-;6fVF3NZky^}vn6!IMoUpG8`+MDsMGL1d>JvHHfTj%)5Y{?Z`|K0xBeaG0km z_CwUeqPF9djRo^KTXV_(f*$!9j;A@C$INo|fPDdK=KRt@5VB--kG*qpw;nV=1jZW* zQh;pE+lQrS2)-EOC1(65joZ3~+2s|HMjHI{qS~&8oz)Kne+b;!l>OeL9Ih5;u5w1U z2tTd&AV%a@CCj1xAXCzHXlw~wkY3O`&^F;kkqFQbe4Ac8uEl;~j-rNbPut;Y#)FL7 z-h|NcYv$~(|Mic+lFrl*?ewGSDI%7tw5lqWy%f-Kg-Y-xPBhxS-;Gum_D!M^5`klf zpsup&)?zcIjPPF7E^dAchH4@vvFK6}=m7nIO(E7eCQRrGWL34FcfJMmFu<8dXV@c< zlq7>4e4LwvHTA{krcqz=ZAFrx?OdrKeootU^F%&+>yoaVAl%Bief&f_ZzUsjnbl15dA zVL{Z+VoH?fN=f;q}hv!K|~iUoA_KN zSJ^l4F?lN8eV##K&qsOb?^$4xjH~2m&j=bV=if|2pajq}S1&Ne-U4V|Efc8)d1nn( z&>F>Iwl?3xjBe#C>5r!ueDcS^NSniwV~2g&79u#gYlv z;$9%M8~va}@T%D0HRjaB2ff1!i|hAw8}SOAi?)dyJS&NGjM%v+R^cljRp9&8GkFM%iYQg%2(bx1A2r{cs!GR6s-P~w>MN~%(l z!{jOd7ra5EkALzobp$K2%Rk~lS_kX*VTmaSoRw+{hzB|Mk6}D;A&daSqtUCjkZW7` zp0SPdG-#n^_UJluWjvD zjRl%d9%NHCj3Xj(N3NA^TitiuGBaMDsx(6|(AwTGyuO8W^*JcGK0c0+u{WiJdWpN` zD(C@z`6022&`MJ{L5YarM9XAN97*~zW0;?|WoZLA=$UnRJ5ZMOSYwWlbn*vJmp0@>ywea@d8(6-(Y5A{YJi3#ya0XM^|DLb?!x2x)Q^mG*RB=-OacRYAJmci0q1n}OdPv4I+C^@@e1-7p(1DT4d$`v_|oSh zi1bAzo{2hCXym`T3^W~<=b&oZL%Pq7Pu=Sp<2xqJ$LHj9vJOuiyW~%_EJzw_MH-yi zhPO}BR3J&uzAT;RD8(}F{>3&Hjz+wZR?f$DjnsOz5_(^=YY)1Kex^Ej59{A!r;lC2 ziME4@Mi^lA%5d7O*vIrB@AesPSImT9NaVUvmZF%jyKDZ&ANI!EC3-7D!vb+9eEEBc z238FCgMod0enNF@r>E&swN}OnP?&waqWVM>eCf!SVx^T5%OXjFwnAGV#`Co7ZQmYj zX-C%45B@aP3jOG1A*q9K1>F`$*x(L*S7_$Sq8SKY)R}rpp4sm&E-#C@!ko_rIVK7BZO!w|BLldDI&?;kI zj4)=NMnG6m_0d-aIZ@XfES|`%Yc{wWp!u=%D_|!N0rD=1TG%C+-$iR~@MxHcVvP zhMoY^1+=~q?ADPDL%13Qew$4b#gva7TQA}IM&6iiX7|p{Kq1c^;lun_K8`b~@qA=# zW>}AFElgwY;V>`uPKM2$F8+n~Z^cS_tu9p%s9MdMo02i6ap52a298?K${1WZ6Fop7 z*N2))wX%WvSe>zP;SKCTsu{>50`{0}YLP%k*LPUjgi_#G2J~(^a}p#uJG1I}{PUgP(9r}qI2L~(nnPyHgiMSv*U$XOVIjhf zx_4|1TNZrj-xn)O4ml0KMAi`EGX3o$a0GVR972hPMB9~;(o zg#OgW8j&m*(~wK%cKOxU3mRoF>RM^vqd&Zv3jnlSYi3};f++U|YDP2tcg&~MT83Kx z)&}#>gGRL>>eUcgF-c1xts!P{I~_K$hYQ)v_;$CT!wlRd_Y6Q@v2Pd8Fn{u;}<@!SqW{~RVTfKO1E~Hkm!&bcd6GYY~ z;1JpD6YObtK6eJVKSL@j+gAW0TZPazUW=J~Kq`9y0sj-fo@ef#?@6*`UzXLh15TC( zDiEJbHsA#LC^(@PfyqJe&~gIa-MLDlk3ZPSLMFY~r_z@5jKD$xbuLh+skR&8iDe;O zfa@rDs>s3|h>rt6u$)=Oe(wDtI1%mh7sRLv;8zxbVP@H-aCyBntTi@ze0we42`6}^ z^e_uxTIf#v0;>%j}_3kSy)3Rq9Yh4Cvsjvl}Y zH~VQRJV#|tFfmExyU?qQ+b9bG(+JwWfyt$a@IoaT1`MYQw{3aLEQOJrUz%TP*=yiu zsOdX7zpQG(iQ*`jIc7K9T^#;Fov>1AF7(^VIqi>=0tNisuY{t;UbfwUa)qjDN$z~RC@$%7joALyC& zokK|vyo7SdBfW}Y|Gp47usb|>P~PsY?(N!3sI6LAex|yCHqSc`?rsDiM@1ii3NH-G zf7dSZL>tIba1iwZq40-1v3~TV82BP9R?0?rd)R18{+Aya!oG$vyR(!yEqk|!tUaQHBe3Q3y_qrcpp_X zqDy1Z4uNcW#U)p^eg_dXZLiv-@5r~i)n6TFK`DAs)ZdC@fng@>r7>(-&!jYqRGFjH zw%LqG3ZsYi$m)G*&by(JNTJ;P)=Yy*HFl=r_#i^2haz;4!}n91V4YN3!*LBK_VKC( z7dU0+maLh~so5S~aggG&#%O5cl2mM+84=by?VA+L)Z1B(VA}Gwfm9~7;`f44#8kn) z4F1v5as!#73ahkqG_Joo4&uIVjpdolMI~Q;Vba{sp=A~2bMq>H+AP<~RYH8)tOAC> z0+O;tfV%xV1TLw}eCx}1vU)pA>9@#SV=zdH6)A8Jn{NmJb&Rxeaf=ZPwFI|ZU#!)v znb$}P@TWokySexTM7%bl;psE?>~{gqeK6IkX`pWvZT2;Y79=lRM>dKcm|cNFq*7vO zkcsEtlWcrm6y2pT;zQ|;-tghezcw4QE;XH-Km+Er66}@zedFD}D~bgU=GX0>S4Bs= zKhBvXL#^o?yaFoz0?@$f1|Usw!fS>RH8pcn69Bj#^hHDs^ralErycwSqcS<2YDFk- z_1$vu(_kAOw@5ax@LFNqsXN^$P$ZEeVa?j}oeS?#CJK#0lM>4T=gwC;Mm0B)LgR0R zDGNhxv{0odt(n`ZJ$Ntm04qb>B!$S`S3z@Ein9NDT|ol}h4r6K4y516>i7%xenz-Y zl^YEld6}X!%uz{F!h3AL^0ZfGF!|H9+i8tO zXRdUztt?-s63$PCyOGJiX>Q5L=JoMpo)s587(jTq zekJ%dwgQ*dI{QGo4V~!&$0n>QT;1h|8piJ0ouHfD@sE8 z@1NcnAEHiM(i6r`TAkIo+4xniG_ig9yrPnyovYsqxpSJu62JRbP~bc9b~kE= zNFQSA?99SBLx)kjYn8jj5>3BeD+^FBaAYt$TLRnw%kG}-F$%5i_e;3}Kb!_!w}r{) zYu^(_;v-)=htKDCxYF0z$@?=TO&t1t!G{J{8!WrYZ zD5${UAVk;aqd1s!0B z%|)3<-QC@1`IxUy8cyND8*XijzQ(Fly|t8zzq7O>U(%RcqtDW~IVst&b`+0xF@7fT zzLHUTdsRx8jEuRgzVM!So5PtehoyzgiooMX1f%Ir)bOa3{8k%!F**4Ouff;-D5hQ} znS=jwt%F1Ffks3MW#z_jc)13*<^LoC7XaO|O z>Hq2n)&z}!jND_R03Rw@uKzND z{kU`IgG_!2UH>9dfQ$WZgos-Setsn^Or5C&{{sQ|gYOFXBMTyPPHs$nXC^WVqIvX( zNGAR)v>AOoj&N9a*#MzWHhPftfi~~#UFw!q=u%7~yOSmRUlWQw8q*6F9@n6`1W0j) zD!?&^au0r*y{Gl(2n7W?VkOzr7Z9x`Ga$7i?Bx#Z7DpL8bsWv-ZQR$GRg)QVQUAL1 zW!yb1wCkT`FGFKob{F!;O|Ko5qb?iFH=|q;DuS0LqVVVAG)dY@O;0{EqxRX-yPfEz z>`u*e^iEK#gUx&Mk@bv2Z$b|&EBf!g*q%KX1T=Fi&|>5rnVb%X7F`;wRv{ckg;;$8 zI9M@;f`XDfNT~kwvdRv^E`?bu!k64(dvnX`$kTNsF6Ei*^LXd?LL{LPIEro{>eE|C`Xf4Dq$};M!qBtIX4t?ZN znMY|DRWn1hLMAKHsjjLo>e}pSGP{p%N>bn>@KP+mKRk3QuJ5@0)9%V@=hG1&jP#C- z{=I!Gk)vZQHiJc*kGXs(^ab12g*~%PL+mhK=W@nCFTYu5bh1i&bv|uRj8F;deVx*X z_*AWBuW!*CGPWBNMrU=fP*VU=HQkYn!6ycZ7v=vya+bAmjsq|TD?Drjas&_T&oFQyDrha*rsad#D-a4mKZ;RzZicq$yr)w=c27f8uCaLV#v4K+L`zb}q;w z?o3A%v-;oa_IW5cto0DA!yCA;7Cka2NKo2ed~; z7_^rDV;dg!oWnlFKyk=^}w z*v9H0GT5ejav_Fr#xEH*^E_T)z5M$i}BJ{?;$!Hmpa{j5X?haQ*WsufB$8}#SDD~~hI)s@G z3n$ZC3DSwyo0|b*fNHmO6C6rapO8I^gcP4AY{~V4?x9bItJ78G(wQYza4~)a+>v+X z3>-LUCNEu~uxL$bLQ76C^W5)zZyG3B(fVq zPX6fNUxG0DE2gM@p&)5ZToz%%olysL3yZl$=|@!?#wd&<1V~zc{|dCj2K#iW6T-1- zt48lVh~P`cyHf*4))kt-3!vJ2Mwvluf7JjTn^aPzv)gNrW{cP~_Z-fFw-shw8WVT% z{|4@s=yL)-oOU_88y5TPRN2I)L%9gJYH=VoJ{14I`7cd%0@OBh)?c^J`S8niW1exa z|FBVBOgP>b&~jwA$?W2P5z&Gt0;wIO9X-kdlWnOgE2`wu1VgQ^_%4oc?idC5++`7I z7}|4ZpgwE@D5Et5@6c4>q^_pke@|(x{(jX)krXDE5XH^zal`Wi>&Bqi)J>5H?Uvz~ z%;U|ej=^i1E|Fy)F?y|O#pO}<=?e$r|0)w9i;FE2g3HwHLk(zJMAe|3KmNJT0hHs^ zd%&A}{fbi;mYWid!YS+wmvD-^Exo{;PI=B%*#3oLKU393F{>5f8Of1Pe)yJ!j#y&y zAt0(w-?+bCdrn(K_rY4Sng8xQ3i^A!=B*t8&^85sY%El{j(}s*kC=Z?X*BuzvGr7x zBKR37oY6@a&RfmUO>h~bm+b?IbOUkwreLo2!w(knVnhBreCF{o8bjs555{0dpDv^K z-yA}wHqxgzhn}ab%Avl=<#@gH$j;}!i50sqZ+@>MHZv?mjolpTfx!Msk;T1F1(`)7OB>gx5Zdnq65B+`tCGwmV^6KBHec@kQ&V+^5R!&s(m4x` zcy3=i7N9+$d34Vui&cRkt}l?qjIlP4Uz06CG7a@EJOY)nKC?PYg;yE@43M+@E>**zI0F8AyEwybhOzTwh4OQWcybO#zD}j`1?<6;zITa#^Xv^ioD&Sf%d(; zz1|N!@c%`Nq7LQuJZrFps5U9#G~X2He(*p1x3GfqIDcxC>Byurl-ANUSm#i5koi`1 zuc?~Q7-q6H$z`l0S5#?`bdJ(;crhA8A$zrG9d)_5?y8!SRjs(W=@V;`BR#dZtaSo^ zzP6HqHqjKs$?bNv$QQ*>)8C(#z`}Of!b+pA(}9 z4S_^#K{;JN3e%#btb%Yvv$9Br?N|S1s8ijmU{$!p6nP!-j*0C+yyzT=?-z6uDZtzlo)>H3RSL{tgv?0Giui-`i6@ zp3(ih_SIgiszFGqfhP;Q_DgDGQI`DxmJ_`UN1fQo$@~#($;H4UsuotAeqjh3$iIr8Zy#WAwIau|fMRH>!zNiIKXw z!JIPfDfW*U6-5GLeAZ`Qp}RF*!$MiD2yU6NrT!V8$ZmDQ73IkD+RFZ0NMV?wfe6Torgy zw4T{%3~c_mZj7Gr3kq=iFjnPIe(c^yhq79KT^q}7X%&W}`yYd2;QMy_`>x2)6hNwj zsxylH`PpZ)#km1S*~oz2Nd=&-iN8nWagBo^_xe!JcFZnJ<#~#em0IhlYaS=1MP2iH zO894OM$Nsv_Nf0}8t+_lntIE!Qf{#&zM9xaJG4k8NM5mVNf)2T+vJ}}`*TsRrX`b7 zqw|5h@E14xoA*Xj%b@fcFJ|!OqPy5h-m zuK{=|loxTYHvy%gL0JLy0&CK5nDI%kv?GhX>npVH$iXACsv|E(SHpnHy2HUTx-WWA zpbh<64g4MbfCx_NR863gK|7H{aM#<`hdgIfzFQ%#+0|2swF}UB@qb0iAyW|#z7-lr z=iiKHMXyRZUa}@)>HXjm+DFeDND5op-0}dq?TFXF5Sh1H||{ z6!S5MNb(bf#eDyv<6IT{nu_|w7mQ_fWOBY(78pQ?a0r473D{f;N!M^a{33S<`8AGZ zaYc4#XcQxl#D4lborfi2$&EU&RZFg+(%7peSmm*QiTKa8WHw&GCBU}W)^INI)@k@F zVili?h``@4(qC8SiIasnq_A=6*fJ9`aI0oV#aGqbd1c5oVMKj1PO2W_OZZk|*L&w0 z%#e;4Fk;uby~wn(&j+}M>{j?mV|2)!YGbT5E?Qu6?lx-+)JxX**qxcsx|H{ELyg$7 z2vMA{Az!xlyt&^Fi}dL_FU=(a&sgzV~(o0fAhQs{&ftYaNO}3jXwR z|Jo(u;?i1DqWF5oAAb;yOD+wz61Y#z7+Y@S^ATN1z$G(G@`el=+7{7o?nybK{mo+W zyvREGM7`658OZY!h1m8XtSsqQ?PyY$o$|laa}QJWSnSiG%)Mwcr)9ig5Q}$8ey29K zB+@B(s>PCE$R$*rlMQ%`3LJ+A%u$sg4hOg18Oxd46H1;(WdzO@dcQrLuXU54HZkF) zT9rY8*DrhhVc4=A)HqBx1oCs$=R%8?+e(xkBzs`rbVj&V+JU#2*xwtt>=h5cd3^0P zz2HL7G`5_eaH|IhgF${`}vSjyibc9&5X!(FwJ=E zWn00l_ML5W@SB{{gV(G@yP=`eID6w#T|Ax+zlh8$zt!>MxU2fNlH-SPNMYPco(&lo z;Q8h9vdUQNXam(rC`)a4Z)-dBYPDkj^;~$^bj&vTfRg6X|l{wzaHG2CcbONj>7E*`tcGchqR|) zFDVDC*Y5^S98WvytX)MN4Bsx|M@AL}t5f-g3B0{4<>;_0M*m#8A?hV=d2%@@$fS2< z52?ygXzsd_7dOZb7@-@^K8*0ayzf6_+NH?QCGL51s*({VmV8zKYP?$$oRhQV=Mn&=2UfZ*$Vcfvb4VUQ^!I zwjFhUaX1RG)^Yg637zS5xV{Q~FFt;I7i5-gPO9$WCs;XdZKmVn&&v_M?Mnm|0Bl2S zEe){(qgAcJ)CdH!(A&+(()v8~IQ_@_IP2Vp@s#16k2L_$tkA|&CQt04QOJr8;L0d` zynz{VQHF&3rByz*mOO{e%4lo-_sJ5loy86Q1#Duf4N1EoZ553} z`^?-05><^rH2jR^vV_jRLS20mTof6oX9N3v(^v!1j@>KzE#=gfwTkK-ggs1)=b+jNP(30Rf^s0Kyt>vuR&RBh|WXST@PfkW%Bm@6V zM;64fH}E2joT{krSg7Z|fuTTQHepy{x{$)f=iVU zzclgnP)pal7iQl~EtG(9XSDbC9*L5X>v(;0_#PDr9)R&RIAkBae+N-f;7`66o?l)tc)cbb!4{C`ih^qTrDNh6M|!Ns0IBret^k9&Ovip{CHV zUmFi<33Je$8+ClT!6O#!OPgp?Z12u=F|{IHf(OlHTChc$`GttvFYj42k{(<5dJ{Bc zcJ`)!cS^k7R54@Kr3c0Z$r8eM^ycBgxQ0#GtRRZ$#Zid_BhgOI00%c4QVl`lfx~ra zLR<^zqFx-eZG+z}MkL4tS>mXc-maD}9o+OYhp3VbG zr31?wS~9yB-QmEhC7B_@5}BQ-tF(Mh4IJaUtVExFSU=|4rkB~_5kC!l4Uci z-A0C!A2oRe_5pc)DE9+k^Odhmsb9yKTKP-AGRnh>pL?)_M{}T#_7|jbH-R{N^*1q5 z^yJEtMJvgXAcYdcOc;gP9#Dj;We{?cAv4<|SY{w4aTM;*z^vHn{-Jy5aZ5sbf=}8!AYq%>hRG%iLtjP7fCh@Y&KhhumW|GDTsQ zPtmwPmDWw?@CvJOE%m881 zSxXgg3FB?2q5K<-tyz@tf!QdA@_%KEysn_A2KFNJL736 zYb)X7fn_c+ef}+iiT}XD%Jk=81PmQ#vt}%vdK(vS#SYIEIivvT2sy@0g3kf(!+W!@ zLt*sjTs=8=lNU75p`1@^StKm`abK!t1`qi{a4ajfekE{(Ai)qA{=kB~5U0LIX3mzR zmxT@p+e0@p2z@^0q?fzn54SX$cousvh!+UwI7d@ljlX`9#LVM*S8)NUQ11*4h?@$} z_}ea&QYuA;JXgr^RGZ#mbU>qM7D?lCSfK~m$Ck@Dj%AJ#kZX2GS1iGRTTPeoxFjb9 znls{ZuXSU&s7*#Qso_4zmjz7e+KN!gEEzhp=1p4c9|AFH{YI$hkyfoGbxgaC0Ag79 zzii-b%)hy7<92JPu*xqQCy}qW$QOx>L3dT2$13JbTB03pf8jwM0_^D|~ zM3njlu!7v7Qbct-R<2n|31v%H9W7;K>c<-)o~kO>cEge+zy<}of0_h~@}M*^x zs)sR45KB}kO2`Vngx+%2Am5%`jHs_nU(2zGi%29>eunu{RPxYK17>D`YL zGz(Q$xc$+u+p{0I_h~*`)ujg0>(Op8e(v={;y0?>pD|ABhH zg1>K}t(w;LceKu+G3MPOsEyO!+xLg=>0xZmANRCgo9(!Xc-n^{PL~f_L zJoPKw7vud~N8wpdmtV3F+hp}8V0l<>L<142#a`1Y;edBO-$!atpnIUTnIAhP%TiY- zqII$ik-1=H5WYgHBTEK%x1${V9WpgRYqR4mQLfDm@uAw53j4ZunI-77D_sCL3r`I` z^Jnh`X7*6^i1>I$Aq=|kW4qndXMMOw#P3BA0B8QC(-a!$Q>S-x?-7FLb5oZ?(ds z**LQZIfCN3&dW3%55_?^3JY~*N7sS#Cr%F{7<$jmM0b%*G~&R|n5vEVFFTS$knWj) zd;+(u`c|((2Y2_dx$GA-Fi60m4F~0zGmp^=2HE#DDw7u*iR&Gr=C4WIf;4vRc$UY} z?CkXqqR;(5&C$l-e%tI#b@lNniF90c0mSp`lAdiT%~cshHn zPMNE<)#&2{1|iX2_dhi53w}B$70^0AIo)sjLdx0JHEU`{No2?p_Uc;Gv;BazU#?L1 z0N3B{y;56jxn((%S$$O;;fRR)a;`s3T%K?;&zwX`%GMFhE)i z_>X0FEdd}?kc$iZSBGJ1qdmJzq!KDpN?q7M_BMIU%B_FsO5OVvnc82Q!o`7LEN@iU+!lt5?oxd)5 z#67n6K3Q&_xvWAG-s$sdEv;L1Vx@n63YXDLiLieeyD+bl8gVsM@RHN3vn+yFqrwlK~tXlT{0|}K=6OOksb13X>sm64Z!CPSx@6+~!*_1YobTd11Tz_{` zp1?4gFVk6CvRfOdO{)WK754k~R)DsHTN2BJgS(%M9&q~Sn#Uk1ER}n_Y&QuCd&-`Q zlPZzu_wlSNA{rV-a492($S6KT1GN86KE8`2xT5Hxn|-EmUdL9{Ws+L(t;t|>6=7wx9;r5XgAv& zRA!WbK2g_#YReqP*qoSt2E35L;!uvBQk?f>bYLJ~4g5tZjyPYkppQeZtFgh;9wy}% z;_qG&MI(vnx=XnjwW$UeK-$nTE6r$b5^P%^#j(;Mks;$jpO_9w!IO_dLGFWR-*&mm z8iH9(@8LZN`QqBMB_13Wav-{Xt9qDJiDE2RUwLpbI4xDD-?{3HqKSFKza`^x_J-1I z6)o7e0*vGpZ9P4&akz=!Tl&>iRUz;~UK_Tfv0m&T8*8csGv)*4B^cIe1$eR^zip3r%>CoZ(LX0NQlO#HPaSdxeGgqbPxCMoJ$1eZE!u;M=8uQ%?@ z9Q^+l>bJ7B2?Nab%GG6~2y%ho6wEZBx6b8GzWa9cM9tglHDTj#P|zk((kfCv`<=Yr zx04S2SnrQ8Kojq$Vf0oh2K7VIe10H6K=_Kue!VOmbVn>p;bvVzQ>JBnSQ4_rJZ54f zA?UKtR`F7x2WB=b(|4HA*39?_n%w^Fi@PU$5!HdDpdSLFPJn?3^3D<>uVsS%$Ad>b zmh~8_*uS!bn@ev}x&6)W9*f$NU9p~7@YApafK z=3SY#clej4c)y--YycC%&I~FYOx6>Drtf(hVxi7vz3s+GLQ2Yk4+_$IJX)fOywT1| zky?&U*QI0c0sUQ0nvZazIPa@3u2c7kQxB)(5>(4MZAs@{iahf+Li(!}ZvV3xfjwn% z3pEc16Rn`n;x4Q75ra-DjHmoZoQo;~HB?)hNe`?b3 zDp3+roT?hMZ1A+q{0Q$wLs10nKb|q>-K5(u{KrV4y|-eiUSRPJr|0&N z-ue0S^_LLBgn!2D59L3Qgdc=pUd!5p3KpTfXM0|me?d%p4TEhDF*OeI%ZXw8SbZqP zsA1p*q40w(>V-%ivkB)-lZHnVlYme26G^vehZQp~Yt8%Fq3t-CCW7&$8 zu>pgYXvLq|)!^9ospfXM-i@j$DG8l*vHo%^z|(h`V$j9jX?(O8&)6WqlbYCAOIERO zvffZ%e_K#RPOibIW*ZcprDbsSk@U9X>>gd2;=!oPpVXnySKY{=`RQv)OkL?>AKSw1 zIpS_I8yp#QM9Z03Gd`@I8mIWr$>7_|79{R7R;t~~RF*hSD^2xy!}u zpjh^LvbGD|6tyr6+LD9fduy)LyCst|8meqD(Kn65-Z*rsvLx;M~K4!R!5*`OvkE!SLnAFb4xddNPO~ zEY}%fd`GRLY^(F9xw!&Vc%~m^b~y8ypN&l`Bm7tWGW;2l;tlqux)`CmOeJIQC4`x< z^z*Qn(&6)oR0yH?DqTy3WxXxeimt@Vn)TQ{jL<_5cWQJ^gL36zb6`WDy~le8HcT?$ zNJBsis2Wwl8jWP3xmZHUJ(=Zy!EG+!K+I^l{>0!nsY~pQc&s;-DZ0;kcx>W$#4*O8!BHZKK!^HX!fG) zVGs0>aDV+nWFt;SAi?a8xKwvu0DZp@MrMNcY8ZIH6WZRr1ux>;YJc|1`C&UUHHL|z z*gKsYh=qWqm4oBQ(=mfa?-nwIY|W7GtW=io;17a?b~S(d4h4fN|1A97`KWn#@Az8# zO7K)13WKj<)NC`Fk!>KV5Sex_*`d}}zgwLxI^$RjEqy6tUWNP770d*QO9iM9R-Ylv z{2wZH0$e{Gs`8bC`t$JdPk;y>9FrDMAExA!p=QdhWSq!IGip_YECogu05<68~Fxce+TE$AzDqG0!1Lo5CY|Grt@qs+}*e10O!GdO*6e;RcKD;-@Q;l{J&&kqaJ@uLDINDl;-prgAT zS8fq*`m!n+ynRz2(XfyslIhqzZ%m=;p|`o7m+J@9bOKCt1keNGYJfO*8=}si$$6#} zfvk84rSUP4ClyH?G6gihvU3>+2gy8ztCS{;?)_o2P(1fgrf~*w8j-LtM?R7smtpP^ zO9$Z%VtgNFbh)E_7}u>>^m`i1{I~m!b=1_}wiEyUnhah6a`2+C;?p|f5e06TH|1#- z_7eZr@2DM~@${?rm(j4Wl(Mn3tOyHu+3B;(;z~;K+^xz)E&H0CcW#A$tY zacBn{)ic`+#HrYEGecO_yuhze%1~0?+3P!~ma3Aru?ny%3xFVcm$fOYP*Ofq-N{mS zX$`CHZTiA~thTbU^3OV}-`oB?ITyC@UDWJf9i?Lz-jf*`HPi>ZibuyAR>;Ept6DJ0 zW80hkR|Jy7^!-;$7rjv`zqkK>_Fw6(5QeQ9(m!T4_d|TRzc;^X1kyNjwgCHmBPRGORIBY!0cIgE zk^Y1?OVj6oxPqsq~$i;4Iz+Ow6XxL3#kv^+l?-jxkiz?wl7nR~{~#C4Q{U1~ymy7X)de36W(k{~y# z1(OBPU!}rj%T>({X~eAxEoB}(%drN%Kw@C1YRu3c5?8?(>%PlB@H%w&l8qnuOuqio zP9BjYM(6$vF+(M;Kq09IK*1?QjIJ74k2;_wh*Ke@G5g?oL(bQrGA@F^fRsdulVRw# zJY{}yW*QrkHv535DtvI#ZB0WC+gkiQNMO->anx`z27fM!s;sb3Ey~G~dAd?-dmS>d z8x(I4Ku2JzS+(gN-J~8DH1?}%$M8Zl66@?|_+M>9bNMr*+PghaQk=ZLV^oK^SRu}` zD27m+{q|>&vN?n`lDvZ0pwy0`b5jCf9l#+rYk$YfARN#z-FLhgRals?i4gA9Q_c{FFK&=3Ov*x zR?v7q@aMubU3abk67xqnga%5`rmnUd+B(SkqBL8eq$R^$xiuCyBgD38yC&Zc^p<{x zBaKZ2Sl@=w-q2x8m3Q?2L(?^|RT{S2y|Zn*CfhbAyQ!UPvZp57wlUeZ&B^9u+d7@| zedl`r!t>r(Yu#)4U&@(pVFxKmV!Zr<47u&x!0J_0G>-M3+BN7P{-YUugqU)`&v!=+ z0b=KUjlyQa`_`S3&eZoCZa4+N(?kx2yyFX$M0W#OI1DQ(3}f1}T~TdYfK$0`n-06( zjqBYGk~TmpZR+}5=3z>3QFK%E%lV5Sm;sF{Q z)v2(!=ZyR|I`z$?VF>I^#~6{YVhvW#Lq92OjKH4EAaK#hSbMXtHS2rxEhlu&3LHiD zp=s`!?~ZJdK63H)4zo*#AIB%aduIV`80<9&5?rSnHQb>L@+%-JK!aWjj~iX2F5xio zCwwP)czA|=R7;f6gagY6})PJY0L}Zv_qzxXb|uango;W4Fh*A}44U~jT%#day>8z~xfW9wrqjEQc>rQ-*q&)eD2afV9$9DB5>4>SR zn7;*pU9#J<2CtOPd2W{`dd)TB(oI#jS-4l_N?-hyW$^b}j`ybQkM@?Z3zWO0#$4p( z2yvZ)H6me)ESeh#g z02fjS%+=MPh}7d8!gA@bkr0f;RUa5X&M)z#Z}TLi;nlnv#>aclB1BXgbo|QS`qM3g zT;LX3x~tGTM}3?5|JSZ_gHvN}WmG3u%&q_-MV+@&j|s|41UUvT6{goC(z!`l<_L>j z5FY?m3rFl9`@#A6S^M~*tem;BS^~L%)Qu<<1QnMf5mzKB(J&pYRALc!Y@1{Y`{(O& z2#n%tS4iX3A{p0_^UAu=3Q7 z{`h_5pTO6+RE9Q5bW_wiY>K@V= z_2RBsd)Nd#xDKEUKGZ$=@+%M;OJt=F{Ii%^{y>~}x)cb2&Z_Yzhw16PCI&wJWy@h* zQfx#HB)CepVr$$d8!*q)_SN)vrsN0mhVd8*DS)dc?owPUGsr+n_dR%kyse96EtG9( zI!%wD9iNK2vZo~l;)gsOsUtk=KNR{I1l+&-hE1#5fe++Nx+-_6pO~3+W}l&W7h&Hk znz^IRz}C8Cthu#(^M3(?+2Hs*%o(4#&}zP=niV?IR{t=N-L79aLlUoZS-Bt5h=l~2 zH1)-eHQw|3|GTfrTGCpr1h-Yta^u<=$Y;#4*Zv(W@|G-;u;T{}_hb+G=LI1{{5OlQ zi0kEa%iN-rEwj19+KWBeZqp-2s|Yld0~o01E9`m?C^k)~3kF53rJp%tl;F%2q=f;hSzACf_+7U&=s%Vcjr_G zF}3}IvDGDwnRw7?QOoYK5Y9ZPg$d6kiZ|@zj(hRPY3mKwlIO0F*pcTq>~Hg>k)Z|| z&C6b6*J67dg5guCY5UrtPIPic?^`30_lgOF98FNXn{ait<~XvZa{Hy(@@B4lG3rGW zVVL|GNq2;UV6knV2wqu)jYZK9(Gp=Epm@j^D*QhpuRuxJT=<5Tnkx|y7wRcNBn)|d z-0mVzl#ejs^9ck?!FCc5%uj;gW~FS9B7KGtY#u447pEUb-yc>g9}oh%#*7b_`@p1sY4 z$UR+sLXq6El4DWyk^=5eFHLa^yqGJ2=y4Fe$!)1lHxtze=#aRHS0FLDkj z;c~yek+fQrbCqNkHp~mV9v?HFC(uA&Tr{!d*W&ZoX9PxSW_R?1SuzbIy~AA@tQ7U6 zsN{$sDGsf-z89Mv%;Y(s2aItDN&LhBky_K0{2<>#Ou?hj@(xPUX*MQg?%Wx1LjioG z!+99G^uR_ui1cMkqxeVX=BaAzV3ZA~=Ud_^nU2Qfg5rm0B_qfj1Z8e&ONnB785}fF zxZL?!sh25oMrrCbkORY`hzg|QDs6`#F5|I@2wUANa^0XdF!ypqyo2y6gz3QihxkPd zqSfPSp|-I{s`G$6WGxcfsA2bkU7}iPzP9a2%qr+N`u;spaK#7c%h*~p=Ks{lpOr`4 zVf)ZVI7p5gMenPD(@Q<%ANclAxx>kUFMoRxSBJC^_HJGyB_&yWQA7IZ_D;ku){YXa zHCBd?ts@br8DOIjl5kl;%RBv(9v0#TraS4gmI?zVc&T*;j=8jzh)u$}2m(-}EHH?s zI)*@0jVo|!Zhrs)!J`xj^jR*g#j1&&98g`PK=^ofnk_>yiOE!A07^*$oq(#M<~He0 z)je+*qXg?gjF9>C(D!{b-{c~gy<|^a+|H|$werbgwVxf1=RWWf>a8(C*6W*LsojnK zOjkjzfE?QXDNSFzh{3{xs)RTxmUfelI}KF)zTm{?Y(Dw*P!b*2h(-J6kDR!;>$w~= zlf>j3s{5fRIvoE4n?RG*`{t9^$&KfY!WSyAK3D%gMh0DCs2MO|3H28JH0%v-w4FK7 zO&Qf0TNPX#G8Vtz?+mNDvyn45^%RSMd;2a73Gew-=*yAs_QlFAKLg6;ciEKAba>kh1`2lP((#! z7cJ_h*&CxB^#OVU@AGrex!iN-ec zDpB)@dM7VGC&1QWV#?Z*M*6Z zt?fVCzF(#~w_<=40i1;2JQpVG`{)_D*-#z1+ORyCGz$hP5^7wicVMXM0E23+Du}%? z_Go$I`A4f@Q>W%V4rj4<)F2xG1?A3r-O-NvkT?4njp3uotB!Ks|r)a zzP_Npg6;Oz8=LP>^=mm_xg8IO1bb4hZl@G`J(37CVi_qzp3Ha z$%Ea7Qwke^4=k2St<(!#87b6Bf;r^~Nm9-G8Yon{v=3EozkwA%ttKR`&WVmxZ-(!f z1Dr#p@lg`+19?7Ix_f!-zi$UKNB_%=x$Xoe#-cJW-&vx4~7YCXT=?0%_+no?9`HK%#2J1p? zF!VEsfrLfktGY6VayITaY==&dV{vBS4V6hI?Y`1noBPK@T?q?_8?m z?5;eR)MM91<^i3#1@id@M#&+=0ynExl+}ZiBYe;)3G!xdbrsB$uZ+}FYr<8I7Y7RY zeJX${qz3FE(QVtE)9+e7Lj=rt4me1~!vC(@0_))*6i!`1BUE=TppI zyLUcOM}(YbL>=99K9%{)YaPl6V9HlNVP$Q+Fy70ysrpejN%ms@XN_P(J`bDPQ%6;J@G)0p@P3` zOJiwgoERydNyff}PMx*Q-m+^%UzrK8P%%|NQFSiyz^2^X@-Oq@L3I`%7c0}vd{~U* zEjOhST!o_mrGpi*4FCPB`>l_I`xXmqBsW5j?>*EiDvoS_;6Z0Ef&G8#7*CPAi1}Q! zA5Pd*H$2ZaTdUJ9xYI-JbIcwQIwtPF5~EGKt>>7$pD@_mB**%X0D~?$Y#kjCbW|h zcD>&9&!oT0nH~DyCGJ65(LNp$WcLezBd(1KMiv(4&Y#enL%AeZwi7W30Q@>Roxcc% zcB7Qe$~|p59Ws9oGIvGEcB`O@#+6PJeGr?O9`uiN`V9gyz{K8O7xyFj8M_iXFP9s! z-0pMuavHv-ze0FJN&Iswiwm0h8WD}ys;KdF;rnyn(koC5X?gFb-;mh0pM(X){B3N8 zOp@#2RCfbipyw(w^?AB(9js%S67%jBMl(ITmLM;OVT! zqRoEERN6qY%EZHy5ws+oMJW0;$Vt|r3ip>WVSBY0g5@ztW(=+)=Cd zBjparGL}lvks=oKO{_2`f+!O}XekumfL)({-`-GgO09Q`&>*sk`P2kT)q_`M%COtt zHA9-~7*3A2IaEv3oh>^IUN*kK2s7rK9=+Pm4CFtah!8%7uPge;b|p0(_ZzN7ja_T~ zp-bUrQp*HLy&!Dd(b@L?I1dx)we;KLXtjhsX$2@LxrkDy;zfk`f5No5Vw*Vr-U2(* z(5D&-MEd*x9z9?IF@N2e4VC1~Jp~Umb+lK;s10Uaspxfhs7)Q)!zZq5%p01;6W!2} zDz<^Rqsr(2s9jo^KW+xqf4j4N-aX!3Ze4V=7LdtKJUUzTecMCYmE?zE9 zkLrMyS7mu&ym1?uPq%+Y$9a6tA4Pi&5#Ty+91oYiEbFYZg?7FA=3oJjs_0|FNG|ACy0|!|ns+MS}rf!tM7jS#_pAA;Fn|u(ylu7%n zhxFMTr?CQ7*Z&4{=v|lVRq}tE_6ca)CTkS7I5W)9VdqS;>g@NEq9;uf8823JA|W#! zMNZ97HiGFGz%KeCVhv@w&ufUhBeNGs-R;j5z*#U3l;+uo@@kL@_pL%r)9=WJ_eer) z!u0v8*N34)K&nqiX{_@#{SYpvtANDHg#`D4ph9>yP!s8g@4R;s4S@wefGj;p(3Yds zaA{JX@`&VzH7@&fS!5GTLFpY!TLl}c{iSi;u3J6;S)WY*ttvFBC0o51))Fe$G`{g* z+Vt@^eaI(;S!tkb1&pQTL~yCq4<|ClA1VsIoed3XI$uBvLRoIW|3O2Q0C}e#-5wzP z@9_jau&bGYR?SO0+*_S>s)|ZeR;NQn-EQlP*Mqfga)A7@G1pEv4lGt@q1pDB(rf@C zEHl*)cuZ-H<_(*MN64~-mopHwja&PmPM(BV8=Q?_L%Obf-1j{Pax#sSpyzB)%{;Rr;{%m}0eI#x$_S#7Du6E|bGf;tQtv z1~!Dl+bklY#q8JKT~odskIQ{7$SVchSss1E(bf_xdoEs!}F2Bkb=?oiM5Pk#qud6a94)6VD#kCl|J&zAee^SueRQM@SE=9kmJ!uh&q`e zWwr-nyqo=6W$zuzhq66;1PD0TL$PU)pQ~f#sFbHWoy1L@hFb~M2kRMJ^;leJlcmF- zX%MTlYN!*nnMf~;ivE7*0g)y3<-IB$c?v7q4xqs`=dC0#8Q#0iuDs9U5%47NeZ zV-={u-H)l&%C}R4=nVS&D`QV63D(DI83~~mhQIs88YGO;m5gjrTOjdQ>42m#cPp!6Xd%U}sc2A_w7Fq6Yn0DWT;TnbiG6Fw}5WhdZl#Ls)< zL1unU9dCzLmj-k0)dvm@RS}b~_M7kbVL~$N18F3v(*XL^D}w+em7eKn<`LijKBNC# z`QDR}=!I!%NOGPDA#?uDr>9{OPvtDey0q-|Z-lzdzNVlTd&TN`y*5@ zwnQ*}v5kzQ_)X6{!Bb7cs(u(&yeBk<(Fv^!&MeLM0Zqb?sZFyxyN2N*?c2g>#i03f zG18miUg!IxBn>##Ud!3p=lkr@R1gy%8X6U@x5`}^Em#kNj{9<(JE+IQeizNA5DNFb z+18WKFNBy+A&xTdy%4A7Tdxd|r%x&(pT5yyrq<%5HrKgO;(N1JCfGXc(Get1+V2xjW;uLf zr>NC=qJ!BhjtDF)l}?V%_u+iEKy0Np`?)p%05{8OtRHiBJUwWND-d*PXxaBq3p8t_FRb)36+3K%K)f8UwBmCa+?bb zn|*LO@tj%nS*jLho7$N^NfPkQqO9ce*Ty5aaqGx|TKS}+pg+$wHKE#X7Z>r(SU4>t@8-ySL zQ*nZPt#-VC9BysKx@kQc0Y=YNq7U}R;bA+W(x}Ulzei@J+J7`>x^bl;@n=wQPu+bL zJ;0Nr(D+5*;WdyD!fFrQ0zM_1oePgTQ<|w1w=XWmEj1tcbb}?0AF0I^{;5s&4kN#R zFE<160_ImQ3u}!n7Oq|d_N8TSuCA7~=C88&(iS4D;gK_!qKAtnX2xK_ljC8Rhd8sB zTsH;0cUmF)3kpoecdqXyexE>|8wfW>{Ye=_aV7`Yy9o?5Z$!Jw^;nEYgrCaL+ujJP z%+Kvuwn0V|={%lO#T57cG{S7?rC4T&P+x7Cj`McJVUzG91hLJ)OiuQQkRo7yz~$IO(kF__o+^@$ovdE-q;i-Qng-Q_EbfhEfoE^_ zQD=ENEK7D;RTW5E7>k-S8m}V2>`I9@H%iaG1fi~1AP*ll!36}`t;y#AXCrNt~%WwMwy_QSsWM*@x%O#*-( z-U9WQd2#kIL4rgB-C;zCKO{z-0ok91C81u_NuYYXNDMtvnN8(r5N`er1A}+#~9EG z@d)HIXX2p4@@!MXzgTMM$6#=84K{i9!=A$2flI<$)O-$0m4o&;Cx7!u*NgLEcJPQqKbm|x;wXd%E3iCh#xV9Zy_>gW%C@mSW*UGC_ zda2>tU86u*;+V={?dqT9YI?i#vSnZYTP183T8P(@RJSZ9PlMK_jq4;O`;?$@4M-Yr; zp~mh=VDWk|Ic1w@@hNh;-JObVrof?W;0stMXexH3_0-|9g#skMCom*a9Ql)ojGnvN zm>#ScFzSd4f;Q43yzP(rru@KvH>zVBH8<*&+^}4jJ2LV+?TGI5#Pxz>*Lgp;SA35{ z)zueFTtI8m{0+}{#~KT6CcdKdGvK@I_5r0#=lMC`8v;9H9}Jt8j<#FF{@TDQqf>kC zWuN3&V6E#H5rKXO3Hc6&eH1ENW^VbCg8it_e$zkhDCXBLw>f=`poO39md3g* zRP z@hVdl|NHV;CtCR(hE;idLH${+j`Q+P@=yt7vQ{N8ia!-Xi%nRQqn&ILyH)O>*{uXq z-HBdEFr6(vL;-Wrx$`dwaolhY#Q9}7gMgbcz%SW2=C4u*B?ljdK=T{vkFCh(gcy(| zuPUcJGl6>BYTp-93`uLdHNxzP5!B^TlefomZq*aow2)ieKIqF9*of#s+h25qgwPTj zg5un_S&6?N(->aE>R93SvKB{M;C6_#H7vS!u z@cdQ{ypl>mX0xQnC%uSXKB(zUFDywzH5Wks^|@U}M-rJ0z)L)i z6zk8}9|X0NlS>4!K_kN$jc@$!5evo=lsF!luIH5W`q^Op$68p9n{g+x=f^7Y=owOt zAJ(~tK$|rzR7O5cok3ULlLX|Rfm!dpTzhxZqT$a^OB-P2@`lQ^>BWk&PEFzbm<&4? z;$~KK9!w&Qa1*v`?sZ;#v)qU^*ZUUwn2u)4%7hgB`e!>W(tR2Q#vutzJ_n;|p*nH46{%8x5KLme_W< z-DVu81}w?C)`r7Ww+3|;UtoE%h0TB-T|^T`<@8j=TvHJ}YG=POQP#EtutK>7av;cp z&JVv#VNrp{TG$j-VTH2baEgnVoxDvD+nf(TzEJ4BS0oTZ&G zP@vR9a*j^m#wz^mXvz-)->HWX!}n8R{Em}#*1-n0U)nZq+kv{D6d(qZJ|QIDJM||j zNd(sY7Q#e0`6(6{amgt7GE!(M@AgaVf)^F1<}zv^NB)yufW;1IEDBE_3&QQy)*Vi8 zm#jhJ{y+Nd(?Na_xOGBP(rMGsD$tyVQF^K~lSQB`=ycO~HQI0*xy0GA@As3qo8oY= zGHc9iapHYN*TB8M!AP}uqzbB(xh$BJs-k^U3RQ*O$jal!MECpQ4zqQUuvH?A@OdV0 z@=Rut$5B|u`*BaEYjYSg@{Ne4Jx2z{ep;SiQbm5zdFW}V*jxrVjNA2S~H#rTCKv)$zyN_4l&jVx_$C!>ECfSsB6J&yeQVI&QN-F-}O-%|VLHNHu1meEfE0$2o9z zirNb|ZWSGt(U#fYPmOM@BC)o+n&%(Q;M1{Dw!6{XeL@1DXAkaVR)9pD#IgP!q7NwF z(Lbt&XHgVE(JFo0``d3W@3km(;UV$mWJSdg)!IP+GrT(JFT-K}gFg)2&z_+|o($GT zF{7+)?fiFIS@_%53i?SP-w^wzv7tg0_-cDZBdS;hr+HXYiCm2b!D_sYe}{*KB!Z

1u?L1|G#y1`m{?SPhr*0&?qM{iS1p3>dLr8tUCSQy|KOmipv~L{s zDbQ@@@dnQu-QIdy?^emAqS)i7e_u&R@MIhiUn!81Pn%P2Zm23+qLK`G(0B&RFM#!r z1(h71f*GOSKn*7r2Y-`-il)^g##N>o`JWYVIiYku2Km}caqjzGqZQR^?_WM%^TDYu z@nKEw{!k;fC1U>3aZ?76|6kCcz&TGpm*-DvnNNxvn_)eapy+MVQ(9b|Fgz2Hso$T@ zRS&4}=W(6~6~Y|CI7SMCjrHGF-dyebWXn{QP$`!TpxG&OaocVD*sEVX@C&=MzQMvm zT!SGZ_DYGN{k7tW-*TLs`6a@qOA-K9_PH9Wp~lI|>exepPqYMeA?V_Eu&p#RvJv+i zo_L+~nb?5aX{WC}{lU?P?@7hjCXs(79~+^x(>7oR>26Lx2NNIv_s;ZGWf~oulOy9B z>wc%i-#vb(qe5&+$%C^rw!`bnn1udoIa{#;Khpuh`V*fYbo}<9*S_-@hIy>Ui}?#e zl7g!qh?O&cSCG2w{^Cl~?}keG1*MhDN~X@c^?#iKyKSpgRsOtg zC8?)h+#Z#(?5Dl00?BVdSEGJA(LB!;rY2Xy$S*-k4|spZ(m}GEz{7Au3hW1GIq9!*-w8$83Oa_Oe z+{uZ>vN3}VW)8VF53)xRv9&Li2a^xCIyArMzXf|Ct2(H3V*JWZtcaPP`-mdc760LE z5CI>z6G3}(XLNnOt(#VrjSv!TH?V++x(0Se+y1x7upN#tJ3Hz18FkQ|@n}o~AD5Yp z(d5C^l_|dWLxP$Nkm-mBc6*4=GKdnd8s6{4z|9Rk;A2w$yP3!JnGNTiW6=r-usw7z zfn^wX9PYaKow>f@RiTyk0Y<#gILd3!@*r;FHbQZjs5E#@`FGB{sLTDwQ6l8pDr?); zT|@&VX<1&a95^nQ>m3XdsQ>;A{*Iobvc$qd4SyDD3`$Ze;vy92Q{L(2N^(ewLJvae!+h)E{RFzT2%k8W^P^*GAPo zJbBi+B#eIOi~|dKd{{jw*{Q3oO^e;>#9N$u zi?hHka@7K9oFfa0+5gvQ)|A5K0Z>w3q+TrKbce`LD_(W)a~FW{%|K8yHyM14?c?7?J5_ly*Yxp{0W?F#5dagVonW+i z3$Ahyrac~!=J+KI@N}^#263loSoHFohSMBMs*JKx_$8Q>b~38mC~j$Am-nU${(X6I zNfCO?0MLx-ZCnD?Eo$$-TZiznGC+5aqxu(6?WAb5zIM%Bj*H~O$EcT=kj}n{jeDCQ z?x9fK8!Kq0XgL9kgD)sr07lL5P(xS+r_hXL3GeA+Bh~geY2o5kbF!lu@AR z&)B<|25UG)Yd&7gplIeI=u{HkVS!|Y1aCD3YgGkz%CF*#jZ^bW%wh}pkBN=0OYmg< zSzlvu*M$of@Cl-!Zd@_3qA+ zu{vnVj8-AudZTMn*N6Y+1K7K2o}TMB&&a|sht_0nO#lrXczwNYz%qV9(IL@+YNAYk zPwi#5V7SxrdpeD-Q5u9=F0;o(Nhc&9=yzeXwYG5c+g;QJ2yRiGvy;n4PSUVs7B1>r znRAnCH?3}v8P`Tk7*!^)EG{mtW~_T{x1QVBltGf)e9e^m2wPHwi3xPiMO!oLT zWLEa;NZ2ID;B}mk4+mF>G7p~rB5WWK-nuxq0Ko4=_W!u-J&QJU#U%|*iB0E*?1-Ka z5dF?S8M9kU)BC6XzdHBgO^^EA+=2ozzr8BWz$kQ7U(6Zg_ZX%7 z^+c9JpCKwJDJW>{WXsniG6g<2)wzr4i8n(@DK8%{%LigA?`_`9uI@BMI&i3p%cfW2 zx!_2I-kTqL|rz?aHFh@4`j@2eyd_4=OaLQeEHxb1b^1OZf5z_0+as&YX2){g9tt*@d z`$+Ou?&=D_?1gXpPA271<%yftlF6TjqqzxwW8rxGMhN-C$GPzEU?__pHw7Qv5)E^4 zsqF{fZ+KVN4EboFrWCK29buXBJFMG%l<4)v{V?>Ur7H zJ3?o%OfLRTOz^9C1y<-L%3Rd$CAWU22eoEz3-S3 zzSm8J>9++Fz%79pp9Z}X1gwE1c+yqgdp|H2UJI~ef8RsTnEc74ig=%~f6#4o(-fCt z(ux(;KQqAf;x$!w9P@{S2gPN^cWmEr%S-+3%)x(j-3!j?NY9v%h3V$zHgKQVcNgNh zejrcj&%ix`j@&5CM)4AT#_$Y3Duu)u zj=iE_NAJ>zjdADZY=Uo{tNS4Op;57RH&DcjMEiqM`>is0e)s;{#s+KUwZvishg8$) z^3Y{r8Zo_4$8}W02_*EEatiTtGjh|Gz~+*&flv7^vMJqGcz9bn#=}Hky=yQt=vh|T z(ClpJARtING%Mu*46+15fSK*Pfi zZ^!+%CcV>IXKd?l3(vxsR0f~KQG5P@h?waVkdB+f`mJiLLaff{i!{%p7{yI@<^EM* z@7EnyUgNGw#0iu^>J*RltN9;i)g;+oubgllH$jqzT%EZJQ&?Aebw*2s{+?RbU)Y#- z5n}^?Cx4wM;i+bAJk&Iqf@xuPAvF2lKPlZ{7}4#iS3XZm^)2w8HFyxBzAlKo;GDht zq&BA~HfmK@euD5GCkcLgiNmv`<=%DPFnfP71S}8rk1R*lV1CijE&_D(khC0b!bc-L z=yXI7)Kaj}3Qll2G=qbEQIm=Ap%mLpd-W0Do<5I1Ws(LQ1?0vbDKEzPoDjwW;y#Q_ zauQCWB`;PzY3+EZdv)YMDx%(Wl6!sptlR&uX6}OYt;JV?9#VwGus;5z#cwAKtJ8ci zrUOoMuANK%@M#u7c%m02z{`2=MT$QT;@w_+vrVHiE?yw^YlU+6^xCP0-Mtg|`-F2* zEi8d;6|&#egd{dh+>kPp)cjoZ5L0)w;IdYYQ5nZ;Q}^S6_0uqvOe|N!45r%a_{Rg5 zhkBTrT9j>~KC=PV#yf=Xd;Z!PfxIDY!%Ruy^709>sk-W#K&mSMVG$Y7LD?RlwC(RNWJG8mjE-|PQC*s=kcA}O3kHh>lLwIv z-I`QJi-xaUOh#4$gJtnkzKeqK{7cwcb~W@8wGfeDTu{KqWyUBPo{{E$q;xirMQpt$ zt#4gHHNnNEGlxY;W|#0dN{)-UN>EopWrfAVzkDK{+oWg_RA^P>Ac~c7a)mm=?yCW} z$_hX$&}PSiI%e^eUnAB2X5_DfmqFoI@aNcFB()6uI~#s)=x(_CjV@~4Jx~*w(8T|K zSsq8Bu?7OxDg$KBp9DI+=OLyKhl=)b6?!Jq!%1Fv9o_wqFgedZI)R*dGEu&VPD6nu zDgM5xCsF`rGH#Q~oa~9};i-xV7a*#knDG5Mo0AKV|;558f|Br^} zsh#lg<2r}vqiRU#efMb#*;g4dD+`gAY#vQSXj{bQ+Y=djX3!=aYg5bpD&kU<1^zL$ zLHJ}5jqBj}s!2w(gk0U|^OEUL$fzfHN6Xr85xgezBW)X( z;un6U;8fG;Y|*ksRyH+h3>VBLV4_v=ih&R5BVrBCXPng8Q&|TF63oj3v1Ehp)x-vk zXH&sgTnYy8^o11!kV7NRVe&}9UHVky8$@B(5Kh2@iA;__IV7Eu*bEkd%fk3fdFYga zke$gB?6U+lS#gp2)>6{=l5936LzMWGdLo+NyV%lddML9xYxb7JU9^|sWDw`cBzinN z#RgH>-^gmjF!hjPUH*H4vvvLJYUk3G|H+LfqLjeiRf@C3n44Xvx zuavT*`TXfAY&Y{Sd*6NiknGDUA4i%U9}^RZJI(C3F2J|*jGG)!FQaz@FTKFa>aK1{ zaeKijXfWcvDug-DyD%q3{@U)eW2-xKMp}b!V|tb9jGFV@LjhWW+i2RiGY_l?sW0oG%o7tcPxd#o0R z>Tu0-aXrph-WyRS(ObdcHrk#17bU> z;ATF+Gq7h90UIbo4$#mOT*it2+;>Vo$6k)oHN*U+eoAri)Ct;WWvZz~D>CdM%9@g= zfK#Yj%#yrpiVi<3>=D4645EZ_$8yOynI^oM7|1WkE1v|K0P8FmgFpoE5qZ8-12&H7`_OhNLe~ABWW=BaOPg*UWe!;7 zqqU@QLFYab?0FP@6GUK1J-fEgJm>Mp+e=@F=ehyxqbba*SN3c9C5w$ffaEmUt`OeK zz{Q4?cF|uN*=&{9q+a>P5^hh)UmhM$XDdlov`c@8<*CV;p6Ao=ZZtLiP!I28Qn4Kp z8^hCpXHUEv!IM?fJi9!1WK0mR-*Z80rak=R*ym6j#-^qWqKH#g*3&~JcI5Dq$G3yW z$AJJOuRq%`CLD3#`AQgg8a<*1e*Nj43Pwb58-!oR&uK1+FqH-`1L*By41sJi6HzvY zp6h%u`ge<>NGUx`dcvzJaOpTns{kJx?r)&Msk}f!1<8Wi(!a~%M58~Jimcc=o{RDj zvpU{-qF^7u-o^kuYmE|fJJ^mrx&9yN*v^fx5?b@mInY<=xl}mMjKb#_N}v}_NP@hv zAM5^ghCMjNV*8A3J<1UZr$HA25QB3Bi=m8?=Ga&!s8=dS?=pJ)? zN(Jl&?LDv@sS_ycLs}>gzFg9^XdD5hgCLJjZCJM4b2=%>*hol2n>Xu%q#HPvMnLuR zkH~g%V?#pu4zq&`7$hiKMf)pz*y#w+IP&Y;zrLV?*86XI*>JqmDC~M@gi#V=Vvo?cZ&(LyqzmmOKWU&@#-* zQ;dx(C_9%_esHegx~w{)hZE9PeO}27e|q}2a$TR0kn^!{rk-?NuR%%8q-B4nDMMMW zl6w2wBxaNMo42GBvh@f_IA@50eJr^Z1%O~u+)CLh9>pUeoGzaBXL!O-Gs;P6rgfSUjhsfDz-k1uc+M71}vG>#9yS>L1cy&YdywthK|Z3xTQ#rP??s)m>#4Mpq{=c zm?W-RmyUgR4I69}$I*2Nv_s3is-jxe#K(^cs;ELg$VjT11PAD3n}*rbJa9OqxqOh& z|I+GLZu}oRJ3b%Lk57NMSn@x+$AEk%q&v$ZBWs7g-H>XKmD1i|ouVEo$MT;-(oS(jy-BkUZsV#$i7kCS^K(|T zfBmxbe0#OaYS(hrzy%Q|iok?6GC_>z!QoU-wPf?UeQhk@ds zU>o!Wa%`g=6W($iS5f#AMm6W&8I=tOTYkhEG-c{ntd?J244Uy6l!8;sb2?$>0m06 z25C&G3e?0-4L1hyDa1?_8YzwdQNj1(8vnszZHR7KB_7n0@E+5C&@Q)QNoElLtrHbd z&r&#|eJ>;)4wI+fgDe1rHT8!}v@bd(R5**gH4KiyaW5yl@SLz}JA}W>Gec;LMsjd& zDOx&;5&F;aUpjD+c@_dmBD$sY@CluXVDJr;Xn-2bSNPLO+nhmRGfu$>38S@9Kc@=q zq^mvH`BxjTRzSyOF$`x;4mzG!W_Jkxj%TL0Z6?_>n7+}YvMZb$`B7r9sutcxOs*tB zu&^CX%XJ42{ZSz1|28wE{{hcHFu%t?J^aJ(Jf{6me~0s!>IdAPUC{qIqDMjYmOlaj z6SN>~chibfr*@Sedk5=}2$Z0xNER9OX!@zV&|?Ik{a#KC(~?*bAjEwgv%Un)`nsE@ zlCz@t_{jRz+rHp@oxiP0OIyEuHFI9u2qG-Mcz$?g3OSHJHHT@x^oqK6Q+w~TmD`HG zS5v%T!R+{?q?)MkHI?DTN%6CiYT|2>;*%F7hiIWol9`>`t$d@yc0UIU0dp4e(2Bl3 z-%g;-X0Q?fuC7ctRh*RczynDThOQ{CAuPD2IDGIAfGSqbZ@3R;17gfCO^ z)#T_F8k?UYH0pj1cxJREwS`Cd74}2YL6+7asFdMK9Kiyg#Hy1S;Rp;ltCH9Q>!}J_ zy=b~vm)7Z0)jFpj2p09CQ%EIT*P^N}r<&$WCF`y3CZWYz+vIMlb?XERn`W|@2q{eM z6;xHSP!$$xvC$F|WmZ^v1Q}b%>*hDm!dyMH0mhELJa$hIXw(_IDxU2y4JdbOQx$3}6Q=p{G>P4ZJxJn#RsaGV63+sjI6?b=Gyd zOlcR@R0lb8Q(ameImfhAr-@tyOPa~qS$DC{;e6!HYmH9qyc;Q`0ypkST7&vakjnEk-hsIf2}9h;fEjo zyD{LW%)o&A3$Wk?sNCo1gr$gT`i$I@kDQFl4c{#hR0YZgav_mD7!wzFGBGhR@0du| zF=1MW4I-+>?xsMCB0J3li=y3QY%@>ufy{T!smfF7M^C}i8IjKB2qvs(gq$a# zsrr6s{cGeU@%5(~XTgOz>=;UBVh2~vs)>q9s#&Q$Xa98Oq8xZY$rc#6m^O%IRxecqXm;Xq|{&Lm4R z(fRny@5944m!~2G`w0Lq>HyrGqQDS>ern;L2S zzVTV)naI!H;QSaWokR=2wCS_Ry!mI2MnE0#`ogiYqLHz&334BwAY*KNd}3sLB8t2i z9~m3DS~xK_F)?S(k~xK27tdKdXX}B9iIItfdt^g0#>XZ$N>_LkUqc#NM_>`8&;m^b z)8>Pirsc6DcM6A*E9TzG zT6Qnu`b4$y~SQ;U6Sl7jZzX{XBUm*dF)^N!E<^2t#qW-g8{&xW|GGP3y-xA1W z7F>fmU{*@4$&H&|aw@N6LtIQb*4YwJCaiVS=G>DTB6mg3CF?^a^ny-;dRJpcU!W`q z^;b}ftJIg)_ji2y%dF#>`nYS^PyIs3o-BGy!gkm+a6-wO*{u_|-pLpT3))-JgX z=C&(?nUDS@DQ4EedTyu$$m_d~tf^!4+#BAkS+qF?EEv4;@$u9h|(kO5Nn!41@u{ zbT{>IaZN~kOUuGc=E&Ux^fD!kR`fkNayE6v({mPVbM5`1>Cw^5hf->^;Y`oY17{I{ zJ0{Jb`%7&;Z+lT|HS;0 ziD%YJ7=y;#r7G2x#Oy1XUve^T-*O)-ZPc`@QBf076BC6KS0`_US0^T}l9h!~69ZaV zA$fOTarJOv#n?pQfsl!)sIk%6A!QTrO=DV!$eMU7)fzQeq0rX~+GorKQ^O3X0n%Fo z@!?7FvwqSu8Uxk{zj|tig?KEO*wjETU}(kw3|Qby*FI)jP+5hEUZA-KYBY&JOQ0TE za6r+echp(T$bGGl2R3UOnKO)(k?91PYK(ntjE_Z4kbhK|evq%IF>+?~nnaQL$e+if zV5O#g!AL#j^G=?ef8s>qvfYwj4QQVU{&GhnPt05Uiw_eM%Q=Z$WLqEx9ViFJ;_P4@ zaBu_x_`ec>hgUy6{pBo%{L?bC>5F$6Sk7iB9&h|oi+VRCN=yFo|1SVMh#}|>5bx4h zYC*v@V8F6kllykw7&+|W;uC8xmqW-@gvLW@;V~OdT_x1v>gE%VT;5G!HcU%kC0`q@ zIwD)y^V?`iu&uQJR%yqlcZc3Pe*A-@&xA1ybFq43@`_jvC0KrmIX})uM<2>sl5<5n z+b8)w9j)q2!hn;)!_$+KpH3Q&53hK7b}~WF83cX_8I4a)POga?NhS=~UR&T6r!v5z zB4Iw5Oc44?Z^26Yo7TZq;QV_ms-h<0f#Uaz$!;p*qksZmVmOg`MvG=pIc+Ef=Po19 ziLWO(S8dEWoMUMjtY(f3Wu_z%IQk^^g#*xxA!}P$&NIh*pFO}<4INIMv*tkA+1A&e z{i=($V(7r|L4SUuXzMo1lGlqRz)Hq-R&);CBMewv9=G=G$j#ximR(x=yrsrkK}ZXCqpb zYX$#iE2eBAIL#ZZ)IQQm4K*Mb4e@9z%B6rQ+ad%js|EyEPzMZUNWF%3J|Nq|&1h#~ zh%p2BHc(GXL}O&wv{(sXUC?_RT4B4OnoJi{$f}LYit@q@_sh zrZkgaN~^0QYa$}*aG1!gPF1;CS{PGT68GZ`C3){(nhXC59F0Cls2qD{-fJJt3y;|q z`IF11&Pfq$pdBG<;~*{oEt{HyUeLi21mOQd0N%)~TTTa}?(*fZZXIk7QqQiY|F3&R9AhdzamfU{RDpvwNGl=0oT^i znoJdhSKH*U&;+Ui_ne!92rv5(gf(~FX&JQpa-Bj8E@ozUW;HsRe6*DRbb54q% zb1J^(RB>f`Qbp34hr-q|VHzRGz?*NCLc`)VUK00=nKEO;T#MW-qtRltR#&%vbyahZ z|JlU=!0c+3?Nr5Q3#BS8T3xR`6uV7)eRM|`q|PZ>h592&uCJF-6Go;4_KXbKFJTB; zbj56#`^nf4OlU5>_M5yOl$m=Kscv7~+Hf+_86KWhax(Y#J+coNFo>V;=YTVy3<+t} z(ASJO(DFeipcxe;gBuznq+_}BfBxF$F>N?%U*z0n>!m=|k;3kq7g}C3JUluaQZjem zQRc9=O5|9Mg(l0529LcJY_qMkUb~UyoJLN1T61!OwaMG+ZEX^CI!|kBtC3|GNp7`E z9LJ<;OPVYkYXK8XYzpBKcpVSjiU4{IIvrN`@>6~odRl2j(H1L@tW$C6fFl;|;cMbj zg+TrndIB3klVu`IA2nWqu1Bbb)+5U{U{0ATo`4z)urr-bFX#i3Fa+Q>7F@yY4BL(^ zrJEE~1ahesu1Ct$K41iqTm+F}nLaS$kRtG1I>=0Vy>C~^&)3c%{|y5nCw?6FnHXpX ztoY6(&Q1It{4b2}I}x``;@B%jE7ky816g364Ckt#7j$q00rw@LW*S|yXSc^(t!F;(q0>OFxaxM9dFO!R}GXGk6)P*YWs!*yu>e*PU()vOT)A@V&gebbFYS`lQ7T`# zo8lV!Ud-mo6$|3SyiqpY}qp8$(UuX>#x86zI zHvkrc6IKedU7JX%DNc%yuS`m>h>uSRkB@(#CMkZ&P#FQ>Oa`o}yoP=_Vx3urZb*!5 zZ0f50f%cqzCt*H-(9D&Y)yxG#mt|Rzq$@Kg2mtSu!1z-1zCQ5NrY$sD+~2XKAL@Vk z>k7of{W5vT*dddXd~_(GPU<_ASdui^54dFQjNNF4MSwc;@`lMi!BO*1{-#_)2Ha8F z|J5`A?u9a>3CICYHDfTL3L3l5QoaRcxi*DOjJve&Pl2B^|D!yb{#9A2{Qi1v*`@Gb zf1&M_)d(fCvhr7zv9&EJm8(`Qj&03a9NjCYIW4R&UaMkVo)fuCB`Lgd z!M`s^S+#YMjg>ZOOFViDORy2NMmn9&?6UAWptw3PrldEh9RiV-o+2(}d7(f@4<=St zJ=F?N=5hs$KMr@w@KI{&`uz!zYWV@q3sTh)zWa#7z z`PvJGcLxbExV!LP#qmB7x*^$S?yu6WZjN8Dam|_q`=2Jrxh6TeIC(*3Wjc92J3f8( zpUM|kGCL2jhVH(v_hAU2u_ybM0tZsxO8|I}HX0wF^gw+4sWtJZ;vdK(J9!|fc=Lpo zq=ad)3{>UHUv*d&XdKZdKCUf%Vf*%HAAfdG`=$7Sc5lz)bN1}n^8!KY3z}9oGE!DH zSfp)ds>qAM5$M*W-MbE_N!Y5sKfCmnjgjlS6*y;zh07TPizQaN`Im81YgXKgQ$5|a zt0gfptO!0Q;-;7l;Zy5F*5<~X6R`}b|7#4`)fYB%S`PTngaJ2#6BhOT2LRR~2ewH| zFVEdKwZA)aOTO@73fRAC-`rjIe{UrxLe~KRvp)J)n3IVQnNDp$8}H-@0CNO)IA`q~ zZQ$OhwzAe$HhNDBaZu0H$Bj0rQ(NK|c(R>IK*_Ub$2pS&`y$ZbGo*X1w0)7@I@v-{ zk6GY=2{a~v(f`T-u2obv-N36;R+Q~%MahB{rP+YSli>brZJ0!2{gj;A%0s(g_(=vd z%4$H@4hU1Xm~(@16z@*-^k6N_sL>*$~M;W~_KLHIs`lRg>! z;?mrC_pjZF56?&{dn1D7xc5)YzrTLj+ldd!Cd~UbV1o*%spbV<*St8G0}hTL0RLA3 z@bE+h^W~QWZ@=6GncWr4a!p(QF8MTF7svq@&mM-1aL8_MD0G4fUNC=+Jc^q*|d?sKj1 zx#hHZkF=e z>!|LTr)gW-LwFK~0bdPnF4d~2D8dp@1x=l>47A1WM5}=n*5gSCT z7lJ$OKJV}MoFLepnceFeXWDnKJW0+uIVU9H1ad$3@8iA^fMeadD)Q>R4{PBaOJ9=M zigSJ40x($w;JxH9YmX({-n^*`^l?%ViQG9>$WSdxDWZ6B^qjXRO-A=MRtGVw9$Znn zZ_;<^$ja9%BpuBO&>XO!<}L7>S&nu8IGh6xk1zoL)k4r@EkpV4tm;`q3{zdPqM>5uAA8FC@23q;<@bljUognAAT|ac8(n4JOqO1XJ9w~h z`t+irnrYK!6xF01oR8Dj znk4z*w5(gJqWNDx%4eJAq82o|LpVwKJlAiYZ=CdTpI;MK$7nH9J$rxYq`6#7Qg$T* zaDnS1Z>FpVjn}!|vJw`2i%-e{TX=y=VNgp1B*6-U?MUPEQDh>y5fl9~i#iglt#ba> zN&Bx=M(>$c7z7p90V=vnUbfWkW-?N-pi9y-L&$i5Hw2CmHK8 z0syCrT{B6+&HSv7>-O4;$c>nIDFs8&m;=rtd7?R%yjxt}Tv3JMdD$h$mnqXeK-dk9$^6f>jCha zj9h|s24Hvi%UJ-xd2m}=As_o}`7EXa%dlpWh%cG7F=Xk|SrrwZz4^xhcrXmWe>ni3 zM$13u)6w7LZXZd0U{h^rX=7t)LPAnPX>IBA3+C^yyiW4jNYYNT){35!sD$O$iv4rd zsMU;oR)gBj9!I~XAFdir7cOvwR=8#N*n#?LG**upE*fBpCY4GncVhWv{1rJsVCK`I za=j~OHhRsZ$nZ#cRCctaK`rPq3c$3u%UgEZqUoMGb?SfIVMplf zz?x!(+zH%9`;d%WN$I|*$zZYIn9?1{e|8fHln2ashjP z02C=rZBx(dKC|JYP$e`qC{ok3EG?b_o=S_CX;ri!ho}`63uiI0z<|fi7_b@|m9X@3 zCzDF<9#-R1sMNI38Ed#`CAFF=fP_qzs1FmoCAW#y9wLdnfI(*X_0vK@bltS;$#0T) zP0ur|4H<9-_WP2tL$nK=G#8Ql2vX0`hF`I`YRY>_lfiRSLWP7~NYd|DzBl=QxN*sB zEdnt8Ffa(vCIIW#^E<;@(BTmV;J+dO4}Zyg7Eu)O<}{i@LI8eXh0KCumNqaezMRR# z$h}ElJ zRL-WxO^@djGDCclv@=+(rFCU$f_|DtHlOSP&Z0)6Cu&zDs88}IVXZ!i>(Z0<>qkvY?c90TXN8u@+AZYPJn!u1w@!MGBm3f}U@Nes zeSH5Uz`QmL3|KNh0t^`I(dAa)va+K9z&jV-kpre?3<4H7waIS0uoR3MuI1pV(mzZ9 z?c33nZX3YtCw=d{wCU}Mm;uW~D*^ z;A8!T!#lQ-8mlqgU??ai8?Dx4azW$f-1bOP>{n6*HUhw(GZ=IRgIlAspEJ;EW!l`U zQd@XA{;Z;%NVtW8X=)EFI}lR9G*Sn_Hig2{&32eL!DwTT387wKss;TTPuqsoD!Bx@ zEkhrQSyQnMT0TuhqGdN=UUmzH4IRg_QVU6>A?W4{MVKA^t zV8F3VJGohy7OU$Ux!#=hd}lK5y+?PLc0 z-s`g@)_}?1P)=Ts#E0FG!Xpg8e^mf3QikG@w*eTte;Jrg$5bqZt>tHC%DqV>f+5qC z%x9lfRLuIL08ERp2LF~tSkw==Dc5K1?6h8STyDyB^(V>X3 zBreXLR5V1ko_I&!*+C+x@x13^SEvpd=$p4cq>3d{MPwSH#fl^`$clb-*?_loplrb9 z^7(vvyG96#e!feTRAuJZNV4pGAX^a8@a{zLSE8|AjuC%6#t!@gyd|5H6{-BjxbuUE z0Boi*Am;{?waKfduPsh1t|=Z$#wR#@t!9W!-He|Z^CXF9{E}Amw`F>y;CLAqtr`ni zJmC8dU1Tjz3@%GrEo|AGHrN0Fm9&1p9~Y9}kH%5xEGS9Zqep2aG(6m--$HH*uAl5L zosh+aEm0+?UgniBIEFkr4`kYyx;1BfjX@brA~ zu$V#)OWj6V1A_I9Rw1 zJheSCQmIL*QH5DvHI>0?lPw!){#QZUgRx{wEpy>EtQt0P2#Wx|%3~Vp6L<{$fDvhh zwvfr8Eb{?$8UdU}ud&%!mi3^qZY;s(`Hu`rRa$+N(jKHIw?gIPI+(Nq|a!0W!z$k7D2y}bZW+= zf2VzCA7^xQI;5bPU^I|Y391W`;XdH-2m|n64}kNSx-(yr;XLL`G7i8o%$sXv?Tz08 z0K=g(a?$f|nUV7iD`w96Qvm$8Z$rW==*t7XE7mK%E1kWn%b&ZN_|a=SC2scF+NkmG zjPs{{T8Ujqz!TZVg!wTOIFj@eGZRT>C`Fstf7B&om=^5~2SP>3egs8|j0lvUP%i?} zukgAuz23}BSCiFeVKfBGPlJz=o$f-MwF#S54lNTAVIr7dN@a|Y( zz?fD=vjiZ*g6s=u3RGqvkD5S>gSER*r5J#A&)HKs_uM`ZwdUm&|BrtoA&&7rU{!9f)n_mnu5{+QfC0~&I+P`e zd*Wu4%A{>L?!>80J)z_#vp8;l`7WWWPD{U_#P(8T3%pn(TKZ z3_-u@@?OsEy<+6sF1KZVRCXG*pzlz^n)+SCp$;AuFfa*hlGK{ve8%TjQ;MyoKEU`y z?kGfdVNmPjnMv>m1hr1N&{`jMg-Q- z0`)dt&pSgQ=0$>kEc#7YyJR+-I?WoBU(%|2(8|c9QuTCLx&Zp@8oS*N0O;}b8(-aPfepB4=rX`i zbQ$>#LaWLYa@G~;RSLZt0j_bG|3$q^(WP){FazA>!-X0VxJx~tc6F&?sg`%*;BhfcLU3OIy9z}#GP?JU6K?tI6QKG?Shrrzw3kJT9~#pZHU@mx^|ch4iCp{eLg$x zh!g|{{Aycfrtga9L#Ib^`Eq92=^hhxLs~Q`1Z~GQB*ADrW&rxDRtwk$EVx-|O7^}v zAr3tKc+$sGDs}#KOM9|cPRXHAKRo@>_hvH{WF3-Y9q(pSyLp8};dVO(g+tI--R^Dy z8SqZY?NmDif!Amh3bRJ=IgCc$=MYeNxqk(z@$kHzs$3e428Ds@fxsL<#p{$N0}3&Z z7e73iTo2E&$3j}rv<->V=~XI)8edmMt%tD$ zn$}%ody-s*)y9u|70SC1=k1)XySv9pA_P1!Y`2ruS!_WY$MU8==@2Wq5r9qgzUN;{Np ztX=u@w^vB4L4oocm;qKeb%4g|kPt_h0f$Ezfd4uG{3W1i5q_^to3*qK{!3@(#r!tn zw?%l3A$b*Fl9_cFZXV8q<;?RVONYtu%)AOYC;ZIfo;+aHzn?PK;R3?!ZS@Xh zB6GGLHT1pckXftj!4N{>Pzc&$(P;gC&+a>B8}xd|Xcx79K#|LWRt}SE^}G~%d$&W; zzmAscV#N?EElyZ6WzNCr(;K57 zo%6DrX(x{{5+j*3urPScRAeyKdaQ16dI`JvDcX8bOzw+5srSWB(Qs! zU>8bFY6aR>CQ4l%*d0&m88``CmkG`Xs%<)?XdXbY)U6LjU-%nYCD-1dqg(A67D4X=(Wq(qg|>%~Snk zzZmT4*}ywAKs*(cdMY#;hq|k0o)1WI7xGb{m|ZRf-*fS_WOLsRaR;dp62cw@;0|d6 zuV`)E^7JoX{UwZ7VHCUy+pj+T%Vkx0zkGEg?EL3n7R+sJb<7pm({}2lBx*07ymR6Z z{I9czKeL1Gq}5yqz_x%GG|km>u)|4i>M--YXUUS`NpAD@-6BfTEBwtaVLdJI{XUZ0*GTaaF`qxs2<_`O*faM_W*_eWW< z?x-gku z50lC&4OA2q7_d)p_UVo()Pi2<4)+0vM;L(b;`qgbcRNY@odh-M`^%rsTqW+}*q*{%;RBG(pQMby0+b-CU&2!-;KGAq+LU+8h8DCXn*J|Zg zm;E3lo7p3nk$h8w2ufEGgOQo~5rFmf47Eei<>>EsIJ){B{SFsw;OOs!m(!cA^4*gz zpF?lxIW3nxYcJ|?squOGJr245w_l_2z^&iY-|sQQllAw*67KY4^gOiJ(~p}dh-K>c zm^^k9HV2#S8oOD8wn)IWB1xhfAz9=WS8j?*T2i@K0_siU@t(3KS5vS4C)2az5~6Z; zosojtaXUiq=e?aih0p49HF@V+WIMu1eZcRY6D(*3s1TfjB2)#f=4Gzivg@6k=-Dq< zpzp5?zSKlsVi#BDLI);vV`>uwJyvRkUcqj#r`-HYf73$&x5PdAa${1|rkD3f9G%fn z%CBT?(p$Tt8@Db&lVuD5q@W&(fYEr3(I{XkG|xvChWmiSBMiWIZ+!2;f4a-h_)iah z6OF&)IbfB`mr=&YBU3jjPyc8NBWGuC2^)tcLs2>?tvUr_GT31K6!H2`47Ie2XY zg9dz}xi!<}bUpPzgqsa|<7- z&?w2Mf;oY+TVXUJ0XE90^nN$((LsDN;z9!#g~0^a<>^Urs(6#T#lXudSb`Bl(9Z~H ziUbT<0fbp4i*C?PUz%4&6qYG4ZBwEaNs16DM##t7u&nx6p!wVIy6shTyRwIvm2YkY1NwzZBMW=}YVL@?vMTvvgV$XlZD`Gf3~bLxxD0B<5OL zTKXg#H7GN!@WJohWki2)~TW}7)^Ho-z`ve~pYlmFNd2I*j!$}(M<4jO+} zV@{WuxU!sxw@LDijNHCM*Gx#vk@_~s4NKym8UN)VbGr{n&H>|HZ4d=95P~&6FVMV;7mv0g?^F9=C^WcKsaw5UhHkbXVA)WAgL?7$^{B%rnqg?Q9=oK%4~uXs*ChfQ6SbswmhCa_cc5Fnvl>=*pT*I@IOh5P=OQ*|y%z-Z>`Sw@vIc z8QmeDJahA%?Lr4NiTMfD_|m zsbLb;qtvn87BdL8NR6%=0_LN?73$2H?Amz;|_gBlvqe2V4f<@=Y}Q+=RZs z^A=(b7}cyz@0Q&Q6R&Q6(e=xPiHV5_z`I8mZtT&m zUwGia!usz{9oxSB)~#aU|T{Oz3k!d{Vk%M6g;KJb|Y8EvJI|*j%Ah)mp%2!x(r7vHX(&#)B~X#2Bu*{MMW%o20Dhy zH>lOE3WwUK!D2FO7w&Sn)F5;yRkR^EWHub~ zVUkS_X+JO;Gw@W9(rLlB<`mf10DxH~!Z1ZlY(p~O39#7VhC90jv|ykN7uLvpQ}KT4 zB&1c!vzgG$LCH?W=Trl{4YgX9=T^|lI6kZe9Ufr-zT0Eud%w7A==+QBm47q8#Lzec zb|KwrLIlQq?}deAm&5`!(*~)mBEo`S3`!GXjVQV3N9u+=kU2(Xm_*TD21p^tpIcio zPOB;N4h-l|pL7iXD8UUbsss5M8SBgW4;Q6nSgLMht&@B&%3qW}STS=KUAkTsMR zADm@6m2k$JEJvz*l$EK44i3nnEIC zBZi=rGCHKXO`*gulD5=P#FQO}U^#w@w-k#BkyjxIu%fO?7~bWLZY+Y5vznOd1>{r< z6y{NP8qt)BS0RQP401vjmxho!v=SvMVSL2j9<*nd7X&p-8`MUs9mxYcg-WL~`he>y zIo8mD`0Mmwlp1@Sju{YuUkf3xjIcaS2!|A>QSr)1JAp&)4n`V_Zkwb2AmYo|v(nM8$^GW;qh@q7a< z6T`-AHO^4l+7w|193Ei+4v#;R1J7Kf#_NiT1CK z=V7VZq6iF_Wq|)SWzzVwtyP8S=JR^{O*Wbq)ndz$4Q~gwv)YFfwJ#7m!)SLWcaV05 zVPc7n@$ar;n2oUUa19b{+O{MwC9OYn7oWhSwfRFw%(SiwW5qwZ@jm{r6Q77d0B&ZO z`t**g>9TpCZBZ<&g8op{SfXwTqFg>rYr3`bF5Zqm`x%ek>>R9rl5At7sl_49taNc< z5l0i%%#TPUgNyGDnV8_B2&zua+@VJ)uR;ezj`@__!VrBx8_FkBy~?1Us&Zn+8Rt24 zx`QlOvSAMR#oWx>{Fml{&E5HT^Z`$O*NtvSfR+L>U>fj520VeVNP(3hD8ZXsE`?^< zPh{{_VhWZG8Z0cQOhJAN08I501=NyIDOk=VXjmJ^83a_9l%*AEi7#b%a4{N@bMnCR zcnYeRamChK9+Sgvok3^P>FgeZ$*sdOX%h?#QkzU{=;p@ku!#aRDvk3-FNZU}ZaL7v z8gOEQBGuFq3Ev6Nj|*{xzi`4M48Y;>^&If-4JxlIQ&r}oQRt?o-V3w}8cUp0UU|9k zoytd9fC|i>+Jabr6cicvuF55|D|c!|TIlo;nc>zR^=5jzXa*ELaYeDK%&YmYl~fOt z(Wzvcw7UonF+a?YC3^rMBX2Bcf(vIe;$zoXW@C-?KagR*vjpo$LxtN8U#($chtht$ z83CBAk99N7tIy3kT$Lp<=gOBd+K^Tjt?u%N%B+L((`n~n|F2n&KQq>&8s^->^(0Me z_8hoXpZ?uulYir_%`t+%-(&XJ{X2#;%*cSB9?o$7XsD(idyw#AGMmkvubrm0KiS&OxX)b2HPS# zz>EH4>cUuEN(XOL3vyIgX0C#YCM{W33ZRHFHsxaCHF!u9+-mBVc@w6jl<*d_&g4J@%fMw8$(fP%+IP3 z_l&H~z<-39V>!e7jNBqDb4J8fR%xT_XW%X31}B3Zz#3wGiaVe~6C=Q19uBzYx!Dwf zdrdEQ`BFQ=HrezS&6cQ)R-4?>gvXE$Q_CgUELfJI=1oe$>267FaXM3V-8!W^HKqGd zsyo%Bbi>QF91`40+}$FaYk3VH)8c-u<+YO6Qr#^rCGfCRcrSRq0#c9*ND}8}$1}g7 z3akJJCsmRKNss}fu@h2YDlTGF^R25N3p3#G2m^3<{0RnZDa*`smCd8*i-G71SOv|( zcS>bkc0y7@LiW~2B>-fgzqTOIHIcm(mwh%NA>r&MfKMAT;E1kPuQybGg+0BZs4k;+ zNR!BH5CEw2;j8sK*4K3Gt^r~z{xESP*(qWlaTa4cP$-Enl(&c*x3dy;7os8^p~B+O zHg+EQ<&}J+ddq(1$)TGyL**&V#-ZXu3c&H}hi~otbW!3{>!&p{;p7|snPa=luO@DBwLLO4y71OhuHN1slfCAF%P#dmYwo`;deN1;V`xjk zRYGoT-_V52--{R5Wfu-F4H}0=*->3Ud}!!q3u=flw#9il2OHmcv?Zh+67(Ylh6znW zU3AXD*;861$p+};IY9R2dNBzc3PB?S{#qaK)Yx+vg2p_mqD^5GFbJ&{css^KgWR4= z(K)j#-(V#<_bb<4xjCt!0$!(bd8!0hc&KP(BxdaVSmODZv9Wv{F=J_I`89=U`D6KG zV=?(PaPa0>3_NHIwqTi9oK{$vR=5rqg`3wE_yBJO3jbK0j3|s^8w!j<>wyE?lr|1? zseqw7hjq(rSj2K3c*SP zzDE_zOl1127GMJ447(wPM;L&^cr1ZBqU4`X_fExi)CKqzkrP@tbg{aW&Z1HJvxBNT1?|& zpKRMB-!c2QkY$ft+tA=qM)Mexy35zqrFN*h1~hs#re-x=@C=#(je0Kf-%h=P(&GM$8b&f-7+rR3^rr91 z!tEN5&uaB`K0PXQI(!b7V!*m%aIXViG2`j$ukPKe2cT>{P0w7DD>t{d7i0J`bEQC> zdDIY~RnUN}Ov)44ar=|@C&k58q7WDsSc^fJh)9(QXJJBfHal(#PILmE?ZAKmdubS2 z24JTtYd!rIAEFGHYC)%Ts8N=gRx)87Q=6hqK*}rbIhd4`RJ$N4VaXneO?As`&F$8v zPDz@-X+cuy5`bn_svu-!c=-Cr@L>7K$jzI>!y~XRAGtYP4vU*3BQQT3fd{~TxD3K= z_{K%SPMEl!T=l|e}Vz;*7KQ7E?NeiOBpb&f)26=@2Sn1 zF$mwlA8buJTge2m#TD?^Jw1CtPQ=K_`G_a>?azKx1OOgNyf`5HA8GY8{;cqNH9$5s zWnQeC!ZK#yjz{(0dApxmw(Qx#jEwSIuWos^Jj3zSje@xw$+9k&YT>e%urOq7?&t2W7y@;w?!T`WPKfg&m>S&zSQ>~32br-E(*7#}sndXQ4 z^$y0b$-OXI;NP)m-Im>H4xf-=v35Q^RnT;K96p!N@!_InR_hDp>W$a+RzO{s%Dce@ zD}dkJUaQsGOHX1Z_VMDi%n+0!kpTzAJyB&$eIP?S2|#n=#>Nzj3&Z7 zZ3V^(EXstjW(;ey@Q9H@ut0s0WOHEG9|PbUWavidLec_t@UH+c4AYE>%fywCe_@Vn zjoY_x$??kQIr|fKNw?3bt*2+1V?ffc@79 z`68lre!}}A0Pw91s6Q!*S~>r#C`0@e)kjM#lw4juw$ua*w0|UPL8*dL)%5ooKLv`Fz$YDVqokwZ- z9B>%kw`ag%xw^OW$_wP#16Q{n7$r}s{Ts`T8~Rc<^gCP*-@gy8KR^mP|NX{>CiGK; z69+duf4NpG-vtParED~VO97ZNU>zqmY+V`Mcz&1+#x%|;&3=cG{8~AnA9Z#m><6Yf zedYdp-hnxeX+0^Bv3DHF=Q`yO^mq;!0T^?@ZIoykX@8HJ`T?g(D-!n4iH;ii!(dF& zz7vgm0^>DVY|i}S$8+8uUKA5GXHL>Cv4zAlHjXo)H=|wfb;8GMb{MUGbEM!=C^Y@6 zh{bAP8K$$7VK~We6&c3l=tNHjg+krkw}I676oRD%os1M6x)ff4kO&Bj99YTfU_KxK z`d|Z-k+u$dgo1(&tHNN=7~rPSz|C&Z*zFp-DdR{=3XonS$E7+A>@ygDW-0!nK!<@h zVF+5lHY==oHqwe`YO~aawhk)!3U{$L7~LMQz8Yn)=(f?<@!$Lx6f(;vxG+UY0N_Cx zk8zujLw%d(pQ@cf?i-1Tihe2kk~rSrB~`w@GGWH>HS&iU?=9IB4e!|?mtNt=(UE~F zDL{d{!%A4;5eDG!_)`qn!k5WSNOB)=?}v+SWHE=f?%#AfHur}m3pVxnk+X@q8T)f? z?_Yajf3(*B;iBQw4lOndQ~Z^Dl>dsFvevFUjS8@Y#qGAC%#c*Alc?N~?ja6Uv;sD5 z0PgBi0t|v9GfCfSlFSwJwIVE8K8s<`!4oitUSn5BMlMGHj%==Anc$)3^vKB7@Z=r; zK&J;H%ZjY~j-UU80vAYE1c&)p?2e8d1us0cvEYK|*cJ`nrFL|h zt!9U2$GUYH4#$Tt4!BgVOt=6F=ia=4P!eB0dn)7}NFo;Oe|w4~^&dbbEcz6oQs|>j*^FUQAMjzf)54=6aOnG9 zu7=Wa?C+9}Zw-As_bu3$GhP-gO-VSuFZ4PiOQJVbx1i&#+qN@#)@O&Ct(Ms2yjfN8 zotFA!l86;unsubZ$J?9pl4Fyb#TBttRmq>NZja6QQEY}n!8`l*lI=bPkIo0cy)8#l zj?w;HB%f+*Am%7bG==(eur5r8_M7nx+zW_I04`D>K(Fvu0sFXs-3~~fVuF1pyTk+n zc9V$P8Z8s(_gQ^dWkwBvseuDdJ$TA;jk4R4o(f;dacG`uW`%UIE^oLUWWGTX6UT1< z^^YVb-psGL4gmZy{3~oPPJ0s{SYB9_Pbl=_ttKBKdG(Z}Q%U1L_1>@J8l+VETS;#u z%}EG-ro&qoB)uZhYH?a74hVeA(nc%9cm6nB1sxt?01l6@kD=RD&@uwc7)+%onZ?B;S?KZf+xtEJ4s=@37}Xk$qwA;wg&=(n7rbwW%H?n%(mFc*o#xIfdMl7{huLrS zTVh{b_Ugu0^(e(?1uATH0PK2c;Z?3nX25Md1`9olGJ3-Ls9Ta&58bC@b|&nPnmC=c zaa*<6#1#}9;?^_{P3%7#cSJO8Cr`V)m;?^-;LN$*rYyM%8gszIG6QyY2Z zqh}TAa2Opmbbn+!#joaa1hF)$TFv)#lQ$jk$`;xWtPn8WiS9-i6XtaQ`X=Qh-6$m> z@-+GsuLS^Wb+5I!Q{76e9#*2*1ue*84F-6hhwN;?o#N(FmF^Tf9MlPhRJTD$u^6mq zHlg4xZ9J`e=0gkWtb|QT)N%bP#F)-kQb@19_={K5prnko<8rN47lGgrY zcYJd(NkagxDoIbzY9A)sv(l>~V*zyw(+9~&e0_Q{A>|bdRwhi~_Dczs0s1T1l<%yZ zKk>h?bxmUnt5YcCx;R>%F6V$FzcqcpBY*dczf`i|R`_c(48Y-WS3}U2GL;vBH^hOd zAFy~SyY&2|hwgi6m+Uw+`|PGkUnFnuUyxzFu;|A7j1=lW0{*MU`YTPDw@aEN>MTj0 zW z&ZMQrnPr|k3YaDF+#whbIS)BMJ#^@t?zKZY1Yljup=w>V?i>{p6f!pG+~-)oNi&aE z3tc_@NxYmypC-Nfq`vi}9w!RHc?J~5Fa!R&Tn-?`c_r0OErM>Hy1AstJQUxCV_Kh1kTO$`fQTu92(jwzOp9j?c1mATGUVP zd7r`dYB4=w!K5Ofs5SR2mP`l8i*!nq8LGj`oO?{0@%1WbWWdw|Nf9dh!AdNaduPqQ zFD5>qsC|_(7nL4OI373gIx|*AH;inS+yKCXhCm7_+)Lu67LR!>(UVSgbP7fz1z?3{ z8p+~zlA3h#T}kJ$M`mS}4|e#}g4$sL1}rN+p#-D?+mJB?-G*WttXr_4z6b4(m5YTr zxBOc^$uO()LJ6K~xby?OKc&0E*YN3YAg z@#amEzt?Ou8f+zpSR>W9qQuvT5R1*hh_^Uv@DOZN;&~&GVPs-09hj29xmElOD5`TwtIUl@SH<9{sx>s!4p zSqH1B$>mjjKJO~oDOM&#O=7ykD{GHq;jX0pEUt0VGyI`;&E6{?4$Wv0L;P2(@MiV{ z7;DN}9U;4V+WR9hpB%U~I=XP`=u{Y^Q%6Uy;^q2vxWV%3^-(%-Yw#(x+|T3kIpnIQ z+}uob2cix^z<@m-*(nM8YQMW^bRiwP7w+DDVBz)yyAgm7?B2fc!0zXsJMi3r0|$0L zyL;in(fk61&!Cenjb#r8>aU2!-IP*$HuPm!M8A3f;Mei=`t?t}u=$avUU=-Or(SsE z$B(@52#lwGxa_H?9(iOvZsOSf?15*W($g@s7x6b25V+UTD@%H2X69z*Hu-G8tg#Kr z-9P)pr1LgBV}AB4REJtR`0FJT`>(BClO0XX7@EA^kG!E0tW59R9=2mb3wn@NL1PXW zYoHZWgc9YM0SsAP>AuoQWxX-c(JffC%Sx3mMSn2?0r!<|YDg=TSU2;)Aj?z_7smrB zTplTq!;J97GOHjc996{PQ9Gs)15+}bUqE74EYIrEGFjx+PL#9q0R#4-?;hoOM$`h4 zAs8Ugz!@@9bQY@9I4&z?>noyvai#!p?&1$t6;3OhS-7fdW?|uHRjXG03h(_2fVucr zg)n}#stU*9S%>R?Rs2D55hc(0R-;DN#z3@{C7)GP8CteO;?aZwM#vB_;0k#!iF_ihoyMz&hx60YhjDA&|BWHZQ`RI* z`kNnqDPg%p4VEkRzdi|=$?MUtaBevsL9c3_rhxg?-x3Cl3ijXmi$wQ^zcJbRFaU?g z|5gCr&9}~LlBJ+?GgVDZz0?hZ2%j z;Q;)V>!16j32y>P3P|6*K6n)%cJjB-;Pt`L8@ ze;vF75g6c%hIL(;4$&_NJv#cts}C{KBa3bhlffI4e=7jsMPw0Bj_ZSq77YzuA4U4H zh!pi3gXbnU0sALRl7QLU^!g2UQS3K)`pw4C!O`oZW20BEjt*VDJ~Vh0&J&#`;M8H^ z&8aYHAd9Xp!WVn7A9bC5fZBk+xmHK79C~(T(qKM-dl2miW9;gmJRda)XopMBJ`MmJ z4BB#jItiGsjm*!UE!oix$$Q!B9T(#8&J|4EQy2cn9d1bHC;(GoW;I$NVJ()CZD~9; zpG=(N;e9#PLCV%D*DRRaZRI++0G4a@g~Tq^G7igCSa{KQ!y_yJlJVO}8Zh70tLw8~yGF>~a?%bHf{48c zM-+f#TVi9gDsI%L(|TyQj-`*lX1=YCkmSmjk|zIwEl8@6klahV_9tAMw14Z*D>;*V zPACP&XaI_Y?fiBqVci`Mx9>gp;Pvn~XBdFP<1UO)A26>f^U?@3DnYwkpUXMm`KO8| zO?}s_Tucpp#K+H;PI68hKCv>x-$7>dNwoh6@R#O)9bQ#GRhmNWDVAnqn?pbGz@^9Y z@*ZFM_@z1+zu(nfSJ%9&xuRnE6QSenk$F2&*^yyHv(Gy3i2Z^!x2cSl8Dl|`RScf) z>pm?*sEuJhU4O6q9XS0`-V-w)c;bU;2*BqfBF@h^KXU%Q^ZB7T`t|(uZUe(|j9(OQ z6LUY>J^6#OH-pxr4Hb4VV(j+Nx8)Zj+s8((jf|Zi8yUNPy?hWZ6zsRJ+n&EJ`LUYB zoeXt3)VctEdmXZ$a;TiVDc3A^>II#2h{UMXvsX@z91NGnRifjgR(ko@llR}7bT*oi z8E~fjBrxyrX3p&~h1`&aZZlvLHDfRusooN0pXjUGvgy=h20R>{Q_Z4MV z4{r8?bCn?4W6C@=_%%W_46;t2{EF6_KuE;BoU^8qlmvQFA`tL*Xs31Hc2v3iWyj)p0%_&1h8Mc5hyA7&lV+o z^QLko9DE0tlqee-s<~Hy|6x3@Qpr}ANbvRckRU18|;iI zxnHYxA8LPNdI)aT?y0V5U%IrS83FiGMP2>Ux}{6=mj3=yDCU-Ix0~GVNcXrH7PT3q z@>*JS?e$Bcq%vazx+tcPhiV^P@$uri$D4QkzWtTDrFnGBoSs&cysDhktXfqF_#4F9 zY{oo*40s%WT{H*m(~5j|-)Wn3=oX**_{t@dD9}Av25m!2i=X_obkY~|jD&lpFrG)q zt5gSzrjZeWQHbL?_!hsz4G9=9k8QNn?j8xSpf;W0bRVjbBlGLl<* zfH;G01K^5JF=M?Idw8+ymFi$31;)Ny-k~sYI-?QQx3uUAp>(@x=oncou9~ZrB?!Mt zWectwN+=l99f-*xI1b&Fw^NyEWF4?!HtWp$-KfrNa_clkqe@YbR=5h-@w$g=mLd7Y zI%u92f>A5rHcQHeP#XfI$CXa&mE2rc)8!@_ zf@X8#PK>w5kn<;g@RJwose^&7F`+hQ{JUhvsWrPqF_O&aX$2V5YP?grxux^#JUbwf!rZ7n7vjWhCZHJ2y@ z|8lEEbU3UIpVfi9JTv$7gmACh}+2X=R@sA#SLI*kC_zGpeo zYM|F2PaB8QnyUJU7!uFi4m^uN>PtvV%Ww-Z_|Wpz%j*jB4<5YD6#Gi5Q&%kC1Mm5* zl079bb}oP8-x`kOg-$?KeMMINoA9h=50GFa>N5PgaA_0y9{Xw2L*$nJ%HE_o6A^{s zsDuO^puLvs%t)x6RBaxWko`Voz~0N0|Mp@wxvUHr@T5LqxeA)PA)zv(LIBK>`)w6& zY0B9jL=E4j!24>KN^%#{^0+x$@43A{YEDiG0S2tJkKOEcvrb1k*&(`9H2Ea`{B{qP z@b+&b$21Ca8ZkNq!JJOM>p?~6VIr8&a!{=hMvARGdLtqHQZ)|D0P}pCV@GlR`SXcm zBmZ&pxvT)zUojGVzSSiyC0}7^IS^3dX)O6ZE?QD?l$4~(_gnrmwWQ_yC8>BTf&F;D zrEEDMCI2)%^2^1IQpv0D53_??bVCs*I?n{^^R#O0em`R2| zutVwF)3TP9J8>q`yp2S3V3uVw%>mcTVjQvEGmEpZPN>~p*cvno;f5T)ATHL<;P^i~uZ2DM>5mG)5qq`or2E{9w~Xt4T{iYEO1T zX%zie9$I_q2TP7f=!VpT$3ps74)uUX*0?}3VNu)vBH;D;C?L4^0>M4=R>`isqVxBy zogNjlwkT@)^eDJoT2XT50r}tiV9Xb!rsxdw(0TyiTq}%REN9Bi)nl2HE7PY9!Ft84 z3ilYf_w`WzclwIu&5u9uK|~D#aM1@drxi`l`+Y^-$1`t74#~(gG8}InPfb76LX|bC z6Ol}XB|lTWYU~Z}O%ewHESJ~J4m@*YMe}E~^JdQi^80w*()9L^tE;R3^Ml*Znh&R_ zT?;f=>uUlM+~jp-!hAu6lLe3Hzg%XNfC1~R>Vwa38fT`1anEO0O4I_$?EPIr(#ZI8 zMU`gfNYo7p6TrE>z1H5Q&sAk*^NxL;0Z%>b!5lCe_!@;atoFe=Xrn#Qkp23cwQt`T z4^T9&2vQ#;mOHq0O49iL;Wk0oSQ_a76$>F#bw91=nH5*L^UuSPqQ|4vVf|gkEji}l=wNY!Mwr)Cg;=PRCT(ev{ zEbYopTDdhUYVF$6IX`%*1*Is-3|0)H{stC4_p4MIT4yYpPxc7vt}adYFuAsNE%^c< z?VTgftjGg?vG$4CFdl#T<;uq^AJ18PPgF(V3~<$Z0f1|OU#~sG{L8{4q7P%by-k^z z09Lg&spbI&XR7-<%{~(&HUIv|Yh*@IsOdH8|0!8IO(uBgh7|fveB#o_d&YU^NI9t~ zPTXd;%ko*~7k?yo31hZ7C})KwadpuHCEp*qHf{Det9eUVF>CFeAIk@if4t(Y5Ci_= z=6{fD*REwb%oqW{+U;IPFV;f$=Jw{6nMA+!BNOu}0I;ujZ_B2%1DREkHPh-OT6AMnwIkEqp4Y|2Z8h{LhVCK<;gy&Dp zIdNjnntctTHsJq|)bxqAF0Z#AvLURmujF381VAI{~axUKnCEbBS*fZfOzk{G5~)ef0f2mt|*a%&|i?T z!J;wJ-q~;07!+MyU8gr@Wi`{0bq@JDl3?c0yLD$$^U2x}tlziz%8Cet{N>ZHKK-->_Gt9>pm=O3k%W+eO1>0fHBk?@fm&+MYEQ^yS${j1qm)P-0x4spJ})`guVdEsVl0U z{k!|`|Ho&mR{UGt2Oq#+N8$&0MWpJpYd}!*>#pZ91`F97*e)mUi!0=S5G6DM2mXsE5P6LIR~R=+;h*p0G9WDfs1=)l&!w-9 zJVD5{58&(agP&A?6{sr_9WWcnb>;RxLbk8^`@b*Tym>0w3-2S-m8)T-)gPBAze}R% zA9K{1mIvTx@5O-tjL&)>#o#YyzqNwq@9w>C5MW?>irLS|3R)cp25-pOLsAuz3-L1_ zKk;P+(@eI?IpF&qJu~xd3* z7epVQb9~C2`IRk6xFbEjJ-#5mxh}pgy`ZkSIi1w>3RM0IYkpC40tK33>5C{|y*z^aHd(iqR9P+k ztH=nsfuCwk)pQI*%&Pc!IYyhSQ@`SrGWxbq?h70k1JM6Tp&2&5|G@vbpN{`CYx&a0 zYk&aP%z9uIVmN-FGs~+O(+2Wb^WzUZ@%YCU0AMRHU|FD2)}vI>rX=CNbwkQ;hbR5R z1pH1~4k7}R8><7_Jvj;UH|>i)_0rkK7D*O@#{OpMNKQi1oH+~jy>vEivE-Hk7#*4v z3clkj)`Agn0RVXH8)3lX=kJdLFthZtS)a{<^_!tRbvP3t8U3$YayY?&bFH17K4a&VUI1Fm0cUXl4*ya;7%$|O&$T$mQcg=2`KKoL` zndLQPZBEqN0FZ#d_sBO`+4pDp97^72V7`e{FihTeFb;egWe)0OLRiu54J0fABNzqjBhF zfM4oR%ycYzYOlo^xzqXNXz_Snn2CRQR@yH2ucj5PB!>sSe^bRSw+&i2pMNK%)oV<=JQx3OA(%9Q9O2}xTw zp}n#eRZZZ0xm-=Xmf2Bp*>MR`l}9A3!A1t`ZMvM>>9eqXmd`JHkDeA}Day%O(C1P* z0PlE(O~dJH6-TJ&X$senJV&sA32UfI`Dn_SGCM%Yb*+qk-sty_Ov|lZ)TTbzo zMTXOWQ4fDMldNV; z8Ki3G@Ze4IfHRrwwPIrus&ViXe9?`8hkGu|U;2yY2U#}IvMYMirun5WSFqB!yfx;5 zgMEuDqYrM{H2akj2~8gjD1(Ll*$Sbfk3A-+)e};be{=qO`~3ZX?7a(EQ+J;K?|~C9 z0YnrPLXdK43{6rMlmJQL5H5*0;Sf!*I*Gy2cp+_+(s)^*ST19y?bO6(r|CFOM{PUM zv01xQ{k7eFcIBC^({y&+_SbEk@o{&Sf5#vN1>r&I%*glu`Fu}MY&)I(?M!F7^W+AqnlM^_v@B4H8JaB%7x$Jf3#@@IOdFE`|H zT0darKnDz=m)?b$B$IO)Xx0(!@$0f$-EL2>Mh2RVqXnF9hY}kaC80KQ{0e26RUz1qg|dWZjF^0WVKFaOM~=`UV51%E?q?NOR+1AduPlTo$=1xciK&7 zr7c?+My8jEz3X3LLPDd1?2mWea6Xopnvmm~J=Pqet&%u3XKZTXUESJd-GSq$OqH|9 zl%SptV01gri`5@rM24SfZ=PM-cTvx%0~&YGBMJR*IP0|^TNoLm-dfFZ0gnd5v)He% zZ&}YC*1o&Qv>>se`yw@F<7VMPB5xpAw^zT2rn}*P*KNtn+>?e4BRGX>keN+#j7iPS zTUwZJ?CpG6!>C2~Sieq^Em#Z;CMc})y>_Po`HR1EoaRz*Z@)+B=_+o}JU?3<`^atxD0AOp*bDyaNZ3lg4Hk;GBM6~XqNFg^HsWOwn`)G~b9Ib&R z7Or^X;=*37Qyd0VNLg>)h7Io~?Afqk&xSn-IAD1KZcq&4B?)xz{>(kNZV#?M0hiQ- z)Czp!3#k=VD|&?3FQM)es9=#$iZU2O)~D3jvDsp(_}Q8A5i(ww zQd^5*RY#<3>V#J{=!z7&%w<-Yr)iKqXg0mqL{;v>iJQ>T)R z5#>8|OBOTnXVBcNW6FgUQ3V_Y@K+VUf8+*ea50IAV0^0LRLqz0R)1IlKW;C*lI_7X zV4qJ3N>_OypB(30++d_?W5|HmH5l9y4K@libQr7_K(edD@{!9bk{Fn;U%T;(-X`?_ z?k?4M^9x#Ef^8>szDu^bVQ36AQMUD0lY0HB`1qxZ0AzytorOO$=1~ZbE}FBbLEApr z(sHg!7YU6rWMlCSPksH)n6$@=2zgqQwK4}EqWE_sF`2{F`}DQ7eeaXuQGvRn0)QjG zAS~z9n))uLCU-|-u3#>Km7CrBXXd=Ou1?qd-bXtN44tK=yLWqfN@!(xNQ(L|-^~I^JHW`?ZLZzNPbZ|dD`cu(2zVi#1lPF$p0w_b=dXt%aUNQ$>O3j9hb$0+S#Q+1uVG)-^c)bC(8QX(tCP@G^FWK z(EMS0jS3TiFa@|#=!c}zoby_+^F1qbxmd3SOJQ5i!3z50HCjMlyDVP(&DcacMdIK% zqucHGb79^eaJvHz;o?AtuqFUYtK09uYrt<{3{4vBV#UJ2m+^9RcPeNfL(*Nv;ka6TZBFNuKDv04x z_;vjL`-gzk`m+0@<9|4407+RSD)CdNlDC-O6~+{fz->eU*VU48J&Iq3siUVPMwfCq z<+3RX;3$Cq+5oJhb4!yD-f&(F{|$veU*<0X;NPGLx|9~;pq*@$GzhDXak;QY)Zied z>cAaro@-S|uz|fNNQVfojS7%+J=e-k)B2NFN;S+!Gt*DpC|tcbl}#wyrgXy@9j<|Z zHLFj1R(p)hDI6W8;&&dP5jyUvI^5VR$!gIAI86O{iZpBc+V>4p<{~ID?&NR26X7qqgvszllgaiilFD!fpddCB z1O&S~9?9RcE@o_ayt@49r`=aPSF*7RG|VpyU1@_m$pWqTS=$2iD`SC>;ZYjHjVQ+L zQfu~{_IBxH=IqEE#jOz;Km)t8Ztl;jjvq=tcwuKU&v2bD1JrxSCtj?UHHekB(78V7 zav6}phL>{#fIkj@bNGXBU_Fff4gIKM0~6lsDGlxFut6 z;anwrYf`G!qt3l`3xlnsP9YVEW*teV%+PT2+xzby(@Q7yLs5|aQ2-wLd;o8xGsl?Q z3V4M19a%ta&>LX}T#hDaVMGBO1@KoKz>6`Qa0Q(;#?-<5@k6>crItaXoA4-%^CU*c z*b*ZEhRJ2E4JMcqWQ8r|GQ-$(w3puRd#k(R8UMsSVEJwVz_cBbCtFDYY(TvRzz7W* zFzzaZc{-q$LJ{5M0wHV&g$yASx7W(v1Cgug-L2u&A6?!2?ZN}6j<1kCc6}Q*?X$Wy zoq)WYcI~98aNdGh5d-w7@QG*;7L~!X3YWH z%-lcoU_cb?^Z;g@6-ZhBMRQpskjs2H{dS-bhYVJZ8KRH!uEy%_(5In z?)YHqW->lP;>qgG$yeO8rIFGd3;>`F=AC4BCIMrx zGY!2uLir04SW0h@&xt=l6SOUAg8rjT&_DUT3i!i23V1PdN>|GWngGsXbx|L16u|#m z0DPG#zg&Js3fV;U)E z2$#`CONzDPmX_^=9OOU&8~iRc7eo#G@l!ErzdFO5(dFzXwDz)KgH~JIR?*GTzP`Q# z@nkfje{aW~Q2i^Ii|4ePOy7zC7>0uaIP?g~tX#5W>9M5+BsmbEU47kd+Jrdde~2u3 zQL0@+t7DE*{d@Zxh!A*~kY{Wr?cx&#p=mK7*rRZ%nf1Rtn3Qt)a!Nwa&M_~es6l^u z+qF-&Y5Z<~09zXSElnDYCg6ufCx~XNLek$K^!2-a!G2{BK5Tz)_N6?ssy7$AFw(Y4 z*{FcoPvrs6-0n@YW2p(1StJs4s2OvTR3ZVQKs{Vg{i~3xB&vwEg`qKb;(7)4FPu`q zK-bR0zXXKi(?nDNqEj0mC zZKkj_C=|m`sd}2c77I%|6dE>|!di3!I|Yxgb5eRFk`S!Lgkb5Ua}sM}9hnw{wdGb3 zc_@r3S|(%RM~v}Ki1R+J^I@Cq;dY(ru#1&>F$~Krfjy>`sIWi@rU4mcU0oP4)z#%P zZZpCiy2QZnt{#?6gZYHf&WoLPUdnpARL`c>&{ESia^V)^+eEhy9!5FC{7D3>@c`1} z%SVg`aJ1xjV9m5g2F=ZaV~4e%|1y=ZzBmYL>SQyefa^>k2Wo9oHaaHi1C9dte+z(9 za1xow{EiT@>1{$r^fnshPp6gT!V?H}t|XF?Gv#E3P7Hc?W8Rr@_#@xAS|9V_L_D+j zbIm=GxBAq-(x2J~{IUd2^{4=a9s;xwhYa16*zmwWy_Ue?P>2?6q)S>uIb_uY6`s=i zM~2FbjAl31-%uOmN7t{HKKtUc&h>{MQ2^6`zYYM8qxrzIV%?$zi$*DN?;_=_h&OoC zajDdl_89pjEo5K@dA8G{4)kIZ!bfsg8x|5?e>jJqa$9nS0B-xKc{*MD@o^II|Kg+{ zn2VxGaM@C0@hOuylcWGD9TdQnz#aDV_JUIFib@|YF4tIa+a8d%NR@A_rGGD*; zNt#-ST%#2*2W5kUF5!2Bq_-cWuf}ifFnr_>_R}I-0N@kZrKP>J9dIc&Lq;F)<1;7j zih{;8B!x<71>A_Nlv7tQ!k6d0UW*s4&}JTi4D^*yF>8c1BBK!>5K$pam93X;!yBU$ zIV{+nsf4C5N4vJ%jQW|fNDji+3(RJ*ASM5-m&f8$0A>t?#sU~X;)8W2y(}CSo3vF~ zL7-QY5uMRoxVu{>?v}}zy1p=0!ip536!L!s08cu#l)aNQHEA+sYSOcM5?D~hpc@$= zECv;g2xh%uJt+_`S(38gKuab$2(tp*8H~o3h+u(TkuWJK*X!!4fftCoR5I^2m^H`{ zz{qgcu3}lQz+T}H>uG;{{`2+HoH=;}3Vgv>wf-&ow@|VYt2gek# zOJmY77nvd$YjMF0pauc_7pa8xg=t7{F&{>5HwqT$cj@`+JSj(0o=zN9z)=AI?@_>S z;Y@NdAeQEh{thOWeqjJS5lJ|S0YQXBaFTUkJO&3Q-g&1gZ|NUjCdCTs3Hy6vwu^A@j*1I!E#vIty_2ul*90ycVGtkJKrxDd`Nkv|ZGL*ekdT{2$d4`Lw> zjo;z$WB8TB>hSwJk|yjODBbhR$=cG1`dqd53>l~%MNnz#+=K0j;Cd=XrU{>FU!erO6BtMf(IQFvm`=GLY$TWz`F|m zQkAfT8Rm-o-QJ=g)}CQ*_Zh;3$CqH!0xq%PHd85x65bf?@6$ z`MXV_92OLCoo(taHWJW@&j_Aj#IcEC>U7L!{?@17>i+xb^!cwU9<*#8&r3|?ao$$CUi6HeNwSlyT#@3^wPL2H;vW>mTsL_YtmmF zBeSRm9)$x1M%f=b2Qq2XDefc4s6l61peCTO>nk;YO07c&NHfCfgx$_~DX>FUWR z7rSq@%mJ}GjImv_h6S>Zj(!!s0TS^6AGXU?3OQP!Rmflz!pLJD5Mw(~dGT0-Nf!2^ z$y7v(WSK22C#^kj@nVCG9rPMinuFi1s;EeS;RWg6;&>IvVIJ#oH7Z&yd`+XMHO*O5 zO}^etR@aT!n#kq>xiRcqvAU{OdKjc__{Bmypa(UdGECTaBt7 zQBdC6-6a>H{*_A<8>)+{V`8dfs`Fs^7A|A(8uM0lb@f|x6fvI`l$g0Kd2P$J5PDwe|tBO!rjuB}RJSsvd z%D?+c^aK7(C9Lz2TN=TVQb&I)uOk!XCgv21-)JSQD1iUBDBxP%8AcZqQMz>Q7=h_! zI?oi=(^d4YPFGise&JeM%EZWrwdI8{^;~=zR{UN7m;Lnt7{iH?lrthW=(m?POiFF* zzkO|QQ^=}j(BEvpo(4+K&yzNo!neZu9Pg@Jbk@3+)U53W1-x}sXVM-RhK(SB$xlG2 zj?SWSC!@D35Y9Pel4ha;o-TkL7K8XA1#r8|ZE#Nk*lMseHJ#f@%5U8=Ef}R-hot~u zK>Jq$z(OUgrZhXXajK^Lvw}^TX9u;%mp)LEkx>#?X_I-4W)V+e0irLbWN93%Ejej& zS$IDE5C5TmCf$8{FZR4a03OzbM!ZY9j7Yp1K223kOnoE!3iG6WWS7qzZpS%kYWeEL zTWs$Z#*D}BtAlS$e?*YEPU(>daqqB~;&-Z35|*aaYE7oP1;05zJf3>Cd~u&HF+NW# z)!TTZp@rlb(^f3L*qoC}GA%6ZkLdK7G&|_it|q%&AwdtcM3wxc12bP!Y zcwphNb|5X9_RSiRnRkUx#g&x2`ug%saSbw=SEvAuEvnE9t-uDw3R(#(S_?Wlq5%GK zeZVoM+Pf5R?PnA)wK>Dx#X9Cp-MFos5YxLj1C`ozrq#78zCZ#0h=hzbXWrpRKPcCP1@rl zM99sZMP0Q+pK_LOI@Kb+ND8I^OtX;O9rowyiqQvrQdg0VP_~8)RzSM7!^&y?j_kW7 zrU1tB8;JCuQ0MaKU;Z1Irhr>(RE;VLs$T^Sn?ext-a*@=%TAs=8F#!Pqh#qR&a2|7 zECc>l?udi+u_xy)Dk*lcP3dIh_YOk#^Ene^(^n1QPjaL{^0kpMGQpw&nx|H1m0VFH z7nvonbjOgE+SEi+F4K|CKBEv<8xLDdEXTeWF^gBct2-jZJ!1_H?Nn80%HT;@rPrU; zYq20SEywATb9D$w<`-ao_&e6j@}irumn9wybAUNfIOT${Wq* zwjN-gh_;ZRm6+wm#4kFYThb1WU@7S7#h{1C_yiH|4_zA}dFQw@aSvpi%&0sWn-TYn z4hf8*SmtxCaO}d9Z$9`$$?}Zl3y+BhjWoJV=ntikQ?I=IPASU2_*v^uQdhn#3g9S! zzj6xrEkWBxe88*k_<(EA5OTK>Prp6 z%9ro%^5{gX0>|Xy=yi_`s9tT`G+^!QIQS~a_Wn3oZKYL<*zMz^VK!K zsCTptEmBAVoZ4Vk*;W3T3G1u-O#3byx8K}`T(hE9bzAqBi^aC;^M%wmD+DzS(N8oQ ziNYG)7<+0`I%zB-V_lpz5KyZFo@}_d1CE{PIeBDc<)Xu_pR7`PXueRyj2zfGuhwMh z8z(f}3P5=~?qu}#ryMP5H%T{;f9IwYu#e^ew~noDh`ktlymE8?m?jXQ?T`$PfYo3P znV%y2#LwDR1JOZ8(|R6v_IEh4q)YcQ+t=LJsEd?gp9;5cwqj$#~DM1!!h798)QqKFL`uh{K)wEr6qIktz;~o zOL^pIeQ$PluW*5%d%7$+TWKK@mzx&^g{gxyf2Wcc0OY?!v3Xw`7l%gcBv|x)OrWOF~Ww4s($ZGgYN>5ol41Y`S z>-ze%G|CDDupV&hMDjX?7KMTjSnvi*wUMeEubBFDRpl^W&0CkU06=~W|BbZopYZI? zB6*rLvDn$otOEe^Aa_B9H)3^ak(u^lkkr)h;es#v7jSZ2cXJ5|Op*-a5fqONkqNIX zZdpbNOtMGD3s0V0Sj&B61obQ8E#cT@8BffGKZxPN9c!1x$z*8pm#fS)42#yI#<;bX z?|vov0sn~#=zix*t&ST7aCH0+6)-@Q5U~x?TkHqS9G>&!qqi-P=hrOU!BYIHz4O=ZxV?dmZjg+!lEmm$%>KUhW1=%RnbG$2IH!|il zXtgiu^}7g3GZ?HEHFpJItHB`bhxWFn!;x9w{MJoWz=8`HhTrPmd!r5rTu1~0&zedv zCbOpfxmW6K+ILCSR2ovitptKwKe$@GXyd%|@6Y)6qPi?Vio z3T|~C5Ev&7xA%9-vJJZ{78mRhwrU9ZTew3Wx9@|MnfnX-$|n}66Fx~}Q~+Q}00FG# zmj2+)Z$=Ji;o5~W+SMHc{tnSOCU#*)qN@cAn`qRp%T{0 zp=k=3w@2!4C};#0)wvor9QUJ>agpu4{b)v|*uwik7_(gQ{3n)2`reFeI(baX#sFW- zM#w}uAZ7yY4-J9rOUHX7Bz=8WP$dAEkmSt;V`S+14Kgw|R5mo0SCpQNMX)F278$@- zMK!R5b|q9u%-9WSy+zZc;l<4WV4k@+95X@|!#DKLTd*0!f)y*uYqi)8i6U4Zk-l*6 ztp2P?f7=2*>6A`7k2sOTdfS%r%YAhK@0jK#gTK%*Tf3yuPED^U|qMBQ_+4E4D^dVJ+ydL_gp^Q45)W`7?Ebivl=0 z{`(5J{PGGLs^3ILe0jwgDu{3A0pC`@ActulaHJB}hYTa7=Y~_#GdiX={tGK%-4)OH zry7wwV0-DMUW#5!`2hd}0Gb)y+y|#6CC~l-lf`P94cxpee@ z(4#`)(Wuaefu29lKT~Ydzmh^u7=${I)CH_mc06+Rr-k^RFr2U#0IW6~QmM{ySg?v^ zI<^9UPnmQx2o1oZDaDcfy$$w}O~rtXqB=$>g%z@&mW8k1nIK&&iTzLZ@HxN6>yo}x^2F_(|Lu;F zSPI|~Qqg)eX}qWv)oo_#xP5lkV${J!TbkW`vH)Ogiqus^QvHD4tyv_!E9qcsCj41X zw26$Y*kzQPfxy(=*@$t_Zshj(L)9Q1Nr6wrcGs3KNYUwZb$w?p!i!Q?{Hl+dm9YTF zRJhdMO5X0^eo1R=46}-QxK8vK7CwSuC7)s+#NA zP_o@aTQJB$08{=67v3f7q|WY&&9F#LNGKam#b2vPQ9>2I*kov>3OKVGH8*`K6|>fe6tYoA035C!m83c$41RXI(oi>YJ8b%M}XT+7(XM)mD)Pw4h{WwK1WKe=mo5?2{}j2-OfX zDC6{|gyu6KcT&i_NJoQFYRVnHt$$~2jMa*zVtp<4rv*@k;c6AR)P@?B`|rlK9o>-m zSf;FJntvBh)!-(~0T>7f;oiV#sux^C-C!f;BXEU%N?f`oyed7@1?HWTu{gE+S?gWTTV0Yb*Tr#bi<~+%iYh4wF_v4>EWp)V=8oR8wDy&HtnfB zY@}YF!P=p5J3s-G&0TG?caH4g9vVwyI&-^23M&BE$W$&rIerI>bLQV`0|5KY>I2J4 z-oA4@H+_F@F=x&vtLl4u>$BkpAlzG8dQXov=W*&tj40p<8U?MwI?QH;Pz!_BieO!p z%QL2_|GBZpWv`h1ev6^~fvJ}A^c3*KFbqIiaF^P1o12(RYuV^MkT{oyDy48_J z6);()swSg*W|IVU+YR!NYBV8fWMpD?COqHhmwQ>AVM*o#N079BGm)F-x!-h+N+F-LFIxG`a6%rRKmK1T^OhfSTI4WE7vZa z{?z49R;p?Lo+Wp!pYeJ|G4pG(NYSfN`+?&9AfNLN`|X_?mwNk+98jA9PW_5L2_SZP zNwH1eo(N2fbTq&mAB=<+_`4|1q!*vnU4CXsN{a2-N%4{OEQ9@)%-g!}d1@%jsvaCv ztA99j(4CDXL)^^ZyZ^jmeP;Ze1@F&Wdg|gaVXz z#A>WwFV?TqbxZZqEiFvQ>aaRss~?bmXRL0;ewO)0GROU*hEt1B0kf`eW|Z7{@$mVD z^K&}<1LkwGB|q3SZL5o(zc-FCqY1jdx4s@!FkC-Y#s&bdqy4ib{Eg-npLgshQk z2;dK_)C5hgcO?qu*$Pcp4%wPEl8}V+%&u_&aJa38cIA`vVzffjg3tr=E? zibX8$7PDba#>r%~9pJ6bZHEpS!rc~&#Vn^rXL%z|1!(?}q=uJ?57jg!QURP=K*q;O zQ61U72S}Spu902n4YILzoM>h)&Ws@i&G=C#$f}&#Bj?-3GC>G0_KuU(;*%$*eMiH~ zmzg-;Y(B>ofB%W;e-e*Ac^m;uv%wUC3`YK{TD}?zm=gGpA5s2B0sNN-aM_>foyz_! z3Rn*4MB8(Hwh~VG2;hTE-9J1rKJBRwJ{TL~I3RG`njO<7(X(ECqL}F+>7BbZYD+1W zlaf4sH9!Aq{@&;Iu1r3JjTks4;r$UZ?_Q+Ai_g~HK*#Fn=)4)DqqpOq0m7q88>C^= zf>~rvAt6;8Ok(Lvyc%0T_-j<#o+3B*ZhbEAxvf`;V1o8^h71#Av2G=a!$0OZr?i)+ zOWy<0_w-wV-ZNJ^#Sk!$Juj~+dkl#_Hd9j)h9kHcY2vzcDZ zBsZR!v51go&WMlA8x^$gtWVQ@H13r2Y=fzQ6g4j>B1;%9;0U%=G(qk3>RgwAF zwIXi!JuLcwe+>X;H$6WMw8JwN&Og{OFyQ~l6}NWbofGr$+so!JK?VGX618vt$MyYy zVcHFenxLoofYAhvB_@TSTdY=vE?}4Qo!1wVp=q#)b+T>yf7oL={=^fb(`4L^jN(;- zg?XZtNhEmyR66_H&QUItp;m_~9s#@;9=V>7w3(#ltke`u@I%1qYb4p8Op?#ZytFv9 z7_HE>HxfceBGGVR3(vd4VV9AY*T}Ilm&Vw{Mg~{cck2~B!q-W=5bE&u`d4con7)4Q^Oc+zZO`RUC^Ff|l4E{4{ZnkArZs%`J+()KgAPR#&_EnO3>VqUJ&tQOE4mb?NE% zrSDBouc%Sh3yHw)ypcV>9G?|O&HZy8*01>e%$23d- z_`SsCk93B??nyl`PH*o@)b^|xr% zX92&UcJ(%Zu~u(_i&i>mvQ6sGn$}|)FnyX9P0+WhuNQQOk-cK91T7Yek-)Gu+qP|X zFT9P$$jZzZ1uc=N(Dn>_QA7C)I|kqX-li3M_z5`fc?a{zp1gEym@!_oC4R~Wyq#aM zrHdqF67tg|)mTE}jjV)KWJ5Z9Bdq}7;<&p&`yb163=ao;u;KY-)7Q_Re~j~rXd$dd zv&1X{F^)c9`TDPl0*;O-fd4AS-~4If3I7}8%MCeu{V9#n@0nGk0! zy+TW1!4-B9$)1|GLN^f~2_RlnY`YkV4I7@Wgy&S+9)4dy@x;*T70IMI1akr<%4kpS z>7$Pv{ipq1ZHM{J!H`<5>Am9a+FRF0h9`E+rLT!)Ks=Mt&lJx@bx>lrZ?k`p)#l`DYAg(=c-g|VUHznst9*XPv=i`*Cm(1Dbqoa04IY1D z`ug~VZ&Y%k$H~!b3Cx5X9sR*zV{h-J({@YNJ6>KX_E_@s=X|Y$KWLNKr=)Nva}bPZl8+@5N0wHIFQxb83(` zi;RP({%!5NY3p~qQOOvAy;y={DiTW}m)ETSiuiz|BMRWZjxqAJKT|0F-+t|DH@;*5 zqYqdjx#9`BgFXSk{kb#AQI3mU^ZJ~rbH@4CpZu}Mg?*9KuBB_A*f@2DpZn(82DN%U z*}MCS0n0`P-AbRLsVmo^bo)FJ0&~nSFYXzq@mBDP$}>{!#l-?Eu`k2CdGi((E@)`i z-_p@6B2xIx>m#b4(URu6Q-zUVCP-r4g0bdMfGS{RB$*gZYYYktIr27Ci%LwiZa9WGv*JAbZC-H1V0l5C}8K;EV@i~4&@PuoAEfL}856u@$o z7dsYVS0qdW?mn+*^}LJ-TuUY0+YX0#6))RcLN-?)d)PX{XhHc%v45!?ZLvhF?(z!=Y$-D5`*?BMRU@sb%w2|aP2DQOMU8`u<7UF|8oN&8|U20Xz|l?{&-Dj-)zw+tl0E$Fk~H6bCS~DUThGA z5XLBI%Xi1dQr6$DQ~P#^OK$`CQ$Apf_q7`t zr(Farq}>Dg!54qD@QFEZk3}XvxGTD-4C+Cbz{msUntYw8D=NqdIqSu!c zP(fUkm6SZ?1J($ovdE3hEjf>sk)q9GBP2axEHCL`Qsx91BYBPRmellYbb%UG@h-6u zy`GJYa&*D6;t#sm(_S&BO?f}D*`(LMIC<;LnX@KSm^nk+5lS%-OD_-@WNxGnAwc(R zBnAtAlj@IXZAYZH7;WEKt?7*PMXjm5R=4`H{uLMPO86{lVVT!{=)E+VH&=pwSLy)9 z9OW7i=RjZ;OeAOtO;{8Z-TCWZNADlDwvLk=WdW%Rd^q5_y_{Facm z*yVR-Pv>L*?V{R9i;How3zy$MnT{-*zhjW4$zY8_F9yoruTCCtbVLFC*F@ky%lLAA z&5=Cdno>zW@ONOqF%VQLB~$^sE$ZThB^hx$HqDt+^7`6kSsyDkgIoyXk{f`)C7U+Q zd9)vXhuw)P!(yis6pmPo znV%-DSZg{vX)=km@w9gW*(7$h=nfw?t#88;9HBvYOHGa35^{+Yof^N!?G9d1dg?Wd zVb6wl({qeT)xt*^FV=6VZSHGNYSz{D)#|qB+S_aUw$#<$F7CN5y?I08iqsah0R?b< zwx?IpEAiys^O`|zIaFgeV2ah@!)=*WkLkajFfsM2vnsvNQhg}e+BrvyT$MyKJZf#Q6uE{`$^))hd ze&hdn<58A#_Sr2>`D5)cb;Vi%~Ah%`LsB%aZln z-Fd(-7*(x6J9CYyyG=!#<6$WdvxRGT0Hb-pjSmjf>qROf1Hi zo;=2aFcj)+j9`f?p#&DK0yQE4*opua9x0>Gq6X-IxL8^Q2_syjz2n{@T(AVI8_NtA_4x2{Csd=KoOXVV*7%`G0>-TbO|Zt8#ZiMv8S&5 zKxVnFR@Ya%rLV8HeCo62SOYGa2iyTdJv$ii2i$(QCSdi$7CWq*TIkjb^9wFK$jGJ| z6)fo%pK1|L>d_`z+pce~Eym6OCUITl@nZ}lP z<%Mg>b`h&SzWmL&8H?u3*|c!sy>o4x)fe>nf)cN~VgABL=gir-X~FX6=g)88ES^jG z0ANpVzpo=G5(VWSd;kD$n!WY23RsR+56wL_K_IVOMO)-GvE7w(Ga61VSaiOy@??n) zeXwTU&!1zt;)QXrzHrg`rLh^u#4bzK7uA9u>IsF`k*O-sk(!jW9Q4p{u|zT%CduX? z_Wc9l%gX_VVlQUho|DKGax_EBMJ(;C>!x)t#$oF5&vh6L7qdF$-CDr|EOcVf>-A@; z!&k4Teh>WDvnJ#9!RrYP$de8xlPG*)? zq7>4PQ2HLqW!aBdvHg&@@QeNjoXqr6ltYor)V&dc)SS%}Kd>hDuEoxik@-=H8_|c9ZtI%xgK{GAYz{c2;wQFBpUeX{_s|}65 z3#5>BXDfYJB2ww52uA-ZMX&=AjKwGoTZH$#F)=beJ{}L(@wefYp45jhY#7e3zqvks zbLZBTd)ZLP5DHl}!7HAiHT03(a=HfF-qRlo5EvT*!@Ulx=gL#p9(pK$Z*pGI-m<*p zyuB08VHdf)^n!x)#DdLLRjDbFkNQd8eydd-;y?g~fxq%x(7&QmI6fWlNAe12`onkS#UcVRI%D9Q!}d;&AF z`+W|_faAh{J%Rvky-NX4uN2ogzX~F z0842&w3bFeqbxRUsjJdmBqT3&^#V*SgAEqQ&i~YtdpfK8G%Hr+%K0Xvit@K6cegwj z{l7K277WBbWVguP|Dykage@D!KIcE<_C5TXXLH=C9n0|0oy;g%YU7+LZ2t&H+Z%Q+ zUG{Hlf3SS*gY)OM0Dpzr+!%c&ihLuq7IahrM@JOE(ee2T_;FCcK1Yxbw_OUz#6Nx$J_&vpVF0RNJ2S5jt(5V|z&ycXfw_YD8p+S!oA;^R8=r`u$csrnpI03dbGu4sCMt6-#9^7v zkO2ow5+ul9MU9mS1xr0aN6*TM8edQ|$k<{t9(Z8k+>%(9F?h23J@x%cpE3yRPnH0d z=g+M)axQnT^3qjuu)fz*uk-<;Kfd(s)1{~FO*x-Zz`KlXSv7Kuyh879BP>L;Euq;c z<7~&{mc~_9>ZF{Q=QY^3$IqLMY`3$xGOjW%_P{A1qd8FU$Nu%mMYR9CMDPR4K=Ia? zSs5>(=}7RyTVR!;8RailntA^s=G{&#e)mAFQ^@i~7q3mLx0$HRS11H6oz$C5CaQ_? z36t0?$)wx!yIS2Cxsh16f{di1kkuJ^iJVmTIp#xfi=a!KyXHMzO4FZNvY z|H|M-=1Tu#|4&-2V(!HQOX8l`@yszD%Q*q909iCbTf(y9*k=|leBhnqPR`q@qA}1| zg##u4Rj)-4@ziz9;iZa*{aQ7TMcy!B&)QVME zNm;AbRjk7C?R5p~wx6gdDER4#?VHn|PT0SH)%I0~tmr&;fa(r<+(D}v_Q4QBvKcx; z2LEo2S{(rVda{wg7b+^A-ucvhTX#Oa87>tSyY5Th`t*NQR8;J|Z|BbRf~Qwrht*r} z+nWB5D-g$+LRPnPMm z%1|1Qjp5pf>t)ql)}}yH0Dd&V&Q3SH9L8=%NUaW*TGd>zx8LLI_~2Ty-RG-!yVPoD z=8u1z1BcPl*x!2zt4$(-K`1-h4>T0pIL;ER&#uqCO0tw#hO#ufwBM8M=`B6o+LZI$ z%!%nf;9btPtX%8|4Dwe*lYvo=Vjm#hD+{yQBT`w|<>k#95l^`+0$Q+~w5zMjD3e*z zK%KQF9ZX8vl6hj!h7Ad+3H0W~hE;oD0XNO7QWN&9N=iDBkN|5E5)xJ=WuAyE;c-}X zB1t5oO0ZGI3w~f$Y>}&2EQo<37(4O71K#j~J(;V^b#=Nv=W+O(i~pUjR`3A>V4ag^ z^(OQIBY@8eYeDgz#mXE~YND3X5?QssDz95HOs;J)UEEi$Td`oII-Zm>EPN0nzO{rp zf2sXBH}@XkuWMV)N3c8Wp&GBuTa%SqmAdPvsi`Yct5T|}s@A2hNZ6AKcT%e=QeQ|( zO-)Tnt)SPc)CByj@RJG``nju8QxjIH%sfnM#9EulDdSipwtqya3-XpXvWBqJ)S~U? zWM00Ju9gU2L(go++atn&@TdZgjwpbmEE#e|7}BlAT3a;J2{kMo z)DH~1$g)^9f;GT}b;0j4Zg5aG=o%d4VCiBpvDGEBcsWLJ9n&RjEd+A~gF(%NM4*2; zPp{JBcKrOQnS1R%Ag#x52*I=hB(msIwntKm-4>KSpHIabu+Nk_Wc7Qn7AQucd$15z zX@4(mid1@!-TLV$Xi&fhbLD97RpEIb01L7VLvTgdCV-W>Sg(=iQT?J$MSmo$_j-Ae zhKC2xWbNukyRbfBytCXnxMvG z3A3H(&F5TjXo6;y+{}AfmyClc4g6hUuLq(1vRTD@EiMD+VvW2RZ4lUvNz|yq1K!h= zhRq29z`LS8;OK|~I66KLz*GVE)(0H}9UZZuz>0Aoma z#6aPQKWgjC3VdmV`2N5Y`>lqEtC`LU49I9Y7`lCQ^>RX^rYXNK?HfUVsHp&E6mW}b zT_H#Nb8o#z=^Oa}@~`G?0|5K#@uNs$FpY#pw5kxcW>mhsNN5o+U>H{M zv}XgZH=8v*Y0g%KNM(^?9JQH+o5&LzDO+fNhsafhz>&ivD%yY;D^ROw2$;~4m)684B{L(%57{lz}pSECVwB2qA1AkeutO;Ya zyuwAydZl8o*ehklUU-mA>+*_?HAWd+*)+kHEwACl#vYtLh>e(OjfMs|8a$8m#VBV5 zu0$D(6B}LxGaWekH0Y{PPJO^|*hLz^FdVKLRa;a6M@JOE(eZl}@Z-6=`z7_tpwCB( zQF@dYKmofwNMKkA7aX9II0GgYfkZ(2FeoNeLVi$_ZUFE$HbbEDi3mk(=~*2rJyuSQ?P;@6%6GO8gsXUtl(;RS%F+u?4~AY!4^&LQv9#9`ZH`{Y5yFNR+9#*&={gVD5)&}X%?(g+n+Dlf^PDqI8OTCv~rnR8+r*}g_ z1>AD5MvlcE;5;u#UtCgKH1bkzj?h%35*|`fTQuLJ64ufM--UH7y=)u8*6VCj2zVBj z=)a`Di3AkW>>8C>PSaZ{W)wmpYO_c#F}h^DTqC2ASkwxQ9qHw?B9$4z)ntj3f|iL} z#F6x0DfRG13UcVR(kZ(%*5a7N6eKAv#i2Jz#o-T00fS|*Xe}(E6f_{S2GA>_wXfjg zG%DmZxw+m!_V2S`A|PY8A%C~2Sg+T+O%Ak$LD?%s3VXc>;caQGI86=!wgZ5>cyC(7 zn=I$q!-wb%BAFKYq~2YX5L<;NXgNLR^ngc<41y5?j*3E#hejk!il&0Fu16JcbVLCh z9n;5DKj7WH*yY|wi&6I1e~eMkKESUBgc;ysz-k?EJAxt$aBOf;;F)320C!!3z+Vvn z=Efn1N07eCi2oNwEZQ+6`j;A^12jkpMW{iDSE3P128;0HiO6RPZ%0QD&zx)R=-Iko z)}#P#WedaODHVZ&{l#vDPuc&`k2d$djELcFR3<;!}V6uuGsvQoQB z%<_lu8RtL_^I{bOxQ1HJF{-+Tf0k-uGuCvDOiM%<;w+~CmebVh2!H7pAQYc8V@pKJ zUw9SB^7RoDbW{OHM-;%(@fihNL*0=|p%ip~w(k*aIs}T$?^3HBL0^Y@(9q#<4EX&n ztHosy{FQWs1`V!$kK@A18{0q`qu}+qZ|5IbF$5Z8upCyZfZYK#6S>@3FzU!H1H|$~ z)HA|+pvTCxeGqEh*~)PC4$#23f4+JkaJ|)~HfXF|AmA5>9+j`)+)Cw)0YQ`jHh2BYcM{I|=LRuTk8fz>vuiXoC2RT}o8|A#ri5~28@R3v! zG%2ghyx;3JTJX?efeoC0pxIkw<~4ZWd86G(HRb_PMPC=lteJ zw)_1(uB@%!*jfES>(lpbt&sRUzMrqs7}QK#62~y1q^ezix6AqK4KM84!ZF+rQ*~iZ z%^0@~su{zU$6m_c<>iw$By3?hbAiW)ps8j&Dyc_TZBQAS*t_40x;Rtb!-47!X>8g`KN8i5;rYX^Kk z@Ld_i#(>}IW?5dCFAd0k{xhybs5&5kazrzvmTj0j6GGmnwKr;wGMWc|7 z#Is0X6*`0E*c3q`_hS8LsUBdP#)h#NbXY8nl!BHX(M}$Tl)S=#E6~GIbO=vQPErrC z5Q(KXiKVynnNlVkz9p54sVkXdS(n(D3joduhY`T`Hkm5d?3H=9orZ<%4COBfT#UjB zV&EL;W*Kc}2>A7Sy;7Enb&YJ$VrIiGkt;0ISi+Vde04Az62V=KJ18>B;KuJj{90UL zv~mox78=q>!hYqYd@RIaQF9j`o&Wml8UL_wN3mKB{O$1he9C^SnyuWiY|VpDKDls5I}kY7 zabe}eA$P>^EYgS+aOzShYwQ{T7%jpPaA@Gn4k+tzU=S9-%IK$&PJWGFb7j~w-%sxIC^Uxcq{|vGUme=D zd9!gl*}H3Ko%#i`w=9$4n4}@6n)&G3Sj7tkX^)Y;50#~}kCBNRvl#=k{S%j(`zW83 zk+GJ?$alU&Dm+(|-y_?U+1TU(1~qfndoVOg5p)MNK=L5$zFFf40c<-Av_gpBdk%%@ z$|XWuiU2$HW?VUrTNDP57;=E&|uWLf572} z^Zg*hzNb4LTWm7GA&}H#C9I?Mv_o@mZ$0c1DBzx^oX79>0l#2u>k`UuV2lvn+Nt|j zWc0eiw<JmB&po8ITt9fT_RN>*A!v7b`CwFo_329s8RrQd3iRrB>}qFG@^LuYzS! z`Yz1QNv*;pon4z>s;H{iRaLP$@f(|~suGKeimHp?IYr;yTu_vlm{^ctL}x5dlb{+E zH4;Gs^PqvfH7XYpSb_ZIw5i`*yuv2c+ML}lo)Moli5W3=06r3F#()@>PHEstp*DvU zl`zIP0%X?BqrNDRvL9P7pAgkq4v z+hpBFJI)69ZRX6xqQdH!x8ACLt2(BrFeWB%A|@{{rYJAwE%-o1h48Twi>eFZULt%h z`Vnz0929t@I=v`;vr1!han4f*j>k6GWE>pRh&cfH%gIa!Vk-}{%Q)7n5gwpfN-!nC zkZ7uaqj|v55e0B`d}d7ffF;@WSo|Ns1Ngx-q=UXD&h^aP*WY|+)28LGKKY{tj>B5f z4xiG`$d=su{n*$CcD(uK@`VlR!C*(v%H%^1RE^f3@7%g~>&~a1`cD4MF>*8c=0tMd zjft|6vZ0|H&rRf&T_3+bG*LYfpH~!rqq_Q`hw{F$dF$4jS8rY&{^b8B*Ho4L*2I=iQSO3Y|Nk)EzzKY zgBFe}erE2E=Ffd&?$Y<*5Hu<;%_Lb$ByWFxJvBjRV>5>5KGh9L-_=STwjxaTQ2`EG zX&pqPmvbI};DI%3GAiRLO;`y_gFhlOa9OuwXR^bMe@2 zP_6*2XXoX#_7&B@?34xu1!o2bS(w{(Q-rHOFjf7G^bQZNP>|;Zw(Ul$5MpvutT`*nkEH8bmJC zqNEj}B{iUcqfyY&5e0B`e7*vHyr#65nxO0JF$lWehk2+DnPJHr85!sCEd2h-jQO$5 zUA&f(45cU4sEdLiM3gvSyR61Kmv zy(*!qpdd9dF=5@V&4~r+1#gjwqM7;Rtz9oXv^DQ){zKo$f9|>GW>&b}ogAr1;y)DiS^;eB(Td_8XY@+TJFJNE$0 zC+a2nGqoy>|g?>dyCmXTgfq2vsUx2#J)-tS*|YwsMP@R2CN@(k4qw zq8m?apxjDvMCZh1rbLIa7JY?s=!1XU{M%vrnD&xQlx{ zoIUk*40Z$z|VuM6D{bi(>v z4mi2B#YXin%~}G1T-~69B~~;)|Kbtg?7E(mh3nqB6+kO!5WxYCTemdjh1hj(#K!i# z@j{4oB>g!r=#BgK) z0@#L5SkWACbVUIiU4I0?v=3NA1D+JYemMkcF&2IOskMrBn0)H(zdC4aYx}rvz+&A0 zNB&$+wzWSKJwkH8p`6#X$~#k?lu%i+E48w6-`R%vhOE0T zno{nB*Wz;CVpl$KabZlDj3qu2`^?wA%?$PjgTasOw?gZF^vuE~m&PWyJo4m&U*FF- zJRTo9VGZ{cRMECcD+mt$Q)H=h-m1J^A6no+tN*+$(1JO8=Pj+Nbiiv7|*UgN{691_S-45*{P; zqCER&0hSO6u{B-rxfrG z3_Kg;E?_^+0soM3Jo5P3**Uf0l#2_y20sqgeJrxir#v#deapqaUB?V|k7k{4VsCKU z@$3^8XLCpl0dP5%o&~H*hi(@zm}6x7ijaJM@^DLV_tEE`+cvrj0e;9Ldg-iQ`L*~v z-y`*)fOGz}t*z>EZKBO^oaEM39W4h|e%vtO^44XJ=fW?ldp+C2Y$h4kYkkQKJjp(i zj3MY<_(ZQKicBln^KyXsKC$9WaB@8-iDBvtulo#bnWMhD<9A1nA$hA503(0tR7E2* z=+$`754McIGEIoiDO!3N<;DN$)fK=~%y73gj9#ci0()JfKAYS4!vA@3y)w&hb%&C<7@jg!X*E;#bg*Vh=GL$v_lf<9US4f?mBpzmRq^u=jNrOB;_Z8#2z zNBm)<5sEJp%dPv-+fORb6JGknI(0zmx7&jOam_eKU+S+FbC!1212I- z!@3iROD7n2DVGu}aI|INh$4HZ%ge_V3A}mDld;dpeZWN7o;&d-H(NcBzUMVfp*$I6ULt2fw%I z-aRk%JaKRk6tKg%_oz-~GvfoDuF9ajQdc-(*y$u8~`}{LUW_Re4r@sD(Xz?5%X;njhBrw1iO-LSgHP8RTJYY29aPc($ ztkTmuXzWuBgx-JXA77mP^E|LNWdo=((7H;+7V@9(y-=i6M20$>s|e@{kIVof1j z%uOWvln+H~N z4jbrEHOq!xI`h&8zu0rN`0Bxz@L$r0tG-V|78QrE1C3zMshlGJX+1R9&2`ndo+AGQZ0f0O@@cKD~)jQvMe zE0<4p9i$@(lUgcD3*#wpcSeQ;Cy4R#h19glgqmp*-wL42%O%yWJ%?N5=yYMx-^H$- z-F1aMYuAY&fhGHO?v0)!v)jW*j;v+f@<3n@%3peLfJIpIqw|2HD+=H*cip{z^MHT+ ztvg?_0@n2TQ3GQFIK66^hM?;*mg4yM*_HCWAA$n@*dfNItowA%Kc$P$9AsK@@{^tD z-wXhjEKbL{nGj+K&_vJilwpurOlStUI}_^Q)H5AihdE$0x_6KLZu}Jzj|$jiF?y*0 zt)e05VgHq%96R>&%kTaCSatQ`oh8-Pxi|fK|9hwX{yxLyW3@it<+HllTHk!v>$Q)T z_=g%Bb*D;h_NDK9Wojz%e>V7zW>4hq^qo4Dr1xH_ohW5N9l!kCscg6@JMq-r)2Fki z#uHEb4Q*Fyf3jovW)-4e`SB0?{T`>$aT6<=+gj*5)mcP#V-p-h^wOgXY)R#M;T+u& zXFAmImhg}RZ|dO8X6O0yZM(Bu&U@jPozI*%)otAWcuL&8BcJEjKA1fC@yEgIgZm$U z``-5Oi%&iHzEO3Q?8E}-bQ*%LDgXeZ6V@z%WhX4h`w6Ik(eesSBC*p*B{|%&OOGtR z_esA1K>OWf0I+!Q`IKe%{&34;W4Go<0KBQ_)5*z^_6ktAt-5;vmgpTwe0vrlyJ|=t zvlsS4JE^>O`}U>1yAZ$}=Vm3GiKJ3t(A7@OH%u7$HF0bQ5*Yh#MQvGA(?)GqS=q+o zU7IR5hC*tyG7af9#eAblHhcyaBavUDwOL9da2dTx%WN%vY1N*ljT_BP*ES|^DB8O< z6teQvh7x`}0m^$e;10CgK>q@NSa zgwxVUk}&~Dok4bQ3Ky0qm*P!%-+nxH&S&O=BTsg?rGAri>)_gpbGC1}xO9Uk$vI#I zFz>PR8uWsmAN7Kct|)-N)b;4o_jNt`)d3h4aG$2H%0N@VRq1`{SOtCBkdd->j?xW3 z^Y)&)wl=Th*1Dc`bAH1oDJg4=Eu*?-i#RyQ7#s2|7E6qTyszM9XI*D!ouN)PwLFgllDyQc%Wo*Cs#8p){Z6Nz&Ia&%k)3^- zn|_UFhX&Yb(EPxA2p)rT1Jc_?qs8H7j4BNRR>OO}dX3HIuLHGP;2*fDp_yk4fTMXN z&UG?4aq1x)6$~l>7AI#Q z?IVYsrh!ACfafK4d)IyM*?YTfV!<;nwhso|f zcEhSvXvVC}*wWWdUaU<^Xjfb?rkH0evHAj$R7 zv^=X!doHwLg&H5qp^rvaNMu4B+f2tG@%kam|FSmzI+|_RPOx3p3ny-=Iq3o@Vkt9I zFGOZXjwi1wohBrsf{*|+{donPxcO%^kW3o(xJpS$DoI75d?tem=h(GJ=KPIrFI>7& z#KgL@Xzep|woe>cy0Q&Bk?1HW!2?GIXi$P7=%@mYt|)-NT>k#_(eVBG-Gz_-^s6H9 ztQU0OFjc^YDjZTYpDgY1qk^lxQxWZ8+X= zJl6&AHO7ipJmvC=XqE*ag>Zup4&RaI|cu6mt0e zha4hv{hjIQ=}W1i=-Aj~E~CM9wZdG`y}dItD1A{81CVFn3*)L5i<5bII)kx@qT2}o z&Ky|x_8b6DUi#iMhuc054qSJ?@mF)U-;P`Q&^i$Se7dS{NbW#_uYv+>L;3?R=;RjO zLp`ok0!;!VirJ<|-hPqH`IotHojLFukZZyHM}9eX`-_jfUlS3#2}PxQazBZie~F}F zVb+KY;JReY0h6qjNm7_s>Lc58VVbU z+-#C0lceY6A%q&xxU~KX^e+o%Zfm^&e+=sd7uzA>pHhe@U|;Ksq}CX6riM%>thyZm zu#qa@ybbW*AulhHRF?Wo;k*Qri(JmXhPTDPkTUlmi7Z@tO$?ZV(#QMX{@nKG|9+*H z8d735oYq03E2T|91su%*M^_ZUU)H+w^wZzEpTGZGPd|P4t9Tzu4meZOr}0PHkkYGg z8q#6Q-ixtY<|yEli+kG!>IR%*?Dvk$`5eFW_S&t+mU)TEjCM0yQPHJ7*R*GA=r03! zrb9i$Xq&jMrp>8a8J06!jYbnF;5z?+e*it92mBuY&;fXcobl|!3e(X-sdA){jOCE& z(|%s#9XhJK0G%*Sk{jS&^F~RQ&7jx&`9?gj$Qd0wrkWyB0~tvqelD`!+i@ewAqCm{1eTHsNT( z4Q6xMjJlWWMc%?UNM1Rn4h){@?LY*BMg!&6B(f4qOTQUL6uakTyZq~V9=W&M7B5@- z%;AsgK2`cz3hzDBH&gZ|$N-+C_s%FKo07&e?u^YU;5q?wz+@Uw zJ6)11EXzMlk}_&tBpxFIG3}EGU_1b@(;_hZ)}slO#sgxQYGA~!&4#VYIE_KF!fLiU zn%TT-j9Tt7!ZWoR6t6mR5x(J~SsTzQHdvs4o3v(5J59=i0A770M^yIRPd%_Miv?1qFvniJOTh5y!-E$!rNCE1;t zmrHVS^P(CBz)yV+z)x%t`=y}d+;rrx=5BxDnX5tkWAGHdXr=8zD@s19fTJr4;4gFi z&C@@CZ)!ct22KYz#Y8+;Lpx++Kx)Htmzl|iRFy(JOKE3W23GX zzJ0o%=na|KclJ2M&AN(}#YyWo?b21(zt7Gez0;U@?9k9?xW?Ml)RfFJn>R2aS4&#U z$%LG&YF~*TZYtW4v0?LGvsiOg?BBgRclZ2#B>zn9+2)<26G=5i@naJ|+*-Qi{XI*5 zo>a0ae&kfivD_=85fR|3^k+pCLfD8cc?LggTwI=VWcxh8o@us9QrhDG0cIQiT0ZbM=^I`@b(DZZr z|MA&5AIx8S>Y-T70iQPXr5B{53zomHps(+Wi-w@b=O|zR@D*NVm**T&yJ!6DXSs#{ z@WjvV0r-KGb)N-VrT(D%g(nt%ZO(uEg$t9FdaIGiYUFJa$=?*8dap1V6fiBqA{kfl z{_U%Mhd(6=rgoBxVcArmaF&W@f90WkXcO&GtdKqEi6s*_Ajzv)>Tm9E4m6`J^pbbA zO|bhy9F_@SO(*@B^1fPn>DGwg}#%W77mexOa z1Ueix0i7r9=oS620Qwj3ENC>|NTY9lJ|U&;z}(Ur-8}%yIpFcl*e+F=OyVoaM2nO} z5>Nr}NuVLqN4Z*@wXiekfcaTD#6QfxKpzb5@7LY0og8ft&6=>=`X@VmbIQpS=CG zxCa)K@mTZ?N~bws+6O!*2Mhpq@pAW%AgBao!eBt$ z|4_<;uiY!FPPrO7DM_$>>x(J>&(CI$s8%n0M4hM5cA{oeRzfS>w8!Ejirof4$SK58 z0Kb!bZT-8c8R1glQ*y^?C27so6{)60z_S54<_tPmrB?~G`ba}F!n78e=7DDu!18jV zku#ERI_91H{O6V|UzERmdHx5B^50pssQjJs>B;iEymw2hODo>ZD}}W_?}OzZeE3ex zhgtZL;2{$Nn2sORc=Wtne}%2TwEl`?PuQ^X%8vRs6UQ8Z{slzybrAsTOuGDbc=i}3 zTD{PfdbC4hHmhW(vr^!(eZ zD$Q^@=761I@{3C^J{zW=8p{@5>}e8%RfbM~(0K4jPtOAMLmD9u_Ixje72B?iPFtC4 z6|hed;bT1f$;Lkq-w;*6+7PoLOyUwrIETEoic~Ndg1&V$#$hsf>w?C3lIG1EUF9ZZ z{k7lA2LW%qv0`}H-<<{yt>tF2GpuC>#LsOx@NHCSq?&D7C0o|rZsN` zJjG4IE}G0IVFa+xC2H3md1RK03*LTc9pfDK{?_hp`sFhVX18B@=Amy|oNxeip{ftP zQ7{fYjKdgQj?a5RPtQAJm0ECIpg^O)6u}^at=ze#|B$j^u~P56tmmnX?&R)PI{@*K zrLixDCnF;6#iEeXhLm%AGQM&*z?S6S^Tq-N>=d%(Hl)eoJvF-ssV(`0-bI&?nvgmT zfBpPA96;}(W0=qw8OfvZ$R^0V3H>PTsDYaupnEZUE1x>p)?KAZt5*FYKE5QrA*nJx zzA`tyRHtjy>1yFCzZNcR)9I??(y?13Y=1Y5q|D_el0T&eb2hfb_QTOGt&WQGpG>p$_zFn!HvC`1HOjN2!)d)WaZw8)r{yhiS7d{T6OUGUedp> z@Iq(i)OyFfPk;aKtK@&R-!29*tZA4!Fml&5G`{3F<0R?VAIjW%q39|h?;Rf-8M|9Q zG_~sF6j>I@tSRGj0(O(t?oq*!{rc-M62a0 zXtQ>++`yF+CU?lBnQ0mIwL6SOf7?SFyWpr}Ny^d}&lv~&!-iqWSoF}+1z7F|$2wac zU;5x*iwNM;{$ZN`O;0cA8v+2IkiDSqDPRCFDqxj71W&J`c36Vl&Wf==I+CKi`DN># z_;$$p8yq}n?b^CD<%MTu0LQKCS;)F8X5-E16iLq&$4RPy>yq>3iY(=yEs>qD6pVx? zNWK>fuR;8J=qms*PD`OZaM=SII3P!%TWtcJGAz*QB-H6ar&DB%jA&_d(%}{sanR{- zI^3ee!Es%VW;g40vm7;Vp|hhc4im>&O_mN;va4Ll0_a*^PbV#DG8O)IVE&itU!1?t zoJo_=8V~*EKbHemR{3m!VNIkDn2psSB!?3|W3<@~ctFkbA7yj=lJuh6m*pm{wRdjgL{lk8P-*ih{^TadXOGyDN zr!3rRbPUu{0K3ls?8 zV0oe(f<921QMsf%u0&{sLI*^Nt7&wcvA2l+Y6Obw&i6Xedek>%av3yQ9N zK;Op)FZ}z8$wb?6GB#FNKQz8e8l5cuclo9TSAYHPM0nSCaz;twzxC(rI!VGee!ZFs z=Pj|nUO{xsK9U0f9$lF{O5#?Z1FABc=Y6^)^-Tb99{{)?J~kJJs5Ema7s254v}#uZjks`_dn7og0Eya=?-c2i59T zl2QeQ02U;+Yu%3)zOZo7*WwoZkDendxxh)u6qL{-`h|zqUW|Qq%a+yuB1#K+}T-_><^9w%e%{Bn=GH`9FXj4=v3C0-IRQp6TF{ zu}~QVD}3SW#1ptLS}B`MreHHHI00d7VncyuF65Bhp)T4)j=AA3OcZmhWD-Nof`emC zd`qZ3Q-vwui2lV&>kh?+Qj+H%f$|Pmu|bJP{(8J6fAA0g9kDA?8aaUu41;3p!(R(a5FSVXA;b_j-|J14m9Fue=R0h5(LRA2U6fMT&Im zDS)pZE#IGdo5aO;H%!$VhDOT+*(7W3D=r*p7?F2L+a6S`ET;z3%`DsOcck1{y0@11O-gU1ChA(CvZV$+=qedH}6)S94GHAq5yuG z+(~_T{@4#K1^V-hd(rkBctv;O3d!OnMOrL=#so0@(59mfbuX2^h-LWZdbMhE(*~N= zy-lV;NyhCpc8?~uc3xaQd>7RL6(0)AtgIBRq19}Hu-$6+$EuN|E!6awSP1bmH9HiyT;IDaC) z&LaSIk*Laadbsb5f?{R?{r7TB2cUUJndb4g8@3 zUd}KP0H3*5@t6LaOw1QU`=2~=F}9~Cw&%$68^r*f@CbW5z#Lrr%e5&B7p5HfhXrdy zR^sin2+c#aKHdd~V?~{?qALpE`w3v?hH_p6u!YMjm>a7$FmIvw4HvI3Dq^-4Z7hmV znkwK$2;7((MR7M)$9!1)R?LUtKmH8={V}@!`~6hF**1^g`*BbTNqk#pm4S}K%k`#v zRLvIAk#;!keOBax9;}b{`|(WW7R9E6YYuKzix!6p*xfRkXl7c=0gp@K?%bJt02S~I zH(PF{NM4%$?G4SgA%&QtII^rbX7Skg1N(n>gE4wd;`Lfz2JWUU?G5uTcr$ZWFc}Gl zTMol>ojbT@Lvdwlk@306E=ej%NGjj5WW=hpEZ_P-#;&IZ)It9b<&DeyH+JF&r8}>T58-!#>YSbCk0YVvX=alTCJVg z_+09qll>&s>GzwMz^eF9@5II3o*Y}eW&Oc2Gf4RvZicq}syo!wi=&rHU)q?YrXlDJ z@YlUvcsm?34u=>UK>=sEyc&}z?p^oPlg~W$_>-|sj9b&!S5;8uuhOV)g$}NL@^2sf z(Sr{?e^9iTG=`y9$p1|NJWP#I`qI-MZf{Qeq5=*iyOcI0iO#?iPynmw48FZTT(|a# zo^`PqR?&*XkW>H+dyow^eS77?mFr?-4|2fe=IZ~C|9Z;n=uliN1VaRCG;|OlRmG@) zfxUJc@8GCmv&K#}FlDdIY~-)qVYE2i4u{2JaXMJh0RTSffPX7ihl6#ntkW5E;+p~j zw+dL*1qT-r55EVXMkg#rI*mIVE`jow4X7o=GUYF-WV=SM8Yut6*S`G2|HKGuZsb@I#*kg|tjy(F< zWA{e`%Q@f!pnyBuRFZhIn<`)oK_5obDZkS)SXWoqCR*wY%Id^9fpu*b9Hn3sEndI3 z&Rf@=yxj z{r$1)Vh?tS?twmP1)7UyBk2X{>6rxx;fK3TU&sMxQzH(&APZoOL<=+qtrDzkKr%_~ z?R#4VhdXeRiZ!|g{-6{HjihPgCjbkuS{p2Hohl;Xv4`JUnkwC)XzncCO#% z@n{5~FLH^hbtPnOQaLm5w>DJ9$DgUrPt4lw1j;tA%3rZ-Q$j*&LS>0AG0y~|8l*2L zV27`b5*UNe7;46Bug%V?1FRzxSS($UV4DOeW+fX9P}@B;_^sbveXJT*Qgumb{8{)) zO|3kWR9U+G-RivR(uzD?ULOAFbZ}Z-f%mM2EqT?|rPX)WzP{O)6CFX!ZJKl6G+Nu`w$-`rkW62I&F zB-OIRKVWH1tt8>wSk+7xuh?MLDs4#0LR$_Q!c-J%&FYSG=B5oFb{S~larj$B+0)(YBd0Ja9$lQb+%wXt2WTUlD)6p$p4Y5V{l zNO8?3Z!qX}iXqk%^ai~qxay63W0uzB6eU+zv%myY@{I$*0dH`?6s+^|cB=TW0vbIy z+-mr>EY+wkLC@Pc>GHV~tsyG_*yd63D&C`LUpl}E&zVirzeuRLR+MqACZRGbakt2E zY;twQ=8c;-Zrr^0+J-Y9>P(W|q(=>mLYNZR4g|KlIS|R9e+4&7%dn{b1{;8T$oiK? zpamR-VCU_6(|{hHdBB7oFW!LxIK&b|Vj$pVPgq4xI^p1~LNgmUA+eGQ-txd9z23@N z51G7rxW!ag=fx5-YrxHkBF9=Kd4IzJg$j+h0m026<{be^P5}sTC<0QSALwomu`Xcr zy>W!m|Gd!^1@L`Uz)Gr@Dqyk-PM51UEMk~4RK8l8<}Kc^1@vDLMx1YKy0Kvs`Lh6i z>@nI1QTSMN-CKovzrSGQvBxIzl3v~ZrhQ&cV+kDuUS)I~q=%O03N$NsLAR@%8T{-Ypy-AGv$j zc&m}*%*(!eH)gMM$G}Ykzqy8lC*me2$l_(|H<-;ca=4jRK&vqdtwvK3I_l}4%w@eD zy;`$*<7zTO!gpxFk}lcl%1&%Ccsv6`Ja5-vNz#=9&#-1lquDW}DbQ$!Z)#lj;CaBH zYFOhRwt4t$l2%nPOr5Z*`p}N@;dW=ufzRiFx6=@`Y=S{;Fa$X$szN&~NtV3mgCS6} zXk`UhEgOKXb~!?d7wI^A5R?JCNfk*bM-(bu66a`7PL?=2_ZJB&QxvnDz#vq?v;s?G z<*cq&LBjEbE!J~a^uR`|&e#pB0GbD|Voc9ti<6|bV)>MnlLTHs z{^|ugbrezdF*=XI1yK95I~PSSkJ^_$Gwi@tJpA!QbHLFR1@Kp;fN|Z3C}4`=a9nuN zaHykwV@-2jGz?fd2r%JN)T9?2=EDtuCwEl=;!m(@yU` zy*o|s)%dGGQg&)Cr#T$mlGvQ7|AEVO;)Km+^EyQL4#8s7XWE(_t`;`Y|;sv3d^8bP^xgxmag|*!}tKD656ihfLUh6)sVT& zT(;HxTIgy#gQG3DjNhx}ISpF%#&RjS*W@}32z8+J#XN975ZLZ!TiTni@B+rX11_HO zm&MRC^4F%31u#4tzF?psT34berR-k`$0b&JbixMO1vQ)O3Ut6fBsKi7t<>cbmY|kS zz?q~@7I4Zj9&E^zrN=zD6X5Nj{g^y;xK#IM|iq?hZ`?G(V#9B_0+0sK`c;2U#t zz*GSPU1NZ+OiYBey*XQ$u)0{jU-4f8@IOaG(0?QZUBVZXz%CgZ85ti9w;0<#8XGSh z8M&Kvx)T7b@pm?ikBr})nm3*19QbH_>TcoPyNP=k3%|o1YJ1N&l{ht3n}4{j?R56h z+N0UN>IBBbJH_1EMqd^nG3}Od_uY|G+qS)Wrp&4L>%Bt8FW_01#TACB0@lj%cZSwH zcgWROGhH2Bu&Gy>h-7ZMhPD>r#b~9RSl)h~ZycZa&%MdJ^#)JhZwoG5zVhFy=se(V zM@{zUov^lBPqu*6qF&I{kQw2rSVFThSnXEITUI_%vkrP$hAf+F6=CU%g`7`E&7?F-^D9Sgh=@3G#x@fH3VoK(_dA$b2 zC~LR5L90rjj9J#zp6qJI2@lkULqPv$HCADP2uA#3r52q?p^bY%}9dwn!-#4r=csmVsO4(JX7fZ70I^|)2%G`Q+fW5cVYrtDYCZ60T zVO^pxF8m*{qQtBzQ$xs-m&(KA)1)|N1uep|%+t+(Yr|U`uBrD;)Ef*#G3WqWC$xq$1($*|Vv5)4qg#sj1sZwE-vj8VpBCb!B{f{4Oig`ey3B_%mm= zkt9*0af_DWMxrbI{;^|ud*M;rlafleZzK86p=Rv%^=$+BnPg>*39o*qI`6qxNUFu} zKQCIZrIPTSY0LrNUS8DH+rf3HXJn6JYJ5fef-xRV^)Tjw%gjY_WQ>F-N!&D`+iEfC zGq3DS+nIKHXWE693zu7Vo<5zHwlfzt<-V7D{PfP;86cCn3a7kvcOmtaN1BLZ^YU=!5n~I_bDKCeql{pL^Gy(D0L80<|(Bb9+dO8`& zgO$MO4^7Ro^z^!10F8E8vU^C-A?5AD$w;4>KWhs8ev(D^XLUy2Mm1bFzh(}-L6V(x z*f1(ucm{!bT}hmqRl6mD&R7c6V-(p1cvhP-X$G3t3}FSdKn`eUaArUF>d0DxOv z9M=wy5476=+b%Sawz2_G!Sav?JxX5*#W0*vbDrc)nL@X`~3(iqe=PlE*>*_4x( znE`X*9a4!58}OG!ov@-S3gE9q0ne?1E~Ypx+DeKy5vKe`5y+uS>bJtQ4|qAY;E)fQ zRg}Pg8o*yc8xr;b?+4-Mo64^r@R}^fgfLlrXIc5O>5&EJLTG`-P|vHGjt+W>_8*02IwHduIM_e| zoJc0eZ@)nvVT|5GgSQSOwc-nVpnqTC6@wu&r<`qVJs~xL=K1d7WQU#k%~)b&mrRO+ z%4uA!Z>aYHBK~%g6X_7WW<}q zF6P$n9@RTUV>izGH90M??G`*l3}F?tMelbq-`$f6Z|u%wVVIE8HCkG6MMnqBgp~Qe zSb^0c16hr?H<|awka4t^x`P02Vod%>5jh;)80cY+a#cQ*se+>%9KVQL=`covAsr5a z(&;p$f&!4h54Sqf4t!1l&jSVA&U=(040^j<4lM{&n%P0zfmYK1UD1UK83I2x$|AgM zkKlw-6!?SsSFUE3Hz_e@SzZfPoNgeu8&S_KkDPa=O-KM$ta-*9Eg+I(t#&kE#%Qx0 z&jgQ0xeE6}cM1=VD)3OhXuHYkh_7UuaPY5LYrYgO;>f~4LWLP)&`nx%=z|f5!-Sd{ zRIEZ^AiNEy9Z_Rx#4(LO2Vo29Up0+CqX(r%w#(83h6TL_39La^3_J@21Q%;{NdZ=^ zC}56;ply;m8573HU|9hRR@g$*x)^#!SqpmB?QC(M==MT?5V>Wy(qAMo;CHHGty z;y({ya_VpHvk?bQL*ffi&{87MFaJ$L!${6}&YincckYgl-<=v8ot`2j=WgNMY*>le z*}emb*{9$_V&buzbpzf3OQ_~KLUhZQ-5CkTZB^QT0m9f0+=17qAC@{4@#jGMMg(yA zk{FT|jwvQdpnz54tyl7DDwa)7E}7qOx885a99@*4OUPfbRjd7stNB?{{QTCOV<5B z;o;V1Y(pCVf)f_PL6NKxFG`hMn+xhrfKPvP%Ay^(l&x?IAd%Tgui+_8o9ql z6-fpQvJ?j11wd*FsP1O#w5YbFIvBIS0k|1msU$2*!qO)kN{BL8Hi@QzSv`$HtB}JK z!En1nyqXX=spZtKnYpsKGz;!gwndlvFJ-W;%xqqfC$b1U#3;}c3Eb@n0V&a-gAD{& z$z|s_p}v__>aVPsHVh!c6Cewz0|<^z5|j`$PYt9&>K`e*UXbC#>j-0{H#` zIO2dMpU2E`!crH7H*5?O=AGY{6|EqP!X)m-CN2xTtzw@I%{(wK+l=uVhz`%J?yjD6w7U}Lx-Y%q8lp#P8Fji5#3XRbS zdPXtgkQH!vSw0yhACyh6LVbiJQ_DY#+OA__I{=g6%$|5Zu`;vE>Y#roQO|5sv}z%Exhi0vRF5NGb-SlL8gB) zZ|rtld0ZmV?J6%aH_gyFz-pAhH~^UI0&&lEse3VcN+mI8HrFgBljtV(J91l>xYcO# z-}LADYITkH?Q4{4tr{P#ZPYa$(>2OpjoTV=9XodHGKgOgy+c)+KI#Ttfa3@ez<-bf zcJX=|3>IW)s$}_#!i)zo7(mq~AUiNOjO+#VCMb=&vW8O$9=Ib$q7T^*DKi}u!cuAN z(c^{yP>A|qD4}N+9e;%G&$6wgMhI|fUWTxSjzdEA8L^~P(K*2YVLi_0^QdrSFpqeK zm*5DwS&O@i(_%=$Dw&Y;_GWAAci9jd_-+&1#4!N@ABWY<8d?i&w*i4M_KvHa7F}gx zQd^QIKS)x*fqhWe0*n*}{^~U@YFsIJ^c0sGJUTJaf;7wlb0=*9)`}3eVF((d%5n%A z2+mtsIK!QW`wb3v^cYl-Gr`nv!!FaFUXnMc^k`2;YoYPU(Fsdvk5)lPR}{ea5x{?X zEsqNq#}E<|2F_Abj&M=Y?<2P@S2k>l`!52pk^^?_NY_-+sA!c2^)Gx^HQ=oyV`C#Y zrruY*y`m4wO%&$s+N6IhVnIyO4XbyNrtL~-Jmr>%; z9hAl)?w%L)uLvo;lvg-HzOgrJ31c*=#Ow2t#N4#Xv#H{~i8O;@h^**83LjhhnGQ8` zhLFjY_$*w-xSRO~d%>aP+kxwR$ zU(VKv7L`Ug#5dlVpEvzG^3APgHTUZ~aTRB;9L*C4ZUX8{(h>{FBf#tqW<4Q`=C_Pt z4%ozqF-y*nxQe(!Qm)gjF@Hvb&NzgygF_E!BrcuDfLFTIax?J$xbffNpLUuoPFi9% znl%33HvWhID2L(g^?A~%4|Lx!8d9dGUvM>Nd@ct(P5Xf5h_hTQrINj{B1+fpPzNLx zdNG;oc1eX9V7vScU)WrW+f~@b8j$_0R1x)i2!D|(B6aP&iA!!tHnnnAoV%cSNUCu5 zFRe2|Fadgbo^>PsP!S_+k-W%Zk9^fbO`|?S;01g-aWx`tb-PIJ8*h~klE~3%kk%cnssxm z+U)?Ts?nqB2Kr(Nw1>79Aq@2baNMe9DSuG`vn2@RthU|No35q)u4y z89z4!-PZ>IM)Fep5>kE0)>5BlYrx0oT#aO8Y(!p#ImCCO&g(S|GL;pjq(r=p}SRVAcwtGnG>r5 zujdhRFr-#9D}aETe>3)TKl0ZwbT`I&W_ooo&L(0ir>D2S+5Jh00sD{)pnwC_t8XKK z)yyWcxcvB)>{XV5fh)=Eg~rMEx50~EZ#MUaYDSlpyxx64=hfV-%N(z`JT>vjN&xT- z^DZf`+&h0H)uPdxjK=&W|3YrBj|)#M%den)z|??4&iO_PvE&3W<*-_Wg`x~pa4;hJu z`dd|ksl!^IY;C=T3Ro_lk|WTHpQOg_K>pI-@1|CidRlEI(Af;gB08S{5scAk>LjVZ z+?1TD(r53ny6y2QJ8r|;C_{XHH89nWiQKw#GH za z4y(;UbHKoAfle{BvslIksFrx%M&r){9}&H@aE;brq3IP?NQ2m=ok|`Vy&jxJNE7h% zWed?h;OL41_{&^Be)`n?eS$}y{_$6+fNeX{{Z+G7La2d<4YC48UH}??ZaX?PHD26LF?984$?Ih7QaTZ^8+1 zd0Ax1wO6x20jmxT-pVF-r>3$C$EU~$RzZ*G*pnG~E1R&zwr0tm4E4#eYRXu{(0F+u zwV13A;Y@@Li%Zis_md=V!LYx|JDgqJl~i02bB)ugnf>F{r7hP-tG!j71Nsv~jfG|V zlFDzdoY87$iaynCZoQsej)hy9ITg+E)#U07nnL_)%dQM->sYGuroY)}%$wX8PvXKO zun~7#TV3FVOU1`nPH*9RS=1{OxNcPa1So>FDEH)xtb?T&XdehT$5mzlqzVY;tF&f+&{S$ z?kUL4L;8qShh8qxLj5a5`kh#{LqJui!L&1|O$}yzL3H94tcc=iBHUBobi#$IR$qq; z4&Vj`^g+?l%?8>Xj0Lvn2MivNp`6%EYod^xdicrAv~q3<%gTfkGzQJv97_EaEASXg z=54$QL_Hd6=rNy5lfm#xc={TsMYN=b+Y!U?Y^|(Xumu3V7>|}Xic@Uer3zTjTiKJm z&<*!iVIvYourYd%Di{m1RG8_t(?~OH!Rj(OYYy)f6fUw-vfz*1r3wryv3q#H8FeHO+d8by&~L`Gy8W-~c!s7g2Z4MS7Q;A$C)ZIN-L z!RL1WL`f%-t7O{Y+bq^t2I}dS3H( zIX(@_n0i4+6>xM#0sQ5yyH7v;t@{i3rzgKc1?(z7ZdEBUXjH)IhL1=j%nXvP#07{T z)tR-Vc8Z*Sosv0+egl9{7`$GuXf!fn=;VBnVMVTsLRUsDNL?C<{;UK0ffx#5S_Rz^ zVm7C4%GjICiJXJ&5Sc;KO*i}&qbaRqr%5!{^=S-4Ipm$%=eBLzo;*0XZ`<~g?bWZ4 zTq@Dg@%gzk4e{}3tc>x^>XPlH@!uyUUMk>+v&or#@s*XSR#Dtsxi58J>Y1^hd-2_Q ze|wZ9r54xJ{K{$+`x9QyNT}I23JQ3@o0;>@%Qc77c4vr;vGqHNXLo1pBdMa_d&qdJ z_!pbZd-iNhjfuNd++@~*@CDJ`g$+pDj9iB`6GA~u^S_uE)|xk#-ieFTl`p%xGC$@U zx0nIVO$2a`vfBvxNhW?4-`(+1mJ8JH-OO$H$CwzKppod@beX+Xv;HY?o8(yh36GF`ALk@ki7*jHZ3{cKHO;!dQn5_qRoJz|j>2@RuDTe)^}U?$dv$ zkw<^}^wW=iC2vFN1I|R@INO;jyKyv-u^bt|fQ4$?@sg5U&3j{HgcRY3h9sLaBM?#;)x9otrMk}*2{pn#2omS9_(DJWV% zl&7aR__$Z+&w9sWVzD}kNjE;@n&KSH2 zq8tw;%xsxDbnaYJnc8fgndt@ms;TK!NS*^MGgvmof(_;}vo^VXuN7oAEI2S3@Ox+o zS~;W{Bd0TS2u^3(J~A~nMoz(j4TxX-f)`YHI(^uWZ+^Is;lir40fqD=Kt~nIW}0}(o+)u^%-m`OhuZG4wst${Rh$LP%N;=;#IJ|id1x@P zYjRnwu6}r-CtB6+WLgDn0)5=p77Q9K8U(P{@Au!--1Jj_F3k>2pQg%?jw0Qkev`LdxM1UV z=$*#k@l&}DR?ye^J3FzK%zxo<8mxMKRh7o(y1X;ZWuul}@XP#}mv`>G&{D7W`!!cu z@LpH+H~n6N*OqoU4X(HJ4T$|M-7mj9e|~G1)9>}3w=n(L6O%D9dl;iw)}%Gd6Bw}e z3QM7B4K#J(fGeR6YRrKE7A;QW$#{+dMQ?HX2lNVn$K@Pw?ogx8cdVYD!X0|Iem9Lj zlc^CvFy?@12XGZmK|&WST$zF+A$#sLq-g-KwT0I!wp6qVT8Pw9DaBY+AM?235Up*d za1|mNmVOCJI#*65Be?A<6B>2QDTAIJ&>)`ze$meg|Ww zupKO&UD%DYJ_S0$Aw8k^XS9697E#3r<+dJYZz1 zaIcG(Za~{+%G8Ln6>Kn>WUESLbOXxdZaOXakX@m&JUdt~*I)sPabSWf()}x+>Xk-f zYOH|+0qwN(3K5LuPdE~|$;u0n0YR86#f8Cco0HCQUEEAiq{&T%*HEL*aqBo^gFQs7!$mhxmDvUKtC*O{l!8s4K>K{ z&>}22rENht4GHVexD&1b%O%^`4p6`}4=f?b^|A-0?1UxJ=3dag$aA4CpQP2{F@Q#} zD|3(NB>=uk@W}Y}(0wD&GHBR@;|QY)IJ%+$j;=qUfDhOTu<9ogex?Wp1&lqwBV!Xe zV`JoBcLIR%I`BgQFqRaJkLQe!CDzvsP^Q6GTf@9$=XtC8Pf&NxR<&9i3TYiqivr-> zK_~nU3gDpK5tMEX`cVO=_oW-sLAO$)kSf_D#9xIyQ)oI#m&P_|#IH8*aDAv=Q)f^d zt<$UMBMr2xdA7w0-y44WWm9WV#fAaI?=0Q{+~)`J_Zf{AyyEo^rj5OFn~-=AwHup0 zYl_SPM%d2KS->cN)#@(F;tmkTWoC1eg#x&B(22Y^4EQ_0Pn3i@D&XB3P{334^Vs)q z-PyDPOX>Im1q??Um<7fZZ~YI`?vE|4ru^fj`<#3KM^`CUpG%$@_)23fIw`a;N zMtnc#FbQ_5faQ6>l*_b-DN+zdYoR5F8c@x(*9X`D02maoE5HR@Ru0>cG&uS}VsQ!s zwjt48YjmL01DFTS0Kz~$zv{XNcr3Ru8Ujv#G%WX)Jwp9{;c@!ID5W8d|?R8q8HI8ZEobi!Fo7bz%WboEC zjJO7!))^+$8^R*25Iu!6yo@jog_QcN-p|Z4oHk&w7?0;<Wi>s1_v8@1$vHY1k{B6KXr{7R_NOH*s*;JCL#9a&{& zt=Z{p8;mEdMki`$!+^K$buv{b_aVV9Jj_%0!impzS^ivx(-E4wo;aL7+*gGbShNVM zub>YQ{IJkmb70=*oUmTCmbv(d5v6`MuB@lFR&p(sJSG^v5w^hCR=dd*i9VYI!K4rv zOP~ZL0gR^5CdzXO=q(H2NDNv~SsiMJ3{EV|VmSw(R;`R$>b3>k>gxbBE05C>{u3*p zfY>eZCY@?AFZh-sUlJ|!!YHqvw)onCye^U zD_2-!Yc4iGp)UtdHLHfV^~3Y=E-StfDbj{Sov2aCH4y1&sWa5v5=$-Oxa0ONPkU z&vWMy>WT$w_--!t0b@9owjqrqx@f!?BfX%2b8_2TT5&EPwg5$N`$r_Omilu9;M27+ zXIt$n0#Y;>Js9IBcU*AnEM)DV+ltmnaGW7T1YlLf6J08}63hv7+@b~F& z865?FoXXS*ccuDPk+|3~?630QD>0)HZER$s@pd^>Er+s|Ga8OY{|zS&14d=NBSZ+L_EI1<1rsT6l%xAL)xH=>-qBHiH6=SU83Sp}1l7dG+9R=IhY{+f14Fx`tg zOS5rkoOtv($*RPkso{ssCQDmR!dVFzX{Oyy@JprHiS^h96$wqx2~cBHT9AZRfe&^d zf6=f~?i!Ms;m`o58qxY?J5{l0b0H5*h@4Qdi`}~(_PZ_Z%sCgWf|e&Dp$jJZNZY9( zmM1fSEX}lXfOso?#Q=4_IyG?Xrb7R%cNej8a#C--ngZ6t)`K zC>jR=(-VREV`0*njzi-4z2A@KfTJr4;OP3|ig-a6Xp{u-usp4&%F{`UurOnZr=#QJ zV`CFzIVgum=S?XsNI5vKfmT5)V+jpyyGKVyCtun2YHdtR{&Tv#5AyQ!7cI{_Q=0c~ z-ip$9-(3MGrQ6>v{m%C7->H80O!aj3E7|j&d+xdK1AsAA>h+t9gF%ytcMKW_-Oe_P z6IPp3IdewN&O3unM|U$^2>!q9y$w`Tce?M-)*WjCqM|_zC`D}CH0%;zFqROApb|@y zP3R6*niyJ*qSUl8r0P*bK}NK`B+6+s9i6t;&cLXYbB|@UbIv^%?wP|h?HOpNQ#`|U zI`udOdwrwrvbMKF_y6}iza6k|v(8$#_Wxi1l^-#$J0#f%pZ$GazKvZASqd)wjXhv~EjO>5ge%@~(ps$P-fn<8eeV7;KN~-#~jH(0_i<q4}ZnI1#1qw(~SuODU*Naxq{N84UrB-P<@MKI!NIll1m333;(^u_UwOCh8$Ny~g$ zTTaZ`^0cgn@lW)LY%IZoe_#Vm7+ly*0KE3uZ{~nYpa@GI#W3n-#p4KHg%CBDlpQtz zc=e8YF^q{|qJ7)^HEm%4D*>$0ZS}j2QKic@wKj>0z0m-*FH8uDAMf&*K3d;C^G@C!zA54lYq3Wxk)%SMe5uE-!Zj+B>!chfpvQVTmE={|dpcLlrctUtn;H zX3mN2xra6^J3edHq}@Yr}>QHhggWgX0Iunl)?P z!Q)Rq`|O@C_BBEXIv5Ey8Vrq&en`P$W7F-689QeTW;40Mc(u$ow=$T6H1!Mgy>0ei z3r;r9){u`WyKZI^!3-mg;r(Z05gArW2QE9t^e-yl340!U485Fh?NGHovbJIE{mZhJU0Sqt-Mx>`y7%#0&;=~X0M4z#k~mBQ4|R8we}&!WkN9uP0bj*F;GR@B zhvibbXxWrpUS*_ak$cI-UR1ECiH%0+{x#BeBmgr%mgF^xO=7glnE<^aa6OcXhrt?7x_JmA=h0XVk43&5BI9-=kH7wF*Hq0C_R@3wA* zX@d*5F4zj!Zry?#3vb=JMQ$%#uob?xlA8+`91M7{g+728+M1e#v_Z30+e)*Y+Cgn76q;C9_sc`8Gq&^Mob7Yx%$YQ4 zYJVf9fXRzC9*3h9y8iahPGvY`7a#TA9BNtwRv3#vYog^$W(^zu*qRAEvons}ZxhkkBP}iXd?TwSZS0nmOYv zU=bLMvy~`*X{r?+HfW3)J*PApQRQ_w99}TOqLYyDPMF7lqY*gSkPF`9`7jNh3vMv_ zs)^=+c?E|x&0qqppcF9B)TOS$@X~Km?m2zL8i>k(FN+&(r#>T$6JALdtmz9_Nj-06wX#-wa|A|f34tIL+b=nwh*ylf`PBYJs?Vp>yWlxYm4H5%o(GEEuNTSie1 zSns82U?8~8CyQY`2fr&VYlS|ckUs=nK*-+FN~wJ{H9J)%$%!Ppt*xHKwalvkw$5Y>Xr{qT&|lgB+@3 z9j$`)(Lybb^0z4qCL%%Ims>>PjsqD$0o&@a`k7@#%mEXYi#W&-YONr#i#}L9B&0v^Bn77RgW%iX{pPkY#AME>4RU_!EXOFv^UJKLRYxi8hV z69ON)I+fcqyvzv2#-oK$}<^GR?$2!JWwbHo3m-@bJb;|q2Cw` z8lmV33$$^1w)#I@oaBRf@99!R`fNh$gNaQ1O@_a-EA}u2x(rAV>L*1H8 z0VS$sZCFP3Z7Eqd=M)Cy!YWE0E3A#s@|#tH@nXBASEIvge?YkdgHo zAkYorZVNd%Bf)?t;&yD&wP3{+6~Y9@9$(X`^$`yd$U#U!lYd6D!5B^d5-|?#z)p|F z%orRF!rT6KC(-W&%LKU&ix(b*WoG(E=?kA6yQ0C^!-Iz=!63YT%WVx$c+5ZqJk-7g zF9fSDXtIN^YG|mu3WLwx7s%)Q$lYcf3U(L%;=Ii|=e9N^aKa)0o(N4dg0(f2YUJf| zEKKYQ*p8$dHMoL~B%??>edXM)K&7u7gO+75Eq11NV{?*h{|xOtZJdJgSEtj6VNkoN zvg{4Hc`c4>u-bYc2g@F_@&t*X1qoOq?)ug`$j4&!GV}_O8w##&u#Qtua8eBOC}y$3 z3I_*MsVjnDrnf~pO&FkyqE|t- z2k0T2S!7dD*&>IKTcU~8fRR8qK+)@L^t3zsA%|;mGJlyc$tt!jT-N{YXHAWJ_VusZ z=QJX;JaX%9w(JU0h3!IAY*$5ldLcMX`=#jX4;9kR-)vnl00#s?7z|-HLk*YN&~L_+ zve^*<-10ie@e&4O+LssBnyqTmO^cn;+;lvo}4{qNuQf&kW9 z|AWJ7E4H48f2`Io(uye^fue#CG8I&>21}rD1R;Qw7i`GVvCJ-TlwyNhIOcz@f(0o7j6&C)zNe;02(AIj75SO4}`c!vU;>QkWn}<;3trE zu+6GXg%Yh0Tf?LN1<4P3A6%bl=oz_-k!En9pK;2+mi&qK7mQif-)t!QwL!;gyClDYB6+~u#Y-JQdt^p=fVCRg0mqF1u?ay z^tgG9!J@-sgm3p8dSXNFh7HTy{f8E|GM4__b?w}QNxN=wyB4}V?Y0e1KYiRCz!st` zbiN8kjjL#68MC~od^0asRZ%A_Wbl)PGy=`NYlAM{0Q3+Uk)IJDDfx;-EQ5|A=mqi& zMOuOcyKszhh3i^4Gv>FZNFGm!z$blU-5!YY}4GiW%u>*stOjdAhV8{)9 zz%eiA*opx-w!XEZeZU%Dz+*JBZ5&m=7lPEW0*3@^qAAzRAPoU$qWbK8)=iXf zH(<7#9B))r5glAeBygrY2e_)LTa*32JrT|qxuD7Hezm@R>erpHCcI)5CfdNA$}dwzjte36({Hbm))I#%uHkJ2=0C_$gE#vaZ=KxCbm6ggPH#I(Z0UAyQ zU5o%m+h!_;6|~_9Rjx=iFJ^g>*&5L&_XfiSR5xSV7)!Ne70uJcuqa~O8J#uc`e&8a z<_@!}ODgF96|}Stnuj!S=!h-E@{smrQU5+kK6MB@tbKI6G6gTTL}8H?&Mo9YF+&9w z5E%CGnC@1zHMO!fg%1^QEC(E0F#yNb_bT9_NTl&2QEWi~S7|b%Ly@Ygf>G&-(O+zf zp?O$McU1qj&@Nz{dypM<#mc4t0v{-y&YAo4UPz5TJ=3@`*SUSq_NQm6o}FZggxzkZ zZNsu7jUOy%{2+aKaKs9BYp@I&-c;dv4S8c>hr?O7CCli5 zTCZR`(;o;xds2Y#*BA~v6+td{#leFIUpaX2gzxxF-S%Z0zgTuWmun~dl?mKJSs4f@ z{Dywi&+Sf-zK(kTdY0T{W-NR6wle)jFB9!Yh6*gIe4`4OTnRX-@TK^bo1Ox)0>+%L zZ1P-14kI$j!2#hgcs*;nhq{A9kowJ(E3mqUva+gtLoGu?-GznS=iB()Z&X1)Cs^w^ zu-xzy1oQF`B+6Z0?mj}BDY?E%2Vz(^TAvkdKax$PjdUO|`a?&kPqh3v-3W&XTIuj% zzgFPMt<<;u*o|bJV}08VnN(FhuNB(ZP(92`f`Lh>eaVWzH4wmDU29Vor7=($n28hy z*{GlaX#_3AuCY`LLe6*xrg>?iSV8fN?ZH@QMH_;BXbOocn074j@;BtMe;92zvS|ES zcI;YD>#wj5TE(UTe~I*^`ClmKf}0vdE#%X|a>GZ>EYXYudXm5=ghN{EAlWOz3v*DJ z1#xJFt$r}%R`41dDBxHQIJRN{{vp>Lord(qkDUX)9E^ksh8kPOEE|EinL{-Ao2en} z14v|I2sJzExGeiy$PC6(tZa@JQpxhK@%+=U7CtTpJpFaIa{C|K=TvN5cq@1NEH7hm z8taZvm@wVlxN(^?qH8>~H8{40x`*(RsNTzPN-BSAT*fU+sy`s>A#$v-B0dvM9wdgKE8Hs!Lti891GW3Htcz3`ko2WI$MN? z-e4+$J#;owL?B{0;PiOB25d7jI~``mV6@;ZgMpxymOo=C+UYkNEGU7YaT%n(#Tl)= zLa59BT7X_Su0gx8?m|fSLNQw*2w+WN*4-CS+*grDsQiV%G-%=~7)6nJp|HE~ZodAh zJ-1gue?H+A!P>-O=2uiu0gOrD(ILM?>hcO%yir}Oi~3T^sb7de(`>H*9Z5!`09DaO zqmlYkMy)vT+#m8==`=zgjOg=XL$Hcfg;cEdNE0Dh8p{#@AGHx`VPKg?vK0}dLJC(13qJ{iH76!vLo&Y0Fe)Ak}rFOL>$ z(ei5@z6NSkkiZu>t5#*p3TeT-OUna|Ln=A{3&zl(hC>i_<~S(Z3aPB3JRKO)=&&0_ z7;(g5Od4X(I{3#ysWVTf0n;`l6#HmO3CBg`#clP^O^7Mr*op!82VDPung_hcT{sjR z3V!5~Gr+XEm?+%f5RM%x4EiF0up{gYJDg!-B!Ue{(SZjtZdeJYK#SW zR*#3vJ@mxE;~TfS8zb8nUVC)=gcFT{6ED3qN4M8$zVh;|3F~H-g}mks*HX5!!3PSfkP6B(DtK8%}R{!`5dOK7H@Tjq3xE4eK6Tw{hdFW#_Yl4nxV> z9jkNe>gG=T6=UA8VBEL`GYw4s#fkOqsdG!_rkOqOUfo(_VA!=qc^xNDy5{CimhY_|= zEesvcck@EVH=M9up++3M0u(RRwy1XT0-d1gL?oVaHZ5_shuV4%V zf@yCOb|wk53K}gcWw0Z*K>>SJW1i4nXb6U;o;E=%Gq1%cJn6`CyG4VMcC_%3+%I1?h=mS$4J3(D{P2c^Ky~&{Q%?WVv7qTbg{>c?1`- z{{~EKg1j%(KV$xPy@;(;Zks$2A|xPLeIX+FIoZ+*rwn2TFqT(yxG?_<3*4bOta=t< z6q5V}!FMMPNAx%xMb2eKLyQ7Q%|5Oii{N z0gf06bs+M}fc+zwPlOS|qt?pUfkc!ZYQ7c^wd5do+9Ko*PovWl=-+aquJMEGljc1A z@uSAZEeqFe-MDPyZ=I3j6RxexXd>VHFAJu(G8-mXnJeHhY3Mh6+hCHsfxj%07Cg3Y z-SowNbN{62(-%x%a7}tCaM{6RNYafZc}LfNF^#!GKiQyR!L+i}vIHqX+R3#4PI}1t z)Idt_6zP*Gk~Agmp@|dcG8?Wh`tljKM-G$|0?#d4yW{yu%+#%A+g3lYlX)~@meqXq zvlYxES7)U#Q>V`_VW!{zXxgt97Qe}?npwP-$(XckEwiIymHnxwn4_!bX3Wi)%2=TN z82X7Z3*HilWRK3c7;RO?e0HWLsKfF0LEq&eB89t$s!$ly7<|>J4;HPMzPmoW?`u`i z*A~8FJ=z9*#mXy%Yx@hK?mn*bDE`#T@-0>R@Ta7qOm>gShvMIEPwOKw|jtq@M*nXtb$o^MH zvK%OX+0^sMU)p~ZI>y?v9LMNXW1I-gi6O0(M}I3UeAe)I1&y$Py)ab*cCA$qMn_HH zNM)%00+&kcXogrcd1qPN&X@v@tr&oR!1cw05B~j~{QiIc;Dew2hzi*DWMSqIjVaR< zEFFrZ32F#^y=I2-y2^H+T>i$3%a`xo=?a+{v&91u;6N0?5Qmmcrh;-+G=bWA9g&w@ zohJ}+p5MCOxiQ!2X{&1wMBE#eZ8&~SS{4Wf_}qgFKc1D^-l%(tcfQLxBkhfWF!U-# z!tKs*pxq)HSz^tT;V;+kH=9Fn7+_|+M#WwWv!4K1<6w44H&*85&9x7l9Mn#o^wgwD zJG5y7oAP!x?6@UKWsGNov}2+q%{ciUIlM`@sXTcyWzioD8z$_zwsj6|9SXDuoZ;y! zKU{o$GV`W1`~F)}9=ViU%mV2~>m!o1guIfpgLzL%=nO5Al9{8Dl)|i*qzXoQ=hT37 zV{oE0|DnawV#Z=LTAW}f?Nq>gM!8i=4nNBQ147z}F-+t#J+iP^9L_*wsF1c^VS*UA zTa`(N5rP25VGQ5Q0fPdDiG$HG3`k#IA^SfIg3%gcy@TdKgLx3Y%xowm0D8k9bY&yT z=sZF~*&fzGF32{rIi)B&Q7T4lqABN%+M}X8_@2GQs>X)=wm}irB@98s<`GfR;|ME! z#!G-1YlZvc!-I7E%1_qM>Jng0>bxX)~Vrc)8-4mP7mG3M;U4mb;JZdssi= z+yxDf8*AuOuw7TAPlS;SoWN?2xE*-dpydgF!9z23y+EkzW!>&ez~d0qUvb!fqzYkp znWyAc$g_Px^MWm>;|kfGuuHF)udoiQFlwre(50gap^%!^XmJyth*d$yRt&&DBp`ot zXJ6nq5B}YcmjfmM9-_8V^1$4v1=VHo#8Jj<-SOh##Kc5(l3JaZlyr~M6u;Z0W%?Zv zBz8-7cGOo2GM+=hKor7QfYtc!r;`HC#zR|;LmLks30MLj>}^vLmCBPP_L{V`{QNX~N!|l-wbORbzbfqp0MFeo^%lRc zl%#QI)+oCkc~hF%zv242g_M0NOq$O>tfMTza7O zk!!V*zCs^GawY|c=RNYt(7^Sa+)tU!YCHA~cC&}8>VXx6LX4c{8AyPOT79iDYRLBu& zh`l@5!J4{>6RlcrND(c=Qi#z}gk$Mop8!Qzz`jca!Q`J;HpF7E1&sr$l*4E!G9K${&ti#fxl~)M$FOT|{52^ex z%NP7apz>KqyMKYGqSbN5JP1F!O+}mjoR`;-uN^d8VMAeo`gRiKuY(x2kD7Hrbegj@ z#T0OC#Q^*Ru7AGMA>w-<{O2D}0WWlGG?~;sIXkmzbXH&0ki&ARreU5kDN(I2Er>5D z&=)jU*Q!l9>e_jEEMss+hJt7SolW`MBJ)>vwZP7vNMOUqPc$96wmJ|vG+{xVd(YMN z9*^z#tw)bI0|Cv3jZZH)m|J(*vr#&@?D2z-=X&1#cxL4Ir=M=U+=6n^3FCpiijO=W zDMW{J`}Ik=OCOb_A{8O*tfe!z&Zz?h>}S?W(<+kV{uC!IuPG^Um5`NRvrYOWZpys5 z_e%qe^N^IWR+>C8?@LL#sl1sy@aGiiq5chv_Dsl7&AO?aJ$u?DqN*<)hg~uy-}SlF zD@mJr)_t06KeXr5hg?(FN!yOTvgodg(B$D+uKmN(1KM9o(!iDHr%c%~I9Yn&oykks z`h>e?FTL@QgJGDppI1&!S*}ews^|puv8n;YX^nd0!BLPp_#%tFW9|;HC3m4u0hwc070)@|9|9D*n?+ipX9&E=a zwEXVY-o_8M9$M&bfdhho#Sm^|m^MXYV_S$34qg52oawiuIM+z$v675oY5L#)PI{{4 zvU%>TgyP*(lK+%=*R-zu5*Im@s`D0}q?@lrUUy-QcFgYwJo8Qspa@pUkP-%IiJP24;z0py@*lX;^j$arm2x^j5X+y_Y zl~<+pbEu6&Slp}-BV?PIe=Y0kun(+QrFDpkhyv@Ybf|(Al&Ct{KoTx+;1PBO)8-+p z$f6HHg%#eRk?kf0t@V5x3)6x*x0TNVZxD{7+8X_+aHtZG9mCZBSKW~J1 zvkLeN0d%5&o-AY@@6Bhz(~9MdEvsZW!$(>ZE&&H=*VHSuMq zm@D28J)|Kb80Qa*)Q^%nVZ{`1Y{dZl0|NNl$o%#9FnRdbk~Hq7^!*S1S6|_dDd0Ws zC&6T+3gvHRCiT*YI1J{wwTTa(I~%VD^&4Lh-&|lK048F%K%bsoezstfnYl6)jHZ8~ z>9vKXe_PO1DgY%&L62wqq6rgrI9np%ws8%V@1bi?@0q^vi-Un+WX`g6TNlpaJR8Xk zbWA=!;oyd=PrbYFAE+rM0NBFTwKRG}UhDqdqTjkVE|4m_v}vdEpT8+>{m<>vvcTp3 z{fl~coSbq`wQ`Emm6lJI%kD}mz7eOqp`;3U%k`O-o%{Cf`^Oz8H|3q&eKK!VSq-yc z(e;cK(x$G>9UUFxr3}Wrc;>X(72A$x%${A@(XncEM`w|1)$GGc*Q&1FbG?(MO)IK@ zBQ7q#EHCfkuXa6^T*11!Dt4B+Mh>qWNN#9w;${PlZ~a& zQ~(D8!6742$Sy+PdlHpu6ZujS2CEN{e@XY;b5HH~8iT0S)z#J6F#qD9Akw}h8NI@7MOfq&KyQj{$Pscl;9m$X9S*@J zuq*{I3Si?UbIRnJuev(AItShiv9t~g`-gZ9mB2dMa0E6Mc%h-hMP=-x-dD5;8vHM4 zh+3WptPw-jIjKx)mQRz_G^lcOT!)T41Um%dqnj3(^bXUr#^Vd^WwHfa2F=A{V8E z!SV6u{%LuM!5j|KIle8l_-fP_8ashK9*^d+k0*&+zS!XL{O;PqI`^K1M?AhQ+xKlb zv3<_vV8EkuZ{IlG-MAsw36;o%R9l|@__u+qM{RWKQP^OC8d~Q^jUI*OqqZ+!QarU% zk{U)-D%BIxw6#5Rq}+hUa^%|UzL=k{p7A>W!#dy#ZnQ|`0n*t zM?+0@ZsFqM;o-$)SG=tEO8uTik7itr+q8Lk&YCm36A}guGgD^F-d4oemD_%DvM9gA z?kZBH&9AL>mAHy_GI>iX8`#-Xl!Iv(H;Kd?oGGmEo0x%2-N}s`y#BXM5#;flk0*Zjpq^?a;=9mb56V-&rr3LEO zl9sauuW_hwC~C-&SqRlwgvd~Y^$joR=Z*?(9H9g4^`#?_$TEhsX4UefL_%DBwW*Yl z!qjJ~Er6wO))zcnT3s7&AH3q|2@~uZ=^O@QkI}2GSkcvG@5t-wD$Ym?(IH8aM4JYeN)#+$BHs7`b=v?!73=Qpc(zK zun1Z<&hSx}Nk!D}nS=gdc{UQ3Z~18Q7&FA8%3{J2Rg=_#qQrAHp-qgX84e)9T&4|!Q|P?*C=OC`|zez)9;C( z0*=5y;B1ALG4IYfK#pQ+m5J(FHPOGOTD81Pr9Uk%Pr4`Rq}l9%OfgJjkc+S&8GLt> zf6mwXfIpw`iq-12LD{WBP5@&sj1anF-mUICvpoGwdVG9AX{nwN*pyRUpf8xGug!^1 zKePNye0-5=knI8E4RqrOlNHK;XXaO3u9Gjm-+A)Qd^VL%D^z^F3R=FU6Ny}O5M()6 zB7Z~VjKzOifp;8p0JC5_2eW#(V`Ov3rjE|{f07XjaS`%n9gsPuqZ1U=4+{Y-J8;m* zG`9Sbt91U6>`qBrgJtVzqEo%BL*N9k4pG=R9b|cl{1$PzAtG4Bj51E}1^(KyQ2(l; z{u`|Jh>a2%6!0;4D5Mf>WMdHux-fqX-Mm;?t>cL-HfuL6Z$6ja9N(-a+y(7>`n0+> zr;jM$^5*9B^70pQ^t%VmA=szb7EH7+uYq&Uw(6Cb6IN`+0DQ*)Tr^76B8)4~NFkRq z7|^&09~Ltojw@oyif1H@`&N*8++^nFhvSyKS6sH_z2WbCh5vpZuK#`~bHICSPiiu= zGim!#6&6#O4Ha=Y^XOX|UQ=LFD@{cEmKNwur3K_fBkIG-^z!9qgCi*WO~~YJp>utq z2l!pLC&J}!+_*8<7>KkTTK4GieR~6*4cC^vG%0u8*1Z=dY<=|6^QPI@MzI&E1uevFoJ;(Y<+p#_E}m&NVX`Qtyjh zn+K9ky5{fDnu|`(9w=&H?QiZL$g^ut<#*XxRmHaPsL6&2-GsOtJ})3yhQ)P_&#dE zp$L-$&W@4y$B*B1s_Vnm1i%V~4mzF4GenAC3S3ckqC|rZn4Ux%lBhoxErG^jXsqo5 zX$fMP6X{FB`*4U@XeFwwG;z$~5JGYfYUZp9guh&t{2r0NDu_JuZbQvf znYD^Ix`D$gGYxhQ?|d#c4Jo!_0KRhoCcGWTyhrqH5j2`gQc6*g%;RxH2^Y;M0`V&q zSA6sPFq4@Xb_urso>zG0zWeT7y7b=r?z=M@II4i3jQUH`Ue&OH8AvRjH+o2*JQp9I zZZeftn+SkwP4T1EOl!)M;yVqFmN8GtY&2kuIzbZ#Yu4R5xNPInmpq- zEx)WNpJ|x3vgTL2R}QfGWep`-dqr`B>XDAO>?LLPixVzidfiE=DDs)daT z9dFbU%m^a5QGgEx3Tap{CP^-BRwynJ0GD-kojmz|S69kvEdj7kxFqmyvX!8LLM3cN zQqXX-Le2!!K}VPh#<{<=`dLBa(>j#5@*E_QXl{qq@31J!u($>&?46^ zp#H@+UzJuw-$|7hQo&&T90CTfPX!Q%*kh0b=7bOdur4|Q$%m5$MF(S_mtOvf{M(@K z%Q=v9njjbiaH(GZI^C<%&Ga0#%Mh|s158mvBhUoEO|Q@pbnFjjY{dY4Cjeabz|#;H%;_s!tIBp1t+LzgW%d#xgSD!(RTtN;U3+nrJ>OpDN-MFK zU7UKcY?XcIsVo+A z>RM%7RD&t?rjvu-kN`jx!p0tdcxS?j&adoU9UYw=Gb@}z1m+j=+!1JPk{u~USpoY9 ze~H+2$R${`7RygAS#3xVbzD$jY2KSylC^SJ zngN%^OflS^AKwn-tX^s)(=awXHR1@HG z=#TfNDJcqHSo+G*AAE0lQrvO_Auvq>%f47yP5!BS7GC?h7xd944)7?_ISV{5c+Cwa zQ+)N<{~~pBU(UauKJajLpGjX(t&bbiVAb*J-DYh_R2YS@&=U?j>wD*`x;DT6;>pf| z`4bgkK_Lo$zrb@a$U#Sk1=D1(P9$29cWAZ8u$dP9sN{&WLx3r|g5c*lMcCN5`exAx zXzH%6m6Mu`MupG8TAQp*f>(%|Y$zy*Ie8cZ4M}U{Tcd83ict!S@_-{BcG+IQd@l#& z1+^Pe@i_BWo>>H6!Oj6}j+feTUL8*&TY5SBq(Q311780?Gaq$7Vt zmdUHFP9Ht2k#5wUR@V~wdm4(d`kK$(HTp>MxunQ*My^w(VT|nDlAF92|{A zRzxrp{_4-J8Tb?WZblmb7ie72j%4G%H4pf4L1?q#{2es? z*NH;N+>oS?zl{`9a(a2GDJQ42v`=rUZhql*0G}z)69QXBF)Tn=u%muf%2!<-MFSnD z{=8zM5wgkJw6rwVdW7FAjyh4&;YnJn%|XPj5x)dKoY5OF`^U=S(?rqOI8(Yf^1gjj zN7q*=E7~IPU4YRcZ4W0~VcpgROjR)S4vlsRi}Dm7jlx4@(dwCqv1JP2Ca$ZfMY8L;5!|H9=8Om zpon3n|;7mRKQ@tK@=x1vSyb$srupOxUs+U z$@*r!zO?TJa;DeEH{Uh(GRiZ}@zq5PD~Qm9)MNA>osp7e-*hprt-A3g8sFS3uUg4(A%9iA(<(H`ZLfA1$D(dVY%YN#^N%cmB81d1` ze*%Z|iin1#G3aPb7G*Low;_qxCM@5Oi4AQ>vfCs;n+{&MU}X`&U?jhMW z0Sq>d*e+3t&dd5&14Yy!FHyiMbmj;_|8g3+c1*B=-3EDkJonF(vaMtrefjFOu_CM#!|~~kerDp$DTn7R*tNebL4rs_^5(%)DyAf1Am9G8VWr&09TSf>`C{y4B>9D;J8qjIYc=8D&M~LYYO;t zqJWROISukxA&NTQs;#Nc(d+w~?->JdTyt}Qo>pO1mp1?WHZ<3!6Q-=On?s_J=wHF% z&7V2H%U;y+=MGoV|FB~TA$W}A z(@IqEw30LezlvWMxjM@Jyt~7dl2Oxxt-qq*VU=l3#~Uf=^jwZM8_5opa$_)k2-3p3 zXfjwsGsGMXM01$z<*XsBxN@j?jmT;pg3-ZR+lX@2vMPs-gE2>1x&B$?s6Qn(`_d|I zRVa&>lfhIxodb7eO}MRN+qP}nPRC})w#^PZw%PHH?T+2CZQIG+=X__}Kd{GGW527a z)~q?_0}9N1UVcdu%l7-x-R9YJ_ZTzGGEjc0*&_ip(MNdyvmT2_``#b^%sJD%HPyIH zE+?UoK7vPKn7~}Y_A3g9rl|ZNC9EnKduXQqE*Z#`1aMyfbi?3;%SDlyiW?Z==_JN~oilN`XoRQcgu@ulG7~FU-&lO;EtA2b-#bd6==FR}3Zwyg6A(Q}YhZfy)Gb4b#gS%Xd zMVWy!E3;K7-q+dOaX7#?gyIwb)wxZVUp==nJT;fndaYj+%ou@V`^Ql(83&$;lzL?% zsz%mC56)F-uOwmUNR#zzBON0lyeRTd!W#&6f}rCLlIKAvV%2VAJbQWh3a=lcSyXbpP-! z82mbZrPNyC=!_=K_X5xd7U`Aa4>9xDTh~b2k;xlVwLp=`+>A<#NMRIM36foa>$rE374O9D|s!Y`&`|=8S)Pr4|lwP6tg-8$r|PG zfmK`DRa4=@hJeA*RRo)vI^t_UJYu_U_->VX{UMK&Mgr_@9*u8dp$Ogx<}Z17I>%j+4o;FQo2xMg zmw}FfoORs)lFruzK_-l%vU+0(@&qHGO}Agi}sZ*)&3On3RlF69(AFzo>#r zEx#Un-oLJtaGggDXLWS4=&U3v$FI2XJgCyr=xhtmwG6z`(blxk0|PXTSnNfwr?RaZ&GYlMmqf^-W8SpKv_ic$D ztopMpV0IUYKlc+#sCn^{C3_00yk>D6zgC|$Y<*H8*9x!_qVmyVX6ehJXqS9k%sA58 z#o^AmJAR~?ttFRVGU?Jw-+j<-$6A+gG^H{8DU17TI#$^L)!BVvDjqN%x3)$bSoz|2 z>QJ`X>afybdkdbgSmw)aGNOBZKd&}5`FEyt+!;1kAs~c900GX6;(J94afXgxoK7s? zUPXWU{0AzQdpyEXZ>I1+9n-)-DjDOCPW)rCK9x^~%UfBy`6q%wU79q|!en9qS3Y=OqZ9G$j9*>=D6#p3Rq_{Z!bkh)Ju&P5TZJh3lzRsx}TF%VBPIFD zU^!eJS3uKYsCc`rRv;bYYR>bM39ZRj1Mjt5J7{jGw_z4%fNleu_c#}J6YT0G;!~2h zDjVp{T@AM-kN3+&7{0umhfn@@(by#5w;VEK-r}r=n;PCQirYEN z?)0~e15LfKD%%R}v7O_z0}cTYBBNoQi)}zRupNV|vfglTTT_|z@sV$RZM4dg<0RhG z>N$T@9#IOhB!c0@pZJAX*0?B_yr%wxUxD)ua94hI*JyLdZ>wNC%EZ9P{7Y_UOSPFz zx`r$BYV2q1CNL1dfvEuUF;RCIRLAJIk#%-N0yZ_c;xPs^6>J&-u!U<$F6qiyuX^Qe9#UvPS9i|RV_wqGO)hrWiUFLn_li$ z2t6qVWkc`0(6d4Ao(J;@K+~z5i?``x1z=1TQva+q5`J+o8Xn|3YwiiaCeC2J%zeF9 z+%gdOS-C_9p0Orq>wrJd7k89ET30o<6AMN7IFiIYCwZQ4?YCAwx;EB9p2#b4PsgF3 zkt#mRHJv@YyokUR6{Hyu{|FO#|NE%R-^TyKAnxfT0m?5|G0#w!MxZs`F@iN5Hcx&C?ic?$qh+DG~BDD zb#XgDrM4%>%;MrLAv_!>&_zcNfA&Hf7X{htcv_MMcg7tx9Ng)a;UzW0u2n z3PrbL{f`>F^JqHp36hCFqli+zJT7n_@o+cUvD@6UUu2*m23OAI1z`V3=JJ4!#Psfl zxnJXKohf=rGOsZ|&cdwx{H&MJ{BL~2Ixs^pKVYEk7J`?~LQ;S0%RtR@759Do;GnGy z|6jg7Ig0k>Br&dvzlJHZx7i|vtgdQyLrqb2iQRIxqY|T!*#laKMCN6uGdzU<}`@Dmi( zv5`|yrJ_SmMoTSc$Qp1^?+@?gnc;sDe4nDT;zPz!>cU}T4pcPSOjpyh|A$>NqFi-x z3HhVC9rv>;(7)|2?&ab3K4q+X%=TY))%$}F+1TT)1T7p3f^2rZSHQTD7Sk(WZ}1aB z+L|&q6eaYk;hF?an>3s-XQ8GG%ggTr@i6uHGIB+G z7ZyCcbP2LBcY!X!3o?r%$|H(g%|ZPb*QsV$*s*bL!$5;Nq8PrwvRELL(bZf`U(DS7 z9-g;6S?M@Ksh8_F?5%bPB%_M{=RW+;|0Ww6;)ak&y6s_va5&-djCt03_1M^gI+ad- z1`7itCAoLn68@pIY~1m4vrUMpTOcw4m*8tAOW|xy)jxisAXFzzbfI5lhU6xl#+W_P z%6BTPSNA*ddu1JtrsW|r>IiIiUHPlQH*xw>D#Q$sWA_l2i`2O90n*y19yxq5?1?RC zQ{Q2sw0^Mm@$^#D=%Hk`R#E{P7pl`)q9w<>It#FmlxqfR@6XISId!_MzR&T(3duq} ztmz;x;HT}ei&fO!A1UFmij=mO3-0GRSk$iO^-ZR4O`DhyeS;9WwtUdgxJUJEx$mAe zhM#^z3kI0VQ!^_M(+6r2Air72t?5#8XFsbF)g<%j@Adhq4Rboqr;d#RydT#-#_lhY zml;a8CA0Jks#6@=a0ZOZS^plS4kvF~WkH*3*_7&f7knI_ZSAfh%L%gAh17*$MboY;z1S{5-t!Z{87OW5^D;qCmidHcl( z&r&Y%Q^D2S)yEGs1v9bHOD%7gh8SxAi7W8mq&+?Tc7^t5+4w|x!z<+vuO;i&>v;)G zK;oP8i%yN!#9fgXHFbnLiQO$8^`ARwV{DJq$tf2rPo}TOwy-T|DrLhe#3&)W;0O*t ze23mx4AAcU+6P=1_WqUt{ra4PA<#G;m8J(egl+TkC)vwP46-&e@dzT=J9gu{n*hKC#*w7$iDVwWR=a8 zc)A$$e{;P(wVduU%zJt4emmv2{5Qji&5=Jpm_b1^Eywq%i<{U-0OPMTc>7=6|3kbs zFyLm3{~c^b;AKX5_&C9}@5;ywF&Nt1;%^S{JjTSCE2#CuhK^AferqOm`|)pJjIx$E zM)EJ3208dW*J1Yf%0C~J4~QY35`D?`W@3861|2-9tl5Y$mdj?7-1u*qQOtEdUtj7G zFk7NW@-V^67OHrJHvP9gkM zvTyK4d^f=f-A3u)VI}u0{|TUoGfDH$xp^I7$FaCVs^b26Byam1o*`rWer%*~@OH~6 z`;T|Kn=@E{tK%^#oWbIFQWiIGC0CT*F3sVJz=UaySZ|1B-{hc|jyE)K)Zbpgn zH}M5QaKgoCL1p8?LVeRmFs*kL(d&4R%_2D^WfjxcExpBIOT?+IP;ynv)|{3Qpdc8u zkQfA1p9oovL2eo4tI}0YKF~%r;N0<+ry-musaN6~>`&_1-!-)(>cjf5a2>xFJ^wyI zmUt8c5?)p}bH9JR)Qe~^RjvxWZ>s(RyQ0^vfext>gxp%#f6t?o9G0}QvlQ=}3g4Wx zS)LYh-hMjYW`kqeim#~~TAJHl7#JO{+a9d}M(LuBP`W|}cX5FAr{mMfUS<2@m34g5 z@&2ir!XuVuQ?Enx7A0N0-+LtV(Yr8G1(GZ&C0zJ91d+qh43JZ|E?=}{;}2l%XikrX|Ht{6a*uzT0JFh2peN-YH&AXA%5~G8h!)5l3zH)FznKFH z6uvjyo==bg_dDC)UT|K>&lCuoW3_m9?3l8p%?H=QyEfL|6>DxH!dIR7nJA8`=ZeOZ ziQuvd4ZQ2bI75yQbbmrXpBwy@EGnDq0|p!-tac#fEW#ITSlHJi`H7N84JPYKxW{|+ zO{tbOWdZ{fDp~bS0%$RNfgRmB9d-mGC@C{PU|i8l^x#{CJ}-vxhS^SUN1p8bo_?N6 z@W=8R=}Io_P_$MtR4=$klJ{?t?`Up6l+fwLgai(kO+O|)t@%W9Zesd@zxI0^jcNuuz|Z( z3n_opw;Ew7SfY0vXa;m&9)*CA?3j~*e)u)DW`BQK8!!-nWhE7~)bT^U-|YUcr){k{bzMrI*I~%dF6_uizecln#R_l&UqjWxn2?lj;E=n2Caa^RNv2$gr zwL1fEG}|jE&;tsLY0B0-BP(XVXw;?ab~DJr1^DHh{+Qu2WX_PriVU(5frHr2LhEvL zq9voDD^uqxf!$XLxvV7BeoY%ia-RAlpW7-wQyv~X5RQ`SQF9`Qb+QxSIJIcZ4E=Yt zgxnfI+|?NL@ecGT?~Q-~=M^5FJyfILcy?@BNaQbeqU|B%TO*`gv*D}1a<_Mjx-yJn z3zr5q%2=s`vDH4RMlDMS$$MK=dC$fpkqO$NnT1qoi$Nau3%}NLO3zK+wynP zb8;q#ax=0$*>Gcu>A2Bz<-@MpK&2Kb!811Q12!xy%*-S>lhPcSPwDE>O)|KyZYri} z0;P4O=~BEU8;x5xAVIDSlDl#!KkVInJ}mCcd@ z84I)tpUX9+NtaA8v9@yI<`a5$Ara>jyda`AI^Q|bV}DWKrH`^CZ>1PI?RN$`sL5qV zJuPO-y;qt@sWw`JAkYpG71N-kj^2MIq+-WOLC)yaklH3ADhLJT4zCZBo(@y7OVquZ z!MI9$*~X5k^W@L+Z0c-^T+L$9xce(iSbICD{|d+irs}LJD2w64s@{5@{xs%)Z9+S2U8v ztemqb9zEl*E*I)kPY-^C%m3}p_1SNxPTc$r-pA#n7z(U6q2x+l*I}4}WyID_f8O=~ zRv_?NUt+%-?&qyS^0lg&kE4Em!o9B!uog@kV8}bNf!rb;53PerkRljf0a_ul_hai= zGmmo@ESa(>DEXfWQ=!7P2n!mFPfLQM5Iu+I*L@6({glG`r@W)=yzW#4J@cp8(#_4f z1je$kvuiL%vcRxVi`!C>+!D*^$6@6|PE(vSggI^;91h&y5SC>jkbX<{1$W3NpPcUk zc(e1ouIgFHIMe|nF=H_UmUj~4aLgYlZ0NDj?g5RrW5zdZCQc}@c6O1Bj7p(2vJ-~m z>nc$onhsYIt#Kb?)SXI(O^%f`l{~yZoL$U`z{@ZsK+4^T@KxMPa~poI_y(#rWeW)X z5CC)*nUa+DH~ZdM=8uE)czbPFavzC7tXXp|q+pkbL*P{dlLXtCxMkArwn#rbt;|hL zDOLKSoV}q45rO2)7hC_n-^J)yGJIR3R{|e+8M=AXD#s~Lr&X?djL!Okqq{#H$`>A_Nu8L=jQ9j9XxZqx7d~~B5efkHmS6qaUTX-(%9wCuHQtF& z%nXKCFL)BnJ6Y=PfmCMyObQZUdNF{VI~s(gBXq_Y^=u-eD=ktbDp`$huY~5$7U++s z1iJgPC^(-24+o+Ke2SV7iLV~Vf$wC+)CVi1hTwt{hXOP^=qsGcm?i@#81g_z5v)1o zh}+7kQ&R@tH|pljYt;y+KXmsZHBXhYl-;-~85tq*3LD`6i?*Uew3l&#;d}CA2ikGI z`eFR2fo<2@R!G3Wp(i(uadA6M1=eKEv=}Hyn<3>#+_C04x~rUGsbxP&)lM~S&mtPA zRmd}|A@BDE&|r>bHVLFz3srwdc0VKAo=rddH=0RKBD0F2bCS?v?z@;~Y1@mBA*cPI z$fBm`$85TQxYXvy7;ah(YStr6w8^%AZi%{R%+7mNG0SkM4mR<~yzudvUcJeYuA9t- z=DXDQ5mC=>S}Op=+@sY_(jaat3g~H zg`0q_AR?6s3Dlfj&13T!i?52sM_%(49o6<;Tb%PXGpDU%_$7olKTgr?y7YgZQ>90$ zcdrzwN$1J;cf8(4fGw@n`P0t@UoWSBw%PZO3JmK3@*sdajF5{N#=0FCw?_H7Yb!Aj zhrdfROsmgJ*Hc`e{)um?hsTG9V@kFDzisNY8!cu=v!Ww=H=#eopCw^L#fbqLfjq=z z_kR?3R4zo&v^?{__iQmcV7z2R$N_^F1GzG)$Vsh4Xa*6dp&5N%cOe+R@vsi+ICF0? zXD4LYJ+&eI8DM^%pZv+-Yl+|E1$Gnyvu!eRIUECfJ3x9GDiwm^Z)qy)L8u5>Y~k|M zMwZkBZ6Mi{eW~xqP1ydZ%vdq8#DeY$XgZ=4Fwbda`}dxH;D?~Y-xyL$C@+qEDQR+) z04Z)UWYy#MGFO`q=!VXt!tL$jZ&fuyFSSa=&fyWy%!RWL(WSv12{tv~z3^(V=~{-M zZzF@o@6+C|K*{azw|t@R@6&Yc6L6`IO~CMs=J9GG9UDCcU#@|@5y0WCw$v??MC+n& zXckG*;D!xm(!&ZbIk?T1P9TY2{uCgg_{T~I!(Ze}gHSuN<7!>@=>jQ7#|Y%Y5~54-s? z;cb8GQ%A0i*|+{FG-h2Tm5N$kf35VcKf_CVJ+Xtc#I1aY{}eazC4=><7cs# zMUTnNsKMLde5OX<8n>rGzdLH1bQNm@QVB;IWu?J&^Ob>Wl(7j~aVsPBkw3A@^1Vu%b7>A@r zIIV5K?Ts5_&|;P|<3P;FlH&&d-KF8Qgn>8I2>UByj6Bzu(XW+&Hq2puQsK`Vgs zoC^qx8G~OXaPlw*%`w^LvgDNDy~3D;3{f2L|=g)X<$W64jMtv0in z$ArHD5nJ@pBTr-?*VXDhx=-G;=C5N(l?~>`+aLOuuAR2qUV~PCgH|jO&A)nm9e8vm zCR(o(!i@&hidBRsbWNqLv$`vo8&*41eLiyxnbXP9u)B|(p>l>tluN*v@gCBbg_(OC zzNRlD(?Y)_sjpT?^13|%KXH2`U8!=HDKW|b_!tlcs1}D~MP$4K4#aNY#q@VVf47-_ z$zv~0B5NvYD#CK%e=yMOq@xDy*I>1SZK(_xX=lB66&s17;aD4$gcjngm3-aYJ))Kb z(@PNvt#y0={RH7x=m=@mIomq9*FPkN3tz_VxSBK1nKqt#10g_S<8wj!_IriFWsQGp zKrnvvt76-lRCx7|o1-jeY4)CC8uAc-0@24XSRUc?;gco|5xD)~;sq?4tt?icoBMFQ zp}e6bxUdm4L1as&29q#^3Qpj$ln4JH0uo8vDA(zAO?IoaV1f~?;NyuE!o9Q@iSjVg z2Mb`NvxN<BHMBxbJ{ zk5fi|_1^4jc0Q+5{8jX+Nz<5=Fn!69FCpGU;&eKKxdUo2C!P|lwvq0m+ zsp3a|K0H81^}DU`;r;t$^IYITHF(Qf1mw%;x^&VVJo@W30Mp% zr6gK_n1sfioMYJ>Xqup?eup>C(^`z{99CpXZ}-JcntW{_%lHJjPXSiF*&*?CHh@gm zI{wmTh1L&#!H?sECwvMp2u4eM6%*|pd#=qaZ&1%9M6r>7AK)mR2!a(|>vFf)Jck)*olLRVMk@wr5P zUn@cE#K@1l#6@aislPrz^a1A9{T?IvkQvs5*82><;)1)|G6EY?;RuDlBA^q$SM{ny zzM+`#jRH?I!J+w4fRFIu=I)~O8wuf05#BGMP)u^4h7=IfY(*s+hIC}`z+<1|!(7gL z$wAIBGPilB$csFd9u}>E?LA^|b7PXL^6{yYA3$XDt~6WcIjG|)1JQ2?NbLpzHfj#me(6R`caHLfM^BXylh|v*;Caad&sr#?=Skd0F@J zEpU%ng&JqsC0P3Zor`O=zRqoLXGM+<>2Z&iT(=ZhS9{J+ar5WE2Q3@yBKg~uhg|sc z>HKSDz_inbi|cuOD7{Atknz+22xw)kscRF(%;aY(4tJ=i5XZ6bM0qMB+&jl0!&v(E) zcByg=ji9b}+ehKstm#)Kh(y8j)?p0tjh|?Fo}BxsT1LNtq`ddkZtJVQ;i{*Op8V%x zuHFPPBR%b^Z_&f-R^RvAU8yEDNrw05R5=on4HJsktY`t#l~9QA&ajLqG}=c=$o(B& z9kcd6e#;_+{oU(ZeE*(3VN20#k+EU}J+9p}Iyh82+TUIB>ENKnnWG14G}sZcL%Tt~ zLGe!anju5{S>c`k}yAU8I+$cZN_s7s0}vijH4J zMk<%TBqrm__*}0(hn667nFMM>V4U>F8Gmg}qPXe4 zq9xNikfIR+4F~l%sS%~8a+Q#Y^gf2TVOAV-U11$iss)gYqVPR)){J&C=f(n9+P0B9 zr(YD0gWsk;#wWVDX$g=H**IRxP)bjR!+~1yye6Y;H{j*(zQ95@O`_XnrVMrYljx(c znA1@I%UXkds5_PMM9fJFjp3|h1;gE`jOWx|l*YkZCKH_j45sJvwfSxPvQN1;)djEU zGT`ZMVrI*~%Wb5;yEIbkPull8>lf{@;*zOOk$P(SjbFW@@@c2)8&f+Gt?}#iOM?=G ziQ&FkoaV&zRI8D%pLzdN4fIo5if*8r?>i6y!pr-$RQWb8N2Z{09x~RB;Q*N@|CY6k zspXCY?lOyhH zfcc&XV35+)nP@J{?$SHxI0WGL64GELd;C7 zla9L++A+zc(+*#Ix5bZv8!uaxH>yW~w9xixcK)+BwZG81M%@f|d;JS(fDKmEroG^xtLw=l7UI{HJZq9)rEvr^ zA_9W8xLxDb2l3ya-Xf!?pzEF0WRJ#f(YthhPYZk{-Ua(^r9b_Zf3yQJT>6ZvLcSiY zk!wSac)0ayJu+ZF%h%C5WWK;bCi$n!d%-ARhf2OU(t0J9;rzu-FK|QV#CBe@Qw|5n z;&)Xoq*b+liN}B*G=XrL#p0S_;RW5+G@ple)$V*(V>%xHBE%|4hYzel#c}w_lFqAY zJ!HavqRpTQzs7C{!7oG3C*H9H@|&u8LyCL@PP`;GHhA}jkY^NC{74HwV$b}ci>So~ z*bt5rBXNd-{I;f^%gs#CedW^&G#YT5177W{)+gdC&-{BM#rFqN`$;8`?VVCvLza6@VzfuEp?kOPuhL9tmK@E4=lv zayP=M*OQaG)nKl3`WrP!C(M}o-Zo&UBSfhvC^bFAwe84;sXgxa+PadHE)Gn7ueM!1 zed@UC*4?n?R>PYgx|_ZnB|n{#$y&W3&x|fLCt1q@eH-DhqDALR#+by|{mgZm8tb9v zN)+xTWJ1LfTP}l{X2DyOdQ!X+$GZ*inCN&A6i&tfLair6Br7bbMwTdi4+26z>9
P79!Xa}a%eZ&nu)^kQTx*^7DF@mH*{_B zu(=*QG?Ym_BP`K?v3ewHptBF|Z|glAtg{vA0HK>#oPm~?L^vL;7(Xi1;HqtRu-FWjv_z8mwd zIp(7kkBKoF(jSpGeaV(tnMKD0+@>)VFMTvgDGPOpsuO|^*ZZ( zFpwE8J5m#4PlVhY+5Q@<=a$bKFe-&fzOLERBB2pSdco=aInwZH-WF_ip`7cLaj9Pk zSBw4dcyL=8Pa$L4#H_P_Z}9l)C-@j@xJ{bSTq&=v%Ic0R2*(%Fjb4P^)F9#kis96U zcQ(P>Yrl(VYvbDo&1PSxCxcFZX&o;M>G?qdodV{;q)xFBUU

8zB{&%+D<3>I!fF%OT}W~u#f2tq#A zIP9cwT~X6_loG3%Lpli?zLL<$#d2~e`ihlT8^+aEwGzZ1)GQW`z2B~rm-uKuk7(dE z8>y9UB5dLFjgSeeP+8D8pU^-LzjN`11hVhl$81W?(86w%Ug&e#08P7NWJc4WPbe>+ z2)4zh_l>51=&cxP!O+UuR#fkoC_$N7$z-&|%37tWIQHbI*B+=-D>3BBLGMeIaw4X8 z&E9YXl`6&AxXqt^&yVTzM=FiGbnVILCDLJYpPMXNm*JuBF#VM=GNrO&b!2uMU^mwI z@g4kPi^#)Fp23%X%_!I3WhBUCsI+>3)60qn%42K=WXEhS%Q>ZZrXBOky=X9K_6-|- zdyk0fG!_KKL>5kPb1r)#TJb7eN`I@3N05RcVi8F8ROQ0-8(y20KBKrH*=AL2vCsR7 zPdlkJSoN5j%0U3C3oo|z)1jZ58!C=s3%C*rk5-<;{M%;$}S`ye1m~SH4z8?N}}fxz61n5j5lv6$E8FRE&lSmaIx$h#)`z*VSp8A8s4v` zp+d97sx~ORb#u_uW`d+1Y15`T@lM-J`oAvX@?8x#6Ko$(#eo)0C~PB_$}1yig85j# zjaWpWF^1WQzJoAsjHQ;eD&_@GY+bpMKz9USL_?9W8uNHR#60j+|5Jl%g19dYh0(fu zEEQK?3w{1L>!x%k1+0R{uPXA5gjg;skR7(R=x($!sSCpP#COR-t#P%=YIZrukV1f#{vQU&ptw#OHYK*{fP*el6FQ4|<)t^>FeyYCY|A`fMO_=`#?<1o6u<-`5r2 z*A)MamqfdZWi`T;~}Q{JS?NB zOET}Gc@-!l=g;u-@~k!jO$P=Af6{0;KPqy@c8d(XE#IunT0{(-&eMVCdS}?pjb0}i z_SEu#KF^ybzG4+?Ia4?&si%uzI;)@O6WMH41&)qyq)nuxrBs|gD|gSYkOy43+=_xQ zeNW-<+(!ye-ZI=1xdZR4nEdjtKP+^P=^zPm--?`YpXjt$ z$*E9#@~2s?Q|xS480O8Nht|5swD0YgidbDLyIIp!1h?Ti%P^DKZ5|^8kRINQTgeJM zzV8AuhQ%MlpEKQo!yyLEC?UTsasmIn<4b6+eb-^qMRO-{KTOv3j#xhy1%{Nb-z4`h zKEH8!-J&49TRnu&(_0!Iu+=m?Q{sNkvsXezK~(4|7OR%d$#7)VOX=XQg%^ATa#nJH z=tZ5WgLXg`RFCabf*8k@$U^-V!#2ai?6t@Lj%;B3paXF_7YQV11XtlwBdd*|lav5qtzy7Zs<3+8rwvcR+;vLEfpjlj=@E@DlzH-Z!$ppz+w89sOA409Rb@K`j2u%pHs;XL6@=;bhyx1nYFA2UUyQMKFE;h#jpHv7bQ#T`MC!1KJ7hm&ZOcw%5D?<+0GR ze=3ls#}2z?z^GfvE@R^16GRY9=Z|^4RZ!6SwCJh*Lz6YoQ#F3yKC277J#w5=g@|Tf z+gJije6o0)C%IZu?G1@w5VSwll>*6f7g876Er@S~)pBv4N8r576o*Df--^GM+1`S< zL&1dNK?quL(Jg#-}|Twr@j> zjb}0uU)I{0r}zV|go$;tuSV>&!z!p;bo6P@wPuz~p>~&n!ADov|4C*WHSpvjs^{3s z=Na}5=3ld}i5uzP{K5-3%LLpSO&NqxM-FWpXV$grTM`7l8dlvIlX6+4XPkYl`mf@F z-(NcPgy9iJ`jRz6ES63XdNH8Lcq>6MfLQLx5$vr-sLj{W(0|Y!GCokQ>(JNffeeZps<%F?W65EBLm7YEkp8XTP2&+~;WwoHYk6)!sF z(!|t4;iNKQYqN$fs7$+D@n*@0X?Uev8v)8H-F7AQzOP_V>T@&HplsnO-g#i}Mf!zE zpJThMV}=r7HQ5#Ke(`|}2zYS2 z;zy;ivNU+0a@3d60mY%KfeUYu*ObIeje&s$YM6h?=DfRI=p#AXk2?G#9;y;%b}BSTB^McFlruVEj+4{m<#@?yCcExC#7) z*E5dd>+0?W%Nm?uDPx*}w<8XU6L1RvW@+zC4s&K6miTxg>HOzJ!6NLYH~*`x*;G^+ z$>%ju&Qmj7e9BVzk^)LC6wBE69<8kLX0RnfnQJdZH$g=w7`YXb5M5a~qQt{M z!CNe>bPnmy*+j03!p~uJX>lvxCG;fUEgs!J&+HVcQ@A}xd%^C^vWH+|!NW^9d2hBG zpHXv&&9f(v>?>kfT}Nwy0r7)@$mN*Dt5T+?CP6;53N8?eAFa67dhWXal-#AS*!L2v zZ#xPd?iTqVLLpgfWC0_)J5UioD!UxT8x_# z)XU^7#sd0P5hbsy>%VKoLakgOMxd z&!O7)>#8MQj^eQu2qw6?JUbh7{SB1W8(KYiG8f8^I+A`I3T&S~LUwD>cZV9nhahNQN$H27wf%U*Y{~Zl(_`UG+HvGA?T#{dNKF0 zxsq9fq{6`*cV1ri^M`=q)R>>g^m|_lP-t*ivjn)3FEzK)LE1(Bg*%z(a5XZpO`xq< zveKo?bNBIb`x`V6ZSy6HmTqI3^xAGadU0zkwB2y0r<#D~yH4>YPQm&g*+lsiL$w44 zCQ|)G6G1DdQQ;>8o7C}m?HL>XbHw+)GN=y&O)$<-MWQsH14~*^pjRij5CrV?Sdmse ziTsA#M7;Td-;RqNS6796nNqZ4_`h@bm%aG@1{Y${>=0W5>zPs^ojm+q6A5nWk8Pxj z)~vi{oLc~l%JyulgiPU^4h`$?_`Toq4(gdF@zjn=XnVfqv-CLk_X_@~Sw$qIs zSI&-yt2sC@btJ+2&cWuBvkh|kF*n&-KyAV^?MN4NDkxTzz2LgxZ@jyf1pSYmQ>Y}j zrJ(7qoS$qlcZFT7LNnlVID`M*af2f&SR0xqT$8oZ={;faRk$tTxB-A-z%Z}MI}t@| zEAP-h`C*#7!O>gU3jUkCYs5Ay)b)+`VW*t};HMN{OUj8@mg3V?ZUJyjwCqpCpnQv$ zu4~WDsi0hyGF}g*X2^>VEGz@ZFu{D2=VI*f=PpKmSuMV5WI4fNZELRc6DSln`W%m- z%Kf>)VOXBFAq_U+W)azLEmJN}F@26!8+y^HpW{YaI^X*jSN8<&$;?U14h;!k79~rf zA~7W;Nyd$55EjoNR({`kB^K==kx4(X%cO#54u;_mgnN~FNkDgAd}krj+IF;zf}ZS~ zHa%6m^D^@(7}N#ct%E5nVqBLSuw*G`)1JaKBi`Eyfp32Wba44sJ}B72PHA|41cLW0 zo|7Whh}WO9vim?hHN`5t$wY&FRLM<$%A0n+7$^= z|NUSjg6w+FU9)SMl!4ny-qClcBD}P0?5$_n}D-$&51YX3JGo#?xs});SfEu*zf9k2utJ;^( z#Z5n6k#FZ%$Z)&80obEE@dYuq14fQ{j_g}{rlbDZu76wMaQ@AGn3rEoJF}q(_Vt-| zJ3HTOYaGMvonS`R zZz{R9IRq}MwzVJY#&z;AOm>~a>blubZ~%O?;X08!G4YyN3*Kj3%b!vV+bY?{Hc1_z z)iefA0`86^(I=f{MSHuAUn9MF;D#SZNh`1sFF(B;u;TeK;Gh+FqIn2dQavu8N0^u- z$dEF!4}P3rz!@}G2^@+l2WOmnl4D*x8AG@l(feV^0U!t`ag8HA`eTwPOxhu5Ebl@~ zt|hBD9J+CiOPtvfXGx~)J}6(eS@J$@DaQ0KvVt=lC1uie1#{A3I!h_O>@Wlx5Q>PQ zuXYqi5+Mcc77U$7HkzgO9gug@8+}YUMqtdfO&M}PBN=8-6X2k}*i={W220R!E+GYc z8Io;sk+y0&uAGzUO^NuPK|n9qJd4fw%DLQojfOf3%VEKJvcdnyWzu-=3*u+@{1#a! zj^w3CuhGsmbKq1#2$#OP%ksQjfq&)Ss%`7EnynAR1lLRsy7eXAL@6|TWrswKVO1{J_}NRmoM^ z)!q99$4E?vY1@rY2dm%B2NDdhGYGm5a~Lwd*vP_mnt%223b;l{5mA0nUr)PNR%01W zXeJPp@Z}#La~|&2@;!bNc>$iRgP0uT1_q%MYp)oSsQr_-?#4u6#5~{pP7dx7*H9wr zitgiUp4G*G4nJpw=5b<}3;3oEH9@BEL35z}*bTVQ?F&Ei0G#*6=srC1%tFlpg)1=8+v2@!Xk z^zhVkedx60jwD>0Z+iQC&X^frx@X3tF=d=#u$5${#{caLh<%>**i9Z31e*X*DzMfX zjciP&=FMuBVsp>-9()``i{#C@Z8NC)oRgWcQ)TU(VEd6+ zPC8sFwgV8~E}KZpZ$>QGC%^iJ%(8dg87)Bcd1P)<@1pnrx zg)8RRV+Aa_zygt}-GqXLVaWCS4u489n$+$5lEml^W_?pzv}i0I1P#BUDdiHtai<1jok&a0BRo^=>daEDI_Z_ zkG#5C5fv70Zp_eCtjJy_E|Jm=49a{` zk?0c@r&eeiJv5{MwBfAFZ_(zVEC4w;wQ~Wc_g62=|KsT_yW)(N zZH>DV+yjK*1P|`+1a}SY?i$?P-QB%uJh;0+TUCFM1|Wcq$LGuT|kl6$0!9FCuf#7e!Hys?L!2-zQ5d+%z8OhXf0TfGdaRXc9&jmwrge?5I~ZH;qRQGDz!`7B z{djH6mwLPQ8o3MOgNQb(WbS5k%+s|0Q0ZlfmN^`|)WVFT zHIJ<8(5~Y~Pel*b(d9r6w`gH8{P__(IqAS#Z5hFo#T$)3XEa8otKz9tG3~a>- zI$TkY#Hk+|P36-AEUW)R#l=z9)6=8ni*=YvE&T4QJboLd{`j+n8O^8L<8Dq+rnD@D zutY_xG15T1K_Su$T<&tjKPxM7O+QNh>5{?TmpDM;Qu!s#B#S9aeW8)2sb@T?$tEVQ zW`0^knO^si`b1lrz(J)n@{y41n&PxHtz@>O+ae8rt+-7>3#&pLH560Nud2FOhsiy> zV$c3{RKP2gO=u3q^{+;)J}`mbdL|Faq2J5h_e~%WYE)F;HO+~8pTj$~<&faL(AlsJ^50?3A9%C9wj@_z%KVtIn zJk&0D8Cyhu>A~RF@KCtDO&G?Aa=kdxvUeZq@|4JaVP?62WInxzL5-%P^&?u+KY`85 ziusg38kgN69mPDLkzRru3yA+m;M;kI8P(=+JKs10E-8g4cK%bbrO$>L;kFs)I%UFD zq=@W<=#gBhT@$kOc2cRc?WvCzGHR;!u_X|h=PV@UzuJU5)HAc8xK;tG&(LwF$bt3Y0Usvb&;?KOkFkKT5=b|5?;?_2E`x8@&Ogt$bMHJP567m* zMG++M_16PTS?2m*S06d73n?inad6P{>IE9ORUwN8N)0@xSS6sP3@PWw;HHINI(;|n z8ncFlw>VF*V*i|+)D0D=xskx+QCgU|fmvx)c<(j*wqcWs936V^alslCxG0+Y=9RF) z2qt2Y?A7n`s;lI~x${TG9MVMJAX@(%$LItP2pc%hbe-z;z+uRyUZJ^vviTzuz-g!2hFjq zS52g4#&I{QR3r45#(z7Cw|=H&?;lb+K_N42IKxzjdNIgZSNkAF&!$f2Bupd{v-lE& z2?BFU%=ji)S-(lL{JpL?nz)TUuGH%{;XGp9dIwZo9`DSwWV-`0kkf071^e2^&EdM@ zC)O7VcCZdg?+1V8qH?A1bT0?0baP2AI1()%LoNj!8j=QQw;LoheK8F=I=t_zx@*l> z6cE(?axPqa3u}F74eY|&oaMAZMtkzfRR=b<22FGL+87!D35zl>Y9(BWr~-u{@~Y3= za~6Dh%2n6%(O5~t5HfZ$ z|F#8mB2sCuGo`IoD;;A+9ES8zJkfuk{dCAoY^ENYroj?Lf(6ZB1W+JXe=m%aVU}T@ zb9t9A@Kl>NJ#Z*t@R*m<%}4wrUDHw?IAF=lFcl!1kE*g4A}*7SVx)V@kfLwu`w6li zojO#^szbBi@SdMc_#i7lKyH}HU(`1en4c%DS~Pj^Fx;0o>fhsgZd_6r_!?A7oSh^5&_>1yiZ`6{br5XyNE~!L z8C5zz*{$nrzKqNyyvdUTFNi9>&}L?;P|VPyo*ePpJh-IWLeDExv!i@>7K_zuncEFsGD* z^;PF_SfXnH_U8^CqDp@w-|Cvvl6K&7Wio|RIpWhT}UwtOSsIVgjM?JN_=%s?NU3LwA&uMR}Y@tkv7vk*s0k5yBH zt*X>MtaWqy=o=>urDLezCP~MBjf=0vp{o~@mLo3h55mAjp}i3hJk$G;v01BnWdBn|rkrTDrnfQ=8ISL3-YTUgm z+5%L|fYOf>v~4GgpL!m9*OxU9W%kT|KERV7AhMUB?e=>LKQK4DD;-ktGh`=EfWOBE zXS!%VaQ{MC^mWAj8Jb#=v=tWp^I|x00sUoBp*X-jHboCfp*r(8{^spSwHpjoWh{uU z5WN5GB1e_$`(+g0x1if-4)9yOzi$L(?i$WKS(;6&h3M5WTimUBSqA}jcUqeBZB_E< zl;}*(fdHU@HT|Mxn1UfMR-cvk{(TPb+x=JZUV6np7Kl5piy4HaFLjsEHBFRIT!tTq zvP=!o%(2nct6=5;grEYX&T>F{j)gEp&}Dd9VD%ucPk`pCzI~eJ_(?2PRUrD6)%`hE zB0=f+l-L!lY8Oa-m6S5z6myY+s)K&#El49v@!HFcDo6!kZI{8*9KplGBhzUWv7kxI zxUkT)Xm>Q@rQ%%uFou^IG=at(97IE|HDb1~JewD&gJGQe8Z=7{n~Cq;KT9<;A&D)l(1sHk8&F}pi0y0i*!v9B9;-T?3u;0 zqSPkg%483yTvlW1ql&)e|L`_K5KUikaxi6}n2<(lNV}D{{pOrBdZ~m_H0o`F8pi;X!u9Y!!Uhqj_XH26Nl#iR9$Rf8yBPR z#V+Q>!|}s+o*2yv5m!Kk;BGu>NmAxp^Mu;(<)6AtVb+`dMP~Mai82e+noB%uTLAm~ z9$z64mZq`{OMqiD0aM~Rb2dAnlk`K}=l-nZ=OI}cl}G^&C?jaEil9K7kmk?tQuALH zO*wUi47hZLt}3#2cjL4)+=A$uIpg-z0#n)|WfeuTPpQdXvOePCN(``^n$ENxj2`7K zC#Pz%8hA|#7gDb@?$3)1S%sSXo3f#PzR2`D^H1he=LVg}{1DeYmiWT~_3KeD$O#8b z=Ocmg4T-Iprjs1Eg>5f~2d!g$eF|5_btYGa^#H$>C2OL`nlIb<2RyEQr&<6Oj1?{x z!-tLHN=(m5tFG}{QtayQBg9r2n+GCSm1}0W&iw`)ou*capL$u_<1&&<(b41(aowsn z^*5nI{b}4#_3=MFx^SxN$uTAfqDeay8aei{51%?hM!b{yB?;Oqn!5VH~1gglqfuV@+}7%|dh^HKq)5AQ3wFB%Zek9Z}H( zV{|-1uMc@^?$4|u(tFoH&@z>h_x)exCy+A54GKwbQC$0GmtzYKw}%7wz{Jj_AvyDc zD4Pgx`ZT$+Z|JL*Obo(p0SK3!O11(1#6D=xPgug*f+@4Ebyb{ zH#&ILXe$EGe-ZLJ=E9OKpNqDuZiKg(%Lsk{S$o=P4c?@14<> z{GLq97=?|orF*l1ZdENkn`=y)Q;L|o^Z^Gi-O8aBEkO+%N~;~e~+w(q>&CwsrWA>#+!OWKoly(>{1G|%|4REoLJjDzpbKbBJM z*vrxlUx>=XC0gun+uV{bH+8hVJdUQ?@-~~_oXCZ8BziR;=={{+Z-R1DQfQK-KtVTb zq@w}3-w<17el?oUXf!MP%&s3ENN-P#jw$v4MrCv+O?#G+bAa?l$&F4(UmQ$Udzb|U zf7GK(?>z34R^pB7A*^K03ru&b)NGk09*irjUA&*P-N%BcVnx7>ALDO$iF#BQ7qG+3 z-6~F?OY<3P1mfF1{)WUxSjcr0d%e!K_oZ)BPsL=h_1^rf0&2J(c{pXl58PQ{1e;!& zj@kWvuv&=Rrq*(=d#w&wJ4qpl^kOZgz+^iP{eCY(x&p)`LfZ=sbr)6p;UOw3*)co7 zOP6%^aedN~`>v+w!%CN~1Vz!14Eq6!p+aCB0%41sz)|iaVuJiqQ~Q4C<}yIxkxs=I z*9qfK2+34(Gj=eU#S&VNMjJ+}2j3_4_iOV72Cn$#dw;#kI?*&8ni zTnvuF@3o=SL$)4g_tmSKaH_vITvF!%L^^POlzic%qptM#xt}GoS-lOGBzu=saffwE z!+Y*BoTW%sjj{!=G8=L-y~(M=?d`y?nRLIj(X#6p<;j^EXNa28Tsv!8^`mQBwX(AM zn9kvCV-$`iacDdTJ`l|w3%+qwzyq2*?=F~exBZ4s#UQpkk8%&^)B*Sq)ocBCWkCb2 z9mRZFRLdq@4D|z0x$e|aRz7)5-N&FEpKGgwe})coL}GJo&h^9Yi)TZS(5N60z`E&{ z<5R=MGzH`asfE4ZmJDj<0-E>wvaUR#-U~vj6fW;MvYx(4I|?%5&Zz*^x)Fwvc&J

CnwJDWOdE1hJVIp52`5$fN+G|tQ<8d! zQ@U7w$=vK5Nzwp(ly_|oqMeU%n_+)6m$q*5d6=bm-igUDeLE%MFo9)Vev+i(nF+oZK>Il0`=SpUE%W^~E#e_LI1Wrz{L2lu*z zH){`Jxqn;#4@u7XVNu?%{r1eutS;7K&8b`0jy4Ij8RdJ+gR#FHlY(8SCMe#oxM8}Pm68Sq}B=%Edk=;r(0$N2m0 z#~k5J-@48*X1XQG&1*)@a1c~^r|>aHs7{Z@`1Y@vUI z)O^pHr~>Q=`ctw5U__Ij&#EqZnmY`Ph0|JWB_4?GHf>VB(ortt#X--=`%V!-Y$tHc zy3^6ok(%qTP?ci-2#~(nSobUMXHDc|fhou`GY>67gyd!%Fa3ge{2Dq;xhS&h3Vp82 zl`!WWy#tN2!bps%wM>E%f2H_b5Nu+zDP+` zPhWPfEh_fFaw}+`_(yoFF$`NauLR}$+0`vk1CER4^?=ZQ(Ssk?zfk17;9>_9#JzN7 zdM_1L731ANZ@2l*6>`0F+mPVD9$T0htQHuD>tNUniK z8^cvK564xL_0 zJq`#$S~f&XopGK&7Dq?JTW#e79kUHVIyFU*L}tsPG$91 z`{C9w10B8DUB6A6xgF0z7*sRzNew1J~po9e+9Mn-369=l<_Z`couXF#bf=Y|J>sY@ywDhahEO#{k zTJ)QTMO%X+c4H%~*Li$WV1v(<`LGd*>@`b}oe^vH?qMNEf*|3ys1AMYOMP*tgw4iWIhst++dNv+)@+*%7r?W* zHZ!#{;7$EFZ~UKsE}Gh+VkFmFvg?RvMLCG(UW(Y#@Byq`ItfFplc1%omCQd#j)@8C zO6&Re7N$8N9caWuwW=^0C{$2cGn2!JE)dw{sh!joxlpqg{$<4I3^(Hgmo1;r4wMtV z`W5W#S9}#9MHDrQkZP)j(RRR)r7Hl_B2K4TqHKsj$Y8bieS0>qcll<^dfZ>jz{<5T zS={R%X0yKEzrpW3L{E7To+T*Hw(CIv6@anMa zP+Ll-KJt#cp@EOkn$-!t-}Y?p4m3Z1%_uxXR^QCOpmq(88ug=!NIc^L=rW(C)$A-dFxBxhpR>wRswcoq+_{)h zGSA5*47G{|JO#J<+1^&#-Pl;hs!2=aLW*-*_xG2GF(M;Ki4Zlz3STdX+(VNX9>r3l z0DYyapUdOW%J~57Q7cm=g)*Gl-<4<~&5V^rm6MAjmvgEQDLw8(A>nZ_J)6eSv0pEE z8w2bN&_HZg`x4Q{2yW4Y{!;ur~Gwhr;h* z(k1#HmddLI=(3fwpW&-oxdyHNb^r?|EwGDr)D&r&e6TgynM1>Od?spZ=|l&S!UF8H zd$Uqhx_m%WK>PaR{6PVZ26!Q&1ng8ZpwnnNhZxLXhu?!g$JG{%o`n0 z8AniJ3W7R$Y>C{D<4$}Ht<4Q}MA3vMVo5}8KSxmM*(g`L@+y~)OcDma4HkteLv#ZusUvh(O~)8yoG6_KSAWb zdo69r^`}4xI5?d+9a@&Xztn0PbjH02^yLPLnBU-1+H+5E7ud{>4IH7cZ~=7p45~`p z;Aa9IAL>avo0>=R9exaHvA#7Ktqa-aCKgi6uq1RH_i7%KXJ>KozmqcbeS(mR0q-X! z1Ax0dEy+rLPeDs7ye4SBAKhQJ!R9ai8Sku&7E@R}`PR#e?0C206_COLW@ng+odO4k zdMEGpZ=K;2ycVS0hJx!kiO|va{ifD z7oz@qVBbi;lud;LX*!8|vpAMNmY8c6)UpBXS3@C!z+Pe!%I~h7t~m;8lhXX*r6ZUI z`?_-5Di8Jp0|PzI*q*`XmXMtpCV261oKAah!cgXc1MP?r$Wcj`1I3$vL0YHRyJGFonQ=k9vzL&E~o1ysV-3yos1_m$7h?#BwkMW?E`43Nswppejtm} zpxIC|%8`bEZ$_Bl)PIQ`&Dq0d8k%>6Dj(-V`Qu|he z2d0s=jKf8mCOu0Jw~@)_HT7~v|FOnp4R`6ey6&}A*c?B3F4~Mu60rEUw4-)#>gO@# zjo1E9q+|@FK=%22U5IPBbEYk}gGxkK=qNbu#@WN+qR+KZ=X`?26DIn5I_yR&yw8=X z1@y1>PWaTx8~+B+u{5Vz-JySs`d!lFlsp^Pr(y0cZq8PUEeMZ2Bb1#@6b@!zPqlJ` zz=JSF3HE~Q`ZMxxctug#zF=3E<$NhKC%@-&ito**?_=mxe@#ixC_rE?%#;@C@lg#I z9{sGM_tVp*c(L){h@wF2$s`wrtK|5S>`lK#`*~_fn+~caOFMs;?9V*&Yb@wUQ3T&gs+JJC2MJqmf zUIGvZ+6F>ISHx>;wG#JupNeOmoUDo;_m4_&lpA(!+NsCMPfl%RERla4(tz?IEkmyH zeg}k-QtiqTL#Ow$#ZX^=Q=}gdLT$#>Q6c;p*BfVN$42eKS|UcvHsGk5v>ABB%uf47 z9u><>w5aezj#>6uHkx6dv|^F0@uKDlmUsG}tB`$S$^`V`V22bkriBqw{Q~)7l7+c)T_;p_nbeJFc#|(vn3*kF`Qwf8<8r$N59& z;`-Fi1c&70_2FcGH)Z(aI8y)3-HX>lSTz+0?A<=pP=B}E@AE=n{rpEG`}wNMd=sXh zKnNXo7bfE=-S>!yKm;9lFoZhJ{&wVp?)_S_y>YGMH?-}0`?8$pTM<$i`vJPjl{~wY zRaiP{R$?rnp8i4>LVV3G=w0Eg$;8}GJ+lHsmO2p8vTzXzkBiJN_s7j>&w$?WFm6PK7-v##G948)10Onz!1ZdF z>1}+W@M)BIXk4qPlIR(@=x#a2<5F=he9>?oZQZAGaoVgG_K zX>|2?<0Lx1*tCRJP>t>iq5G?4M;Go|N_6|hU-H46mXjH_(fvdyD@M_`+!o|Nnkq&@ z!C$fr1B=b-58wo7Y^B%euZg*17((*JD^Hmy$0BC9eMDj!y%5aa)oRN&)2l z9tjn&x|e|N)I^Kvy3J>V{tS7QOg@Da)^Q_VZg;(_oRE52aPSU3J4@fIp>Xlm`a|@0 z4aH2PSl#?p*{0v4#*>0B8jMA%Ex)#ku3R+tFyVMqVvqRB2xUduJ{8Ne_LOU%!%oMq zWqps?2LXdLpIg=KMVY_vUSNQ+k8r!brd-BT7RF)Kn@lAc8|E5<=K^`>?YX>paWs{y zR&BZB?k=PvI37-d6~CwM@h!>os>)fLnRi_h_<1@eH3WK?fq$zv8f}on6o-&&1Rk5{ zoQCKd8Zx*36B4u=47@%4#Chj1z!l~GfDr#*LJE}M&|hsCh8e^9zmL8 z*@D|AR5%Qg{Q};z5(h&DrN+Ur3HK;yfSb_wU%9`p6jMm$sF(q;>{ogxISL}K9R^_p z0&h$)-8i`mY3Ps#`z$b|Rpbggm^bzB=8dxu(ux#PQG^z}aWn7Wqnj?PWI!9*`Kyft z%`20*sl|8JFP2qkjRomo;U$`7GTzAQJv7b?%(wq1Aqzbo*fy*20`w|wFPtTs^F5L+cs3~jJ9SH>f!(=laCKL&VRHFv z+-ho_fJ^x`!goXZyP~d=u+}T3+eF+*B+e^I{93KSy7cq|4FcTWdm@NyMz6(FX!syb zPi19!v(YfSN6EZAhafRuE7g->+aXjwbWlsRvjQ{TFogT)LHuW^vQ!1&r>BO&ayB0V zGhsGem~W1Tj!k%PO45OV{S4Rnof>X(pAhv%VAZJS1%}@vgb+T|{p*@!QIU4l_M8Uk zs6iIZc-W}q4v0Zi@I~saHl>@n>e4JHP|+_63_Tmm52YX>fb)Yqa;cL7Lg{kZ!Rf(U zzX-XJVTOBva2x6{U)$^0%GyU4V4&kFjZXXXCd|VIw$jtN<;pDD!mwX`q`!a{yDd9U z#6X-_J~&WaPn7)r5i&o32hp?A6jba-KuZc4Jzf}Efzo~-(Z??>bpd++giej?$%0hg}&CYZp892zFK!RZ@1&{yF1IGGXb^W^h`@7V0 zt{8+Jo9i;ITgK$6Dt}J(*3};sc4Ch|Z_L`ndO|Y!O>dL`g;01QkhX+Yr#h3Bm;OF8ey7v(o@uKU2r@js&A4x;dPJ33WLx#}5Kc)QC zh{5^Z>U*xyA(0ZB2dSkKl_q{G5he)XYNp+A=x|Y^WEC+w-#C-q^cJ`qzbaOmnyH?w z&3e%(IjShP{xPl+8P0Mti_Ea?yOf#{8cpR0Z#&BNHmIV82{+i21mr#4gWlWUL4ftj zk1gk`j-!u5F2%Q3X8!jX*;n4qO7(@dbGdJ6k&tr3_V0lJu9Y$Cm|r~)8Ja*Is4z4b zepTsu1glzzGY<_d^y7?HnpD;l=JM1tZENsO$Dz-ox9(wa)TN0cn?p{`IKIa=!EeYb zFTVBDpdOg z77quSHYo(_+t|ij$C@k3!tM=Jx^sCs9;?RCT?z7rtN|TSK9<{aY-R7JFh>{uAbNwW zzNQcJm$hZUeTC-ulR#KoDVBX zgo#tQ&64=7j112s-~D|QGvFBy{EN8)Jny;pz7Ec#i?_MC9<)UCS8^VCu7_JjB`Z;1O z{_6DAVo2??{*?bPYiLBb?QJeazU|dY5_ohU>F(ZL3kU)9JOS?a^863R1z*M#0dEJ) zpHF#jF9tqO5l`x_ztk3+o|-1m5AH`9FaSe=eCYn}ECG-(__`x-Q`6H1Gd<6mbK`_> zmQJ+1COHaTaW6TH4^;hB10)=JdTORv%j|GE-!Vs-nK$4!ZY4~RCHEcRszmZ`e1J_U zcTI%Qe5$D8a|1!YD+P8|zXDg&lko1ZDO;>wdK`qi^GTNICDiIWhM&{=JY(w8w41Pr z^Q@xGCYeD$w1B?8_HWPU*~^EV+|>m|61}rG?s|IfY1TC@m%_L^?wOgV>OLMfHL!7f z&XX@62f3vn!g|pC3ne`kvK>;c^<-!KUDqsa7^Nk9r}vguh+K9UUpUJ zG)d#m1$9-`=5OZanHx`K2C=ZVul!C5u=Uh9HicyxT=x6tS>bmZOj1U8$gccaeX=3> z6aqZe`)`lVvX);>861SnzhjM58Ws!G6_*xSd{(Ayc^?;qZFyTRerQTc%j@eXaj=Z+ z%NXw0fR9I6vse-w{I7+We6}+aoaqbLrM|j1t2tqk$N_?7-0JNLQ6a~o<~x>}dpr%O z>=Z*@_7tw)&vuXE63|sEgaAX*>Eveqy>Zu873Bu8TQiMm{eP;#-Z^v=e^f!fLpp0^ zzv&x!%jh z@!!PQcRvqqzZt0+TWjDfTS0BLx7)!cbI30+%xrIJAw!{%0}WM}at~JeDPIl_ih)tQ z^hwA`M3!2e$-mOsxjW*kcLA4|!(NR?L7RO7pBX0lot^B`>YM08aOT*|<=y$8ZYyI` zk5v*7)4xz>y|^7(QMEJke;+H&RIY1q2t`>ieXlkpU{^s+p2pj$RRJeqSMqL$j%j$wOa1rt2MU1`~UX+y&3rg9~sN1V&p0E zS<>F?wUVj!<#VZ)OFDpPpNtf=dL=_fx%y97AXe;CxYb>cHWqf$`Ku#?j9qeRnr1ck zUjNv!+J&i!jH2{X`S z6S#iMeXk<4TI*O-bJJ;9{L|iBT1`WqG-E(*y{h$SQS$V3SUXj%U7C8?k^hPLYIw1J z+k@}-ngRF&-UO(VPB$Ku{?3S)sber)0}aJ#_6v__1zljw(B(JrQ;Yiez#Q2SHESp` z{53zVTR%NJJ-u5?o{OAc&^&D?MLA#0JXa%~E}SGAY#OCvbroW8w{uQywc@!6R57e; z^}EQQb6jki;2^+}UK?f7JV(AT5iV7UWmjD+tt{=OPe~iWnXB}ltSVD6LyfDNnG-P3 z{b?9FeiwGoHGppj0SULv83-SCcZcVi1i^gYNHilcyE{J`QZ&Uz?MREZ&T9A*37kp(gmx{C2WA7g`7U1ps%FfcoAO0 zq^(Yie7!sTyhG37tlvO-am?(P@^%&F?B3=`R(~b5+*S=6wepxfJG;I8kQ2+4hN-e| zYhdu>SxQy)E|OAxQ1z^puVUsP@$=>HZ{$bfkEJp7%lw$nWy##t_p$C(E8^=vSNCP0 zhx{UC9E@?LB>DstGE_ZWNI*7W4>4QSiTdlL()og5&lW~a>`*MH$6+n$j4#j`eWDTY z^rzi`!;R}U1jX0N=ivt(4;|2yWks{4P)4<>r!-+9jgD6~X@pKtPYP=S)D^#;_tf}t zi?P#$N23XRt2wdT;UHGecnyTEMAepc;3F-s0;kkwu4iUZ7WaGwR90v;YooKx33DdX zr}{PV)VzZ?BSOqz!HoCL6RcDWC^uf5JdOOM!+8}Q!E+9)SDfs!e&rvRcP>SqIIXik zYVUyQS>-goDC}la%6r;yzJWll2b{jMOSUdreC2J?7@6NGkgs#)$4le1%ShzfIx51p zl1r31dJ9l+kg}?~ElMo_TAkM(_bO%$%K+8f8x>tqoe7-5kffrGon4WWYo)`IBgtWK z@>7VV#kZ6Cj*jpG?W###5!KxtGlG8iY`fwT7&1Z+rGEqF~RG)5N+o zE}_Pjv2!zxj9OG|Q8jBIf~DKz+I3@6wfmI!!TyXsu4uE_vopIIS8~i#LtPu&Aqs1a zcYayE_V{3Gb{F|nQ=_J)^JL?ik{rF%+ge^b$lXZ)7uRZM{Qw8qoL|E2>}TQ>4Ug{J z>iTrdv?*-U8(}wre1~pt}knTA0WzlKOUrOu&&A zde!5R1Oau;=U~t`K?kzdd9x|?JhQH4x+^E`7%6pnV-)5N16wq zRQ_`@UI4b^1k{qjI?F2X;lUWX2_Z`CZ@OU%5r&?6n4_gnYHt9ipO%@9ZCZ7EYg|iF z6RQ{WPiKk>RU2sMXX)IhzjfcfnmXS8^!+^6&;y>AG1N@?I`X>)C%u~cf|JWgQb#~` z`%}8In(LjcN%p>5*6=Ey&&+%s+X~96W{~T5#GWYx6RJ;ZKfbHo-GlzZ8*h!}f30ME zMq3!Y?;SIVI)wuqwfZ@%RdgnKcE_JGJW6|As4@0ci)HxIF@!~8Fy3+Au*U}m-Mo0UV68gyeXew}U{_DvuaEwU1%hW8Vewa-Z zRXFilvlW$Za3G#=6zcJyZtH%cdV7k_R!8|^e_P;nol=rh2bCU;*Z1Qx(csFL`>oN_ z>dF86mQ&^6Lt2-CKecXii|5(nlEOBK4{OIW>X5Ls3qJV6W3Sq_zTe-!7yhNg|)GH|RHkRxl;Q2*DJN%Mx&+`(N z$(;at~X`jrE4OuN`oUg(G zp1jPJ%b4WLTXp0Ofcw>Y+y&W6PQ_qmdE{g4T&IL5{+;i&PO5{smX%6|_}crY9D5mp zM~St@qiLlf8QJxPXWqebmE3j?;Gwv;Yuxrd^gn-!9c|rT!wU%SsrI?5PxC`jyh%}` z>L!fjEyvY-z6>2M6yCq7>8I;`7?L}Zx{cvzbU=xI+S*h1If%b<8mp0iCNY;=5RW~{ z7%Mxm#5(HFbWBXGCVd#PX8(@21T`u_F}%TK=1ykWyJM>t-jTjWdCFHZ8v>IuW#)xOqv=V*gotLWI*_ewl&a%YqZ$JS~k8!C{gMU4Tk z4DBZkzjVSfE$U(`Zxc7?t1ZEjUI$i_7V7zdbdc|ql)k>RJ`pW3ea_!p4f*YSF%6K5 zuj7F|HC%b;<-*i2eNKbL{POnBQr{X=_T)(P3suJXMvoL<`c2@i5#;9cg!D7P!6MBl z^-QyUS!V@8lcN37t54X_rP!9AW(K;MJBq3kM<%J?7)x5aDOJrSWkMNXn#P`WYbHSxEU|EtBkd#T-7wpl9wRf1jc(q^ym+tiZd&tq}K>*$-M zEAZ+L&uWu&sw{B*7&UZf!9XDPxSJG;>a9D;+I~Bn?tQxSw??w7Th*U`sPpge9#3U- z{;-kfBv7lj?9_2g^0KKKBcNblKC>AsmPQxC*PnpDi5j!Q-{05vKJi_Bffd>QEcTe*sW%R3^7p64yZcUZv$+YlVp-E-* z9af@P-3^Ho+e3_fzwc~ma&6$RJs?Zz#NEEQzr;$B67|h7&~etq$r}=o%avu%nbXZN z{1$WH*S5@o>?Oq~p0S;UjCf}F)3C;UpgDEJLM1pISUw>3V)l(lbm;FW+(Z%wKw)-K<2ir-iQT4PhGyRrI<_69>5++VzpG)htp zq{veZ{!aAszl~nLD${F>&eUE%)ZByRSFJXn?pyn!o&+^L6RXLJVkuDzb!5@-EFKkw z%d3cIuK%MIKDZdjxXEA{!#KKRm?)5u(?^%pPQk$K8^C znTI#4yx)N#!$vyyr?Z4t)oKCn%I4gAUt5@U9%yzW!;AP@8PRKTk=bv$dJxQ;_Q6ZO zsx~Nnr-Slg|A$0UgQll2G?A-Wy(0eY=HoPXrKw8G*9?E|d{fa3u(q;^Wn+Y1eTk?2 zn))aW{qcho?21$+aWrA`){cO2#$Z+1l}X%|VJ^`;zbf5!;19n)ZzsEPgz|B#KKc6j zBJR0?R&!lNDzm9r!4u@UN5!*ycb03cZeWJG+z`3+;weEbfHQMgtH0u7=Nf6wn*#{I z|C_x;@7K2xIF^LwDJ}lahY2~FvRxLfn3t)u{F^9qjI=~h<#(Oc)B&3S$6H#Liug-0 zw5FUs=Ls}lO+4_lEIEyaAra0bqa~bO*^cVOhxH+-d!5;KMqt+7ayK;&eI*4_Cr}Mn zOt^$2!=4C(<3ZNSK7fNuNakFFaYDvwm2Iun#}{&y=}^A@8|zhkC6Dsv$yXSB@Tvb2 zZFrzI4$w4JWb|MZ>P@_tl@^iAGBn8Z@7Z1*gKsqId3d@>Xj(jZI#YF3^F~HmXb!HV z)O3HfI#8ROW;_2G$f)C{)>ePE__QL9?0% zClbd!#Mpe{?R-Ov5qN~l*K+P1MS*Vfu#>0HOQsyHC9I>=IyuoRKvVfBe3bK3BF_5=BZkUylPG4 zto_U}1;9~tBEVVw0{F_y>$@MZPEu6p)$#1SX5rf*QRIGJyzFixkIk(_)$ zlLU)9U20m&^tx|h`F9a^$;^mOXxBF^%i1#4hslk*v2_XkuCueO7ddx*=euc!l0rT# z&B>_Z=-pMe^QoN;0Yg_~iOY7%11w)*$q>MG)_YWBr`0nX;Y$)4c&#Iu9U_uK$=EMs z3;9;3q5KDw-sh=unV`=yE9$fEh;xeGI0ad=0*-Rx_%5P6-d_UN3XEB`d8o9^$F;M5 zh{FZu(B{bP25zsi66iA6E{^ctrZ@&}p&|{NhX;ErXNv_zMGb!(#9IrV!4X?l*WQfT zW#qo8mAOhd`6^3O3UeDWt7RAa-KrJpTY9=D7iUb`z}{UqvON!)wFszcDi5Vhrm-}8 z%WtT)^p%uqHC0u}gPvhe&++P{>0gdSSN|pQ6BU;zd>qFIn=X!y%{D&2vnpa4#En2Z z#bOQZccWg%Mq67QPz<{oi;i$u1+X5CRP+q&K^~yv&hRg=7X2W5U4{6~>r-|tXrN@? zZYQ1=p9T4oQI$eAxHJ6`08ak#5w#cM0P@<7TnAjFrK;Zj^^I^|46(wn;?wY{hDzMm z5vcu09LTDS>GOPcaK6j+JlOkLwvjh2@*jmyZWHdC^J({6=H1mx!O@ZZR=3mo*pWu9 zZb!GT>g%oTdMjhzHo$zO^dKv>joAR;Gnv4V-yGlc0i9DTzN=upsPYxD)+4gZ0dPCX`xn|hPin~exlJpWn$G`Pio@4i>V4 z&hL;PzSJY8JiArMFHZ9uy5eofe6fJDx-j~o?-g-vv2uv8{H2{oS<>|nsIq6<;PC-A z?s@=yveo><@U#5P(0{r76p`uVH)JY7Lg%wsLzMx;&got<{lQvZ`DMiLhov>$;O)Be z0?M>r4&!KtA}TEJk02>$B7WOqMiJ&_&T&U)ot!mQ`V}8#^;pfy>9!#O)M`kQ7cLfr`4jWsmxO_AnYqgnHsP&^zg+kzmHYxU%Li_B z6*iQU!YT2WD;wF~imnQJ^LVEo12ktZ;+IuP68F7P#rb1WA(u?Fryf$SVrc)mYk^AN zPM;<~Lj_K1&V`lO=LTT)h3i{irT87+6CGM4!o0oLhZ^p;ZT*M9ZWOe*e{m@2Xl#_t zv0tL2QSeaWP|#wcQEp~uX09>lrTb>;{`jT5sC`R%SyVFDl6dCQ4q0t_sWY@_XXvf= zG0<8q5DgncOL-tI>`Cbw%N1-+MEif0U1wBNOSBGMq$!|+6fX)Qy-2T@Cf%s?5_$+t zsv#698bCoIv=EAbfCQw3UINmUj?{z}nsh0GG^xIT_pSHdkN4Jn=f_!RoteGQxA&R7 z=bM>z<^;lu2~a1V--Fe##qK@%fE zfy{}W!SVCDa>tHT$u#`>J+_RJPpJO%3P**qOna3BlqYxhAO&P@ zOU&Rm(}E*I!K=~H?FE{kWBZ&u_LAN8j1E^DypSkmr?u=Be#43@-g=a{2uyekN`|@jE#T7+>nDW%FrWM-a{xGNq;BK#f;ek zr<+!^AII)ig{UciS(sidw}_WI?sLg|S~%p7MNd2CIlWm)h$Ak*c#TLUy;`?&uWP`r zVjo=j$QF|3)x|^8mz|heC-7v+D*n`3^R6bi;hy-Ju?Ewow)HLKGteL>tTEr?tn>Z% zv+y%g;^YX|=Xc$&$(h>V+--JrleEBcY1YL<^A8mwvZ_KQMcn1}Kx5g4{)e&f;K|y_ z#bx#wW&TW0$-L^=V#&8gx4I9+3L;_9cDb|MQ@dj{{SZx|XQX$yu>lz(iJh6m(V}(& zc?lE~QJ@y7?&TEn&2Sw#J{K{qSIu&N#?;K%*ur>nEgv+lD^G9EOkW@|;A>*G(XCeR zf-5htE^@61;l|_y>{H2%PM6cM5^q2V6KL?pM2HGCs%DM*Cx+vQLw;9&q2co@Ib>s5L*c=O z;p7BPa}ZP$R9oBt%3D6=*x2A7l=`LyHQ%pUWs6StK+&Ytd?fFY_L%Hlw?E{#Is-ZT z{#O%#l-B+0<*!@)vcKQIp$E2V?Ss{mR8BjZ{{GN+=WsL}$sJNa%iof@B^_T(ZP_5@ zxe-9>jBE7f@ur}_f0^^emRg9HAzf86N@h<*SEwF z;&l2y-|Pv4ZKV0de_ij%G_8mu0R0G&$Pd(2AG~tK${a975dE`zOhA3V)UMI>jrI@{ zEQ%LxRBwVs6-btC$orjrx8?v`vGEKNFzvM&ng!o(GqJ$fJSsL%F}N?KWes*E^_}UXIE|YsM?h zKH64coP!ISbRzkecE4aACB|)?+ z=r?gKb0_t!r5Fafr9#fPwx_8T%I`{|ZU^#NOsjeajOKFA2EBtrT;STyjRQUA`kNyC*McRQ>wyxWV z#|$!NAY*rHe%pAJv3wSGj`QUcanc!@vHmucU8I0EAP&_a-V3FAYRoCfX?G8`9{9APr(+~HD@}YE`D4rfaotOUp${q&3sBN3kIK(~!p;W{5OGI;k5$ku~Gx|1S1Rgh%pZyd!KMsjiF zrF$6I)IGSYsg{&t9RDv zte9jAQ&ZDHi(h)-aNhuD0~LXJ&qO-;ZkgdKaMd+1f)hr23zld!LXSeqa&p|{zsIJe z>>X?q8V$tB6{N;{M3tk1-F)PHTw=zC=;TMG%#&+N}n^Qt@o9$J?$q(=_ba( zwV@i5I|R`P?SJ@GHV|LeEzXJ`|2S-K0STQ;mfqf#lX3RKw@93qjc<+1!x4QUX@Na>O1ZbF$Q#`0g!w zwob8^OTtZL=|zQsCg~6oQlsnI=Gsn3=CTbDs+s2jTNkU1B_j7WrN`bYFl5E)elt5NQgoJ(&s&lMXg$V z2%g25ry{b!WAN|UweFLR1bh0adHkBcm|7@FD1Zz=QoTNAO-7c0er9$;gXp7P2c`M}q_ znU;Mbg+Bxk+4Y&u>2MMmI}&1pnsr1v%my>h)~Bx?mtR=n$*`?kFSLj1+=W}Y0f^vg zU)72?cX@iLn{Rw-#-~9C2C>-=%OEYBoQEo>E6>Q zf|@_cg=luutsmx!bhj!4x;kpqWM!Ik#fL4mMthDcuiYm8PYRLMd{M3c5V|&t^4XZR#-~SXplm5=Ki)24Q_V{7UdrTt-HUs4Jrsf zFP^R59;~c(6gE2;3_{NEEuH2-e-Q5f1EZx5Iy|14YF4w^*zF-)SdwwzTKRCMaPiXl zyQvp$uHh!9pV)QLUhgBUBI-G$Yun+3UCkLk^kvKw;{sZ!qj*Z8BRwfC(SIk})TKGu zqmQ$sJ2XUSCs;P~?}ZV+kon?CK#&SD*nzyk?g@Z2+n%2+I!b{8?DU!wZMxw>ir4Y0 zB@QzoHEphZfd^{B>bV~67RK`AB*SRTC;w9@N-e-D)!ya7&tFUyA7=>*Jc-@|(UZJ=JyFZ4SM<@wt>=^*>sA z<}X7Bcg)#nyUMOg%I@>6ue+QMMIHDdM=BD&v4&!#ua!zpysl;ad;8tW02jeVpJ_zi3Gncz1JRUdXGGQw}lt4c` z|AE6cC$w*n^bI1LlDeqtm6`0SBtN!HG$nES)fK28Bwk_4{} zF~uiN=vO^FbF%Iq1cX^#bIHx-6)l~)=0`WO#3j^!gVK*=$Jq*(~9|541Fo^(IodH z<7=9Zk1$VB)dfr1`<3(gm4sp(iL2Y!djf!Np!%~b#{Cu(ZLO~Hj1{JD6pLaJwYDUU z4t`o{Ot*92QHz7k?DTKYY-uNazl=^{{D=~lcuG^7*fUUyZ|A0&qtx_J$?CbYxc1_Y zTgw5`EVjjZ;Yqv`Oz89kht{&o$cd=$aZ(mpkG`fjuQB!{mD!FNxP)mtcK*egfRVr3 z+%ROzZ=n|1*zMA;1u^Kf8tW_q+am7(V*szBdz1NoXi2lInljX!?#EDXMWkJsRqc-9 z1-Y;&65~_5$AqS z$kXyWHtep`c{XmjZc`q>W@<40TB0pi%vDG`F&T;1#+AC7t$s_?mB1B0RT$1uD0w?Q zj~=&Q$rxTO4Gr87iUi5sp|SuJ@ovd8Z*`@jn%{pZLFmxxV5HHml<@J zH8)5LH+LA^RsJ+7YRL~w>d;HWdl}t+5WboP%we(=b(C?#r}9Qqwk0I#=!t;a@~eBc z97tH3av!6f*ruG3aqPb< zdV0xPN9!edm--mK(zz;B2-fNuxjJFr{#Jd?k0x0Vq-Ob6AE?&aDRuIb`q&D!pzjOY z6Ebg}qg8y4mIG@+WWcS=yn+~Z<^c|U1YFXLy0kF#^El`eer!O1lznsCkas8}Ifavd zMN(MNGo5i^8|HVx%DaxZ}wGfO_UgSiwf_JrN9W;6mDH@ zD6|fpGz0>_!YZBD)?Gl}G=4pUUlNt+kT8echI+}*ERhCWL zj9zoQfMjMuv_blHe@gwMy(1}>xhN+c*yMCJ#dAJf^L!|c<>1?!RC<{#?xmOSD=57A zITowsZ+Ph6`FZNSkjI|CyNS;7NWNznowT&dKTXS=DD+^ANou;H(%LJ__M|($rRwn= zujko-`Zu`(l1bt>1=Wrfl_zXiBDt<21Ys`hqT^BMyca%eQjEE)$(&T{kuD~iuBOdm z97+6w^BIAaeHJW|wA)*o96cxc=FN%@N99dWTbEzl49k1TDXInh$*9lhuVJ7L8XoDT z-03Lm$ncX3fT_K0U1RmeOXYuKuE)&IMya_HSf=@Crx~iYR);(xKc%^M+O_ zCEfl6Z|0lyn$E3SH#H z;%e?S0+wDScXOVOwJ`Scx=bWAYt^=AgE4Pw%>D%-hM3}N=%iE78415u^^>Xka#0>NjZ(eLc9WpUtd`qK+0(zZk%!xwjJj zC&8uyfXjLTg&uG~Nuw?gv~Tqi6m z-m;|UX-{}(zYdYNJ*;GPuz$fOf+mPeqt0Zzgoa1~2s6*CH7f<&${4@2kB_}FxHthuWli!H;to*j@uFbN0F0_vETpL{I-@S1~A zQXre|X2r=v*&n)_S)Tys0F>q`YLrv2<9@AdOxo9CGSDY6{l}1l2V6Q<5nI4>5JYbF zho=#v=Ypq^oYOU8FrCYvU;a-PcV0>)s>I`>%Kulv#WViD3NAqY!z2H-f + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 7 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.ewp b/bsp/gd32/arm/gd32470z-lckfb/project.ewp new file mode 100644 index 0000000000..0b77ae33fc --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/project.ewp @@ -0,0 +1,2321 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 64 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 25 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + + Release + + ARM + + 0 + + General + 3 + + 33 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 25 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + + Applications + + $PROJ_DIR$\applications\main.c + + + + Compiler + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\stdlib.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\time.c + + + + CPU + + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S + + + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\..\libraries\gd32_drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\gd32_drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\IAR\startup_gd32f4xx.s + + + + Finsh + + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c + + + + Kernel + + $PROJ_DIR$\..\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\..\src\timer.c + + + + Libraries + + $PROJ_DIR$\..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c + + + $PROJ_DIR$\..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c + + + $PROJ_DIR$\..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c + + + $PROJ_DIR$\..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c + + + $PROJ_DIR$\..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c + + + $PROJ_DIR$\..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + + + $PROJ_DIR$\..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c + + + + POSIX + + diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.eww b/bsp/gd32/arm/gd32470z-lckfb/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.uvoptx b/bsp/gd32/arm/gd32470z-lckfb/project.uvoptx new file mode 100644 index 0000000000..05849dd0d1 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/project.uvoptx @@ -0,0 +1,917 @@ + + + + 1.0 + +

### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F4xx_1MB -FL0100000 -FS08000000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB.FLM -FS08000000 -FL0100000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cstdio.c + cstdio.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 3 + 12 + 2 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 4 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\completion.c + completion.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 5 + 23 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 5 + 24 + 2 + 0 + 0 + 0 + ..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s + startup_gd32f4xx.s + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + ..\libraries\gd32_drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\libraries\gd32_drivers\drv_usart.c + drv_usart.c + 0 + 0 + + + + + Filesystem + 0 + 0 + 0 + 0 + + 6 + 27 + 1 + 0 + 0 + 0 + ..\..\..\..\components\dfs\src\dfs_posix.c + dfs_posix.c + 0 + 0 + + + 6 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\components\dfs\src\dfs_fs.c + dfs_fs.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\components\dfs\src\dfs.c + dfs.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\components\dfs\src\dfs_file.c + dfs_file.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 7 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 7 + 32 + 1 + 0 + 0 + 0 + ..\..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 7 + 33 + 1 + 0 + 0 + 0 + ..\..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 7 + 34 + 1 + 0 + 0 + 0 + ..\..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 7 + 35 + 1 + 0 + 0 + 0 + ..\..\..\..\components\finsh\msh_file.c + msh_file.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 8 + 36 + 1 + 0 + 0 + 0 + ..\..\..\..\src\clock.c + clock.c + 0 + 0 + + + 8 + 37 + 1 + 0 + 0 + 0 + ..\..\..\..\src\components.c + components.c + 0 + 0 + + + 8 + 38 + 1 + 0 + 0 + 0 + ..\..\..\..\src\device.c + device.c + 0 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + ..\..\..\..\src\idle.c + idle.c + 0 + 0 + + + 8 + 40 + 1 + 0 + 0 + 0 + ..\..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + ..\..\..\..\src\irq.c + irq.c + 0 + 0 + + + 8 + 42 + 1 + 0 + 0 + 0 + ..\..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + ..\..\..\..\src\mem.c + mem.c + 0 + 0 + + + 8 + 44 + 1 + 0 + 0 + 0 + ..\..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + ..\..\..\..\src\object.c + object.c + 0 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + ..\..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + ..\..\..\..\src\thread.c + thread.c + 0 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + ..\..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 9 + 49 + 1 + 0 + 0 + 0 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c + gd32f4xx_syscfg.c + 0 + 0 + + + 9 + 50 + 1 + 0 + 0 + 0 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c + gd32f4xx_exti.c + 0 + 0 + + + 9 + 51 + 1 + 0 + 0 + 0 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c + gd32f4xx_gpio.c + 0 + 0 + + + 9 + 52 + 1 + 0 + 0 + 0 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c + gd32f4xx_rcu.c + 0 + 0 + + + 9 + 53 + 1 + 0 + 0 + 0 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c + gd32f4xx_misc.c + 0 + 0 + + + 9 + 54 + 1 + 0 + 0 + 0 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + gd32f4xx_usart.c + 0 + 0 + + + 9 + 55 + 1 + 0 + 0 + 0 + ..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c + system_gd32f4xx.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.uvproj b/bsp/gd32/arm/gd32470z-lckfb/project.uvproj new file mode 100644 index 0000000000..c114f67f78 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/project.uvproj @@ -0,0 +1,838 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 0 + + + GD32F450ZK + GigaDevice + IRAM(0x20000000-0x20030000) IRAM2(0x10000000-0x10010000) IROM(0x08000000-0x08300000) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000) + 0 + gd32f4xx0.h + + + + + + + + + + SFD\GD\GD32F4xx\GD32F4xx.SFR + 0 + 0 + + + + GD\GD32F4xx\ + GD\GD32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\output\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 3 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 1 + 0x8000000 + 0x300000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x300000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + __STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, GD32F450, __RTTHREAD__, RT_USING_ARM_LIBC + + applications;.;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\libcpu\arm\common;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;board;..\libraries\gd32_drivers;..\..\..\..\components\dfs\include;..\..\..\..\components\finsh;.;..\..\..\..\include;..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Include;..\libraries\GD32F4xx_Firmware_Library\CMSIS;..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\libc\posix\io\stdio;..\..\..\..\components\libc\posix\ipc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdio.c + 1 + ..\..\..\..\components\libc\compilers\common\cstdio.c + + + + + cstdlib.c + 1 + ..\..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\..\components\libc\compilers\common\ctime.c + + + + + cwchar.c + 1 + ..\..\..\..\components\libc\compilers\common\cwchar.c + + + + + CPU + + + backtrace.c + 1 + ..\..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + cpuport.c + 1 + ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + DeviceDrivers + + + completion.c + 1 + ..\..\..\..\components\drivers\ipc\completion.c + + + + + dataqueue.c + 1 + ..\..\..\..\components\drivers\ipc\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\..\components\drivers\ipc\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\..\components\drivers\ipc\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\..\components\drivers\ipc\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\..\components\drivers\ipc\workqueue.c + + + + + pin.c + 1 + ..\..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\..\components\drivers\serial\serial.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + startup_gd32f4xx.s + 2 + ..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s + + + + + drv_gpio.c + 1 + ..\libraries\gd32_drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\gd32_drivers\drv_usart.c + + + + + Filesystem + + + dfs_posix.c + 1 + ..\..\..\..\components\dfs\src\dfs_posix.c + + + + + dfs_fs.c + 1 + ..\..\..\..\components\dfs\src\dfs_fs.c + + + + + dfs.c + 1 + ..\..\..\..\components\dfs\src\dfs.c + + + + + dfs_file.c + 1 + ..\..\..\..\components\dfs\src\dfs_file.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\..\components\finsh\cmd.c + + + + + msh_file.c + 1 + ..\..\..\..\components\finsh\msh_file.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\..\src\scheduler.c + + + + + thread.c + 1 + ..\..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\..\src\timer.c + + + + + Libraries + + + gd32f4xx_syscfg.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c + + + + + gd32f4xx_exti.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c + + + + + gd32f4xx_gpio.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c + + + + + gd32f4xx_rcu.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c + + + + + gd32f4xx_misc.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c + + + + + gd32f4xx_usart.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + + + + + system_gd32f4xx.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c + + + + + + + diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx b/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx new file mode 100644 index 0000000000..c76740ed61 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx @@ -0,0 +1,732 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 0 + + + GD32F470ZG + GigaDevice + GigaDevice.GD32F4xx_DFP.3.0.0 + http://gd32mcu.com/data/documents/pack/ + IRAM(0x20000000,0x070000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x0100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB -FS08000000 -FL0100000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM)) + 0 + $$Device:GD32F470ZG$Device\F4XX\Include\gd32f4xx.h + + + + + + + + + + $$Device:GD32F470ZG$SVD\GD32F4xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x70000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x70000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, GD32F470, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__ + + ..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\stdio;..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\finsh;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\gd32_drivers;board;..\..\..\..\libcpu\arm\common;..\libraries\GD32F4xx_Firmware_Library\CMSIS;applications;..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\include;.;..\..\..\..\components\libc\posix\ipc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\gd32_rom.ld + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + syscalls.c + 1 + ..\..\..\..\components\libc\compilers\armlibc\syscalls.c + + + cctype.c + 1 + ..\..\..\..\components\libc\compilers\common\cctype.c + + + cstdio.c + 1 + ..\..\..\..\components\libc\compilers\common\cstdio.c + + + cstdlib.c + 1 + ..\..\..\..\components\libc\compilers\common\cstdlib.c + + + cstring.c + 1 + ..\..\..\..\components\libc\compilers\common\cstring.c + + + ctime.c + 1 + ..\..\..\..\components\libc\compilers\common\ctime.c + + + cwchar.c + 1 + ..\..\..\..\components\libc\compilers\common\cwchar.c + + + + + CPU + + + div0.c + 1 + ..\..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + cpuport.c + 1 + ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + DeviceDrivers + + + completion.c + 1 + ..\..\..\..\components\drivers\ipc\completion.c + + + dataqueue.c + 1 + ..\..\..\..\components\drivers\ipc\dataqueue.c + + + pipe.c + 1 + ..\..\..\..\components\drivers\ipc\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\..\components\drivers\ipc\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\..\components\drivers\ipc\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\..\components\drivers\ipc\waitqueue.c + + + workqueue.c + 1 + ..\..\..\..\components\drivers\ipc\workqueue.c + + + pin.c + 1 + ..\..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\..\components\drivers\serial\serial.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + startup_gd32f4xx.s + 2 + ..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s + + + drv_gpio.c + 1 + ..\libraries\gd32_drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\gd32_drivers\drv_usart.c + + + + + Filesystem + + + dfs_posix.c + 1 + ..\..\..\..\components\dfs\src\dfs_posix.c + + + dfs_fs.c + 1 + ..\..\..\..\components\dfs\src\dfs_fs.c + + + dfs.c + 1 + ..\..\..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\..\..\components\dfs\src\dfs_file.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\..\components\finsh\msh.c + + + msh_parse.c + 1 + ..\..\..\..\components\finsh\msh_parse.c + + + cmd.c + 1 + ..\..\..\..\components\finsh\cmd.c + + + msh_file.c + 1 + ..\..\..\..\components\finsh\msh_file.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\..\src\components.c + + + device.c + 1 + ..\..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\..\src\scheduler.c + + + thread.c + 1 + ..\..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\..\src\timer.c + + + + + Libraries + + + gd32f4xx_syscfg.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c + + + gd32f4xx_exti.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c + + + gd32f4xx_gpio.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c + + + gd32f4xx_rcu.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c + + + gd32f4xx_misc.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c + + + gd32f4xx_usart.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + + + system_gd32f4xx.c + 1 + ..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/gd32/arm/gd32470z-lckfb/rtconfig.h b/bsp/gd32/arm/gd32470z-lckfb/rtconfig.h new file mode 100644 index 0000000000..ccdb397b6a --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/rtconfig.h @@ -0,0 +1,201 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 11 +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50000 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define SOC_SERIES_GD32F4xx +#define SOC_GD32470Z + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/gd32/arm/gd32470z-lckfb/rtconfig.py b/bsp/gd32/arm/gd32470z-lckfb/rtconfig.py new file mode 100644 index 0000000000..81ad46ee79 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='keil' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -DGD32F450' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/gd32/arm/gd32470z-lckfb/template.ewp b/bsp/gd32/arm/gd32470z-lckfb/template.ewp new file mode 100644 index 0000000000..963857b281 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/template.ewp @@ -0,0 +1,1892 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/gd32/arm/gd32470z-lckfb/template.uvoptx b/bsp/gd32/arm/gd32470z-lckfb/template.uvoptx new file mode 100644 index 0000000000..14dde5e4db --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/template.uvoptx @@ -0,0 +1,185 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F4xx_1MB -FL0100000 -FS08000000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB.FLM -FS08000000 -FL0100000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/gd32/arm/gd32470z-lckfb/template.uvproj b/bsp/gd32/arm/gd32470z-lckfb/template.uvproj new file mode 100644 index 0000000000..d7a936eb29 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/template.uvproj @@ -0,0 +1,628 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 0 + + + GD32F450ZK + GigaDevice + IRAM(0x20000000-0x20030000) IRAM2(0x10000000-0x10010000) IROM(0x08000000-0x08300000) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000) + 0 + gd32f4xx0.h + + + + + + + + + + SFD\GD\GD32F4xx\GD32F4xx.SFR + 0 + 0 + + + + GD\GD32F4xx\ + GD\GD32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\output\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 3 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 1 + 0x8000000 + 0x300000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x300000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Include;..\..\..\Library\Utilities;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application + + + main.c + 1 + ..\main.c + + + gd32f4xx_it.c + 1 + ..\gd32f4xx_it.c + + + + + CMSIS + + + system_gd32f4xx.c + 1 + ..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c + + + + + GD32F4xx_Peripherals + + + gd32f4xx_adc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c + + + gd32f4xx_can.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c + + + gd32f4xx_crc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_crc.c + + + gd32f4xx_ctc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c + + + gd32f4xx_dac.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c + + + gd32f4xx_dbg.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c + + + gd32f4xx_dci.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c + + + gd32f4xx_dma.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c + + + gd32f4xx_enet.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c + + + gd32f4xx_exmc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exmc.c + + + gd32f4xx_exti.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c + + + gd32f4xx_fmc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c + + + gd32f4xx_fwdgt.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fwdgt.c + + + gd32f4xx_gpio.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c + + + gd32f4xx_i2c.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c + + + gd32f4xx_ipa.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c + + + gd32f4xx_iref.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c + + + gd32f4xx_misc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c + + + gd32f4xx_pmu.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c + + + gd32f4xx_rcu.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c + + + gd32f4xx_rtc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rtc.c + + + gd32f4xx_sdio.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c + + + gd32f4xx_spi.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c + + + gd32f4xx_syscfg.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c + + + gd32f4xx_timer.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c + + + gd32f4xx_tli.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_tli.c + + + gd32f4xx_trng.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_trng.c + + + gd32f4xx_usart.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + + + gd32f4xx_wwdgt.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c + + + + + GD32F4xx_EVAL + + + gd32f450z_eval.c + 1 + ..\..\..\Library\Utilities\gd32f450z_eval.c + + + + + Startup + + + startup_gd32f4xx.s + 2 + ..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + + + + diff --git a/bsp/gd32/arm/gd32470z-lckfb/template.uvprojx b/bsp/gd32/arm/gd32470z-lckfb/template.uvprojx new file mode 100644 index 0000000000..6b18f2e8f2 --- /dev/null +++ b/bsp/gd32/arm/gd32470z-lckfb/template.uvprojx @@ -0,0 +1,412 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 0 + + + GD32F470ZG + GigaDevice + GigaDevice.GD32F4xx_DFP.3.0.0 + http://gd32mcu.com/data/documents/pack/ + IRAM(0x20000000,0x070000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x0100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB -FS08000000 -FL0100000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM)) + 0 + $$Device:GD32F470ZG$Device\F4XX\Include\gd32f4xx.h + + + + + + + + + + $$Device:GD32F470ZG$SVD\GD32F4xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x70000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x70000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\gd32_rom.ld + + + + + + + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/gd32/arm/libraries/.ignore_format.yml b/bsp/gd32/arm/libraries/.ignore_format.yml new file mode 100644 index 0000000000..eecf5a711f --- /dev/null +++ b/bsp/gd32/arm/libraries/.ignore_format.yml @@ -0,0 +1,9 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- GD32F10x_Firmware_Library +- GD32F20x_Firmware_Library +- GD32F30x_Firmware_Library +- GD32F4xx_Firmware_Library diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h index a901975bbd..de1d1364f7 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h @@ -1,7 +1,7 @@ /*! \file gd32f4xx.h \brief general definitions for GD32F4xx - + \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx @@ -10,27 +10,27 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -39,16 +39,19 @@ OF SUCH DAMAGE. #ifdef __cplusplus extern "C" { -#endif +#endif /* define GD32F4xx */ -#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) /* #define GD32F450 */ /* #define GD32F405 */ /* #define GD32F407 */ + /* #define GD32F470 */ + /* #define GD32F425 */ + /* #define GD32F427 */ #endif /* define GD32F4xx */ - -#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) + +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427) #error "Please select the target GD32F4xx device in gd32f4xx.h file" #endif /* undefine GD32F4xx tip */ @@ -63,7 +66,7 @@ OF SUCH DAMAGE. #endif /* high speed crystal oscillator startup timeout */ /* define value of internal 16MHz RC oscillator (IRC16M) in Hz */ -#if !defined (IRC16M_VALUE) +#if !defined (IRC16M_VALUE) #define IRC16M_VALUE ((uint32_t)16000000) #endif /* internal 16MHz RC oscillator value */ @@ -73,12 +76,12 @@ OF SUCH DAMAGE. #endif /* internal 16MHz RC oscillator startup timeout */ /* define value of internal 32KHz RC oscillator(IRC32K) in Hz */ -#if !defined (IRC32K_VALUE) +#if !defined (IRC32K_VALUE) #define IRC32K_VALUE ((uint32_t)32000) #endif /* internal 32KHz RC oscillator value */ /* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) +#if !defined (LXTAL_VALUE) #define LXTAL_VALUE ((uint32_t)32768) #endif /* low speed crystal oscillator value */ @@ -89,7 +92,7 @@ OF SUCH DAMAGE. #define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ #define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\ |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\ |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\ @@ -162,8 +165,8 @@ typedef enum IRQn TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */ - -#if defined (GD32F450) + +#if defined (GD32F450) || defined (GD32F470) EXMC_IRQn = 48, /*!< EXMC interrupt */ SDIO_IRQn = 49, /*!< SDIO interrupt */ TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ @@ -205,9 +208,9 @@ typedef enum IRQn TLI_IRQn = 88, /*!< TLI interrupt */ TLI_ER_IRQn = 89, /*!< TLI error interrupt */ IPA_IRQn = 90, /*!< IPA interrupt */ -#endif /* GD32F450 */ +#endif /* GD32F450 and GD32F470 */ -#if defined (GD32F405) +#if defined (GD32F405) || defined (GD32F425) SDIO_IRQn = 49, /*!< SDIO interrupt */ TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ SPI2_IRQn = 51, /*!< SPI2 interrupt */ @@ -238,9 +241,9 @@ typedef enum IRQn DCI_IRQn = 78, /*!< DCI interrupt */ TRNG_IRQn = 80, /*!< TRNG interrupt */ FPU_IRQn = 81, /*!< FPU interrupt */ -#endif /* GD32F405 */ +#endif /* GD32F405 and GD32F425 */ -#if defined (GD32F407) +#if defined (GD32F407) || defined (GD32F427) EXMC_IRQn = 48, /*!< EXMC interrupt */ SDIO_IRQn = 49, /*!< SDIO interrupt */ TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ @@ -274,7 +277,7 @@ typedef enum IRQn DCI_IRQn = 78, /*!< DCI interrupt */ TRNG_IRQn = 80, /*!< TRNG interrupt */ FPU_IRQn = 81, /*!< FPU interrupt */ -#endif /* GD32F407 */ +#endif /* GD32F407 and GD32F427 */ } IRQn_Type; @@ -285,7 +288,6 @@ typedef enum IRQn /* enum definitions */ typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {FALSE = 0, TRUE = !FALSE} bool; typedef enum {RESET = 0, SET = !RESET} FlagStatus; typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; @@ -294,7 +296,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) /* main flash and SRAM memory map */ @@ -355,12 +357,12 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; /* define marco USE_STDPERIPH_DRIVER */ #if !defined USE_STDPERIPH_DRIVER #define USE_STDPERIPH_DRIVER -#endif +#endif #ifdef USE_STDPERIPH_DRIVER #include "gd32f4xx_libopt.h" #endif /* USE_STDPERIPH_DRIVER */ -#ifdef cplusplus +#ifdef __cplusplus } #endif -#endif +#endif diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f405_425.s b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f405_425.s new file mode 100644 index 0000000000..2e5eba5f0d --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f405_425.s @@ -0,0 +1,423 @@ +;/*! +; \file startup_gd32f405_425.s +; \brief start up file +; +; \version 2016-08-15, V1.0.0, firmware for GD32F4xx +; \version 2018-12-12, V2.0.0, firmware for GD32F4xx +; \version 2020-09-30, V2.1.0, firmware for GD32F4xx +; \version 2022-03-09, V3.0.0, firmware for GD32F4xx +;*/ +; +;/* +; Copyright (c) 2022, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect + DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC_IRQHandler ; 34:ADC + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 + DCD 0 ; 64:Reserved + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD 0 ; 77:Reserved + DCD 0 ; 78:Reserved + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 + DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 + DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 + DCD USART5_IRQHandler ; 87:USART5 + DCD I2C2_EV_IRQHandler ; 88:I2C2 Event + DCD I2C2_ER_IRQHandler ; 89:I2C2 Error + DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out + DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in + DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line + DCD USBHS_IRQHandler ; 93:USBHS + DCD DCI_IRQHandler ; 94:DCI + DCD 0 ; 95:Reserved + DCD TRNG_IRQHandler ; 96:TRNG + DCD FPU_IRQHandler ; 97:FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT DMA0_Channel7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_DAC_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT USBHS_EP1_Out_IRQHandler [WEAK] + EXPORT USBHS_EP1_In_IRQHandler [WEAK] + EXPORT USBHS_WKUP_IRQHandler [WEAK] + EXPORT USBHS_IRQHandler [WEAK] + EXPORT DCI_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +DMA0_Channel7_IRQHandler +SDIO_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_DAC_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +USART5_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +USBHS_EP1_Out_IRQHandler +USBHS_EP1_In_IRQHandler +USBHS_WKUP_IRQHandler +USBHS_IRQHandler +DCI_IRQHandler +TRNG_IRQHandler +FPU_IRQHandler + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f407_427.s b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f407_427.s new file mode 100644 index 0000000000..4569d8adaa --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f407_427.s @@ -0,0 +1,429 @@ +;/*! +; \file startup_gd32f407_427.s +; \brief start up file +; +; \version 2016-08-15, V1.0.0, firmware for GD32F4xx +; \version 2018-12-12, V2.0.0, firmware for GD32F4xx +; \version 2020-09-30, V2.1.0, firmware for GD32F4xx +; \version 2022-03-09, V3.0.0, firmware for GD32F4xx +;*/ +; +;/* +; Copyright (c) 2022, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect + DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC_IRQHandler ; 34:ADC + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Capture Compare + DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 + DCD EXMC_IRQHandler ; 64:EXMC + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 + DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 + DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 + DCD USART5_IRQHandler ; 87:USART5 + DCD I2C2_EV_IRQHandler ; 88:I2C2 Event + DCD I2C2_ER_IRQHandler ; 89:I2C2 Error + DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out + DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in + DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line + DCD USBHS_IRQHandler ; 93:USBHS + DCD DCI_IRQHandler ; 94:DCI + DCD 0 ; 95:Reserved + DCD TRNG_IRQHandler ; 96:TRNG + DCD FPU_IRQHandler ; 97:FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT DMA0_Channel7_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_DAC_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT ENET_WKUP_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT USBHS_EP1_Out_IRQHandler [WEAK] + EXPORT USBHS_EP1_In_IRQHandler [WEAK] + EXPORT USBHS_WKUP_IRQHandler [WEAK] + EXPORT USBHS_IRQHandler [WEAK] + EXPORT DCI_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +DMA0_Channel7_IRQHandler +EXMC_IRQHandler +SDIO_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_DAC_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +ENET_IRQHandler +ENET_WKUP_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +USART5_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +USBHS_EP1_Out_IRQHandler +USBHS_EP1_In_IRQHandler +USBHS_WKUP_IRQHandler +USBHS_IRQHandler +DCI_IRQHandler +TRNG_IRQHandler +FPU_IRQHandler + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f450_470.s b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f450_470.s new file mode 100644 index 0000000000..85b978a681 --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f450_470.s @@ -0,0 +1,454 @@ +;/*! +; \file startup_gd32f450_470.s +; \brief start up file +; +; \version 2016-08-15, V1.0.0, firmware for GD32F4xx +; \version 2018-12-12, V2.0.0, firmware for GD32F4xx +; \version 2020-09-30, V2.1.0, firmware for GD32F4xx +; \version 2022-03-09, V3.0.0, firmware for GD32F4xx +;*/ +; +;/* +; Copyright (c) 2022, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect + DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC_IRQHandler ; 34:ADC + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 + DCD EXMC_IRQHandler ; 64:EXMC + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 + DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 + DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 + DCD USART5_IRQHandler ; 87:USART5 + DCD I2C2_EV_IRQHandler ; 88:I2C2 Event + DCD I2C2_ER_IRQHandler ; 89:I2C2 Error + DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out + DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in + DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line + DCD USBHS_IRQHandler ; 93:USBHS + DCD DCI_IRQHandler ; 94:DCI + DCD 0 ; 95:Reserved + DCD TRNG_IRQHandler ; 96:TRNG + DCD FPU_IRQHandler ; 97:FPU + DCD UART6_IRQHandler ; 98:UART6 + DCD UART7_IRQHandler ; 99:UART7 + DCD SPI3_IRQHandler ; 100:SPI3 + DCD SPI4_IRQHandler ; 101:SPI4 + DCD SPI5_IRQHandler ; 102:SPI5 + DCD 0 ; 103:Reserved + DCD TLI_IRQHandler ; 104:TLI + DCD TLI_ER_IRQHandler ; 105:TLI Error + DCD IPA_IRQHandler ; 106:IPA + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT DMA0_Channel7_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_DAC_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT ENET_WKUP_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT USBHS_EP1_Out_IRQHandler [WEAK] + EXPORT USBHS_EP1_In_IRQHandler [WEAK] + EXPORT USBHS_WKUP_IRQHandler [WEAK] + EXPORT USBHS_IRQHandler [WEAK] + EXPORT DCI_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART6_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT TLI_IRQHandler [WEAK] + EXPORT TLI_ER_IRQHandler [WEAK] + EXPORT IPA_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +DMA0_Channel7_IRQHandler +EXMC_IRQHandler +SDIO_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_DAC_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +ENET_IRQHandler +ENET_WKUP_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +USART5_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +USBHS_EP1_Out_IRQHandler +USBHS_EP1_In_IRQHandler +USBHS_WKUP_IRQHandler +USBHS_IRQHandler +DCI_IRQHandler +TRNG_IRQHandler +FPU_IRQHandler +UART6_IRQHandler +UART7_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +TLI_IRQHandler +TLI_ER_IRQHandler +IPA_IRQHandler + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f405_425.s b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f405_425.s new file mode 100644 index 0000000000..28eb812a71 --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f405_425.s @@ -0,0 +1,602 @@ +;/*! +; \file startup_gd32f405_425.s +; \brief start up file +; +; \version 2016-08-15, V1.0.0, firmware for GD32F4xx +; \version 2018-12-12, V2.0.0, firmware for GD32F4xx +; \version 2020-09-30, V2.1.0, firmware for GD32F4xx +; \version 2022-03-09, V3.0.0, firmware for GD32F4xx +;*/ +; +;/* +; Copyright (c) 2022, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Vector Number 1,Reset Handler + + DCD NMI_Handler ; Vector Number 2,NMI Handler + DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler + DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler + DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler + DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; Vector Number 11,SVCall Handler + DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; Vector Number 14,PendSV Handler + DCD SysTick_Handler ; Vector Number 15,SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect + DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC_IRQHandler ; 34:ADC + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Capture Compare + DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 + DCD 0 ; 64:Reserved + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD 0 ; 77:Reserved + DCD 0 ; 78:Reserved + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 + DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 + DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 + DCD USART5_IRQHandler ; 87:USART5 + DCD I2C2_EV_IRQHandler ; 88:I2C2 Event + DCD I2C2_ER_IRQHandler ; 89:I2C2 Error + DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out + DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in + DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line + DCD USBHS_IRQHandler ; 93:USBHS + DCD DCI_IRQHandler ; 94:DCI + DCD 0 ; 95:Reserved + DCD TRNG_IRQHandler ; 96:TRNG + DCD FPU_IRQHandler ; 97:FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_CTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_CTC_IRQHandler + B RCU_CTC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_TX_IRQHandler + B CAN0_TX_IRQHandler + + PUBWEAK CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX0_IRQHandler + B CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_TIMER8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_TIMER8_IRQHandler + B TIMER0_BRK_TIMER8_IRQHandler + + PUBWEAK TIMER0_UP_TIMER9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_TIMER9_IRQHandler + B TIMER0_UP_TIMER9_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_TIMER10_IRQHandler + B TIMER0_TRG_CMT_TIMER10_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBFS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_WKUP_IRQHandler + B USBFS_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_TIMER11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_TIMER11_IRQHandler + B TIMER7_BRK_TIMER11_IRQHandler + + PUBWEAK TIMER7_UP_TIMER12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_TIMER12_IRQHandler + B TIMER7_UP_TIMER12_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_TIMER13_IRQHandler + B TIMER7_TRG_CMT_TIMER13_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK DMA0_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel7_IRQHandler + B DMA0_Channel7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_DAC_IRQHandler + B TIMER5_DAC_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_EWMC_IRQHandler + B CAN1_EWMC_IRQHandler + + PUBWEAK USBFS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_IRQHandler + B USBFS_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK USART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART5_IRQHandler + B USART5_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK USBHS_EP1_Out_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_EP1_Out_IRQHandler + B USBHS_EP1_Out_IRQHandler + + PUBWEAK USBHS_EP1_In_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_EP1_In_IRQHandler + B USBHS_EP1_In_IRQHandler + + PUBWEAK USBHS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_WKUP_IRQHandler + B USBHS_WKUP_IRQHandler + + PUBWEAK USBHS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_IRQHandler + B USBHS_IRQHandler + + PUBWEAK DCI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCI_IRQHandler + B DCI_IRQHandler + + PUBWEAK TRNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TRNG_IRQHandler + B TRNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + END \ No newline at end of file diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f407_427.s b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f407_427.s new file mode 100644 index 0000000000..c11f8e7851 --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f407_427.s @@ -0,0 +1,617 @@ +;/*! +; \file startup_gd32f407_427.s +; \brief start up file +; +; \version 2016-08-15, V1.0.0, firmware for GD32F4xx +; \version 2018-12-12, V2.0.0, firmware for GD32F4xx +; \version 2020-09-30, V2.1.0, firmware for GD32F4xx +; \version 2022-03-09, V3.0.0, firmware for GD32F4xx +;*/ +; +;/* +; Copyright (c) 2022, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Vector Number 1,Reset Handler + + DCD NMI_Handler ; Vector Number 2,NMI Handler + DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler + DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler + DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler + DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; Vector Number 11,SVCall Handler + DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; Vector Number 14,PendSV Handler + DCD SysTick_Handler ; Vector Number 15,SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect + DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC_IRQHandler ; 34:ADC + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 + DCD EXMC_IRQHandler ; 64:EXMC + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 + DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 + DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 + DCD USART5_IRQHandler ; 87:USART5 + DCD I2C2_EV_IRQHandler ; 88:I2C2 Event + DCD I2C2_ER_IRQHandler ; 89:I2C2 Error + DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out + DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in + DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line + DCD USBHS_IRQHandler ; 93:USBHS + DCD DCI_IRQHandler ; 94:DCI + DCD 0 ; 95:Reserved + DCD TRNG_IRQHandler ; 96:TRNG + DCD FPU_IRQHandler ; 97:FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_CTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_CTC_IRQHandler + B RCU_CTC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_TX_IRQHandler + B CAN0_TX_IRQHandler + + PUBWEAK CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX0_IRQHandler + B CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_TIMER8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_TIMER8_IRQHandler + B TIMER0_BRK_TIMER8_IRQHandler + + PUBWEAK TIMER0_UP_TIMER9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_TIMER9_IRQHandler + B TIMER0_UP_TIMER9_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_TIMER10_IRQHandler + B TIMER0_TRG_CMT_TIMER10_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBFS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_WKUP_IRQHandler + B USBFS_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_TIMER11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_TIMER11_IRQHandler + B TIMER7_BRK_TIMER11_IRQHandler + + PUBWEAK TIMER7_UP_TIMER12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_TIMER12_IRQHandler + B TIMER7_UP_TIMER12_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_TIMER13_IRQHandler + B TIMER7_TRG_CMT_TIMER13_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK DMA0_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel7_IRQHandler + B DMA0_Channel7_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_DAC_IRQHandler + B TIMER5_DAC_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK ENET_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_IRQHandler + B ENET_IRQHandler + + PUBWEAK ENET_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_WKUP_IRQHandler + B ENET_WKUP_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_EWMC_IRQHandler + B CAN1_EWMC_IRQHandler + + PUBWEAK USBFS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_IRQHandler + B USBFS_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK USART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART5_IRQHandler + B USART5_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK USBHS_EP1_Out_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_EP1_Out_IRQHandler + B USBHS_EP1_Out_IRQHandler + + PUBWEAK USBHS_EP1_In_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_EP1_In_IRQHandler + B USBHS_EP1_In_IRQHandler + + PUBWEAK USBHS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_WKUP_IRQHandler + B USBHS_WKUP_IRQHandler + + PUBWEAK USBHS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_IRQHandler + B USBHS_IRQHandler + + PUBWEAK DCI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCI_IRQHandler + B DCI_IRQHandler + + PUBWEAK TRNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TRNG_IRQHandler + B TRNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + END \ No newline at end of file diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f450_470.s b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f450_470.s new file mode 100644 index 0000000000..6727f0714e --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f450_470.s @@ -0,0 +1,666 @@ +;/*! +; \file startup_gd32f450_470.s +; \brief start up file +; +; \version 2016-08-15, V1.0.0, firmware for GD32F4xx +; \version 2018-12-12, V2.0.0, firmware for GD32F4xx +; \version 2020-09-30, V2.1.0, firmware for GD32F4xx +; \version 2022-03-09, V3.0.0, firmware for GD32F4xx +;*/ +; +;/* +; Copyright (c) 2022, GigaDevice Semiconductor Inc. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Vector Number 1,Reset Handler + + DCD NMI_Handler ; Vector Number 2,NMI Handler + DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler + DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler + DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler + DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; Vector Number 11,SVCall Handler + DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; Vector Number 14,PendSV Handler + DCD SysTick_Handler ; Vector Number 15,SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect + DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC_IRQHandler ; 34:ADC + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 + DCD EXMC_IRQHandler ; 64:EXMC + DCD SDIO_IRQHandler ; 65:SDIO + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 + DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 + DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 + DCD USART5_IRQHandler ; 87:USART5 + DCD I2C2_EV_IRQHandler ; 88:I2C2 Event + DCD I2C2_ER_IRQHandler ; 89:I2C2 Error + DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out + DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in + DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line + DCD USBHS_IRQHandler ; 93:USBHS + DCD DCI_IRQHandler ; 94:DCI + DCD 0 ; 95:Reserved + DCD TRNG_IRQHandler ; 96:TRNG + DCD FPU_IRQHandler ; 97:FPU + DCD UART6_IRQHandler ; 98:UART6 + DCD UART7_IRQHandler ; 99:UART7 + DCD SPI3_IRQHandler ; 100:SPI3 + DCD SPI4_IRQHandler ; 101:SPI4 + DCD SPI5_IRQHandler ; 102:SPI5 + DCD 0 ; 103:Reserved + DCD TLI_IRQHandler ; 104:TLI + DCD TLI_ER_IRQHandler ; 105:TLI Error + DCD IPA_IRQHandler ; 106:IPA + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_CTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_CTC_IRQHandler + B RCU_CTC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_TX_IRQHandler + B CAN0_TX_IRQHandler + + PUBWEAK CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX0_IRQHandler + B CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_TIMER8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_TIMER8_IRQHandler + B TIMER0_BRK_TIMER8_IRQHandler + + PUBWEAK TIMER0_UP_TIMER9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_TIMER9_IRQHandler + B TIMER0_UP_TIMER9_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_TIMER10_IRQHandler + B TIMER0_TRG_CMT_TIMER10_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBFS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_WKUP_IRQHandler + B USBFS_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_TIMER11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_TIMER11_IRQHandler + B TIMER7_BRK_TIMER11_IRQHandler + + PUBWEAK TIMER7_UP_TIMER12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_TIMER12_IRQHandler + B TIMER7_UP_TIMER12_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_TIMER13_IRQHandler + B TIMER7_TRG_CMT_TIMER13_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK DMA0_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel7_IRQHandler + B DMA0_Channel7_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_DAC_IRQHandler + B TIMER5_DAC_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK ENET_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_IRQHandler + B ENET_IRQHandler + + PUBWEAK ENET_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_WKUP_IRQHandler + B ENET_WKUP_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_EWMC_IRQHandler + B CAN1_EWMC_IRQHandler + + PUBWEAK USBFS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_IRQHandler + B USBFS_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK USART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART5_IRQHandler + B USART5_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK USBHS_EP1_Out_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_EP1_Out_IRQHandler + B USBHS_EP1_Out_IRQHandler + + PUBWEAK USBHS_EP1_In_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_EP1_In_IRQHandler + B USBHS_EP1_In_IRQHandler + + PUBWEAK USBHS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_WKUP_IRQHandler + B USBHS_WKUP_IRQHandler + + PUBWEAK USBHS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBHS_IRQHandler + B USBHS_IRQHandler + + PUBWEAK DCI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCI_IRQHandler + B DCI_IRQHandler + + PUBWEAK TRNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TRNG_IRQHandler + B TRNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART6_IRQHandler + B UART6_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK TLI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TLI_IRQHandler + B TLI_IRQHandler + + PUBWEAK TLI_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TLI_ER_IRQHandler + B TLI_ER_IRQHandler + + PUBWEAK IPA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IPA_IRQHandler + B IPA_IRQHandler + END \ No newline at end of file diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c index 2ea97ae3f8..25020f2795 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c @@ -52,14 +52,26 @@ //#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000) //#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000) #define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000) +//#define __SYSTEM_CLOCK_240M_PLL_IRC16M (uint32_t)(240000000) +//#define __SYSTEM_CLOCK_240M_PLL_8M_HXTAL (uint32_t)(240000000) +//#define __SYSTEM_CLOCK_240M_PLL_25M_HXTAL (uint32_t)(240000000) + +#define RCU_MODIFY(__delay) do{ \ + volatile uint32_t i; \ + if(0 != __delay){ \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ + for(i=0; i<__delay; i++){ \ + } \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \ + for(i=0; i<__delay; i++){ \ + } \ + } \ + }while(0) #define SEL_IRC16M 0x00U #define SEL_HXTAL 0x01U #define SEL_PLLP 0x02U -#define RCU_MODIFY {volatile uint32_t i; \ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ - for(i=0;i<50000;i++);} - + /* set the system clock frequency and declare the system clock configuration function */ #ifdef __SYSTEM_CLOCK_IRC16M uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC16M; @@ -94,6 +106,15 @@ static void system_clock_200m_8m_hxtal(void); #elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL; static void system_clock_200m_25m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_IRC16M; +static void system_clock_240m_irc16m(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_8M_HXTAL; +static void system_clock_240m_8m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_25M_HXTAL; +static void system_clock_240m_25m_hxtal(void); #endif /* __SYSTEM_CLOCK_IRC16M */ @@ -108,34 +129,41 @@ static void system_clock_config(void); */ void SystemInit (void) { - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCU clock configuration to the default reset state ------------*/ - /* Set IRC16MEN bit */ - RCU_CTL |= RCU_CTL_IRC16MEN; +#endif + /* Reset the RCU clock configuration to the default reset state */ + /* Set IRC16MEN bit */ + RCU_CTL |= RCU_CTL_IRC16MEN; + while(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + } + RCU_MODIFY(0x50); + + RCU_CFG0 &= ~RCU_CFG0_SCS; + + /* Reset HXTALEN, CKMEN and PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); - RCU_MODIFY + /* Reset HSEBYP bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* Reset CFG0 register */ + RCU_CFG0 = 0x00000000U; - /* Reset CFG0 register */ - RCU_CFG0 = 0x00000000U; + /* wait until IRC16M is selected as system clock */ + while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ + } - /* Reset HXTALEN, CKMEN and PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* Reset PLLCFGR register */ + RCU_PLL = 0x24003010U; - /* Reset PLLCFGR register */ - RCU_PLL = 0x24003010U; - - /* Reset HSEBYP bit */ - RCU_CTL &= ~(RCU_CTL_HXTALBPS); - - /* Disable all interrupts */ - RCU_INT = 0x00000000U; - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - system_clock_config(); + /* Disable all interrupts */ + RCU_INT = 0x00000000U; + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + system_clock_config(); } /*! \brief configure the system clock @@ -167,7 +195,13 @@ static void system_clock_config(void) system_clock_200m_8m_hxtal(); #elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) system_clock_200m_25m_hxtal(); -#endif /* __SYSTEM_CLOCK_IRC16M */ +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) + system_clock_240m_irc16m(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) + system_clock_240m_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) + system_clock_240m_25m_hxtal(); +#endif /* __SYSTEM_CLOCK_IRC16M */ } #ifdef __SYSTEM_CLOCK_IRC16M @@ -181,33 +215,33 @@ static void system_clock_16m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; - + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); - + /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ while(1){ } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - + /* select IRC16M as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_IRC16M; - + /* wait until IRC16M is selected as system clock */ while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ } @@ -224,33 +258,33 @@ static void system_clock_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; - + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - + /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ while(1){ } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - + /* select HXTAL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - + /* wait until HXTAL is selected as system clock */ while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ } @@ -267,7 +301,7 @@ static void system_clock_120m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -282,7 +316,7 @@ static void system_clock_120m_irc16m(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -294,7 +328,7 @@ static void system_clock_120m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (5U << 24U)); @@ -304,17 +338,17 @@ static void system_clock_120m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -335,7 +369,7 @@ static void system_clock_120m_8m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -350,7 +384,7 @@ static void system_clock_120m_8m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -362,7 +396,7 @@ static void system_clock_120m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (5U << 24U)); @@ -372,17 +406,17 @@ static void system_clock_120m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -403,7 +437,7 @@ static void system_clock_120m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -418,7 +452,7 @@ static void system_clock_120m_25m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -430,7 +464,7 @@ static void system_clock_120m_25m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (5U << 24U)); @@ -440,17 +474,17 @@ static void system_clock_120m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -471,7 +505,7 @@ static void system_clock_168m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -486,7 +520,7 @@ static void system_clock_168m_irc16m(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -498,7 +532,7 @@ static void system_clock_168m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (7U << 24U)); @@ -508,17 +542,17 @@ static void system_clock_168m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -538,7 +572,7 @@ static void system_clock_168m_irc16m(void) static void system_clock_168m_8m_hxtal(void) { uint32_t timeout = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -562,7 +596,7 @@ static void system_clock_168m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) | (RCU_PLLSRC_HXTAL) | (7 << 24U)); @@ -572,12 +606,12 @@ static void system_clock_168m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ @@ -603,7 +637,7 @@ static void system_clock_168m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -618,7 +652,7 @@ static void system_clock_168m_25m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -630,7 +664,7 @@ static void system_clock_168m_25m_hxtal(void) /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (7U << 24U)); @@ -640,17 +674,17 @@ static void system_clock_168m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -671,7 +705,7 @@ static void system_clock_200m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -686,7 +720,7 @@ static void system_clock_200m_irc16m(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -698,7 +732,7 @@ static void system_clock_200m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (9U << 24U)); @@ -708,17 +742,17 @@ static void system_clock_200m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -739,7 +773,7 @@ static void system_clock_200m_8m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -754,7 +788,7 @@ static void system_clock_200m_8m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -766,7 +800,7 @@ static void system_clock_200m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (9U << 24U)); @@ -776,17 +810,17 @@ static void system_clock_200m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -807,7 +841,7 @@ static void system_clock_200m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -822,7 +856,7 @@ static void system_clock_200m_25m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -834,7 +868,7 @@ static void system_clock_200m_25m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (9U << 24U)); @@ -844,17 +878,17 @@ static void system_clock_200m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -864,6 +898,209 @@ static void system_clock_200m_25m_hxtal(void) } } +#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M) +/*! + \brief configure the system clock to 240M by PLL which selects IRC16M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_irc16m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC16M */ + RCU_CTL |= RCU_CTL_IRC16MEN; + + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC16M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 16, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (16U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_IRC16M) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (8U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} + +#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL) +/*! + \brief configure the system clock to 240M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_240m_25m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 25, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */ + RCU_PLL = (25U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (10U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 240 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } +} #endif /* __SYSTEM_CLOCK_IRC16M */ /*! \brief update the SystemCoreClock with current core clock retrieved from cpu registers @@ -871,11 +1108,11 @@ static void system_clock_200m_25m_hxtal(void) \param[out] none \retval none */ -void SystemCoreClockUpdate (void) +void SystemCoreClockUpdate(void) { uint32_t sws; uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; - + /* exponent of AHB, APB1 and APB2 clock divider */ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; @@ -902,7 +1139,7 @@ void SystemCoreClockUpdate (void) } else { ck_src = IRC16M_VALUE; } - SystemCoreClock = ((ck_src / pllpsc) * plln)/pllp; + SystemCoreClock = ((ck_src / pllpsc) * plln) / pllp; break; /* IRC16M is selected as CK_SYS */ default: diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cm4.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cm4.h index e3cd89f728..d82841442c 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cm4.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cm4.h @@ -100,7 +100,7 @@ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline -#elif defined ( __CSMC__ ) /* Cosmic */ +#elif defined ( __CSMC__ ) /* Cosmic */ #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ @@ -170,8 +170,8 @@ #define __FPU_USED 0 #endif -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cmFunc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cmFunc.h index 834bd17645..3c932e0d6e 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cmFunc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cmFunc.h @@ -1,39 +1,25 @@ /**************************************************************************//** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.10 - * @date 18. March 2015 + * @version V3.01 + * @date 06. March 2012 * * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - #ifndef __CORE_CMFUNC_H #define __CORE_CMFUNC_H @@ -198,7 +184,7 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) } -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) +#if (__CORTEX_M >= 0x03) /** \brief Enable FIQ @@ -242,20 +228,6 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) } -/** \brief Set Base Priority with condition - - This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xff); -} - - /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. @@ -281,10 +253,10 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) __regFaultMask = (faultMask & (uint32_t)1); } -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ +#endif /* (__CORTEX_M >= 0x03) */ -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) +#if (__CORTEX_M == 0x04) /** \brief Get FPSCR @@ -317,7 +289,19 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) #endif } -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ @@ -330,7 +314,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) { - __ASM volatile ("cpsie i" : : : "memory"); + __ASM volatile ("cpsie i"); } @@ -341,7 +325,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) { - __ASM volatile ("cpsid i" : : : "memory"); + __ASM volatile ("cpsid i"); } @@ -368,7 +352,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) { - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ASM volatile ("MSR control, %0" : : "r" (control) ); } @@ -440,7 +424,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); } @@ -467,7 +451,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); } @@ -494,7 +478,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); } @@ -507,7 +491,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t p */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) { - __ASM volatile ("cpsie f" : : : "memory"); + __ASM volatile ("cpsie f"); } @@ -518,7 +502,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) { - __ASM volatile ("cpsid f" : : : "memory"); + __ASM volatile ("cpsid f"); } @@ -532,7 +516,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); return(result); } @@ -545,20 +529,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Set Base Priority with condition - - This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); } @@ -585,13 +556,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); } #endif /* (__CORTEX_M >= 0x03) */ -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) +#if (__CORTEX_M == 0x04) /** \brief Get FPSCR @@ -604,10 +575,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) uint32_t result; - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); return(result); #else return(0); @@ -624,41 +592,25 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); #endif } -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include +#endif /* (__CORTEX_M == 0x04) */ #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ + /* * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, + * Please use "carm -?i" to get an up to date list of all instrinsics, * Including the CMSIS ones. */ - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - #endif /*@} end of CMSIS_Core_RegAccFunctions */ + #endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cmInstr.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cmInstr.h index fca425c51d..597e64df04 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cmInstr.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/CMSIS/core_cmInstr.h @@ -1,39 +1,25 @@ /**************************************************************************//** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.10 - * @date 18. March 2015 + * @version V3.01 + * @date 06. March 2012 * * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - #ifndef __CORE_CMINSTR_H #define __CORE_CMINSTR_H @@ -89,33 +75,24 @@ so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0) +#define __ISB() __isb(0xF) + /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0) +#define __DSB() __dsb(0xF) + /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0) +#define __DMB() __dmb(0xF) + /** \brief Reverse byte order (32 bit) @@ -134,13 +111,12 @@ \param [in] value Value to reverse \return Reversed value */ -#ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } -#endif + /** \brief Reverse byte order in signed short value @@ -149,13 +125,11 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u \param [in] value Value to reverse \return Reversed value */ -#ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr } -#endif /** \brief Rotate Right in unsigned value (32 bit) @@ -169,16 +143,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in #define __ROR __ror -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - +#if (__CORTEX_M >= 0x03) /** \brief Reverse bit order of value @@ -187,42 +152,12 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value Value to reverse \return Reversed value */ -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end +#define __RBIT __rbit - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero - return(result); -} -#endif - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief LDR Exclusive (8 bit) - This function executes a exclusive LDR instruction for 8 bit value. + This function performs a exclusive LDR command for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) @@ -232,7 +167,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) /** \brief LDR Exclusive (16 bit) - This function executes a exclusive LDR instruction for 16 bit values. + This function performs a exclusive LDR command for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) @@ -242,7 +177,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) /** \brief LDR Exclusive (32 bit) - This function executes a exclusive LDR instruction for 32 bit values. + This function performs a exclusive LDR command for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) @@ -252,7 +187,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) /** \brief STR Exclusive (8 bit) - This function executes a exclusive STR instruction for 8 bit values. + This function performs a exclusive STR command for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location @@ -264,7 +199,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) /** \brief STR Exclusive (16 bit) - This function executes a exclusive STR instruction for 16 bit values. + This function performs a exclusive STR command for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location @@ -276,7 +211,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) /** \brief STR Exclusive (32 bit) - This function executes a exclusive STR instruction for 32 bit values. + This function performs a exclusive STR command for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location @@ -316,104 +251,39 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) #define __USAT __usat -/** \brief Rotate Right with Extend (32 bit) +/** \brief Count leading zeros - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. + This function counts the number of leading zeros of a data value. - \param [in] value Value to rotate - \return Rotated value + \param [in] value Value to count the leading zeros + \return number of leading zeros in value */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ -/** \brief LDRT Unprivileged (8 bit) - This function executes a Unprivileged LDRT instruction for 8 bit value. +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) +#include -/** \brief LDRT Unprivileged (16 bit) +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ +#include #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) { __ASM volatile ("nop"); } @@ -424,7 +294,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) { __ASM volatile ("wfi"); } @@ -435,7 +305,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __WFI(void) Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) { __ASM volatile ("wfe"); } @@ -445,7 +315,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __WFE(void) Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) { __ASM volatile ("sev"); } @@ -457,9 +327,9 @@ __attribute__((always_inline)) __STATIC_INLINE void __SEV(void) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) { - __ASM volatile ("isb 0xF":::"memory"); + __ASM volatile ("isb"); } @@ -468,9 +338,9 @@ __attribute__((always_inline)) __STATIC_INLINE void __ISB(void) This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) { - __ASM volatile ("dsb 0xF":::"memory"); + __ASM volatile ("dsb"); } @@ -479,9 +349,9 @@ __attribute__((always_inline)) __STATIC_INLINE void __DSB(void) This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) { - __ASM volatile ("dmb 0xF":::"memory"); + __ASM volatile ("dmb"); } @@ -492,16 +362,12 @@ __attribute__((always_inline)) __STATIC_INLINE void __DMB(void) \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) { -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else uint32_t result; - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); return(result); -#endif } @@ -512,11 +378,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); return(result); } @@ -528,16 +394,12 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) { -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else uint32_t result; - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); return(result); -#endif } @@ -549,22 +411,15 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) \param [in] value Number of Bits to rotate \return Rotated value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - return (op1 >> op2) | (op1 << (32 - op2)); + + __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); } -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - +#if (__CORTEX_M >= 0x03) /** \brief Reverse bit order of value @@ -573,152 +428,113 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end - - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero -#endif - return(result); + return(result); } -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - /** \brief LDR Exclusive (8 bit) - This function executes a exclusive LDR instruction for 8 bit value. + This function performs a exclusive LDR command for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { - uint32_t result; + uint8_t result; -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); } /** \brief LDR Exclusive (16 bit) - This function executes a exclusive LDR instruction for 16 bit values. + This function performs a exclusive LDR command for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { - uint32_t result; + uint16_t result; -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); } /** \brief LDR Exclusive (32 bit) - This function executes a exclusive LDR instruction for 32 bit values. + This function performs a exclusive LDR command for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); return(result); } /** \brief STR Exclusive (8 bit) - This function executes a exclusive STR instruction for 8 bit values. + This function performs a exclusive STR command for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); return(result); } /** \brief STR Exclusive (16 bit) - This function executes a exclusive STR instruction for 16 bit values. + This function performs a exclusive STR command for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); return(result); } /** \brief STR Exclusive (32 bit) - This function executes a exclusive STR instruction for 32 bit values. + This function performs a exclusive STR command for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); return(result); } @@ -728,9 +544,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, This function removes the exclusive lock which is created by LDREX. */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) { - __ASM volatile ("clrex" ::: "memory"); + __ASM volatile ("clrex"); } @@ -766,149 +582,35 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) }) -/** \brief Rotate Right with Extend (32 bit) +/** \brief Count leading zeros - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. + This function counts the number of leading zeros of a data value. - \param [in] value Value to rotate - \return Rotated value + \param [in] value Value to count the leading zeros + \return number of leading zeros in value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) { - uint32_t result; + uint8_t result; - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); return(result); } - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} +#endif /* (__CORTEX_M >= 0x03) */ -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ + /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - #endif /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h index 4f6020a50a..096b0c9568 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h @@ -1,36 +1,37 @@ /*! \file gd32f4xx_adc.h \brief definitions for the ADC - + \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -45,365 +46,365 @@ OF SUCH DAMAGE. #define ADC2 (ADC_BASE + 0x200U) /* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ -#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */ -#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */ -#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization regular data register */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC routine sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC routine sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC routine sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC routine data register */ +#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ +#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */ +#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */ +#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization routine data register */ /* bits definitions */ /* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ -#define ADC_STAT_ROVF BIT(5) /*!< regular data register overflow */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< routine channel start flag */ +#define ADC_STAT_ROVF BIT(5) /*!< routine data register overflow */ /* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ -#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted sequence conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on routine channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ +#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ /* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */ -#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted group */ -#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */ -#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */ -#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for regular group */ -#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for regular channels */ -#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of regular channels */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */ +#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted sequence */ +#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */ +#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for routine sequence */ +#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for routine channels */ +#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of routine channels */ /* ADC_SAMPTx x=0..1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ /* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ /* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ /* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ /* ADC_RSQx */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in routine sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< routine channel sequence length */ /* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in inserted sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ /* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ /* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< routine data */ /* ADC_OVSAMPCTL */ -#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ /* ADC_SSTAT */ -#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */ -#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */ -#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */ -#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */ -#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */ -#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */ -#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */ -#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */ -#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */ -#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */ -#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */ -#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */ -#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */ -#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */ -#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */ -#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */ -#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */ -#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */ +#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */ +#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */ +#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */ +#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */ +#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */ +#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */ +#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */ +#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */ +#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */ +#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */ +#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */ +#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */ +#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */ +#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */ +#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */ +#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */ +#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */ +#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */ /* ADC_SYNCCTL */ -#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */ -#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */ -#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */ -#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */ -#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */ -#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */ -#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */ +#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */ +#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */ +#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */ +#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */ +#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */ +#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */ +#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */ /* ADC_SYNCDATA */ -#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< regular data1 in ADC synchronization mode */ -#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< regular data2 in ADC synchronization mode */ +#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< routine data1 in ADC synchronization mode */ +#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< routine data2 in ADC synchronization mode */ /* constants definitions */ /* ADC status flag */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ -#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< routine channel start flag */ +#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ /* adc_ctl0 register value */ #define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ /* ADC special function definitions */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ /* temperature sensor channel, internal reference voltage channel, VBAT channel */ #define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */ #define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */ /* ADC synchronization mode */ -#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ -#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined regular parallel & inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined regular parallel & trigger rotation mode */ +#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined routine parallel & inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined routine parallel & trigger rotation mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in routine parallel mode. ADC2 works independently */ +#define ADC_DAUL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined routine parallel & inserted parallel mode */ +#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined routine parallel & trigger rotation mode */ #define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in regular parallel mode */ -#define ADC_ALL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ +#define ADC_ALL_ROUTINE_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in routine parallel mode */ +#define ADC_ALL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ #define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */ /* ADC data alignment */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ -/* external trigger mode for regular and inserted channel */ -#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ -#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ -#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ -#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ +/* external trigger mode for routine and inserted channel */ +#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ +#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ +#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ +#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ -/* ADC external trigger select for regular channel */ +/* ADC external trigger select for routine channel */ #define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */ -#define ADC_EXTTRIG_REGULAR_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */ +#define ADC_EXTTRIG_ROUTINE_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */ +#define ADC_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */ +#define ADC_EXTTRIG_ROUTINE_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */ /* ADC external trigger select for inserted channel */ #define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) -#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */ -#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */ -#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */ -#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */ -#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */ -#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */ -#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */ -#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */ -#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ +#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */ +#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */ +#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */ +#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */ +#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */ +#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ +#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ /* ADC channel sample time */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ -#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ -#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ -#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ -#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ -#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ -#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ -#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ +#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ +#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ +#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ +#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ +#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ +#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ +#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ /* adc_ioffx register value */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ /* adc_wdht register value */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ /* adc_wdlt register value */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ /* adc_rsqx register value */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ /* adc_isq register value */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ /* adc_ovsampctl register value */ /* ADC resolution */ -#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ -#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ +#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ /* oversampling shift */ -#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ -#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ /* oversampling ratio */ -#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ -/* triggered Oversampling */ -#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ +/* triggered oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ +/* ADC channel sequence definitions */ +#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< adc routine sequence */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted sequence */ +#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted sequence */ /* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ /* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ -#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ +#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ /* ADC interrupt flag */ -#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted group conversion interrupt */ -#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< regular data register overflow */ +#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of sequence conversion interrupt */ +#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< routine data register overflow */ /* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ -#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt */ +#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */ /* configure the ADC clock for all the ADCs */ #define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */ -#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */ -#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */ -#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */ -#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */ -#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */ -#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ -#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ +#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */ +#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */ +#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */ +#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */ +#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */ +#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */ +#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ +#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ /* ADC synchronization delay */ -#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ -#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ -#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */ -#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */ -#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */ -#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */ -#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */ -#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */ -#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */ -#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */ -#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */ -#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */ -#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */ -#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */ -#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */ -#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */ +#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ +#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ +#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */ +#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */ +#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */ +#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */ +#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */ +#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */ +#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */ +#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */ +#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */ +#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */ +#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */ +#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */ +#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */ +#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */ /* ADC synchronization DMA mode selection */ -#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */ -#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */ -#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */ +#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */ +#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */ +#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */ /* end of conversion mode */ -#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of regular conversions, the EOC bit is set */ -#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each regular conversion, the EOC bit is set */ +#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of routine conversions, the EOC bit is set */ +#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each routine conversion, the EOC bit is set */ /* function declarations */ /* initialization config */ @@ -437,35 +438,35 @@ void adc_oversample_mode_disable(uint32_t adc_periph); void adc_dma_mode_enable(uint32_t adc_periph); /* disable DMA request */ void adc_dma_mode_disable(uint32_t adc_periph); -/* when DMA=1, the DMA engine issues a request at end of each regular conversion */ +/* when DMA=1, the DMA engine issues a request at end of each routine conversion */ void adc_dma_request_after_last_enable(uint32_t adc_periph); /* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */ void adc_dma_request_after_last_disable(uint32_t adc_periph); -/* regular group and inserted group config */ +/* routine sequence and inserted sequence config */ /* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_sequence , uint8_t length); +/* configure the length of routine sequence or inserted sequence */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t length); +/* configure ADC routine channel */ +void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); /* configure ADC inserted channel */ void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); /* configure ADC inserted channel offset */ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); /* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source); +void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t external_trigger_source); /* enable ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode); +void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t trigger_mode); /* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence); /* configure end of conversion mode */ void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); /* get channel data */ -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ +/* read ADC routine data register */ +uint16_t adc_routine_data_read(uint32_t adc_periph); +/* read ADC inserted data register */ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); /* watchdog config */ @@ -473,10 +474,10 @@ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); void adc_watchdog_single_channel_disable(uint32_t adc_periph ); /* enable ADC analog watchdog single channel */ void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group); +/* configure ADC analog watchdog sequence */ +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph , uint8_t adc_sequence); /* disable ADC analog watchdog */ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group); +void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_sequence); /* configure ADC analog watchdog threshold */ void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); @@ -486,7 +487,7 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); /* clear the ADC flag bits */ void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); /* get the bit state of ADCx software start conversion */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph); /* get the bit state of ADCx software inserted channel start conversion */ FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); /* get the ADC interrupt bits */ @@ -509,7 +510,7 @@ void adc_sync_dma_config(uint32_t dma_mode ); void adc_sync_dma_request_after_last_enable(void); /* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */ void adc_sync_dma_request_after_last_disable(void); -/* read ADC sync regular data register */ -uint32_t adc_sync_regular_data_read(void); +/* read ADC sync routine data register */ +uint32_t adc_sync_routine_data_read(void); #endif /* GD32F4XX_ADC_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h index 7310f63a75..cff2ef7fc8 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h @@ -1,15 +1,16 @@ /*! \file gd32f4xx_can.h \brief definitions for the CAN - + \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2019-11-27, V2.0.1, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -35,105 +36,106 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI OF SUCH DAMAGE. */ + #ifndef GD32F4XX_CAN_H #define GD32F4XX_CAN_H #include "gd32f4xx.h" /* CAN definitions */ -#define CAN0 CAN_BASE /*!< CAN0 base address */ -#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ /* registers definitions */ -#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ -#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ -#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ -#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ -#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ -#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ -#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ -#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ -#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ -#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ -#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ -#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ -#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ -#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ -#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ -#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ -#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ -#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ -#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ -#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ -#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ -#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ -#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ -#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ -#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ -#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ -#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ -#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ -#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ -#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ -#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ -#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ -#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ -#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ -#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ -#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ -#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ -#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ -#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ -#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ -#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ -#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ -#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ -#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ -#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ -#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ -#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ -#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ -#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ -#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ -#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ -#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ -#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ -#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ -#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ -#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ -#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ -#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ -#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ -#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ -#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ -#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ -#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ -#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ -#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ -#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ -#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ -#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ -#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ -#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ -#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ -#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ -#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ -#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ -#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ -#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ -#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ -#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ -#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ -#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ -#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ -#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ -#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ -#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ -#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ -#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ +#define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */ /* CAN transmit mailbox bank */ #define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ @@ -145,7 +147,7 @@ OF SUCH DAMAGE. #define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ #define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ -/* CAN receive fifo mailbox bank */ +/* CAN receive FIFO mailbox bank */ #define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ #define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ #define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ @@ -295,10 +297,10 @@ OF SUCH DAMAGE. #define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ /* CAN_FMCFG */ -#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask */ /* CAN_FSCFG */ -#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits */ /* CAN_FAFIFO */ #define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ @@ -309,7 +311,7 @@ OF SUCH DAMAGE. /* CAN_FxDATAy */ #define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ -/* consts definitions */ +/* constants definitions */ /* define the CAN bit position and its register index offset */ #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) @@ -328,8 +330,7 @@ OF SUCH DAMAGE. #define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ /* CAN flags */ -typedef enum -{ +typedef enum { /* flags in STAT register */ CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ @@ -341,9 +342,9 @@ typedef enum CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ /* flags in TSTAT register */ - CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ - CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ - CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ + CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */ + CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */ + CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */ CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ @@ -369,11 +370,10 @@ typedef enum CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ -}can_flag_enum; +} can_flag_enum; /* CAN interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt flags in STAT register */ CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ @@ -389,17 +389,16 @@ typedef enum /* interrupt flags in RFIFO0 register */ CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ - CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */ + CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */ /* interrupt flags in ERR register */ CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ -}can_interrupt_flag_enum; +} can_interrupt_flag_enum; -/* CAN initiliaze parameters struct */ -typedef struct -{ +/* CAN initiliaze parameters structure */ +typedef struct { uint8_t working_mode; /*!< CAN working mode */ uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ uint8_t time_segment_1; /*!< time segment 1 */ @@ -407,26 +406,24 @@ typedef struct ControlStatus time_triggered; /*!< time triggered communication mode */ ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ + ControlStatus auto_retrans; /*!< automatic retransmission mode */ ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ ControlStatus trans_fifo_order; /*!< transmit FIFO order */ uint16_t prescaler; /*!< baudrate prescaler */ -}can_parameter_struct; +} can_parameter_struct; -/* CAN transmit message struct */ -typedef struct -{ +/* CAN transmit message structure */ +typedef struct { uint32_t tx_sfid; /*!< standard format frame identifier */ uint32_t tx_efid; /*!< extended format frame identifier */ uint8_t tx_ff; /*!< format of frame, standard or extended format */ uint8_t tx_ft; /*!< type of frame, data or remote */ uint8_t tx_dlen; /*!< data length */ uint8_t tx_data[8]; /*!< transmit data */ -}can_trasnmit_message_struct; +} can_trasnmit_message_struct; -/* CAN receive message struct */ -typedef struct -{ +/* CAN receive message structure */ +typedef struct { uint32_t rx_sfid; /*!< standard format frame identifier */ uint32_t rx_efid; /*!< extended format frame identifier */ uint8_t rx_ff; /*!< format of frame, standard or extended format */ @@ -436,10 +433,9 @@ typedef struct uint8_t rx_fi; /*!< filtering index */ } can_receive_message_struct; -/* CAN filter parameters struct */ -typedef struct -{ - uint16_t filter_list_high; /*!< filter list number high bits*/ +/* CAN filter parameters structure */ +typedef struct { + uint16_t filter_list_high; /*!< filter list number high bits */ uint16_t filter_list_low; /*!< filter list number low bits */ uint16_t filter_mask_high; /*!< filter mask number high bits */ uint16_t filter_mask_low; /*!< filter mask number low bits */ @@ -448,11 +444,10 @@ typedef struct uint16_t filter_mode; /*!< filter mode, list or mask */ uint16_t filter_bits; /*!< filter scale */ ControlStatus filter_enable; /*!< filter work or not */ -}can_filter_parameter_struct; +} can_filter_parameter_struct; /* CAN errors */ -typedef enum -{ +typedef enum { CAN_ERROR_NONE = 0, /*!< no error */ CAN_ERROR_FILL, /*!< fill error */ CAN_ERROR_FORMATE, /*!< format error */ @@ -461,38 +456,36 @@ typedef enum CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ CAN_ERROR_CRC, /*!< CRC error */ CAN_ERROR_SOFTWARECFG, /*!< software configure */ -}can_error_enum; +} can_error_enum; /* transmit states */ -typedef enum -{ - CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ -}can_transmit_state_enum; +typedef enum { + CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ +} can_transmit_state_enum; -typedef enum -{ +typedef enum { CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ CAN_FILTER_STRUCT, /* CAN filter parameters struct */ CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ -}can_struct_type_enum; +} can_struct_type_enum; -/* CAN baudrate prescaler*/ +/* CAN baudrate prescaler */ #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) -/* CAN bit segment 1*/ +/* CAN bit segment 1 */ #define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) -/* CAN bit segment 2*/ +/* CAN bit segment 2 */ #define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) -/* CAN resynchronization jump width*/ +/* CAN resynchronization jump width */ #define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) -/* CAN communication mode*/ +/* CAN communication mode */ #define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) /* CAN FDATA high 16 bits */ @@ -501,13 +494,13 @@ typedef enum /* CAN FDATA low 16 bits */ #define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* CAN1 filter start bank_number*/ +/* CAN1 filter start bank_number */ #define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) -/* CAN transmit mailbox extended identifier*/ +/* CAN transmit mailbox extended identifier */ #define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) -/* CAN transmit mailbox standard identifier*/ +/* CAN transmit mailbox standard identifier */ #define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) /* transmit data byte 0 */ @@ -534,10 +527,10 @@ typedef enum /* transmit data byte 7 */ #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -/* receive mailbox extended identifier*/ +/* receive mailbox extended identifier */ #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) -/* receive mailbox standrad identifier*/ +/* receive mailbox standard identifier */ #define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) /* receive data length */ @@ -581,14 +574,14 @@ typedef enum /* CAN errors */ #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ +#define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */ +#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ @@ -642,11 +635,11 @@ typedef enum #define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ #define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ -/* CAN receive fifo */ +/* CAN receive FIFO */ #define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ -/* frame number of receive fifo */ +/* frame number of receive FIFO */ #define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ @@ -692,15 +685,18 @@ typedef enum #define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ /* function declarations */ +/* initialization functions */ /* deinitialize CAN */ void can_deinit(uint32_t can_periph); -/* initialize CAN struct */ -void can_struct_para_init(can_struct_type_enum type, void* p_struct); +/* initialize CAN structure */ +void can_struct_para_init(can_struct_type_enum type, void *p_struct); /* initialize CAN */ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); -/* CAN filter init */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); -/* set can1 fliter start bank number */ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); +/* CAN filter initialization */ +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); + +/* function configuration */ +/* set can1 filter start bank number */ void can1_filter_start_bank(uint8_t start_bank); /* enable functions */ /* CAN debug freeze enable */ @@ -714,14 +710,14 @@ void can_time_trigger_mode_disable(uint32_t can_periph); /* transmit functions */ /* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); /* get CAN transmit state */ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); /* stop CAN transmission */ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); /* CAN receive message */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); -/* CAN release fifo */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); +/* CAN release FIFO */ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); /* CAN receive message length */ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); @@ -730,21 +726,22 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); /* CAN wakeup from sleep mode */ ErrStatus can_wakeup(uint32_t can_periph); -/* CAN get error */ +/* CAN get error type */ can_error_enum can_error_get(uint32_t can_periph); /* get CAN receive error number */ uint8_t can_receive_error_number_get(uint32_t can_periph); /* get CAN transmit error number */ uint8_t can_transmit_error_number_get(uint32_t can_periph); -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* interrupt & flag functions */ /* CAN get flag state */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); /* CAN clear flag state */ void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); /* CAN get interrupt flag state */ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); /* CAN clear interrupt flag state */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h index 01f2c6bc3f..db3cd23ed7 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,12 +41,12 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* CRC definitions */ -#define CRC CRC_BASE +#define CRC CRC_BASE /*!< CRC base address */ /* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ +#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */ /* bits definitions */ /* CRC_DATA */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h index 00e4e7f298..c07a5db82a 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -50,7 +51,7 @@ OF SUCH DAMAGE. /* bits definitions */ /* CTC_CTL0 */ -#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ +#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ #define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ #define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ #define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ @@ -64,7 +65,6 @@ OF SUCH DAMAGE. #define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ #define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ #define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ -#define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */ #define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ /* CTC_STAT */ @@ -93,15 +93,10 @@ OF SUCH DAMAGE. #define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ #define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ -/* USBFS or USBHS SOF signal selection definitions */ -#define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/ -#define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/ - /* reference signal source selection definitions */ #define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ -#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */ /* reference signal source prescaler definitions */ #define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) @@ -155,8 +150,6 @@ void ctc_hardware_trim_mode_config(uint32_t hardmode); /* configure reference signal source polarity */ void ctc_refsource_polarity_config(uint32_t polarity); -/* select USBFS or USBHS SOF signal */ -void ctc_usbsof_signal_select(uint32_t usbsof); /* select reference signal source */ void ctc_refsource_signal_select(uint32_t refs); /* configure reference signal source prescaler */ @@ -181,7 +174,7 @@ void ctc_interrupt_enable(uint32_t interrupt); /* disable the CTC interrupt */ void ctc_interrupt_disable(uint32_t interrupt); /* get CTC interrupt flag */ -FlagStatus ctc_interrupt_flag_get(uint32_t int_flag); +FlagStatus ctc_interrupt_flag_get(uint32_t int_flag); /* clear CTC interrupt flag */ void ctc_interrupt_flag_clear(uint32_t int_flag); /* get CTC flag */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h index 573fb31336..ee471c23f3 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h @@ -1,36 +1,37 @@ /*! \file gd32f4xx_dac.h \brief definitions for the DAC - + \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -70,7 +71,7 @@ OF SUCH DAMAGE. #define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ #define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ #define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ @@ -201,7 +202,7 @@ void dac_disable(uint32_t dac_periph); /* enable DAC DMA */ void dac_dma_enable(uint32_t dac_periph); /* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); +void dac_dma_disable(uint32_t dac_periph); /* enable DAC output buffer */ void dac_output_buffer_enable(uint32_t dac_periph); /* disable DAC output buffer */ @@ -254,14 +255,14 @@ void dac_concurrent_interrupt_enable(void); void dac_concurrent_interrupt_disable(void); /* DAC interrupt configuration */ -/* enable DAC interrupt(DAC DMA underrun interrupt) */ -void dac_interrupt_enable(uint32_t dac_periph); -/* disable DAC interrupt(DAC DMA underrun interrupt) */ -void dac_interrupt_disable(uint32_t dac_periph); /* get the specified DAC flag(DAC DMA underrun flag) */ FlagStatus dac_flag_get(uint32_t dac_periph); /* clear the specified DAC flag(DAC DMA underrun flag) */ void dac_flag_clear(uint32_t dac_periph); +/* enable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_enable(uint32_t dac_periph); +/* disable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_disable(uint32_t dac_periph); /* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph); /* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h index fde91597f7..ba2fa8296e 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h @@ -1,36 +1,37 @@ /*! \file gd32f4xx_dbg.h \brief definitions for the DBG - + \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -57,7 +58,6 @@ OF SUCH DAMAGE. #define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ #define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ #define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ -#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ /* DBG_CTL1 */ #define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */ @@ -122,19 +122,13 @@ typedef enum DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */ DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */ DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */ - DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ - DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ + DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ }dbg_periph_enum; -#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) -#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ -#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ -#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ -#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ - /* function declarations */ /* deinitialize the DBG */ void dbg_deinit(void); @@ -155,7 +149,5 @@ void dbg_periph_disable(dbg_periph_enum dbg_periph); void dbg_trace_pin_enable(void); /* disable trace pin assignment */ void dbg_trace_pin_disable(void); -/* set trace pin mode */ -void dbg_trace_pin_mode_set(uint32_t trace_mode); #endif /* GD32F4XX_DBG_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h index 4986d5afd4..c27e41a13d 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -125,14 +126,14 @@ OF SUCH DAMAGE. /* constants definitions */ /* DCI parameter structure definitions */ typedef struct -{ +{ uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */ uint32_t clock_polarity; /*!< clock polarity selection */ uint32_t hsync_polarity; /*!< horizontal polarity selection */ uint32_t vsync_polarity; /*!< vertical polarity selection */ uint32_t frame_rate; /*!< frame capture rate */ uint32_t interface_format; /*!< digital camera interface format */ -}dci_parameter_struct; +}dci_parameter_struct; #define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */ #define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */ @@ -145,13 +146,13 @@ typedef struct #define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ #define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/ - -#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) + +#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) #define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */ #define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */ #define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */ -#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) +#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) #define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */ @@ -171,7 +172,7 @@ typedef struct #define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */ #define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */ -/* DCI flag definitions */ +/* DCI flag definitions */ #define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */ #define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */ #define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h index cac70b85eb..044662a708 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h @@ -1,36 +1,36 @@ /*! - \file gd32f4xx_dma.c + \file gd32f4xx_dma.h \brief definitions for the DMA - \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,70 +40,70 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* DMA definitions */ -#define DMA0 (DMA_BASE) /*!< DMA0 base address */ -#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */ /* registers definitions */ -#define DMA_INTF0(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register 0 */ -#define DMA_INTF1(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag register 1 */ -#define DMA_INTC0(dmax) REG32((dmax) + 0x08U) /*!< DMA interrupt flag clear register 0 */ -#define DMA_INTC1(dmax) REG32((dmax) + 0x0CU) /*!< DMA interrupt flag clear register 1 */ +#define DMA_INTF0(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register 0 */ +#define DMA_INTF1(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag register 1 */ +#define DMA_INTC0(dmax) REG32((dmax) + 0x00000008U) /*!< DMA interrupt flag clear register 0 */ +#define DMA_INTC1(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA interrupt flag clear register 1 */ -#define DMA_CH0CTL(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x18U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 0 memory 0 base address register */ -#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 0 memory 1 base address register */ -#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 0 FIFO control register */ +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000018U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 0 memory 0 base address register */ +#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 0 memory 1 base address register */ +#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 0 FIFO control register */ -#define DMA_CH1CTL(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT(dmax) REG32((dmax) + 0x2CU) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 1 memory 0 base address register */ -#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 1 memory 1 base address register */ -#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 1 FIFO control register */ +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x0000002CU) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 1 memory 0 base address register */ +#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 1 memory 1 base address register */ +#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 1 FIFO control register */ -#define DMA_CH2CTL(dmax) REG32((dmax) + 0x40U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 2 memory 0 base address register */ -#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 2 memory 1 base address register */ -#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x54U) /*!< DMA channel 2 FIFO control register */ +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000040U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 2 memory 0 base address register */ +#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 2 memory 1 base address register */ +#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x00000054U) /*!< DMA channel 2 FIFO control register */ -#define DMA_CH3CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 3 memory 0 base address register */ -#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x68U) /*!< DMA channel 3 memory 1 base address register */ -#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 3 FIFO control register */ +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 3 memory 0 base address register */ +#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x00000068U) /*!< DMA channel 3 memory 1 base address register */ +#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 3 FIFO control register */ -#define DMA_CH4CTL(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x7CU) /*!< DMA channel 4 memory 0 base address register */ -#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 4 memory 1 base address register */ -#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 4 FIFO control register */ +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x0000007CU) /*!< DMA channel 4 memory 0 base address register */ +#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 4 memory 1 base address register */ +#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 4 FIFO control register */ -#define DMA_CH5CTL(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x90U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x94U) /*!< DMA channel 5 memory 0 base address register */ -#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x98U) /*!< DMA channel 5 memory 1 base address register */ -#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x9CU) /*!< DMA channel 5 FIFO control register */ +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000090U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x00000094U) /*!< DMA channel 5 memory 0 base address register */ +#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x00000098U) /*!< DMA channel 5 memory 1 base address register */ +#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x0000009CU) /*!< DMA channel 5 FIFO control register */ -#define DMA_CH6CTL(dmax) REG32((dmax) + 0xA0U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT(dmax) REG32((dmax) + 0xA4U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR(dmax) REG32((dmax) + 0xA8U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0xACU) /*!< DMA channel 6 memory 0 base address register */ -#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0xB0U) /*!< DMA channel 6 memory 1 base address register */ -#define DMA_CH6FCTL(dmax) REG32((dmax) + 0xB4U) /*!< DMA channel 6 FIFO control register */ +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x000000A0U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x000000A4U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x000000A8U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0x000000ACU) /*!< DMA channel 6 memory 0 base address register */ +#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0x000000B0U) /*!< DMA channel 6 memory 1 base address register */ +#define DMA_CH6FCTL(dmax) REG32((dmax) + 0x000000B4U) /*!< DMA channel 6 FIFO control register */ -#define DMA_CH7CTL(dmax) REG32((dmax) + 0xB8U) /*!< DMA channel 7 control register */ -#define DMA_CH7CNT(dmax) REG32((dmax) + 0xBCU) /*!< DMA channel 7 counter register */ -#define DMA_CH7PADDR(dmax) REG32((dmax) + 0xC0U) /*!< DMA channel 7 peripheral base address register */ -#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0xC4U) /*!< DMA channel 7 memory 0 base address register */ -#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0xC8U) /*!< DMA channel 7 memory 1 base address register */ -#define DMA_CH7FCTL(dmax) REG32((dmax) + 0xCCU) /*!< DMA channel 7 FIFO control register */ +#define DMA_CH7CTL(dmax) REG32((dmax) + 0x000000B8U) /*!< DMA channel 7 control register */ +#define DMA_CH7CNT(dmax) REG32((dmax) + 0x000000BCU) /*!< DMA channel 7 counter register */ +#define DMA_CH7PADDR(dmax) REG32((dmax) + 0x000000C0U) /*!< DMA channel 7 peripheral base address register */ +#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0x000000C4U) /*!< DMA channel 7 memory 0 base address register */ +#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0x000000C8U) /*!< DMA channel 7 memory 1 base address register */ +#define DMA_CH7FCTL(dmax) REG32((dmax) + 0x000000CCU) /*!< DMA channel 7 FIFO control register */ /* bits definitions */ /* DMA_INTF */ @@ -161,7 +161,7 @@ OF SUCH DAMAGE. /* constants definitions */ /* DMA channel select */ -typedef enum +typedef enum { DMA_CH0 = 0, /*!< DMA Channel 0 */ DMA_CH1, /*!< DMA Channel 1 */ @@ -174,7 +174,7 @@ typedef enum } dma_channel_enum; /* DMA peripheral select */ -typedef enum +typedef enum { DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */ DMA_SUBPERI1, /*!< DMA Peripheral 1 */ @@ -191,7 +191,7 @@ typedef struct { uint32_t periph_addr; /*!< peripheral base address */ uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t periph_inc; /*!< peripheral increasing mode */ + uint32_t periph_inc; /*!< peripheral increasing mode */ uint32_t memory0_addr; /*!< memory 0 base address */ uint32_t memory_width; /*!< transfer data size of memory */ @@ -211,7 +211,7 @@ typedef struct typedef struct { uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_inc; /*!< peripheral increasing mode */ + uint32_t periph_inc; /*!< peripheral increasing mode */ uint32_t memory0_addr; /*!< memory 0 base address */ uint32_t memory_inc; /*!< memory increasing mode */ @@ -416,13 +416,13 @@ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx); FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* clear DMA a channel flag */ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* check DMA flag is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); -/* clear DMA a channel flag */ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); /* enable DMA interrupt */ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); /* disable DMA interrupt */ void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* check DMA flag is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); +/* clear DMA a channel flag */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); #endif /* GD32F4XX_DMA_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h index 1dfc880d37..517c7c0d7d 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -61,7 +62,7 @@ OF SUCH DAMAGE. #define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ #endif -//#define SELECT_DESCRIPTORS_ENHANCED_MODE +//#define SELECT_DESCRIPTORS_ENHANCED_MODE //#define USE_DELAY @@ -72,7 +73,7 @@ OF SUCH DAMAGE. #define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ -/* PHY read write timeouts */ +/* PHY read write timeouts */ #define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ #define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ @@ -80,7 +81,7 @@ OF SUCH DAMAGE. #define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ #define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ -/* PHY register address */ +/* PHY register address */ #define PHY_REG_BCR 0U /*!< tranceiver basic control register */ #define PHY_REG_BSR 1U /*!< tranceiver basic status register */ @@ -101,7 +102,7 @@ OF SUCH DAMAGE. #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ -#if(PHY_TYPE == LAN8700) +#if(PHY_TYPE == LAN8700) #define PHY_SR 31U /*!< tranceiver status register */ #define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ @@ -123,7 +124,7 @@ OF SUCH DAMAGE. #define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */ #define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */ #define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC MII data register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC PHY data register */ #define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */ #define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */ #define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */ @@ -154,7 +155,7 @@ OF SUCH DAMAGE. #define ENET_MSC_RGUFCNT REG32((ENET) + 0x01C4U) /*!< ethernet MSC received good unicast frames counter register */ #define ENET_PTP_TSCTL REG32((ENET) + 0x0700U) /*!< ethernet PTP time stamp control register */ -#define ENET_PTP_SSINC REG32((ENET) + 0x0704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x0704U) /*!< ethernet PTP subsecond increment register */ #define ENET_PTP_TSH REG32((ENET) + 0x0708U) /*!< ethernet PTP time stamp high register */ #define ENET_PTP_TSL REG32((ENET) + 0x070CU) /*!< ethernet PTP time stamp low register */ #define ENET_PTP_TSUH REG32((ENET) + 0x0710U) /*!< ethernet PTP time stamp update high register */ @@ -166,7 +167,7 @@ OF SUCH DAMAGE. #define ENET_PTP_PPSCTL REG32((ENET) + 0x072CU) /*!< ethernet PTP PPS control register */ #define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ -#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ #define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ #define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ #define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ @@ -175,7 +176,7 @@ OF SUCH DAMAGE. #define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ #define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ #define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ -#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ #define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ #define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ #define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ @@ -194,7 +195,7 @@ OF SUCH DAMAGE. #define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ #define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ -#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ #define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ #define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ #define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ @@ -202,49 +203,49 @@ OF SUCH DAMAGE. /* ENET_MAC_FRMF */ #define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ #define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ -#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ -#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ -#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ -#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ -#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ -#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ -#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ -#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ -#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ - +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + /* ENET_MAC_HLH */ #define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ - + /* ENET_MAC_HLL */ #define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ - + /* ENET_MAC_PHY_CTL */ -#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ -#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ -#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ -#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ -#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ - +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + /* ENET_MAC_PHY_DATA */ #define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ - + /* ENET_MAC_FCTL */ #define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ #define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ #define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ #define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ -#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ #define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ - + /* ENET_MAC_VLT */ #define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ - + /* ENET_MAC_RWFF */ #define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ - -/* ENET_MAC_WUM */ + +/* ENET_MAC_WUM */ #define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ #define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ #define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ @@ -253,7 +254,7 @@ OF SUCH DAMAGE. #define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ #define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ -/* ENET_MAC_DBG */ +/* ENET_MAC_DBG */ #define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ #define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ #define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ @@ -267,7 +268,7 @@ OF SUCH DAMAGE. #define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ #define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ -/* ENET_MAC_INTF */ +/* ENET_MAC_INTF */ #define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ #define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ #define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ @@ -281,28 +282,28 @@ OF SUCH DAMAGE. /* ENET_MAC_ADDR0H */ #define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ #define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ - + /* ENET_MAC_ADDR0L */ #define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ - + /* ENET_MAC_ADDR1H */ #define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ -#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ #define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ #define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ - + /* ENET_MAC_ADDR1L */ #define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ - + /* ENET_MAC_ADDR2H */ #define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ #define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ #define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ #define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ - + /* ENET_MAC_ADDR2L */ #define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ - + /* ENET_MAC_ADDR3H */ #define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ #define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ @@ -311,11 +312,11 @@ OF SUCH DAMAGE. /* ENET_MAC_ADDR3L */ #define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ - + /* ENET_MAC_FCTH */ #define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ #define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ - + /* ENET_MSC_CTL */ #define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ #define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ @@ -328,7 +329,7 @@ OF SUCH DAMAGE. #define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ #define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ #define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ - + /* ENET_MSC_TINTF */ #define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ #define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ @@ -338,30 +339,30 @@ OF SUCH DAMAGE. #define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ #define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ #define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ - + /* ENET_MSC_TINTMSK */ #define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ #define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ #define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ - + /* ENET_MSC_SCCNT */ #define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ - + /* ENET_MSC_MSCCNT */ #define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ - + /* ENET_MSC_TGFCNT */ #define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ - + /* ENET_MSC_RFCECNT */ #define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ - + /* ENET_MSC_RFAECNT */ #define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ - + /* ENET_MSC_RGUFCNT */ #define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ - + /* ENET_PTP_TSCTL */ #define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ @@ -381,37 +382,37 @@ OF SUCH DAMAGE. #define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ #define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ #define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ - + /* ENET_PTP_SSINC */ #define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ - + /* ENET_PTP_TSH */ #define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ - + /* ENET_PTP_TSL */ #define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ #define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ - + /* ENET_PTP_TSUH */ #define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ - + /* ENET_PTP_TSUL */ #define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ #define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ /* ENET_PTP_TSADDAND */ #define ENET_PTP_TSADDAND_TMSA BITS(0,31) /*!< timestamp addend */ - + /* ENET_PTP_ETH */ #define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ - + /* ENET_PTP_ETL */ #define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ - + /* ENET_PTP_TSF */ #define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ #define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ - + /* ENET_PTP_PPSCTL */ #define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ @@ -428,19 +429,19 @@ OF SUCH DAMAGE. #define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ #define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ - + /* ENET_DMA_TPEN */ #define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ - + /* ENET_DMA_RPEN */ #define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ /* ENET_DMA_RDTADDR */ #define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ - + /* ENET_DMA_TDTADDR */ #define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ - + /* ENET_DMA_STAT */ #define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ #define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ @@ -463,7 +464,7 @@ OF SUCH DAMAGE. #define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ #define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ #define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ - + /* ENET_DMA_CTL */ #define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ #define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ @@ -477,7 +478,7 @@ OF SUCH DAMAGE. #define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ #define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ #define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ - + /* ENET_DMA_INTEN */ #define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ #define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ @@ -494,7 +495,7 @@ OF SUCH DAMAGE. #define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ #define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ #define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ - + /* ENET_DMA_MFBOCNT */ #define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ #define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ @@ -507,10 +508,10 @@ OF SUCH DAMAGE. /* ENET_DMA_CRDADDR */ #define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ - + /* ENET_DMA_CTBADDR */ #define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ - + /* ENET_DMA_CRBADDR */ #define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ @@ -570,7 +571,7 @@ OF SUCH DAMAGE. #define ENET_RDES0_LCO BIT(6) /*!< late collision */ #define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ #define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ -#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ #define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ #define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ #define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ @@ -582,7 +583,7 @@ OF SUCH DAMAGE. #define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ #define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ -/* ENET DMA Rx descriptor RDES1 */ +/* ENET DMA Rx descriptor RDES1 */ #define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ #define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ #define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ @@ -624,7 +625,7 @@ OF SUCH DAMAGE. #define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) /* define MAC address configuration and reference address */ -#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) #define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) #define ENET_ADDRH_BASE ((ENET) + 0x40U) #define ENET_ADDRL_BASE ((ENET) + 0x44U) @@ -646,7 +647,7 @@ OF SUCH DAMAGE. #define MSC_RFCECNT_REG_OFFSET ((uint16_t)0x0194U) /*!< MSC received frames with CRC error counter register offset */ #define MSC_RFAECNT_REG_OFFSET ((uint16_t)0x0198U) /*!< MSC received frames with alignment error counter register offset */ #define MSC_RGUFCNT_REG_OFFSET ((uint16_t)0x01C4U) /*!< MSC received good unicast frames counter register offset */ - + #define PTP_TSF_REG_OFFSET ((uint16_t)0x0728U) /*!< PTP time stamp flag register offset */ #define DMA_STAT_REG_OFFSET ((uint16_t)0x1014U) /*!< DMA status register offset */ @@ -663,7 +664,7 @@ typedef enum { /* ENET_MAC_WUM register */ ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ - ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ /* ENET_MAC_FCTL register */ ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ /* ENET_MAC_INTF register */ @@ -673,13 +674,13 @@ typedef enum ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ /* ENET_PTP_TSF register */ - ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ + ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ /* ENET_MSC_RINTF register */ ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ + /* ENET_MSC_TINTF register */ ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ @@ -704,7 +705,7 @@ typedef enum ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ }enet_flag_enum; /* ENET stutus flag clear */ @@ -725,7 +726,7 @@ typedef enum ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ }enet_flag_clear_enum; /* ENET interrupt enable/disable */ @@ -734,15 +735,15 @@ typedef enum /* ENET_MAC_INTMSK register */ ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ - /* ENET_MSC_RINTMSK register */ + /* ENET_MSC_RINTMSK register */ ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ - /* ENET_MSC_TINTMSK register */ + /* ENET_MSC_TINTMSK register */ ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ - /* ENET_DMA_INTEN register */ + /* ENET_DMA_INTEN register */ ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ @@ -759,7 +760,7 @@ typedef enum ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ }enet_int_enum; - + /* ENET interrupt flag get */ typedef enum { @@ -795,7 +796,7 @@ typedef enum ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ }enet_int_flag_enum; /* ENET interrupt flag clear */ @@ -839,7 +840,7 @@ typedef enum ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ -}enet_msc_counter_enum; +}enet_msc_counter_enum; /* function option, used for ENET initialization */ typedef enum @@ -919,7 +920,7 @@ typedef enum ENET_REG_WRITE /*!< write register */ }enet_regdirection_enum; -/* ENET MAC addresses */ +/* ENET MAC addresses */ typedef enum { ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ @@ -953,7 +954,7 @@ typedef enum{ ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ - ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ @@ -971,24 +972,24 @@ typedef enum{ typedef struct { uint32_t option_enable; /*!< select which function to configure */ - uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t forward_frame; /*!< frame forward related parameters */ uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ uint32_t dma_maxburst; /*!< DMA max burst related parameters */ uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ uint32_t store_forward_mode; /*!< store forward mode related parameters */ uint32_t dma_function; /*!< DMA control related parameters */ - uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ uint32_t flow_control; /*!< flow control related parameters */ uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ uint32_t framesfilter_mode; /*!< frame filter control related parameters */ - uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ uint32_t timer_config; /*!< frame timer related parameters */ uint32_t interframegap; /*!< inter frame gap related parameters */ }enet_initpara_struct; -/* structure for ENET DMA desciptors */ -typedef struct +/* structure for ENET DMA desciptors */ +typedef struct { uint32_t status; /*!< status */ uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ @@ -999,12 +1000,12 @@ typedef struct uint32_t extended_status; /*!< extended status */ uint32_t reserved; /*!< reserved */ uint32_t timestamp_low; /*!< timestamp low */ - uint32_t timestamp_high; /*!< timestamp high */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - + uint32_t timestamp_high; /*!< timestamp high */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + } enet_descriptors_struct; -/* structure of PTP system time */ +/* structure of PTP system time */ typedef struct { uint32_t second; /*!< second of system time */ @@ -1017,10 +1018,10 @@ typedef struct #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ -#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ #define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ -#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ #define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ @@ -1035,13 +1036,13 @@ typedef struct #define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ #define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ - + #define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ #define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ #define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ #define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ - + #define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ #define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ @@ -1073,10 +1074,10 @@ typedef struct #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ #define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ - + #define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ #define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ - + #define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ #define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ #define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ @@ -1085,14 +1086,14 @@ typedef struct #define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ #define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ - + #define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ #define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ #define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ #define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ #define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ - + #define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ #define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ #define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ @@ -1112,7 +1113,7 @@ typedef struct #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */ #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-200 MHz; MDC clock= HCLK/102 */ +#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-240 MHz; MDC clock= HCLK/102 */ #define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ @@ -1126,7 +1127,7 @@ typedef struct #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ -#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ #define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ #define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ @@ -1134,7 +1135,7 @@ typedef struct #define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ #define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ - + #define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ #define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ #define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ @@ -1146,21 +1147,21 @@ typedef struct #define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ - + #define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ /* mac_vlt register value */ #define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ - + #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ -/* mac_wum register value */ +/* mac_wum register value */ #define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ #define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ #define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ -#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ -#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ -#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ #define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ /* mac_dbg register value */ @@ -1202,9 +1203,9 @@ typedef struct #define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ #define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ - + /* mac_fcth register value */ -#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ +#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0)) << 8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ #define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ #define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ @@ -1213,7 +1214,7 @@ typedef struct #define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ #define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ -#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ +#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4)) << 8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ #define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ #define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ #define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ @@ -1241,7 +1242,7 @@ typedef struct /* ptp_tsl register value */ #define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ - + #define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ #define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ @@ -1285,7 +1286,7 @@ typedef struct #define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ #define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ #define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ #define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ #define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ #define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ @@ -1297,7 +1298,7 @@ typedef struct #define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ #define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ #define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ -#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ #define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ #define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ @@ -1309,13 +1310,13 @@ typedef struct #define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ #define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ #define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ -#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ #define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ #define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ #define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ #define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ #define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ -#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ #define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ #define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ @@ -1378,13 +1379,13 @@ typedef struct #define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ #define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ -#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF << 2) /*!< all frame received with error except runt error are forwarded to memory */ #define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ -#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF << 2) /*!< the function that all frame received with error except runt error are forwarded to memory */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF << 2) /*!< forward undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF << 2) /*!< the function that forwarding undersized good frames */ #define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ #define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ @@ -1402,10 +1403,10 @@ typedef struct #define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ #define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ -#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ -#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ -#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ -#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ /* dma tx descriptor tdes1 register value */ #define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ @@ -1444,13 +1445,13 @@ typedef struct #else #define ETH_DMATXDESC_SIZE ((uint32_t)0x00000010U) /*!< TxDMA descriptor size */ #define ETH_DMARXDESC_SIZE ((uint32_t)0x00000010U) /*!< RxDMA descriptor size */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ /* ENET remote wake-up frame register length */ #define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ -/* ENET frame size */ -#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ /* ENET delay timeout */ #define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ @@ -1485,12 +1486,12 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); /* configure the transmit IP frame checksum offload calculation and insertion */ void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); /* ENET Tx and Rx function enable (include MAC and DMA module) */ -void enet_enable(void); +void enet_enable(void); /* ENET Tx and Rx function disable (include MAC and DMA module) */ void enet_disable(void); /* configure MAC address */ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); -/* get MAC address */ +/* get MAC address */ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); /* get the ENET MAC/MSC/PTP/DMA status flag */ @@ -1558,7 +1559,7 @@ void enet_flowcontrol_feature_disable(uint32_t feature); /* DMA function */ /* get the dma transmit/receive process state */ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); /* poll the dma transmission/reception enable */ void enet_dmaprocess_resume(enet_dmadirection_enum direction); /* check and recover the Rx process */ @@ -1578,7 +1579,7 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) /* set the bit flag of ENET dma tx descriptor */ void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); /* clear the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); /* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); /* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ @@ -1642,13 +1643,13 @@ void enet_wum_feature_disable(uint32_t feature); /* MSC function */ /* reset the MAC statistics counters */ void enet_msc_counters_reset(void); -/* enable the MAC statistics counter features */ +/* enable the MAC statistics counter features */ void enet_msc_feature_enable(uint32_t feature); -/* disable the MAC statistics counter features */ +/* disable the MAC statistics counter features */ void enet_msc_feature_disable(uint32_t feature); /* configure MAC statistics counters preset mode */ void enet_msc_counters_preset_config(enet_msc_preset_enum mode); -/* get MAC statistics counter */ +/* get MAC statistics counter */ uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); /* PTP function */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h index 94baf2f6f3..e46ec388a5 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h @@ -1,36 +1,38 @@ /*! \file gd32f4xx_exmc.h \brief definitions for the EXMC - + \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx + \version 2022-06-08, V3.0.1, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -113,13 +115,13 @@ OF SUCH DAMAGE. #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ #define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ #define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_WEN BIT(12) /*!< write enable */ #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ #define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */ +#define EXMC_SNCTL_ASYNCWTEN BIT(15) /*!< asynchronous wait enable */ #define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ -#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */ -#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock config */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write configuration */ +#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock configuration */ /* EXMC_SNTCFGx,x=0..3 */ #define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ @@ -207,7 +209,7 @@ OF SUCH DAMAGE. /* EXMC_SDARI */ #define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ #define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ -#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */ +#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable */ /* EXMC_SDSTAT */ #define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ @@ -273,12 +275,12 @@ typedef struct uint32_t databus_width; /*!< specifies the databus width of external memory */ uint32_t memory_type; /*!< specifies the type of external memory */ uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing parameters for read if the extendedmode is used. */ exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */ }exmc_norsram_parameter_struct; -/* EXMC NAND/PC card timing initialize struct */ +/* EXMC NAND/PC card timing initialize structure */ typedef struct { uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ @@ -287,10 +289,10 @@ typedef struct uint32_t setuptime; /*!< configure the address setup time */ }exmc_nand_pccard_timing_parameter_struct; -/* EXMC NAND initialize struct */ +/* EXMC NAND initialize structure */ typedef struct { - uint32_t nand_bank; /*!< select the bank of NAND */ + uint32_t nand_bank; /*!< select the bank of NAND */ uint32_t ecc_size; /*!< the page size for the ECC calculation */ uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ @@ -301,7 +303,7 @@ typedef struct exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ }exmc_nand_parameter_struct; -/* EXMC PC card initialize struct */ +/* EXMC PC card initialize structure */ typedef struct { uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ @@ -312,7 +314,7 @@ typedef struct exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */ }exmc_pccard_parameter_struct; -/* EXMC SDRAM timing initialize struct */ +/* EXMC SDRAM timing initialize structure */ typedef struct { uint32_t row_to_column_delay; /*!< configure the row to column delay */ @@ -324,12 +326,12 @@ typedef struct uint32_t load_mode_register_delay; /*!< configure the load mode register delay */ }exmc_sdram_timing_parameter_struct; -/* EXMC SDRAM initialize struct */ +/* EXMC SDRAM initialize structure */ typedef struct { uint32_t sdram_device; /*!< device of SDRAM */ uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */ - uint32_t brust_read_switch; /*!< enable or disable the burst read */ + uint32_t burst_read_switch; /*!< enable or disable the burst read */ uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ @@ -340,7 +342,7 @@ typedef struct exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */ }exmc_sdram_parameter_struct; -/* EXMC SDRAM command initialize struct */ +/* EXMC SDRAM command initialize structure */ typedef struct { uint32_t mode_register_content; /*!< the SDRAM mode register content */ @@ -349,7 +351,7 @@ typedef struct uint32_t command; /*!< the commands that will be sent to SDRAM */ }exmc_sdram_command_parameter_struct; -/* EXMC SQPISRAM initialize struct */ +/* EXMC SQPISRAM initialize structure */ typedef struct{ uint32_t sample_polarity; /*!< read data sample polarity */ uint32_t id_length; /*!< SPI PSRAM ID length */ @@ -357,7 +359,7 @@ typedef struct{ uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */ }exmc_sqpipsram_parameter_struct; -/* EXMC_register address */ +/* EXMC register address */ #define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */ #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */ #define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */ @@ -418,6 +420,7 @@ typedef struct{ /* synchronous clock divide ratio */ #define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) +#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ #define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ #define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ #define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ @@ -430,7 +433,7 @@ typedef struct{ #define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ #define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ #define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK*/ #define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ #define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ @@ -541,7 +544,7 @@ typedef struct{ #define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ #define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ -/* SDRAM command select */ +/* SDRAM command selection */ #define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) #define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ #define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ @@ -661,13 +664,13 @@ typedef struct{ #define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ #define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */ -/* SDRAM device0 select */ -#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device0 unselect */ -#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< SDRAM device0 select */ +/* SDRAM device0 selection */ +#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device0 */ +#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< select SDRAM device0 */ -/* SDRAM device1 select */ -#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device1 unselect */ -#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< SDRAM device1 select */ +/* SDRAM device1 selection */ +#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device1 */ +#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< select SDRAM device1 */ /* SDRAM device status */ #define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ @@ -716,7 +719,7 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region); /* NAND */ /* deinitialize EXMC NAND bank */ void exmc_nand_deinit(uint32_t exmc_nand_bank); -/* initialize exmc_norsram_parameter_struct with the default values */ +/* initialize exmc_nand_parameter_struct with the default values */ void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); /* initialize EXMC NAND bank */ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); @@ -742,6 +745,8 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device); void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); /* initialize EXMC SDRAM device */ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* initialize exmc_sdram_command_parameter_struct with the default values */ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct); /* SQPIPSRAM */ /* deinitialize EXMC SQPIPSRAM */ void exmc_sqpipsram_deinit(void); @@ -772,7 +777,7 @@ void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_c void exmc_sdram_refresh_count_set(uint32_t exmc_count); /* set the number of successive auto-refresh command */ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); -/* config the write protection function */ +/* configure the write protection function */ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); /* get the status of SDRAM device0 or device1 */ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h index 3c2a27149d..294b5872b7 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h @@ -1,36 +1,36 @@ /*! \file gd32f4xx_exti.h \brief definitions for the EXTI - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -177,34 +177,33 @@ OF SUCH DAMAGE. #define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ /* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ -#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */ -#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ -#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */ +#define EXTI_PD_PD20 BIT(20) /*!< interrupt pending status from line 20 */ +#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */ +#define EXTI_PD_PD22 BIT(22) /*!< interrupt pending status from line 22 */ /* constants definitions */ /* EXTI line number */ -typedef enum -{ +typedef enum { EXTI_0 = BIT(0), /*!< EXTI line 0 */ EXTI_1 = BIT(1), /*!< EXTI line 1 */ EXTI_2 = BIT(2), /*!< EXTI line 2 */ @@ -225,31 +224,29 @@ typedef enum EXTI_17 = BIT(17), /*!< EXTI line 17 */ EXTI_18 = BIT(18), /*!< EXTI line 18 */ EXTI_19 = BIT(19), /*!< EXTI line 19 */ - EXTI_20 = BIT(20), /*!< EXTI line 20 */ + EXTI_20 = BIT(20), /*!< EXTI line 20 */ EXTI_21 = BIT(21), /*!< EXTI line 21 */ - EXTI_22 = BIT(22), /*!< EXTI line 22 */ -}exti_line_enum; + EXTI_22 = BIT(22) /*!< EXTI line 22 */ +} exti_line_enum; /* external interrupt and event */ -typedef enum -{ +typedef enum { EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; +} exti_mode_enum; /* interrupt trigger mode */ -typedef enum -{ +typedef enum { EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ EXTI_TRIG_NONE /*!< none EXTI edge trigger */ -}exti_trig_type_enum; +} exti_trig_type_enum; /* function declarations */ /* deinitialize the EXTI */ void exti_deinit(void); -/* enable the configuration of EXTI initialize */ +/* initialize the EXTI line x */ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); /* enable the interrupts from EXTI line x */ void exti_interrupt_enable(exti_line_enum linex); @@ -259,19 +256,19 @@ void exti_interrupt_disable(exti_line_enum linex); void exti_event_enable(exti_line_enum linex); /* disable the events from EXTI line x */ void exti_event_disable(exti_line_enum linex); -/* EXTI software interrupt event enable */ +/* enable the software interrupt event from EXTI line x */ void exti_software_interrupt_enable(exti_line_enum linex); -/* EXTI software interrupt event disable */ +/* disable the software interrupt event from EXTI line x */ void exti_software_interrupt_disable(exti_line_enum linex); /* interrupt & flag functions */ -/* get EXTI lines pending flag */ +/* get EXTI line x interrupt pending flag */ FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ +/* clear EXTI line x interrupt pending flag */ void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ +/* get EXTI line x interrupt pending flag */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ +/* clear EXTI line x interrupt pending flag */ void exti_interrupt_flag_clear(exti_line_enum linex); #endif /* GD32F4XX_EXTI_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h index 9b1b82c083..db4d0f44f6 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h @@ -5,10 +5,12 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2020-12-20, V2.1.1, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -45,15 +47,17 @@ OF SUCH DAMAGE. #define OB OB_BASE /*!< option byte base address */ /* registers definitions */ -#define FMC_WS REG32((FMC) + 0x0000U) /*!< FMC wait state register */ -#define FMC_KEY REG32((FMC) + 0x0004U) /*!< FMC unlock key register */ -#define FMC_OBKEY REG32((FMC) + 0x0008U) /*!< FMC option byte unlock key register */ -#define FMC_STAT REG32((FMC) + 0x000CU) /*!< FMC status register */ -#define FMC_CTL REG32((FMC) + 0x0010U) /*!< FMC control register */ -#define FMC_OBCTL0 REG32((FMC) + 0x0014U) /*!< FMC option byte control register 0 */ -#define FMC_OBCTL1 REG32((FMC) + 0x0018U) /*!< FMC option byte control register 1 */ -#define FMC_WSEN REG32((FMC) + 0x00FCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32((FMC) + 0x0100U) /*!< FMC product ID register */ +#define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */ +#define FMC_KEY REG32((FMC) + 0x00000004U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option byte unlock key register */ +#define FMC_STAT REG32((FMC) + 0x0000000CU) /*!< FMC status register */ +#define FMC_CTL REG32((FMC) + 0x00000010U) /*!< FMC control register */ +#define FMC_OBCTL0 REG32((FMC) + 0x00000014U) /*!< FMC option byte control register 0 */ +#define FMC_OBCTL1 REG32((FMC) + 0x00000018U) /*!< FMC option byte control register 1 */ +#define FMC_PECFG REG32((FMC) + 0x00000020U) /*!< FMC page erase configuration register */ +#define FMC_PEKEY REG32((FMC) + 0x00000024U) /*!< FMC unlock page erase key register */ +#define FMC_WSEN REG32((FMC) + 0x000000FCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x00000100U) /*!< FMC product ID register */ #define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */ #define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/ @@ -107,6 +111,13 @@ OF SUCH DAMAGE. /* FMC_OBCTL1 */ #define FMC_OBCTL1_WP1 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */ +/* FMC_PECFG */ +#define FMC_PE_EN BIT(31) /*!< the enable bit of page erase function */ +#define FMC_PE_ADDR BITS(0,28) /*!< page erase address */ + +/* FMC_PEKEY */ +#define FMC_PE_KEY BITS(0,31) /*!< FMC_PECFG unlock key value */ + /* FMC_WSEN */ #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ @@ -115,21 +126,21 @@ OF SUCH DAMAGE. /* constants definitions */ /* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ +typedef enum { + FMC_READY = 0, /*!< the operation has been completed */ FMC_BUSY, /*!< the operation is in progress */ FMC_RDDERR, /*!< read D-bus protection error */ FMC_PGSERR, /*!< program sequence error */ FMC_PGMERR, /*!< program size not match error */ FMC_WPERR, /*!< erase/program protection error */ FMC_OPERR, /*!< operation error */ - FMC_PGERR, /*!< program error */ -}fmc_state_enum; + FMC_TOERR /*!< timeout error */ +} fmc_state_enum; /* unlock key */ #define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ +#define UNLOCK_PE_KEY ((uint32_t)0xA9B8C7D6U) /*!< unlock page erase function key */ #define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */ #define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */ @@ -241,14 +252,15 @@ typedef enum #define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */ #define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */ #define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */ +#define OB_DRP_ALL ((uint32_t)0x0FFF0FFFU) /*!< D-bus read protection protection of all sectors */ /* double banks or single bank selection when flash size is 1M bytes */ -#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval)<<30)) +#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval) << 30U)) #define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */ #define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */ /* option bytes D-bus read protection mode */ -#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval)<<31)) +#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval) << 31U)) #define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */ #define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */ @@ -285,23 +297,35 @@ typedef enum /* FMC program size */ -#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8) +#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8U) #define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */ #define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */ #define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */ /* FMC interrupt enable */ -#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */ -#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ +#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */ +#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ /* FMC flags */ -#define FMC_FLAG_END ((uint32_t)0x00000001U) /*!< FMC end of operation flag bit */ -#define FMC_FLAG_OPERR ((uint32_t)0x00000002U) /*!< FMC operation error flag bit */ -#define FMC_FLAG_WPERR ((uint32_t)0x00000010U) /*!< FMC erase/program protection error flag bit */ -#define FMC_FLAG_PGMERR ((uint32_t)0x00000040U) /*!< FMC program size not match error flag bit */ -#define FMC_FLAG_PGSERR ((uint32_t)0x00000080U) /*!< FMC program sequence error flag bit */ -#define FMC_FLAG_RDDERR ((uint32_t)0x00000100U) /*!< FMC read D-bus protection error flag bit */ -#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */ +#define FMC_FLAG_END FMC_STAT_END /*!< FMC end of operation flag bit */ +#define FMC_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error flag bit */ +#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error flag bit */ +#define FMC_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error flag bit */ +#define FMC_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error flag bit */ +#define FMC_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error flag bit */ +#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ + +/* FMC interrupt flags */ +#define FMC_INT_FLAG_END FMC_STAT_END /*!< FMC end of operation interrupt flag */ +#define FMC_INT_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error interrupt flag */ +#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error interrupt flag */ +#define FMC_INT_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error interrupt flag */ +#define FMC_INT_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error interrupt flag */ +#define FMC_INT_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error interrupt flag */ + + +/* FMC time out */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x4FFFFFFFU) /*!< count to judge of FMC timeout */ /* function declarations */ /* FMC main memory programming functions */ @@ -311,6 +335,10 @@ void fmc_wscnt_set(uint32_t wscnt); void fmc_unlock(void); /* lock the main FMC operation */ void fmc_lock(void); +#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470) +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_addr); +#endif /* FMC erase sector */ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector); /* FMC erase whole chip */ @@ -336,22 +364,22 @@ void ob_start(void); /* erase option byte */ void ob_erase(void); /* enable write protect */ -void ob_write_protection_enable(uint32_t ob_wp); +ErrStatus ob_write_protection_enable(uint32_t ob_wp); /* disable write protect */ -void ob_write_protection_disable(uint32_t ob_wp); +ErrStatus ob_write_protection_disable(uint32_t ob_wp); /* enable erase/program protection and D-bus read protection */ void ob_drp_enable(uint32_t ob_drp); /* disable erase/program protection and D-bus read protection */ -void ob_drp_disable(uint32_t ob_drp); -/* set the option byte security protection level */ +void ob_drp_disable(void); +/* configure security protection level */ void ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte user */ +/* program the FMC user option byte */ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby); -/* option byte BOR threshold value */ +/* program the option byte BOR threshold value */ void ob_user_bor_threshold(uint32_t ob_bor_th); /* configure the boot mode */ void ob_boot_mode_config(uint32_t boot_mode); -/* get the FMC option byte user */ +/* get the FMC user option byte */ uint8_t ob_user_get(void); /* get the FMC option byte write protection */ uint16_t ob_write_protection0_get(void); @@ -363,21 +391,25 @@ uint16_t ob_drp0_get(void); uint16_t ob_drp1_get(void); /* get option byte security protection code value */ FlagStatus ob_spc_get(void); -/* get the FMC threshold value */ +/* get the FMC option byte BOR threshold value */ uint8_t ob_user_bor_threshold_get(void); /* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t fmc_int); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t fmc_int); /* get flag set or reset */ FlagStatus fmc_flag_get(uint32_t fmc_flag); /* clear the FMC pending flag */ void fmc_flag_clear(uint32_t fmc_flag); -/* return the FMC state */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t fmc_int); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t fmc_int); +/* get FMC interrupt flag set or reset */ +FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag); +/* clear the FMC interrupt flag */ +void fmc_interrupt_flag_clear(uint32_t fmc_int_flag); +/* get the FMC state */ fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ -fmc_state_enum fmc_ready_wait(void); +/* check whether FMC is ready or not */ +fmc_state_enum fmc_ready_wait(uint32_t timeout); #endif /* GD32F4XX_FMC_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h index ebee04b637..a3e6c6d7d4 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,7 +41,7 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* FWDGT definitions */ -#define FWDGT FWDGT_BASE +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ /* registers definitions */ #define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ @@ -87,6 +88,9 @@ OF SUCH DAMAGE. #define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ #define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + /* function declarations */ /* enable write access to FWDGT_PSC and FWDGT_RLD */ void fwdgt_write_enable(void); @@ -95,6 +99,10 @@ void fwdgt_write_disable(void); /* start the free watchdog timer counter */ void fwdgt_enable(void); +/* configure the free watchdog timer counter prescaler value */ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); +/* configure the free watchdog timer counter reload value */ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value); /* reload the counter of FWDGT */ void fwdgt_counter_reload(void); /* configure counter reload value, and prescaler divider value */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h index 81da899427..e62d99c69b 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -57,7 +58,7 @@ OF SUCH DAMAGE. #define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */ #define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */ #define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operate register */ #define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */ #define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */ #define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */ @@ -66,7 +67,7 @@ OF SUCH DAMAGE. /* bits definitions */ /* GPIO_CTL */ -#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ +#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ #define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ #define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ #define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ @@ -156,22 +157,22 @@ OF SUCH DAMAGE. #define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ /* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output control bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output control bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output control bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output control bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output control bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output control bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output control bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output control bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output control bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output control bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output control bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output control bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output control bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output control bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output control bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output control bit */ /* GPIO_BOP */ #define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ @@ -224,7 +225,7 @@ OF SUCH DAMAGE. #define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ #define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ #define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin lock sequence key */ /* GPIO_AFSEL0 */ #define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ @@ -344,14 +345,14 @@ typedef FlagStatus bit_status; #define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */ #define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */ #define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */ -#define GPIO_OSPEED_200MHZ GPIO_OSPEED_LEVEL3 /*!< output max speed 200MHz */ +#define GPIO_OSPEED_MAX GPIO_OSPEED_LEVEL3 /*!< GPIO very high output speed, max speed more than 50MHz */ /* GPIO alternate function values */ #define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) #define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) - + /* GPIO alternate function */ -#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) #define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ #define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ #define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h index 121e42f497..5876e50aa0 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h @@ -6,10 +6,11 @@ \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2019-04-16, V2.0.1, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -35,198 +36,173 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI OF SUCH DAMAGE. */ - #ifndef GD32F4XX_I2C_H #define GD32F4XX_I2C_H #include "gd32f4xx.h" /* I2Cx(x=0,1,2) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */ -#define I2C2 (I2C_BASE+0x800U) /*!< I2C2 base address */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ +#define I2C2 (I2C_BASE + 0x00000800U) /*!< I2C2 base address */ /* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0 */ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register 1 */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ -#define I2C_FCTL(i2cx) REG32((i2cx) + 0x24U) /*!< I2C filter control register */ -#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ +#define I2C_FCTL(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C filter control register */ +#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */ /* bits definitions */ /* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ /* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ /* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ /* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ /* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ /* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ /* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ /* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ /* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ +#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ /* I2Cx_FCTL */ -#define I2C_FCTL_DF BITS(0,3) /*!< digital noise filter */ -#define I2C_FCTL_AFD BIT(4) /*!< analog noise filter disable */ +#define I2C_FCTL_DF BITS(0,3) /*!< digital noise filter */ +#define I2C_FCTL_AFD BIT(4) /*!< analog noise filter disable */ /* I2Cx_SAMCS */ -#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ -#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ -#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ -#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ -#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ -#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ -#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ -#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ -#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag, cleared by software write 0 */ -#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag, cleared by software write 0 */ -#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */ -#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */ - -/* constants definitions */ - -/* the digital noise filter can filter spikes's length */ -typedef enum { - I2C_DF_DISABLE, /*!< disable digital noise filter */ - I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */ - I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */ - I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */ - I2C_DF_4PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 */ - I2C_DF_5PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 */ - I2C_DF_6PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 */ - I2C_DF_7PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 */ - I2C_DF_8PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 */ - I2C_DF_9PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 */ - I2C_DF_10PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 */ - I2C_DF_11PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 */ - I2C_DF_12PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 */ - I2C_DF_13PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 */ - I2C_DF_14PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 */ - I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */ -}i2c_digital_filter_enum; +#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ +#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ +#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ +#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ +#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ +#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ +#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ +#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ +#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ +#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ +#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ +#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ /* constants definitions */ /* define the I2C bit position and its register index offset */ #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) /* register offset */ -#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ -#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ +#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */ /* I2C flags */ -typedef enum -{ +typedef enum { /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ /* flags in SAMCS register */ - I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ - I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ - I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ - I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ -}i2c_flag_enum; + I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ + I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ + I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ + I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ +} i2c_flag_enum; /* I2C interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt flags in CTL1 register */ I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */ I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ @@ -237,90 +213,105 @@ typedef enum I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */ /* interrupt flags in SAMCS register */ I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ - I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ + I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ - I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ -}i2c_interrupt_flag_enum; + I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ +} i2c_interrupt_flag_enum; -/* I2C interrupt enable or disable */ -typedef enum -{ +/* I2C interrupt */ +typedef enum { /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */ /* interrupt in SAMCS register */ - I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */ - I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */ - I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */ - I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */ -}i2c_interrupt_enum; + I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */ + I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */ + I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */ + I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */ +} i2c_interrupt_enum; + +/* the digital noise filter can filter spikes's length */ +typedef enum { + I2C_DF_DISABLE = 0, /*!< disable digital noise filter */ + I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */ + I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */ + I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */ + I2C_DF_4PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 */ + I2C_DF_5PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 */ + I2C_DF_6PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 */ + I2C_DF_7PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 */ + I2C_DF_8PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 */ + I2C_DF_9PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 */ + I2C_DF_10PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 */ + I2C_DF_11PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 */ + I2C_DF_12PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 */ + I2C_DF_13PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 */ + I2C_DF_14PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 */ + I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */ +} i2c_digital_filter_enum; /* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ /* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ /* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ /* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */ /* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ +#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */ /* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */ /* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ /* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ /* I2C DMA mode configure */ /* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */ /* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ /* I2C PEC configure */ /* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ /* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */ /* I2C SMBus configure */ /* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ /* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */ /* transmit I2C data */ #define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) @@ -329,21 +320,24 @@ typedef enum #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) /* I2C duty cycle in fast mode */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode */ /* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */ /* function declarations */ +/* initialization functions */ /* reset I2C */ void i2c_deinit(uint32_t i2c_periph); /* configure I2C clock */ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); /* configure I2C address */ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ + +/* application function declarations */ +/* select SMBus type */ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); /* whether or not to send an ACK */ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); @@ -359,7 +353,6 @@ void i2c_dualaddr_disable(uint32_t i2c_periph); void i2c_enable(uint32_t i2c_periph); /* disable I2C */ void i2c_disable(uint32_t i2c_periph); - /* generate a START condition on I2C bus */ void i2c_start_on_bus(uint32_t i2c_periph); /* generate a STOP condition on I2C bus */ @@ -368,35 +361,32 @@ void i2c_stop_on_bus(uint32_t i2c_periph); void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); /* I2C receive data function */ uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure I2C DMA mode */ +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate); /* configure whether next DMA EOT is DMA last transfer or not */ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); /* whether to stretch SCL low when data is not ready in slave mode */ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); /* whether or not to response to a general call */ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ +/* configure software reset of I2C */ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ +/* configure I2C PEC calculation */ +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate); +/* configure whether to transfer PEC value */ +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara); +/* get packet error checking value */ uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -/* I2C analog noise filter disable */ +/* configure I2C alert through SMBA pin */ +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara); +/* configure I2C ARP protocol in SMBus */ +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate); +/* disable analog noise filter */ void i2c_analog_noise_filter_disable(uint32_t i2c_periph); -/* I2C analog noise filter enable */ +/* enable analog noise filter */ void i2c_analog_noise_filter_enable(uint32_t i2c_periph); -/* digital noise filter */ -void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara); - +/* configure digital noise filter */ +void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara); /* enable SAM_V interface */ void i2c_sam_enable(uint32_t i2c_periph); /* disable SAM_V interface */ @@ -406,17 +396,18 @@ void i2c_sam_timeout_enable(uint32_t i2c_periph); /* disable SAM_V interface timeout detect */ void i2c_sam_timeout_disable(uint32_t i2c_periph); -/* check I2C flag is set or not */ +/* interrupt & flag functions */ +/* get I2C flag status */ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ +/* clear I2C flag status */ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); /* enable I2C interrupt */ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); /* disable I2C interrupt */ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ +/* get I2C interrupt flag status */ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ +/* clear I2C interrupt flag status */ void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); #endif /* GD32F4XX_I2C_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h index d9ae8ce33a..354a490e26 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,30 +41,30 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* TLI definitions */ -#define IPA IPA_BASE /*!< IPA base address */ +#define IPA IPA_BASE /*!< IPA base address */ /* bits definitions */ /* registers definitions */ -#define IPA_CTL REG32(IPA + 0x00U) /*!< IPA control register */ -#define IPA_INTF REG32(IPA + 0x04U) /*!< IPA interrupt flag register */ -#define IPA_INTC REG32(IPA + 0x08U) /*!< IPA interrupt flag clear register */ -#define IPA_FMADDR REG32(IPA + 0x0CU) /*!< IPA foreground memory base address register */ -#define IPA_FLOFF REG32(IPA + 0x10U) /*!< IPA foreground line offset register */ -#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */ -#define IPA_BLOFF REG32(IPA + 0x18U) /*!< IPA background line offset register */ -#define IPA_FPCTL REG32(IPA + 0x1CU) /*!< IPA foreground pixel control register */ -#define IPA_FPV REG32(IPA + 0x20U) /*!< IPA foreground pixel value register */ -#define IPA_BPCTL REG32(IPA + 0x24U) /*!< IPA background pixel control register */ -#define IPA_BPV REG32(IPA + 0x28U) /*!< IPA background pixel value register */ -#define IPA_FLMADDR REG32(IPA + 0x2CU) /*!< IPA foreground LUT memory base address register */ -#define IPA_BLMADDR REG32(IPA + 0x30U) /*!< IPA background LUT memory base address register */ -#define IPA_DPCTL REG32(IPA + 0x34U) /*!< IPA destination pixel control register */ -#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */ -#define IPA_DMADDR REG32(IPA + 0x3CU) /*!< IPA destination memory base address register */ -#define IPA_DLOFF REG32(IPA + 0x40U) /*!< IPA destination line offset register */ -#define IPA_IMS REG32(IPA + 0x44U) /*!< IPA image size register */ -#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */ -#define IPA_ITCTL REG32(IPA + 0x4CU) /*!< IPA inter-timer control register */ +#define IPA_CTL REG32(IPA + 0x00000000U) /*!< IPA control register */ +#define IPA_INTF REG32(IPA + 0x00000004U) /*!< IPA interrupt flag register */ +#define IPA_INTC REG32(IPA + 0x00000008U) /*!< IPA interrupt flag clear register */ +#define IPA_FMADDR REG32(IPA + 0x0000000CU) /*!< IPA foreground memory base address register */ +#define IPA_FLOFF REG32(IPA + 0x00000010U) /*!< IPA foreground line offset register */ +#define IPA_BMADDR REG32(IPA + 0x00000014U) /*!< IPA background memory base address register */ +#define IPA_BLOFF REG32(IPA + 0x00000018U) /*!< IPA background line offset register */ +#define IPA_FPCTL REG32(IPA + 0x0000001CU) /*!< IPA foreground pixel control register */ +#define IPA_FPV REG32(IPA + 0x00000020U) /*!< IPA foreground pixel value register */ +#define IPA_BPCTL REG32(IPA + 0x00000024U) /*!< IPA background pixel control register */ +#define IPA_BPV REG32(IPA + 0x00000028U) /*!< IPA background pixel value register */ +#define IPA_FLMADDR REG32(IPA + 0x0000002CU) /*!< IPA foreground LUT memory base address register */ +#define IPA_BLMADDR REG32(IPA + 0x00000030U) /*!< IPA background LUT memory base address register */ +#define IPA_DPCTL REG32(IPA + 0x00000034U) /*!< IPA destination pixel control register */ +#define IPA_DPV REG32(IPA + 0x00000038U) /*!< IPA destination pixel value register */ +#define IPA_DMADDR REG32(IPA + 0x0000003CU) /*!< IPA destination memory base address register */ +#define IPA_DLOFF REG32(IPA + 0x00000040U) /*!< IPA destination line offset register */ +#define IPA_IMS REG32(IPA + 0x00000044U) /*!< IPA image size register */ +#define IPA_LM REG32(IPA + 0x00000048U) /*!< IPA line mark register */ +#define IPA_ITCTL REG32(IPA + 0x0000004CU) /*!< IPA inter-timer control register */ /* IPA_CTL */ #define IPA_CTL_TEN BIT(0) /*!< transfer enable */ @@ -189,8 +190,7 @@ OF SUCH DAMAGE. /* constants definitions */ /* IPA foreground parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t foreground_memaddr; /*!< foreground memory base address */ uint32_t foreground_lineoff; /*!< foreground line offset */ uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */ @@ -199,11 +199,10 @@ typedef struct uint32_t foreground_prered; /*!< foreground pre-defined red value */ uint32_t foreground_pregreen; /*!< foreground pre-defined green value */ uint32_t foreground_preblue; /*!< foreground pre-defined blue value */ -}ipa_foreground_parameter_struct; +} ipa_foreground_parameter_struct; /* IPA background parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t background_memaddr; /*!< background memory base address */ uint32_t background_lineoff; /*!< background line offset */ uint32_t background_prealpha; /*!< background pre-defined alpha value */ @@ -212,11 +211,10 @@ typedef struct uint32_t background_prered; /*!< background pre-defined red value */ uint32_t background_pregreen; /*!< background pre-defined green value */ uint32_t background_preblue; /*!< background pre-defined blue value */ -}ipa_background_parameter_struct; +} ipa_background_parameter_struct; /* IPA destination parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t destination_memaddr; /*!< destination memory base address */ uint32_t destination_lineoff; /*!< destination line offset */ uint32_t destination_prealpha; /*!< destination pre-defined alpha value */ @@ -226,11 +224,10 @@ typedef struct uint32_t destination_preblue; /*!< destination pre-defined blue value */ uint32_t image_width; /*!< width of the image to be processed */ uint32_t image_height; /*!< height of the image to be processed */ -}ipa_destination_parameter_struct; +} ipa_destination_parameter_struct; /* destination pixel format */ -typedef enum -{ +typedef enum { IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */ IPA_DPF_RGB888, /*!< destination pixel format RGB888 */ IPA_DPF_RGB565, /*!< destination pixel format RGB565 */ @@ -341,19 +338,19 @@ void ipa_pixel_format_convert_mode_set(uint32_t pfcm); /* structure initialization, foreground, background, destination and LUT initialization */ /* initialize the structure of IPA foreground parameter struct with the default values, it is suggested that call this function after an ipa_foreground_parameter_struct structure is defined */ -void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct); +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct); /* initialize foreground parameters */ -void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct); +void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct); /* initialize the structure of IPA background parameter struct with the default values, it is suggested that call this function after an ipa_background_parameter_struct structure is defined */ -void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct); +void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct); /* initialize background parameters */ -void ipa_background_init(ipa_background_parameter_struct* background_struct); +void ipa_background_init(ipa_background_parameter_struct *background_struct); /* initialize the structure of IPA destination parameter struct with the default values, it is suggested that call this function after an ipa_destination_parameter_struct structure is defined */ -void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct); +void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct); /* initialize destination parameters */ -void ipa_destination_init(ipa_destination_parameter_struct* destination_struct); +void ipa_destination_init(ipa_destination_parameter_struct *destination_struct); /* initialize IPA foreground LUT parameters */ void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr); /* initialize IPA background LUT parameters */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h index 4be9181ed8..807ab08ba8 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -50,7 +51,7 @@ OF SUCH DAMAGE. #define IREF_CTL_CSDT BITS(0,5) /*!< current step data */ #define IREF_CTL_SCMOD BIT(7) /*!< sink current mode */ #define IREF_CTL_CPT BITS(8,12) /*!< current precision trim */ -#define IREF_CTL_SSEL BIT(14) /*!< step selection */ +#define IREF_CTL_SSEL BIT(14) /*!< step selection */ #define IREF_CTL_CREN BIT(15) /*!< current reference enable */ /* constants definitions */ @@ -155,19 +156,19 @@ OF SUCH DAMAGE. #define IREF_CUR_STEP_DATA_61 CTL_CSDT(61) /*!< IREF current step data 61 */ #define IREF_CUR_STEP_DATA_62 CTL_CSDT(62) /*!< IREF current step data 62 */ #define IREF_CUR_STEP_DATA_63 CTL_CSDT(63) /*!< IREF current step data 63 */ - + /* IREF mode selection */ #define IREF_STEP(regval) (BIT(14) & ((uint32_t)(regval) << 14)) #define IREF_MODE_LOW_POWER IREF_STEP(0) /*!< low power, 1uA step */ #define IREF_MODE_HIGH_CURRENT IREF_STEP(1) /*!< high current, 8uA step */ - -/* IREF sink current mode*/ + +/* IREF sink current mode*/ #define IREF_CURRENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) #define IREF_SOURCE_CURRENT IREF_CURRENT(0) /*!< IREF source current */ #define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */ /* function declarations */ -/* deinit IREF */ +/* deinitialize IREF */ void iref_deinit(void); /* enable IREF */ void iref_enable(void); diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h index 21ae664c14..b265608b41 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h @@ -1,36 +1,36 @@ /*! \file gd32f4xx_misc.h \brief definitions for the MISC - \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,8 +41,8 @@ OF SUCH DAMAGE. /* constants definitions */ /* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ /* set the NVIC vector table offset mask */ #define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) @@ -51,24 +51,24 @@ OF SUCH DAMAGE. #define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ /* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ #define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT #define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP #define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ /* function declarations */ /* set the priority group */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h index f19b1cb2ec..64f6dfd5c7 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,159 +42,165 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ +#define PMU PMU_BASE /*!< PMU base address */ /* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ +#define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */ /* bits definitions */ /* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ -#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ -#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ -#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ -#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ -#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ -#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ +#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ +#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ +#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ +#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ +#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ /* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */ -#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ -#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */ -#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ -#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ -#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ -#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ +#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */ +#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ +#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ +#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ +#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */ /* constants definitions */ +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deep-sleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deep-sleep mode */ + /* PMU low voltage detector threshold definitions */ #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ - -/* PMU LDO output voltage select definitions */ -#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ -#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ -#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ - -/* PMU low-driver mode enable in deep-sleep mode */ -#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ -#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ - -/* PMU high-driver mode switch */ -#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) -#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ -#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ /* PMU low-driver mode when use low power LDO */ #define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) -#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ -#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ +#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ +#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ /* PMU low-driver mode when use normal power LDO */ #define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) -#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ -#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ +#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ +#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ -/* PMU low power mode ready flag definitions */ -#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ -#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ +/* PMU LDO output voltage select definitions */ +#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) +#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ +#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ +#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ + + +/* PMU high-driver mode switch */ +#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) +#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ + +/* PMU low-driver mode enable in deep-sleep mode */ +#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ +#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ /* PMU backup SRAM LDO on or off */ #define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9)) -#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */ -#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */ +#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */ +#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */ + +/* PMU low power mode ready flag definitions */ +#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ +#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ /* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ -#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */ -#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ -#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ -#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ -#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ +#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */ +#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ +#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ +#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ +#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ /* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ /* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ /* function declarations */ -/* reset PMU register */ +/* reset PMU registers */ void pmu_deinit(void); +/* LVD functions */ /* select low voltage detector threshold */ void pmu_lvd_select(uint32_t lvdt_n); -/* LDO output voltage select */ -void pmu_ldo_output_select(uint32_t ldo_output); -/* PMU lvd disable */ +/* disable PMU lvd */ void pmu_lvd_disable(void); -/* functions of low-driver mode and high-driver mode in deep-sleep mode */ -/* high-driver mode switch */ -void pmu_highdriver_switch_select(uint32_t highdr_switch); -/* high-driver mode enable */ +/* LDO functions */ +/* select LDO output voltage */ +void pmu_ldo_output_select(uint32_t ldo_output); + +/* functions of low-driver mode and high-driver mode */ +/* enable high-driver mode */ void pmu_highdriver_mode_enable(void); -/* high-driver mode disable */ +/* disable high-driver mode */ void pmu_highdriver_mode_disable(void); -/* low-driver mode enable in deep-sleep mode */ -void pmu_low_driver_mode_enable(uint32_t lowdr_mode); -/* in deep-sleep mode, low-driver mode when use low power LDO */ -void pmu_lowdriver_lowpower_config(uint32_t mode); -/* in deep-sleep mode, low-driver mode when use normal power LDO */ -void pmu_lowdriver_normalpower_config(uint32_t mode); +/* switch high-driver mode */ +void pmu_highdriver_switch_select(uint32_t highdr_switch); +/* enable low-driver mode in deep-sleep */ +void pmu_lowdriver_mode_enable(void); +/* disable low-driver mode in deep-sleep */ +void pmu_lowdriver_mode_disable(void); +/* in deep-sleep mode, driver mode when use low power LDO */ +void pmu_lowpower_driver_config(uint32_t mode); +/* in deep-sleep mode, driver mode when use normal power LDO */ +void pmu_normalpower_driver_config(uint32_t mode); /* set PMU mode */ -/* PMU work at sleep mode */ +/* PMU work in sleep mode */ void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work at standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); -/* PMU wakeup pin enable */ +/* PMU work in deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); +/* PMU work in standby mode */ +void pmu_to_standbymode(void); +/* enable PMU wakeup pin */ void pmu_wakeup_pin_enable(void); -/* PMU wakeup pin disable */ +/* disable PMU wakeup pin */ void pmu_wakeup_pin_disable(void); /* backup related functions */ /* backup SRAM LDO on */ void pmu_backup_ldo_config(uint32_t bkp_ldo); -/* backup domain write enable */ +/* enable write access to the registers in backup domain */ void pmu_backup_write_enable(void); -/* backup domain write disable */ +/* disable write access to the registers in backup domain */ void pmu_backup_write_disable(void); /* flag functions */ -/* reset flag bit */ -void pmu_flag_reset(uint32_t flag_reset); -/* get flag status */ -FlagStatus pmu_flag_get(uint32_t pmu_flag); +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag); #endif /* GD32F4XX_PMU_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h index 0445df4eb0..c2471ddcb9 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h @@ -1,36 +1,37 @@ /*! \file gd32f4xx_rcu.h \brief definitions for the RCU - + \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -59,14 +60,14 @@ OF SUCH DAMAGE. #define RCU_APB2EN REG32(RCU + 0x44U) /*!< APB2 enable register */ #define RCU_AHB1SPEN REG32(RCU + 0x50U) /*!< AHB1 sleep mode enable register */ #define RCU_AHB2SPEN REG32(RCU + 0x54U) /*!< AHB2 sleep mode enable register */ -#define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ +#define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ #define RCU_APB1SPEN REG32(RCU + 0x60U) /*!< APB1 sleep mode enable register */ #define RCU_APB2SPEN REG32(RCU + 0x64U) /*!< APB2 sleep mode enable register */ #define RCU_BDCTL REG32(RCU + 0x70U) /*!< backup domain control register */ #define RCU_RSTSCK REG32(RCU + 0x74U) /*!< reset source / clock register */ #define RCU_PLLSSCTL REG32(RCU + 0x80U) /*!< PLL clock spread spectrum control register */ -#define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ -#define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ +#define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ +#define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ #define RCU_CFG1 REG32(RCU + 0x8CU) /*!< clock configuration register 1 */ #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ @@ -148,7 +149,7 @@ OF SUCH DAMAGE. #define RCU_AHB1RST_PGRST BIT(6) /*!< GPIO port G reset */ #define RCU_AHB1RST_PHRST BIT(7) /*!< GPIO port H reset */ #define RCU_AHB1RST_PIRST BIT(8) /*!< GPIO port I reset */ -#define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ +#define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ #define RCU_AHB1RST_DMA0RST BIT(21) /*!< DMA0 reset */ #define RCU_AHB1RST_DMA1RST BIT(22) /*!< DMA1 reset */ #define RCU_AHB1RST_IPARST BIT(23) /*!< IPA reset */ @@ -159,7 +160,7 @@ OF SUCH DAMAGE. #define RCU_AHB2RST_DCIRST BIT(0) /*!< DCI reset */ #define RCU_AHB2RST_TRNGRST BIT(6) /*!< TRNG reset */ #define RCU_AHB2RST_USBFSRST BIT(7) /*!< USBFS reset */ - + /* RCU_AHB3RST */ #define RCU_AHB3RST_EXMCRST BIT(0) /*!< EXMC reset */ @@ -386,24 +387,22 @@ OF SUCH DAMAGE. #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ /* RCU_PLLSSCTL */ -#define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation - profile amplitude and frequency. the following criteria +#define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria must be met: MODSTEP*MODCNT=215-1 */ -#define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation - profile amplitude and frequency. the following criteria +#define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria must be met: MODSTEP*MODCNT=215-1 */ #define RCU_PLLSSCTL_SS_TYPE BIT(30) /*!< PLL spread spectrum modulation type select */ #define RCU_PLLSSCTL_SSCGON BIT(31) /*!< PLL spread spectrum modulation enable */ /* RCU_PLLI2S */ #define RCU_PLLI2S_PLLI2SN BITS(6,14) /*!< the PLLI2S VCO clock multi factor */ -#define RCU_PLLI2S_PLLI2SQ BITS(24,27) /*!< the PLLI2S Q output frequency division factor from PLLI2S VCO clock */ #define RCU_PLLI2S_PLLI2SR BITS(28,30) /*!< the PLLI2S R output frequency division factor from PLLI2S VCO clock */ /* RCU_PLLSAI */ #define RCU_PLLSAI_PLLSAIN BITS(6,14) /*!< the PLLSAI VCO clock multi factor */ #define RCU_PLLSAI_PLLSAIP BITS(16,17) /*!< the PLLSAI P output frequency division factor from PLLSAI VCO clock */ -#define RCU_PLLSAI_PLLSAIQ BITS(24,27) /*!< the PLLSAI Q output frequency division factor from PLLSAI VCO clock */ #define RCU_PLLSAI_PLLSAIR BITS(28,30) /*!< the PLLSAI R output frequency division factor from PLLSAI VCO clock */ /* RCU_CFG1 */ @@ -463,7 +462,7 @@ OF SUCH DAMAGE. #define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ #define ADD_APB1SPEN_REG_OFFSET 0xE8U /*!< APB1 additional sleep mode enable register offset */ -/* peripherals reset */ +/* peripherals reset */ #define AHB1RST_REG_OFFSET 0x10U /*!< AHB1 reset register offset */ #define AHB2RST_REG_OFFSET 0x14U /*!< AHB2 reset register offset */ #define AHB3RST_REG_OFFSET 0x18U /*!< AHB3 reset register offset */ @@ -529,7 +528,7 @@ typedef enum RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ @@ -539,7 +538,7 @@ typedef enum RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ - RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ @@ -613,7 +612,7 @@ typedef enum RCU_TIMER6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 5U), /*!< TIMER6 clock */ RCU_TIMER11_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 6U), /*!< TIMER11 clock */ RCU_TIMER12_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ RCU_WWDGT_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 11U), /*!< WWDGT clock */ RCU_SPI1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 14U), /*!< SPI1 clock */ RCU_SPI2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 15U), /*!< SPI2 clock */ @@ -623,7 +622,7 @@ typedef enum RCU_UART4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 20U), /*!< UART4 clock */ RCU_I2C0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 21U), /*!< I2C0 clock */ RCU_I2C1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 22U), /*!< I2C1 clock */ - RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ RCU_CAN0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 25U), /*!< CAN0 clock */ RCU_CAN1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 26U), /*!< CAN1 clock */ RCU_PMU_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 28U), /*!< PMU clock */ @@ -670,7 +669,7 @@ typedef enum RCU_DMA0RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 21U), /*!< DMA0 clock reset */ RCU_DMA1RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 22U), /*!< DMA1 clock reset */ RCU_IPARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 23U), /*!< IPA clock reset */ - RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ + RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ RCU_USBHSRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 29U), /*!< USBHS clock reset */ /* AHB2 peripherals */ RCU_DCIRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 0U), /*!< DCI clock reset */ @@ -687,7 +686,7 @@ typedef enum RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ @@ -697,7 +696,7 @@ typedef enum RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ - RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ + RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ @@ -963,13 +962,13 @@ typedef enum #define RCU_PLLSAIR_DIV16 CFG1_PLLSAIRDIV(3) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/16 */ /* TIMER clock selection */ -#define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) +#define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) */ -#define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), - 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; +#define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) */ /* RCU_PLLSSCTL register bit define */ @@ -991,7 +990,7 @@ typedef enum /* The PLLP output frequency division factor from PLL VCO clock */ #define RCU_PLLP_DIV_MIN ((uint32_t)2U) /*!< PLLP_DIV min value */ #define RCU_PLLP_DIV_MAX ((uint32_t)8U) /*!< PLLP_DIV max value */ - + /* PLL Clock Source Selection */ #define RCU_PLLSRC_IRC16M ((uint32_t)0x00000000U) /*!< IRC16M clock selected as source clock of PLL, PLLSAI, PLLI2S */ #define RCU_PLLSRC_HXTAL RCU_PLL_PLLSEL /*!< HXTAL clock selected as source clock of PLL, PLLSAI, PLLI2S */ @@ -1000,10 +999,10 @@ typedef enum #define RCU_PLLQ_DIV_MIN ((uint32_t)2U) /*!< PLLQ_DIV min value */ #define RCU_PLLQ_DIV_MAX ((uint32_t)15U) /*!< PLLQ_DIV max value */ -#define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) -#define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) -#define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) -#define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) +#define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) +#define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) +#define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) +#define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) /* RCU_BDCTL register bit define */ /* LXTAL drive capability */ @@ -1058,7 +1057,7 @@ typedef enum #define CHECK_PLLSAI_R_VALID(val) (((val) >= RCU_PLLSAIR_DIV_MIN)&&((val) <= RCU_PLLSAIR_DIV_MAX)) /* RCU_ADDCTL register bit define */ -/* 48MHz clock selection */ +/* 48MHz clock selection */ #define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ #define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ @@ -1068,13 +1067,14 @@ typedef enum /* Deep-sleep mode voltage */ #define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0 DSV_DSLPVS(0) /*!< core voltage is default value in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1 DSV_DSLPVS(1) /*!< core voltage is (default value-0.1)V in deep-sleep mode(customers are not recommended to use it)*/ +#define RCU_DEEPSLEEP_V_2 DSV_DSLPVS(2) /*!< core voltage is (default value-0.2)V in deep-sleep mode(customers are not recommended to use it)*/ +#define RCU_DEEPSLEEP_V_3 DSV_DSLPVS(3) /*!< core voltage is (default value-0.3)V in deep-sleep mode(customers are not recommended to use it)*/ /* function declarations */ +/* peripherals clock configure functions */ /* deinitialize the RCU */ void rcu_deinit(void); /* enable the peripherals clock */ @@ -1094,6 +1094,7 @@ void rcu_bkp_reset_enable(void); /* disable the BKP reset */ void rcu_bkp_reset_disable(void); +/* system and peripherals clock source, system reset configure functions */ /* configure the system clock source */ void rcu_system_clock_source_config(uint32_t ck_sys); /* get the system clock source */ @@ -1125,11 +1126,47 @@ void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); /* configure the PLL48M clock selection */ void rcu_pll48m_clock_config(uint32_t pll48m_clock_source); /* configure the TIMER clock prescaler selection */ -void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); +void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); /* configure the TLI clock division selection */ void rcu_tli_clock_div_config(uint32_t pllsai_r_div); +/* LXTAL, IRC8M, PLL and other oscillator configure functions */ +/* configure the LXTAL drive capability */ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* set the IRC16M adjust value */ +void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval); +/* configure the spread spectrum modulation for the main PLL clock */ +void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt); +/* enable the spread spectrum modulation for the main PLL clock */ +void rcu_spread_spectrum_enable(void); +/* disable the spread spectrum modulation for the main PLL clock */ +void rcu_spread_spectrum_disable(void); +/* clock monitor configure functions */ +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* voltage configure and clock frequency get functions */ +/* unlock the voltage key */ +void rcu_voltage_key_unlock(void); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +/* flag & interrupt functions */ /* get the clock stabilization and periphral reset flags */ FlagStatus rcu_flag_get(rcu_flag_enum flag); /* clear the reset flag */ @@ -1143,37 +1180,4 @@ void rcu_interrupt_enable(rcu_int_enum interrupt); /* disable the stabilization interrupt */ void rcu_interrupt_disable(rcu_int_enum interrupt); -/* configure the LXTAL drive capability */ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); -/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC16M adjust value */ -void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval); -/* configure the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt); -/* enable the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_enable(void); -/* disable the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_disable(void); -/* unlock the voltage key */ -void rcu_voltage_key_unlock(void); -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - #endif /* GD32F4XX_RCU_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h index 75e66f236e..fe6df1fca2 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -280,7 +281,7 @@ typedef struct ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ -}rtc_tamper_struct; +}rtc_tamper_struct; /* time register value */ #define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */ @@ -501,12 +502,12 @@ typedef struct #define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */ /* RTC alarm */ -#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ -#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ +#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ +#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ /* RTC coarse calibration direction */ -#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */ -#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */ +#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */ +#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */ /* RTC wakeup timer clock */ #define CTL_WTCS(regval) (BITS(0,2) & ((regval)<< 0)) @@ -516,7 +517,7 @@ typedef struct #define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */ #define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */ #define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */ - + /* RTC_AF pin */ #define RTC_AF0_TIMESTAMP ((uint32_t)0x00000000) /*!< RTC_AF0 use for timestamp */ #define RTC_AF1_TIMESTAMP RTC_TAMP_TSSEL /*!< RTC_AF1 use for timestamp */ @@ -524,7 +525,7 @@ typedef struct #define RTC_AF1_TAMPER0 RTC_TAMP_TP0SEL /*!< RTC_AF1 use for tamper0 */ /* RTC flags */ -#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ +#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ #define RTC_FLAG_ALRM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */ #define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */ #define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h index a18214c023..7b8189d62b 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -43,24 +44,24 @@ OF SUCH DAMAGE. #define SDIO SDIO_BASE /* registers definitions */ -#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ -#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ -#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ -#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ -#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ -#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ -#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ -#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ -#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ -#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ -#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ -#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ -#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ -#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ -#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ -#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ -#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ -#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ +#define SDIO_PWRCTL REG32(SDIO + 0x00000000U) /*!< SDIO power control register */ +#define SDIO_CLKCTL REG32(SDIO + 0x00000004U) /*!< SDIO clock control register */ +#define SDIO_CMDAGMT REG32(SDIO + 0x00000008U) /*!< SDIO command argument register */ +#define SDIO_CMDCTL REG32(SDIO + 0x0000000CU) /*!< SDIO command control register */ +#define SDIO_RSPCMDIDX REG32(SDIO + 0x00000010U) /*!< SDIO command index response register */ +#define SDIO_RESP0 REG32(SDIO + 0x00000014U) /*!< SDIO response register 0 */ +#define SDIO_RESP1 REG32(SDIO + 0x00000018U) /*!< SDIO response register 1 */ +#define SDIO_RESP2 REG32(SDIO + 0x0000001CU) /*!< SDIO response register 2 */ +#define SDIO_RESP3 REG32(SDIO + 0x00000020U) /*!< SDIO response register 3 */ +#define SDIO_DATATO REG32(SDIO + 0x00000024U) /*!< SDIO data timeout register */ +#define SDIO_DATALEN REG32(SDIO + 0x00000028U) /*!< SDIO data length register */ +#define SDIO_DATACTL REG32(SDIO + 0x0000002CU) /*!< SDIO data control register */ +#define SDIO_DATACNT REG32(SDIO + 0x00000030U) /*!< SDIO data counter register */ +#define SDIO_STAT REG32(SDIO + 0x00000034U) /*!< SDIO status register */ +#define SDIO_INTC REG32(SDIO + 0x00000038U) /*!< SDIO interrupt clear register */ +#define SDIO_INTEN REG32(SDIO + 0x0000003CU) /*!< SDIO interrupt enable register */ +#define SDIO_FIFOCNT REG32(SDIO + 0x00000048U) /*!< SDIO FIFO counter register */ +#define SDIO_FIFO REG32(SDIO + 0x00000080U) /*!< SDIO FIFO data register */ /* bits definitions */ /* SDIO_PWRCTL */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h index 61bf8b1af2..d56967877f 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -53,27 +54,27 @@ OF SUCH DAMAGE. #define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U) /* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register */ +#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register */ /* I2S_ADD registers definitions */ -#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00U) /*!< I2S_ADD control register 0 */ -#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x04U) /*!< I2S_ADD control register 1*/ -#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x08U) /*!< I2S_ADD status register */ -#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0CU) /*!< I2S_ADD data register */ -#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x10U) /*!< I2S_ADD CRC polynomial register */ -#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x14U) /*!< I2S_ADD receive CRC register */ -#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x18U) /*!< I2S_ADD transmit CRC register */ -#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x1CU) /*!< I2S_ADD I2S control register */ -#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */ +#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00000000U) /*!< I2S_ADD control register 0 */ +#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x00000004U) /*!< I2S_ADD control register 1*/ +#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x00000008U) /*!< I2S_ADD status register */ +#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0000000CU) /*!< I2S_ADD data register */ +#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x00000010U) /*!< I2S_ADD CRC polynomial register */ +#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x00000014U) /*!< I2S_ADD receive CRC register */ +#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x00000018U) /*!< I2S_ADD transmit CRC register */ +#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x0000001CU) /*!< I2S_ADD I2S control register */ +#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x00000020U) /*!< I2S_ADD I2S clock prescaler register */ /* bits definitions */ /* SPI_CTL0 */ @@ -146,8 +147,7 @@ OF SUCH DAMAGE. /* constants definitions */ /* SPI and I2S parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t device_mode; /*!< SPI master or slave */ uint32_t trans_mode; /*!< SPI transtype */ uint32_t frame_size; /*!< SPI frame size */ @@ -155,7 +155,7 @@ typedef struct uint32_t endian; /*!< SPI big endian or little endian */ uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ uint32_t prescale; /*!< SPI prescale factor */ -}spi_parameter_struct; +} spi_parameter_struct; /* SPI mode definitions */ #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ @@ -283,19 +283,19 @@ typedef struct /* initialization functions */ /* deinitialize SPI and I2S */ void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI struct with the default values */ -void spi_struct_para_init(spi_parameter_struct* spi_struct); +/* initialize the parameters of SPI struct with default values */ +void spi_struct_para_init(spi_parameter_struct *spi_struct); /* initialize SPI parameter */ -void spi_init(uint32_t spi_periph,spi_parameter_struct* spi_struct); +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); /* enable SPI */ void spi_enable(uint32_t spi_periph); /* disable SPI */ void spi_disable(uint32_t spi_periph); /* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl); +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl); /* configure I2S prescale */ -void i2s_psc_config(uint32_t spi_periph,uint32_t i2s_audiosample,uint32_t i2s_frameformat,uint32_t i2s_mckout); +void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout); /* enable I2S */ void i2s_enable(uint32_t spi_periph); /* disable I2S */ @@ -312,24 +312,28 @@ void spi_nss_internal_high(uint32_t spi_periph); void spi_nss_internal_low(uint32_t spi_periph); /* SPI DMA functions */ -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph,uint8_t spi_dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph,uint8_t spi_dma); +/* enable SPI DMA send or receive */ +void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma); +/* diable SPI DMA send or receive */ +void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma); /* SPI/I2S transfer configure functions */ /* configure SPI/I2S data frame format */ -void spi_i2s_data_frame_format_config(uint32_t spi_periph,uint16_t frame_format); +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); /* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph,uint16_t data); +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); /* SPI receive data */ uint16_t spi_i2s_data_receive(uint32_t spi_periph); /* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph,uint32_t transfer_direction); +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); +/* configure i2s full duplex mode */ +void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl, uint32_t i2s_frameformat); +/* clear TI Mode Format Error flag status */ +void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag); /* SPI CRC functions */ /* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly); +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); /* get SPI CRC polynomial */ uint16_t spi_crc_polynomial_get(uint32_t spi_periph); /* turn on SPI CRC function */ @@ -339,7 +343,9 @@ void spi_crc_off(uint32_t spi_periph); /* SPI next data is CRC value */ void spi_crc_next(uint32_t spi_periph); /* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc); +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); /* SPI TI mode functions */ /* enable SPI TI mode */ @@ -347,33 +353,28 @@ void spi_ti_mode_enable(uint32_t spi_periph); /* disable SPI TI mode */ void spi_ti_mode_disable(uint32_t spi_periph); -/* configure i2s full duplex mode */ -void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat); - /* quad wire SPI functions */ /* enable quad wire SPI */ -void qspi_enable(uint32_t spi_periph); +void spi_quad_enable(uint32_t spi_periph); /* disable quad wire SPI */ -void qspi_disable(uint32_t spi_periph); +void spi_quad_disable(uint32_t spi_periph); /* enable quad wire SPI write */ -void qspi_write_enable(uint32_t spi_periph); +void spi_quad_write_enable(uint32_t spi_periph); /* enable quad wire SPI read */ -void qspi_read_enable(uint32_t spi_periph); -/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_enable(uint32_t spi_periph); -/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_disable(uint32_t spi_periph); +void spi_quad_read_enable(uint32_t spi_periph); +/* enable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_enable(uint32_t spi_periph); +/* disable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_disable(uint32_t spi_periph); -/* flag & interrupt functions */ -/* enable SPI interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph,uint8_t spi_i2s_int); -/* disable SPI interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph,uint8_t spi_i2s_int); -/* get SPI and I2S interrupt status*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph,uint8_t spi_i2s_int); +/* flag and interrupt functions */ /* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t spi_i2s_flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); #endif /* GD32F4XX_SPI_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h index 047910478a..2e9922db1d 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h @@ -1,36 +1,37 @@ /*! \file gd32f4xx_syscfg.h \brief definitions for the SYSCFG - + \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -166,7 +167,7 @@ void syscfg_bootmode_config(uint8_t syscfg_bootmode); /* configure FMC memory mapping swap */ void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap); /* configure the EXMC swap */ -void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap); +void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap); /* configure the GPIO pin as EXTI Line */ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); /* configure the PHY interface for the ethernet MAC */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h index 9da6e12bdd..f80c8014be 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h @@ -5,33 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - All rights reserved. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -113,7 +113,7 @@ OF SUCH DAMAGE. #define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - + /* TIMER_DMAINTEN */ #define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ #define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ @@ -266,7 +266,7 @@ OF SUCH DAMAGE. /* constants definitions */ /* TIMER init parameter struct definitions*/ typedef struct -{ +{ uint16_t prescaler; /*!< prescaler value */ uint16_t alignedmode; /*!< aligned mode */ uint16_t counterdirection; /*!< counter direction */ @@ -277,7 +277,7 @@ typedef struct /* break parameter struct definitions*/ typedef struct -{ +{ uint16_t runoffstate; /*!< run mode off-state */ uint16_t ideloffstate; /*!< idle mode off-state */ uint16_t deadtime; /*!< dead time */ @@ -289,7 +289,7 @@ typedef struct /* channel output parameter struct definitions */ typedef struct -{ +{ uint16_t outputstate; /*!< channel output state */ uint16_t outputnstate; /*!< channel complementary output state */ uint16_t ocpolarity; /*!< channel output polarity */ @@ -300,7 +300,7 @@ typedef struct /* channel input parameter struct definitions */ typedef struct -{ +{ uint16_t icpolarity; /*!< channel input polarity */ uint16_t icselection; /*!< channel input mode selection */ uint16_t icprescaler; /*!< channel input capture prescaler */ @@ -341,8 +341,6 @@ typedef struct #define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ #define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF - - /* TIMER DMA source enable */ #define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ #define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ @@ -352,7 +350,7 @@ typedef struct #define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ #define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ -/* channel DMA request source selection */ +/* channel DMA request source selection */ #define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ #define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ @@ -418,8 +416,8 @@ typedef struct #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ /* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ +#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ /* count direction */ #define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ @@ -432,18 +430,18 @@ typedef struct #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ /* single pulse mode */ -#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ /* update source */ -#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ +#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ /* run mode off-state configure */ #define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ -/* idle mode off-state configure */ +/* idle mode off-state configure */ #define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ @@ -488,11 +486,11 @@ typedef struct #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ -/* idle state of channel output */ +/* idle state of channel output */ #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ -/* idle state of channel complementary output */ +/* idle state of channel complementary output */ #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ @@ -518,7 +516,7 @@ typedef struct #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ -/* channel control shadow register update control */ +/* channel control shadow register update control */ #define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ #define TIMER_UPDATECTL_CCUTRI ((uint32_t)0x00000001U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ @@ -539,7 +537,7 @@ typedef struct #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ /* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ @@ -561,19 +559,19 @@ typedef struct #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ /* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */ +#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */ +#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */ #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ /* external trigger prescaler */ #define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) @@ -586,19 +584,19 @@ typedef struct #define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ /* timer1 internal trigger input1 remap */ -#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) +#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) #define TIMER1_ITI1_RMP_TIMER7_TRGO TIMER1_IRMP(0) /*!< timer1 internal trigger input 1 remap to TIMER7_TRGO */ #define TIMER1_ITI1_RMP_ETHERNET_PTP TIMER1_IRMP(1) /*!< timer1 internal trigger input 1 remap to ethernet PTP */ #define TIMER1_ITI1_RMP_USB_FS_SOF TIMER1_IRMP(2) /*!< timer1 internal trigger input 1 remap to USB FS SOF */ #define TIMER1_ITI1_RMP_USB_HS_SOF TIMER1_IRMP(3) /*!< timer1 internal trigger input 1 remap to USB HS SOF */ /* timer4 channel 3 input remap */ -#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) +#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) #define TIMER4_CI3_RMP_GPIO TIMER4_IRMP(0) /*!< timer4 channel 3 input remap to GPIO pin */ #define TIMER4_CI3_RMP_IRC32K TIMER4_IRMP(1) /*!< timer4 channel 3 input remap to IRC32K */ #define TIMER4_CI3_RMP_LXTAL TIMER4_IRMP(2) /*!< timer4 channel 3 input remap to LXTAL */ @@ -610,8 +608,8 @@ typedef struct #define TIMER10_ITI1_RMP_RTC_HXTAL_DIV TIMER10_IRMP(2) /*!< timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) */ /* timerx(x=0,1,2,13,14,15,16) write cc register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ /* the output value selection */ #define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ @@ -660,20 +658,6 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); /* configure TIMER update source */ void timer_update_source_config(uint32_t timer_periph, uint32_t update); -/* TIMER interrupt and flag*/ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get timer interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flags */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flags */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - /* timer DMA and event*/ /* enable the TIMER DMA */ void timer_dma_enable(uint32_t timer_periph, uint16_t dma); @@ -778,4 +762,18 @@ void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); /* configure TIMER output value selection */ void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); +/* TIMER interrupt and flag*/ +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get timer interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); + #endif /* GD32F4XX_TIMER_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h index 8b1232fa17..78e6670177 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,37 +41,37 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* TLI definitions */ -#define TLI TLI_BASE /*!< TLI base address */ +#define TLI TLI_BASE /*!< TLI base address */ /* TLI layer definitions */ -#define LAYER0 TLI_BASE /*!< TLI layer0 base address */ -#define LAYER1 (TLI_BASE+0x80) /*!< TLI layer1 base address */ +#define LAYER0 TLI_BASE /*!< TLI layer0 base address */ +#define LAYER1 (TLI_BASE + 0x00000080U) /*!< TLI layer1 base address */ /* registers definitions */ -#define TLI_SPSZ REG32(TLI + 0x08U) /*!< TLI synchronous pulse size register */ -#define TLI_BPSZ REG32(TLI + 0x0CU) /*!< TLI back-porch size register */ -#define TLI_ASZ REG32(TLI + 0x10U) /*!< TLI active size register */ -#define TLI_TSZ REG32(TLI + 0x14U) /*!< TLI total size register */ -#define TLI_CTL REG32(TLI + 0x18U) /*!< TLI control register */ -#define TLI_RL REG32(TLI + 0x24U) /*!< TLI reload Layer register */ -#define TLI_BGC REG32(TLI + 0x2CU) /*!< TLI background color register */ -#define TLI_INTEN REG32(TLI + 0x34U) /*!< TLI interrupt enable register */ -#define TLI_INTF REG32(TLI + 0x38U) /*!< TLI interrupt flag register */ -#define TLI_INTC REG32(TLI + 0x3CU) /*!< TLI interrupt flag clear register */ -#define TLI_LM REG32(TLI + 0x40U) /*!< TLI line mark register */ -#define TLI_CPPOS REG32(TLI + 0x44U) /*!< TLI current pixel position register */ -#define TLI_STAT REG32(TLI + 0x48U) /*!< TLI status register */ -#define TLI_LxCTL(layerx) REG32((layerx) + 0x84U) /*!< TLI layer x control register */ -#define TLI_LxHPOS(layerx) REG32((layerx) + 0x88U) /*!< TLI layer x horizontal position parameters register */ -#define TLI_LxVPOS(layerx) REG32((layerx) + 0x8CU) /*!< TLI layer x vertical position parameters register */ -#define TLI_LxCKEY(layerx) REG32((layerx) + 0x90U) /*!< TLI layer x color key register */ -#define TLI_LxPPF(layerx) REG32((layerx) + 0x94U) /*!< TLI layer x packeted pixel format register */ -#define TLI_LxSA(layerx) REG32((layerx) + 0x98U) /*!< TLI layer x specified alpha register */ -#define TLI_LxDC(layerx) REG32((layerx) + 0x9CU) /*!< TLI layer x default color register */ -#define TLI_LxBLEND(layerx) REG32((layerx) + 0xA0U) /*!< TLI layer x blending register */ -#define TLI_LxFBADDR(layerx) REG32((layerx) + 0xACU) /*!< TLI layer x frame base address register */ -#define TLI_LxFLLEN(layerx) REG32((layerx) + 0xB0U) /*!< TLI layer x frame line length register */ -#define TLI_LxFTLN(layerx) REG32((layerx) + 0xB4U) /*!< TLI layer x frame total line number register */ -#define TLI_LxLUT(layerx) REG32((layerx) + 0xC4U) /*!< TLI layer x look up table register */ +#define TLI_SPSZ REG32(TLI + 0x00000008U) /*!< TLI synchronous pulse size register */ +#define TLI_BPSZ REG32(TLI + 0x0000000CU) /*!< TLI back-porch size register */ +#define TLI_ASZ REG32(TLI + 0x00000010U) /*!< TLI active size register */ +#define TLI_TSZ REG32(TLI + 0x00000014U) /*!< TLI total size register */ +#define TLI_CTL REG32(TLI + 0x00000018U) /*!< TLI control register */ +#define TLI_RL REG32(TLI + 0x00000024U) /*!< TLI reload Layer register */ +#define TLI_BGC REG32(TLI + 0x0000002CU) /*!< TLI background color register */ +#define TLI_INTEN REG32(TLI + 0x00000034U) /*!< TLI interrupt enable register */ +#define TLI_INTF REG32(TLI + 0x00000038U) /*!< TLI interrupt flag register */ +#define TLI_INTC REG32(TLI + 0x0000003CU) /*!< TLI interrupt flag clear register */ +#define TLI_LM REG32(TLI + 0x00000040U) /*!< TLI line mark register */ +#define TLI_CPPOS REG32(TLI + 0x00000044U) /*!< TLI current pixel position register */ +#define TLI_STAT REG32(TLI + 0x00000048U) /*!< TLI status register */ +#define TLI_LxCTL(layerx) REG32((layerx) + 0x00000084U) /*!< TLI layer x control register */ +#define TLI_LxHPOS(layerx) REG32((layerx) + 0x00000088U) /*!< TLI layer x horizontal position parameters register */ +#define TLI_LxVPOS(layerx) REG32((layerx) + 0x0000008CU) /*!< TLI layer x vertical position parameters register */ +#define TLI_LxCKEY(layerx) REG32((layerx) + 0x00000090U) /*!< TLI layer x color key register */ +#define TLI_LxPPF(layerx) REG32((layerx) + 0x00000094U) /*!< TLI layer x packeted pixel format register */ +#define TLI_LxSA(layerx) REG32((layerx) + 0x00000098U) /*!< TLI layer x specified alpha register */ +#define TLI_LxDC(layerx) REG32((layerx) + 0x0000009CU) /*!< TLI layer x default color register */ +#define TLI_LxBLEND(layerx) REG32((layerx) + 0x000000A0U) /*!< TLI layer x blending register */ +#define TLI_LxFBADDR(layerx) REG32((layerx) + 0x000000ACU) /*!< TLI layer x frame base address register */ +#define TLI_LxFLLEN(layerx) REG32((layerx) + 0x000000B0U) /*!< TLI layer x frame line length register */ +#define TLI_LxFTLN(layerx) REG32((layerx) + 0x000000B4U) /*!< TLI layer x frame total line number register */ +#define TLI_LxLUT(layerx) REG32((layerx) + 0x000000C4U) /*!< TLI layer x look up table register */ /* bits definitions */ /* TLI_SPSZ */ @@ -192,8 +193,7 @@ OF SUCH DAMAGE. /* constants definitions */ /* TLI parameter struct definitions */ -typedef struct -{ +typedef struct { uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ @@ -209,11 +209,10 @@ typedef struct uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */ uint32_t signalpolarity_de; /*!< data enable polarity selection */ uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */ -}tli_parameter_struct; +} tli_parameter_struct; /* TLI layer parameter struct definitions */ -typedef struct -{ +typedef struct { uint16_t layer_window_rightpos; /*!< window right position */ uint16_t layer_window_leftpos; /*!< window left position */ uint16_t layer_window_bottompos; /*!< window bottom position */ @@ -230,29 +229,27 @@ typedef struct uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ uint16_t layer_frame_line_length; /*!< frame line length */ uint16_t layer_frame_total_line_number; /*!< frame total line number */ -}tli_layer_parameter_struct; +} tli_layer_parameter_struct; /* TLI layer LUT parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t layer_table_addr; /*!< look up table write address */ uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */ uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */ uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ -}tli_layer_lut_parameter_struct; +} tli_layer_lut_parameter_struct; /* packeted pixel format */ -typedef enum -{ - LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ - LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ - LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ - LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ - LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ - LAYER_PPF_L8, /*!< layerx pixel format L8 */ - LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ - LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ -}tli_layer_ppf_enum; +typedef enum { + LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ + LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ + LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ + LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ + LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ + LAYER_PPF_L8, /*!< layerx pixel format L8 */ + LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ + LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ +} tli_layer_ppf_enum; /* TLI flags */ #define TLI_FLAG_VDE TLI_STAT_VDE /*!< current VDE status */ @@ -333,16 +330,16 @@ void tli_reload_config(uint8_t reload_mod); that call this function after a tli_layer_parameter_struct structure is defined */ void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct); /* initialize TLI layer */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct); +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct); /* reconfigure window position */ -void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y); +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y); /* initialize the parameters of TLI layer LUT structure with the default values, it is suggested that call this function after a tli_layer_lut_parameter_struct structure is defined */ void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct); /* initialize TLI layer LUT */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct); +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct); /* initialize TLI layer color key */ -void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey); +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey); /* enable TLI layer */ void tli_layer_enable(uint32_t layerx); /* disable TLI layer */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h index f321b15d28..dc6cd3af42 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h @@ -5,32 +5,33 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -43,14 +44,14 @@ OF SUCH DAMAGE. #define TRNG TRNG_BASE /* registers definitions */ -#define TRNG_CTL REG32(TRNG + 0x00U) /*!< control register */ -#define TRNG_STAT REG32(TRNG + 0x04U) /*!< status register */ -#define TRNG_DATA REG32(TRNG + 0x08U) /*!< data register */ +#define TRNG_CTL REG32(TRNG + 0x00000000U) /*!< control register */ +#define TRNG_STAT REG32(TRNG + 0x00000004U) /*!< status register */ +#define TRNG_DATA REG32(TRNG + 0x00000008U) /*!< data register */ /* bits definitions */ /* TRNG_CTL */ #define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */ -#define TRNG_CTL_IE BIT(3) /*!< interrupt enable bit */ +#define TRNG_CTL_TRNGIE BIT(3) /*!< interrupt enable bit */ /* TRNG_STAT */ #define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */ @@ -60,45 +61,43 @@ OF SUCH DAMAGE. #define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */ /* TRNG_DATA */ -#define TRNG_DATA_TRNDATA BITS(0,31) /*!< 32-Bit Random data */ +#define TRNG_DATA_TRNGDATA BITS(0,31) /*!< 32-Bit Random data */ /* constants definitions */ -/* trng status flag */ -typedef enum -{ +/* TRNG status flag */ +typedef enum { TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ -}trng_flag_enum; +} trng_flag_enum; -/* trng inerrupt flag */ -typedef enum -{ +/* TRNG inerrupt flag */ +typedef enum { TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */ TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */ -}trng_int_flag_enum; +} trng_int_flag_enum; /* function declarations */ /* initialization functions */ -/* deinitialize the TRNG */ +/* reset TRNG */ void trng_deinit(void); -/* enable the TRNG interface */ +/* enable TRNG */ void trng_enable(void); -/* disable the TRNG interface */ +/* disable TRNG */ void trng_disable(void); /* get the true random data */ uint32_t trng_get_true_random_data(void); -/* flag & interrupt functions */ -/* trng interrupt enable */ +/* interrupt & flag functions */ +/* enable TRNG interrupt */ void trng_interrupt_enable(void); -/* trng interrupt disable */ +/* disable TRNG interrupt */ void trng_interrupt_disable(void); -/* get the trng status flags */ +/* get TRNG flag status */ FlagStatus trng_flag_get(trng_flag_enum flag); -/* get the trng interrupt flags */ +/* get TRNG interrupt flag status */ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag); -/* clear the trng interrupt flags */ +/* clear TRNG interrupt flag status */ void trng_interrupt_flag_clear(trng_int_flag_enum int_flag); #endif /* GD32F4XX_TRNG_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h index 3cd49d827f..6f55eeee35 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -64,94 +65,94 @@ OF SUCH DAMAGE. /* bits definitions */ /* USARTx_STAT0 */ -#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT0_TC BIT(6) /*!< transmission complete */ -#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ +#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT0_TC BIT(6) /*!< transmission complete */ +#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ /* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ /* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ /* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ -#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< enable receiver */ +#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */ +#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */ +#define USART_CTL0_RBNEIE BIT(5) /*!< enable read data buffer not empty interrupt and overrun error interrupt */ +#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */ +#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter buffer empty interrupt */ +#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< enable parity check function */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< enable USART */ +#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ /* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< enable LIN break detected interrupt */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< enable CK pin */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< enable LIN mode */ /* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ -#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ +#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt */ +#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< enable half-duplex */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */ +#define USART_CTL2_DENR BIT(6) /*!< enable DMA request for reception */ +#define USART_CTL2_DENT BIT(7) /*!< enable DMA request for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */ +#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */ +#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */ +#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ /* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ /* USARTx_CTL3 */ -#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ -#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ -#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ -#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ -#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ -#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ -#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ -#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ +#define USART_CTL3_RTEN BIT(0) /*!< enable receiver timeout */ +#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ +#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ +#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ +#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ +#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ +#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ +#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ /* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ /* USARTx_STAT1 */ -#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT1_BSY BIT(16) /*!< busy flag */ +#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT1_BSY BIT(16) /*!< busy flag */ /* USARTx_CHC */ -#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ -#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ -#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ -#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ +#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ +#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ +#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ +#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ /* constants definitions */ /* define the USART bit position and its register index offset */ @@ -164,17 +165,16 @@ OF SUCH DAMAGE. #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) /* register offset */ -#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ -#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ -#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ -#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ -#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ +#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ +#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ /* USART flags */ -typedef enum -{ +typedef enum { /* flags in STAT0 register */ USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ @@ -192,11 +192,10 @@ typedef enum USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ /* flags in CHC register */ USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ -}usart_flag_enum; +} usart_flag_enum; /* USART interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt flags in CTL0 register */ USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ @@ -214,11 +213,10 @@ typedef enum /* interrupt flags in CTL3 register */ USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ -}usart_interrupt_flag_enum; +} usart_interrupt_flag_enum; /* USART interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt in CTL0 register */ USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ @@ -233,11 +231,10 @@ typedef enum /* interrupt in CTL3 register */ USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ -}usart_interrupt_enum; +} usart_interrupt_enum; -/* USART invert configure */ -typedef enum -{ +/* configure USART invert */ +typedef enum { /* data bit level inversion */ USART_DINV_ENABLE, /*!< data bit level inversion */ USART_DINV_DISABLE, /*!< data bit level not inversion */ @@ -247,14 +244,14 @@ typedef enum /* RX pin level inversion */ USART_RXPIN_ENABLE, /*!< RX pin level inversion */ USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ -}usart_invert_enum; +} usart_invert_enum; -/* USART receiver configure */ +/* configure USART receiver */ #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ -/* USART transmitter configure */ +/* configure USART transmitter */ #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ @@ -307,32 +304,32 @@ typedef enum #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ -/* USART DMA request for receive configure */ +/* configure USART DMA request for receive */ #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ +#define USART_RECEIVE_DMA_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_RECEIVE_DMA_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ -/* USART DMA request for transmission configure */ +/* configure USART DMA request for transmission */ #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ +#define USART_TRANSMIT_DMA_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_TRANSMIT_DMA_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ -/* USART RTS configure */ +/* configure USART RTS */ #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< enable RTS */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< disable RTS */ -/* USART CTS configure */ +/* configure USART CTS */ #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< enable CTS */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< disable CTS */ -/* USART one sample bit method configure */ +/* configure USART one sample bit method */ #define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) #define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */ #define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */ -/* USART IrDA low-power enable */ +/* enable USART IrDA low-power */ #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ @@ -394,7 +391,7 @@ void usart_receiver_timeout_disable(uint32_t usart_periph); /* configure receiver timeout threshold */ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); /* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); +void usart_data_transmit(uint32_t usart_periph, uint16_t data); /* USART receive data function */ uint16_t usart_data_receive(uint32_t usart_periph); @@ -434,7 +431,7 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32 /* smartcard communication */ /* configure guard time value in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +void usart_guard_time_config(uint32_t usart_periph, uint8_t guat); /* enable smartcard mode */ void usart_smartcard_mode_enable(uint32_t usart_periph); /* disable smartcard mode */ @@ -444,9 +441,9 @@ void usart_smartcard_mode_nack_enable(uint32_t usart_periph); /* disable NACK in smartcard mode */ void usart_smartcard_mode_nack_disable(uint32_t usart_periph); /* configure smartcard auto-retry number */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint8_t scrtnum); /* configure block length */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); +void usart_block_length_config(uint32_t usart_periph, uint8_t bl); /* IrDA communication */ /* enable IrDA mode */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h index 525b9a6e5a..69cdbff306 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h @@ -1,36 +1,37 @@ /*! \file gd32f4xx_wwdgt.h - \brief definitions for the WWDGT + \brief definitions for the WWDGT \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,7 +41,7 @@ OF SUCH DAMAGE. #include "gd32f4xx.h" /* WWDGT definitions */ -#define WWDGT WWDGT_BASE +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ /* registers definitions */ #define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ @@ -67,6 +68,11 @@ OF SUCH DAMAGE. #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ #define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + /* function declarations */ /* reset the window watchdog timer configuration */ void wwdgt_deinit(void); @@ -78,11 +84,11 @@ void wwdgt_counter_update(uint16_t counter_value); /* configure counter value, window value, and prescaler divider value */ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); /* check early wakeup interrupt state of WWDGT */ FlagStatus wwdgt_flag_get(void); /* clear early wakeup interrupt state of WWDGT */ void wwdgt_flag_clear(void); +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); #endif /* GD32F4XX_WWDGT_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c index f249e6c840..3ea466fcd6 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -36,32 +37,32 @@ OF SUCH DAMAGE. #include "gd32f4xx_adc.h" -#define REGULAR_TRIGGER_MODE ((uint32_t)28U) -#define INSERTED_TRIGGER_MODE ((uint32_t)20U) +#define ROUTINE_TRIGGER_MODE ((uint32_t)28U) +#define INSERTED_TRIGGER_MODE ((uint32_t)20U) /* discontinuous mode macro*/ -#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) -/* ADC regular channel macro */ -#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) -#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) -#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) -#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) +/* ADC routine channel macro */ +#define ADC_ROUTINE_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_ROUTINE_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_ROUTINE_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_ROUTINE_CHANNEL_RANK_LENGTH ((uint8_t)5U) /* ADC sampling time macro */ -#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) -#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) -#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) /* ADC inserted channel macro */ -#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) -#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) /* ADC inserted channel offset macro */ -#define ADC_OFFSET_LENGTH ((uint8_t)3U) -#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) /*! - \brief reset ADC + \brief reset ADC \param[in] none \param[out] none \retval none @@ -73,9 +74,9 @@ void adc_deinit(void) } /*! - \brief configure the ADC clock for all the ADCs - \param[in] prescaler: configure ADCs prescaler ratio - only one parameter can be selected which is shown as below: + \brief configure the ADC clock for all the ADCs + \param[in] prescaler: configure ADCs prescaler ratio + only one parameter can be selected which is shown as below: \arg ADC_ADCCK_PCLK2_DIV2: PCLK2 div2 \arg ADC_ADCCK_PCLK2_DIV4: PCLK2 div4 \arg ADC_ADCCK_PCLK2_DIV6: PCLK2 div6 @@ -84,8 +85,8 @@ void adc_deinit(void) \arg ADC_ADCCK_HCLK_DIV6: HCLK div6 \arg ADC_ADCCK_HCLK_DIV10: HCLK div10 \arg ADC_ADCCK_HCLK_DIV20: HCLK div20 - \param[out] none - \retval none + \param[out] none + \retval none */ void adc_clock_config(uint32_t prescaler) { @@ -94,42 +95,42 @@ void adc_clock_config(uint32_t prescaler) } /*! - \brief enable or disable ADC special function - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] function: the function to config - only one parameter can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] function: the function to config + only one parameter can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted sequence convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none */ -void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue) +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) { - if(newvalue){ - if(0U != (function & ADC_SCAN_MODE)){ + if(newvalue) { + if(0U != (function & ADC_SCAN_MODE)) { /* enable scan mode */ ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* enable inserted channel group convert automatically */ + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + /* enable inserted sequence convert automatically */ ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; } - if(0U != (function & ADC_CONTINUOUS_MODE)){ + if(0U != (function & ADC_CONTINUOUS_MODE)) { /* enable continuous mode */ ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; } - }else{ - if(0U != (function & ADC_SCAN_MODE)){ + } else { + if(0U != (function & ADC_SCAN_MODE)) { /* disable scan mode */ ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* disable inserted channel group convert automatically */ + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + /* disable inserted sequence convert automatically */ ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; } - if(0U != (function & ADC_CONTINUOUS_MODE)){ + if(0U != (function & ADC_CONTINUOUS_MODE)) { /* disable continuous mode */ ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; } @@ -137,45 +138,45 @@ void adc_special_function_config(uint32_t adc_periph , uint32_t function , Contr } /*! - \brief configure ADC data alignment - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment - \param[out] none - \retval none + \brief configure ADC data alignment + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none */ -void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) { - if(ADC_DATAALIGN_RIGHT != data_alignment){ + if(ADC_DATAALIGN_RIGHT != data_alignment) { /* MSB alignment */ ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - }else{ + } else { /* LSB alignment */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); } } /*! - \brief enable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief enable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_enable(uint32_t adc_periph) { - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) { /* enable ADC */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; } } /*! - \brief disable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief disable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_disable(uint32_t adc_periph) { @@ -184,52 +185,52 @@ void adc_disable(uint32_t adc_periph) } /*! - \brief ADC calibration and reset calibration - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_calibration_enable(uint32_t adc_periph) { /* reset the selected ADC calibration registers */ ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; /* check the RSTCLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { } /* enable ADC calibration process */ ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; /* check the CLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) { } } /*! - \brief configure temperature sensor and internal reference voltage channel or VBAT channel function - \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel - only one parameter can be selected which is shown as below: - \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 - \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 - \param[in] newvalue: ENABLE or DISABLE -\param[out] none - \retval none + \brief configure temperature sensor and internal reference voltage channel or VBAT channel function + \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel + only one parameter can be selected which is shown as below: + \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 + \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none */ void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue) { - if(newvalue){ - if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ + if(newvalue) { + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) { /* enable ADC0 Vbat channel */ ADC_SYNCCTL |= ADC_VBAT_CHANNEL_SWITCH; } - if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)) { /* enable ADC0 Vref and Temperature channel */ ADC_SYNCCTL |= ADC_TEMP_VREF_CHANNEL_SWITCH; } - }else{ - if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ + } else { + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) { /* disable ADC0 Vbat channel */ ADC_SYNCCTL &= ~ADC_VBAT_CHANNEL_SWITCH; } - if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)) { /* disable ADC0 Vref and Temperature channel */ ADC_SYNCCTL &= ~ADC_TEMP_VREF_CHANNEL_SWITCH; } @@ -237,59 +238,59 @@ void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue) } /*! - \brief configure ADC resolution - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] resolution: ADC resolution - only one parameter can be selected which is shown as below: - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none + \brief configure ADC resolution + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none */ -void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) { ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES); ADC_CTL0(adc_periph) |= (uint32_t)resolution; } /*! - \brief configure ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] mode: ADC oversampling mode - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 - \param[out] none - \retval none + \brief configure ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none */ -void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio) +void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio) { - if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode) { ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; - }else{ + } else { ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); } /* config the shift and ratio */ @@ -298,10 +299,10 @@ void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t s } /*! - \brief enable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_oversample_mode_enable(uint32_t adc_periph) { @@ -309,10 +310,10 @@ void adc_oversample_mode_enable(uint32_t adc_periph) } /*! - \brief disable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_oversample_mode_disable(uint32_t adc_periph) { @@ -320,10 +321,10 @@ void adc_oversample_mode_disable(uint32_t adc_periph) } /*! - \brief enable DMA request - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none + \brief enable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none */ void adc_dma_mode_enable(uint32_t adc_periph) { @@ -344,7 +345,7 @@ void adc_dma_mode_disable(uint32_t adc_periph) } /*! - \brief when DMA=1, the DMA engine issues a request at end of each regular conversion + \brief when DMA=1, the DMA engine issues a request at end of each routine conversion \param[in] adc_periph: ADCx,x=0,1,2 \param[out] none \retval none @@ -355,7 +356,7 @@ void adc_dma_request_after_last_enable(uint32_t adc_periph) } /*! - \brief the DMA engine is disabled after the end of transfer signal from DMA controller is detected + \brief the DMA engine is disabled after the end of transfer signal from DMA controller is detected \param[in] adc_periph: ADCx,x=0,1,2 \param[out] none \retval none @@ -366,69 +367,69 @@ void adc_dma_request_after_last_disable(uint32_t adc_periph) } /*! - \brief configure ADC discontinuous mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel ,the number has no effect for inserted channel - \param[out] none - \retval none + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of routine & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for routine sequence ,the number has no effect for inserted sequence + \param[out] none + \retval none */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length) +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_sequence, uint8_t length) { - /* disable discontinuous mode of regular & inserted channel */ - ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: + /* disable discontinuous mode of routine & inserted channel */ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: /* config the number of conversions in discontinuous mode */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); - if((length <= 8U) && (length >= 1U)){ + if((length <= 8U) && (length >= 1U)) { ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } - /* enable regular channel group discontinuous mode */ + /* enable routine sequence discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; break; case ADC_INSERTED_CHANNEL: - /* enable inserted channel group discontinuous mode */ + /* enable inserted sequence discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; break; case ADC_CHANNEL_DISCON_DISABLE: - /* disable discontinuous mode of regular & inserted channel */ + /* disable discontinuous mode of routine & inserted channel */ default: break; } } /*! - \brief configure the length of regular channel group or inserted channel group - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none + \brief configure the length of routine sequence or inserted sequence + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_sequence: select the sequence + only one parameter can be selected which is shown as below: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] length: the length of the channel + routine channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length) +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t length) { - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - if((length >= 1U) && (length <= 16U)){ - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + if((length >= 1U) && (length <= 16U)) { + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } break; case ADC_INSERTED_CHANNEL: - if((length >= 1U) && (length <= 4U)){ - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + if((length >= 1U) && (length <= 4U)) { + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } break; default: @@ -437,124 +438,124 @@ void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , } /*! - \brief configure ADC regular channel - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles - \param[out] none - \retval none + \brief configure ADC routine channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] rank: the routine sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles + \param[out] none + \retval none */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +void adc_routine_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { - uint32_t rsq,sampt; + uint32_t rsq, sampt; - /* ADC regular sequence config */ - if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ - /* the regular group sequence rank is smaller than six */ + /* ADC routine sequence config */ + if(rank < ADC_ROUTINE_CHANNEL_RANK_SIX) { + /* the routine sequence rank is smaller than six */ rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank)); ADC_RSQ2(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ - /* the regular group sequence rank is smaller than twelve */ + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_TWELVE) { + /* the routine sequence rank is smaller than twelve */ rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX))); ADC_RSQ1(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ - /* the regular group sequence rank is smaller than sixteen */ + } else if(rank < ADC_ROUTINE_CHANNEL_RANK_SIXTEEN) { + /* the routine sequence rank is smaller than sixteen */ rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */ + rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE))); ADC_RSQ0(adc_periph) = rsq; - }else{ + } else { } /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the regular group sequence rank is smaller than ten */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { + /* the routine sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)); ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the regular group sequence rank is smaller than eighteen */ + } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { + /* the routine sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); ADC_SAMPT0(adc_periph) = sampt; - }else{ + } else { } } /*! - \brief configure ADC inserted channel + \brief configure ADC inserted channel \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] rank: the inserted sequence rank,this parameter must be between 0 to 3 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx \param[in] sample_time: The sample time value only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles \param[out] none \retval none */ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { uint8_t inserted_length; - uint32_t isq,sampt; + uint32_t isq, sampt; - /* get inserted channel group length */ - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ - if(rank < 4U){ + /* get inserted sequence length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted sequence */ + if(rank < 4U) { isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); - isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH))); + isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)); ADC_ISQ(adc_periph) = isq; } /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the inserted group sequence rank is smaller than ten */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { + /* the inserted sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ - sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); + sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel); ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the inserted group sequence rank is smaller than eighteen */ + } else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) { + /* the inserted sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ - sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN))); + sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); ADC_SAMPT0(adc_periph) = sampt; - }else{ + } else { } } @@ -563,23 +564,23 @@ void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t ad \param[in] adc_periph: ADCx,x=0,1,2 \param[in] inserted_channel : insert channel select only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 \param[in] offset : the offset data \param[out] none \retval none */ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) { uint8_t inserted_length; uint32_t num = 0U; - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); - if(num <= ADC_OFFSET_LENGTH){ + if(num <= ADC_OFFSET_LENGTH) { /* calculate the offset of the register */ num = num * ADC_OFFSET_SHIFT_LENGTH; /* config the offset of the selected channels */ @@ -590,60 +591,60 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_c /*! \brief configure ADC external trigger source \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - for regular channel: + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] external_trigger_source: routine or inserted sequence trigger source + for routine sequence: only one parameter can be selected which is shown as below: - \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH2: external trigger timer 1 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH3: external trigger timer 1 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_TRGO: external trigger timer 1 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_CH0 : external trigger timer 2 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_TRGO : external trigger timer 2 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T3_CH3: external trigger timer 3 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH0: external trigger timer 4 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH1: external trigger timer 4 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH2: external trigger timer 4 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_CH0: external trigger timer 7 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_TRGO: external trigger timer 7 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger extiline 11 select for regular channel - for inserted channel: + \arg ADC_EXTTRIG_ROUTINE_T0_CH0: external trigger timer 0 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH1: external trigger timer 0 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T0_CH2: external trigger timer 0 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH1: external trigger timer 1 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH2: external trigger timer 1 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_CH3: external trigger timer 1 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T1_TRGO: external trigger timer 1 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_CH0 : external trigger timer 2 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T2_TRGO : external trigger timer 2 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T3_CH3: external trigger timer 3 CC3 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH0: external trigger timer 4 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH1: external trigger timer 4 CC1 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T4_CH2: external trigger timer 4 CC2 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_CH0: external trigger timer 7 CC0 event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_T7_TRGO: external trigger timer 7 TRGO event select for routine sequence + \arg ADC_EXTTRIG_ROUTINE_EXTI_11: external trigger extiline 11 select for routine sequence + for inserted sequence: only one parameter can be selected which is shown as below: - \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event - \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event - \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event + \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event + \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 \param[out] none \retval none */ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source) +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t external_trigger_source) { - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure ADC regular group external trigger source */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger source */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; case ADC_INSERTED_CHANNEL: - /* configure ADC inserted group external trigger source */ + /* configure ADC inserted sequence external trigger source */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; @@ -655,56 +656,56 @@ void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channe /*! \brief enable ADC external trigger \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence \param[in] trigger_mode: external trigger mode only one parameter can be selected which is shown as below: - \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable - \arg EXTERNAL_TRIGGER_RISING: rising edge of external trigger - \arg EXTERNAL_TRIGGER_FALLING: falling edge of external trigger - \arg EXTERNAL_TRIGGER_RISING_FALLING: rising and falling edge of external trigger + \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable + \arg EXTERNAL_TRIGGER_RISING: rising edge of external trigger + \arg EXTERNAL_TRIGGER_FALLING: falling edge of external trigger + \arg EXTERNAL_TRIGGER_RISING_FALLING: rising and falling edge of external trigger \param[out] none \retval none */ -void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode) +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t trigger_mode) { - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure ADC regular channel group external trigger mode */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); - ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << REGULAR_TRIGGER_MODE); - break; - case ADC_INSERTED_CHANNEL: - /* configure ADC inserted channel group external trigger mode */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); - ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << INSERTED_TRIGGER_MODE); - break; - default: - break; - } + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* configure ADC routine sequence external trigger mode */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); + ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << ROUTINE_TRIGGER_MODE); + break; + case ADC_INSERTED_CHANNEL: + /* configure ADC inserted sequence external trigger mode */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); + ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << INSERTED_TRIGGER_MODE); + break; + default: + break; + } } /*! \brief enable ADC software trigger \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence \param[out] none \retval none */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group) +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_sequence) { - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* enable ADC regular channel group software trigger */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* enable ADC routine sequence software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; break; case ADC_INSERTED_CHANNEL: - /* enable ADC inserted channel group software trigger */ + /* enable ADC inserted sequence software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; break; default: @@ -717,56 +718,56 @@ void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group \param[in] adc_periph: ADCx,x=0,1,2 \param[in] end_selection: end of conversion mode only one parameter can be selected which is shown as below: - \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of regular conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. - \arg ADC_EOC_SET_CONVERSION: at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically. + \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of routine conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. + \arg ADC_EOC_SET_CONVERSION: at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically. \param[out] none \retval none */ -void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection) +void adc_end_of_conversion_config(uint32_t adc_periph, uint8_t end_selection) { - switch(end_selection){ - case ADC_EOC_SET_SEQUENCE: - /* only at the end of a sequence of regular conversions, the EOC bit is set */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); - break; - case ADC_EOC_SET_CONVERSION: - /* at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically */ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); - break; - default: - break; + switch(end_selection) { + case ADC_EOC_SET_SEQUENCE: + /* only at the end of a sequence of routine conversions, the EOC bit is set */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); + break; + case ADC_EOC_SET_CONVERSION: + /* at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); + break; + default: + break; } } /*! - \brief read ADC regular group data register + \brief read ADC routine data register \param[in] adc_periph: ADCx,x=0,1,2 \param[in] none \param[out] none \retval the conversion value */ -uint16_t adc_regular_data_read(uint32_t adc_periph) +uint16_t adc_routine_data_read(uint32_t adc_periph) { return (uint16_t)(ADC_RDATA(adc_periph)); } /*! - \brief read ADC inserted group data register + \brief read ADC inserted data register \param[in] adc_periph: ADCx,x=0,1,2 \param[in] inserted_channel : insert channel select only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 \param[out] none \retval the conversion value */ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) { uint32_t idata; /* read the data of the selected channel */ - switch(inserted_channel){ + switch(inserted_channel) { case ADC_INSERTED_CHANNEL_0: /* read the data of channel 0 */ idata = ADC_IDATA0(adc_periph); @@ -796,7 +797,7 @@ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) \param[out] none \retval none */ -void adc_watchdog_single_channel_disable(uint32_t adc_periph ) +void adc_watchdog_single_channel_disable(uint32_t adc_periph) { ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDSC); } @@ -806,11 +807,11 @@ void adc_watchdog_single_channel_disable(uint32_t adc_periph ) \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) + \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) \param[out] none \retval none */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel) +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) { ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDCHSEL); @@ -820,31 +821,31 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channe } /*! - \brief configure ADC analog watchdog group channel + \brief configure ADC analog watchdog sequence channel \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog + \param[in] adc_sequence: the sequence use analog watchdog only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence \param[out] none \retval none */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group) +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph, uint8_t adc_sequence) { ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC)); - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* regular channel analog watchdog enable */ + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* routine channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; break; case ADC_INSERTED_CHANNEL: /* inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* regular and inserted channel analog watchdog enable */ + case ADC_ROUTINE_INSERTED_CHANNEL: + /* routine and inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); break; default: @@ -855,28 +856,28 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel /*! \brief disable ADC analog watchdog \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog + \param[in] adc_sequence: the sequence use analog watchdog only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence \param[out] none \retval none */ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) +void adc_watchdog_disable(uint32_t adc_periph, uint8_t adc_sequence) { - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* disable ADC analog watchdog regular channel group */ + /* select the sequence */ + switch(adc_sequence) { + case ADC_ROUTINE_CHANNEL: + /* disable ADC analog watchdog routine sequence */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN); break; case ADC_INSERTED_CHANNEL: - /* disable ADC analog watchdog inserted channel group */ + /* disable ADC analog watchdog inserted sequence */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN); break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* disable ADC analog watchdog regular and inserted channel group */ + case ADC_ROUTINE_INSERTED_CHANNEL: + /* disable ADC analog watchdog routine and inserted sequence */ ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN)); break; default: @@ -892,7 +893,7 @@ void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) \param[out] none \retval none */ -void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold) +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) { /* configure ADC analog watchdog low threshold */ ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); @@ -905,19 +906,19 @@ void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_flag: the adc flag bits only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) { FlagStatus reval = RESET; - if(ADC_STAT(adc_periph) & adc_flag){ + if(ADC_STAT(adc_periph) & adc_flag) { reval = SET; } return reval; @@ -929,16 +930,16 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_flag: the adc flag bits only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence + \arg ADC_FLAG_ROVF: routine data register overflow flag \param[out] none \retval none */ -void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) { ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); } @@ -950,10 +951,10 @@ void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) +FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph) { FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)){ + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)) { reval = SET; } return reval; @@ -969,7 +970,7 @@ FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) { FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)){ + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)) { reval = SET; } return reval; @@ -980,45 +981,45 @@ FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_interrupt: the adc interrupt bits only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) { FlagStatus interrupt_flag = RESET; uint32_t state; /* check the interrupt bits */ - switch(adc_interrupt){ + switch(adc_interrupt) { case ADC_INT_FLAG_WDE: /* get the ADC analog watchdog interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) { + interrupt_flag = SET; } break; case ADC_INT_FLAG_EOC: - /* get the ADC end of group conversion interrupt bits */ + /* get the ADC end of sequence conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { interrupt_flag = SET; - } + } break; case ADC_INT_FLAG_EOIC: - /* get the ADC end of inserted group conversion interrupt bits */ + /* get the ADC end of inserted sequence conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { interrupt_flag = SET; } break; case ADC_INT_FLAG_ROVF: - /* get the ADC regular data register overflow interrupt bits */ + /* get the ADC routine data register overflow interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; - if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state){ - interrupt_flag = SET; + if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) { + interrupt_flag = SET; } break; default: @@ -1032,14 +1033,14 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_interrupt: the adc status flag only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt + \arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt \param[out] none \retval none */ -void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) { ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); } @@ -1049,26 +1050,26 @@ void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_interrupt: the adc interrupt flag only one parameter can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag \param[out] none \retval none */ -void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) { - switch(adc_interrupt){ + switch(adc_interrupt) { case ADC_INT_WDE: /* enable analog watchdog interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; break; case ADC_INT_EOC: - /* enable end of group conversion interrupt */ + /* enable end of sequence conversion interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; break; case ADC_INT_EOIC: - /* enable end of inserted group conversion interrupt */ + /* enable end of inserted sequence conversion interrupt */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; break; case ADC_INT_ROVF: @@ -1084,16 +1085,16 @@ void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_flag: the adc interrupt flag only one parameter can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag + \arg ADC_INT_ROVF: routine data register overflow interrupt flag \param[out] none \retval none */ -void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt) +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) { - switch(adc_interrupt){ + switch(adc_interrupt) { /* select the interrupt source */ case ADC_INT_WDE: ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDEIE); @@ -1116,19 +1117,19 @@ void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt) \brief configure the ADC sync mode \param[in] sync_mode: ADC sync mode only one parameter can be selected which is shown as below: - \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel & inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel & trigger rotation mode - \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode - \arg ADC_DAUL_REGULAL_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode - \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode - \arg ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined regular parallel & inserted parallel mode - \arg ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION: all ADCs work in combined regular parallel & trigger rotation mode - \arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode - \arg ADC_ALL_REGULAL_PARALLEL: all ADCs work in regular parallel mode - \arg ADC_ALL_REGULAL_FOLLOW_UP: all ADCs work in follow-up mode - \arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode + \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined routine parallel & inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined routine parallel & trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL: ADC0 and ADC1 work in routine parallel mode + \arg ADC_DAUL_ROUTINE_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode + \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined routine parallel & inserted parallel mode + \arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION: all ADCs work in combined routine parallel & trigger rotation mode + \arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode + \arg ADC_ALL_ROUTINE_PARALLEL: all ADCs work in routine parallel mode + \arg ADC_ALL_ROUTINE_FOLLOW_UP: all ADCs work in follow-up mode + \arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode \param[out] none \retval none */ @@ -1142,7 +1143,7 @@ void adc_sync_mode_config(uint32_t sync_mode) \brief configure the delay between 2 sampling phases in ADC sync modes \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes only one parameter can be selected which is shown as below: - \arg ADC_SYNC_DELAY_xCYCLE: x=5..20,the delay between 2 sampling phases in ADC sync modes is x ADC clock cycles + \arg ADC_SYNC_DELAY_xCYCLE: x=5..20,the delay between 2 sampling phases in ADC sync modes is x ADC clock cycles \param[out] none \retval none */ @@ -1156,13 +1157,13 @@ void adc_sync_delay_config(uint32_t sample_delay) \brief configure ADC sync DMA mode selection \param[in] dma_mode: ADC sync DMA mode only one parameter can be selected which is shown as below: - \arg ADC_SYNC_DMA_DISABLE: ADC sync DMA disabled - \arg ADC_SYNC_DMA_MODE0: ADC sync DMA mode 0 - \arg ADC_SYNC_DMA_MODE1: ADC sync DMA mode 1 + \arg ADC_SYNC_DMA_DISABLE: ADC sync DMA disabled + \arg ADC_SYNC_DMA_MODE0: ADC sync DMA mode 0 + \arg ADC_SYNC_DMA_MODE1: ADC sync DMA mode 1 \param[out] none \retval none */ -void adc_sync_dma_config(uint32_t dma_mode ) +void adc_sync_dma_config(uint32_t dma_mode) { ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDMA); ADC_SYNCCTL |= dma_mode; @@ -1191,12 +1192,12 @@ void adc_sync_dma_request_after_last_disable(void) } /*! - \brief read ADC sync regular data register + \brief read ADC sync routine data register \param[in] none \param[out] none - \retval sync regular data + \retval sync routine data */ -uint32_t adc_sync_regular_data_read(void) +uint32_t adc_sync_routine_data_read(void) { return (uint32_t)ADC_SYNCDATA; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c index 5eb2974739..09a246217c 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c @@ -7,10 +7,12 @@ \version 2019-11-27, V2.0.1, firmware for GD32F4xx \version 2020-07-14, V2.0.2, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2021-12-28, V2.1.1, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,6 +39,7 @@ OF SUCH DAMAGE. */ #include "gd32f4xx_can.h" +#include #define CAN_ERROR_HANDLE(s) do{}while(1) @@ -66,74 +69,77 @@ void can_deinit(uint32_t can_periph) \arg CAN_FILTER_STRUCT: the CAN filter struct \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct - \param[in] p_struct: the pointer of the specific struct - \param[out] none + \param[out] p_struct: the pointer of the specific struct \retval none */ -void can_struct_para_init(can_struct_type_enum type, void* p_struct) +void can_struct_para_init(can_struct_type_enum type, void *p_struct) { uint8_t i; + if(NULL == p_struct) { + CAN_ERROR_HANDLE("struct parameter can not be NULL \r\n"); + } + /* get type of the struct */ - switch(type){ - /* used for can_init() */ - case CAN_INIT_STRUCT: - ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; - ((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE; - ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; - ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; - ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; - ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; - ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; - ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; - ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; - ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; - ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; + switch(type) { + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct *)p_struct)->auto_retrans = DISABLE; + ((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct *)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct *)p_struct)->rec_fifo_overwrite = DISABLE; + ((can_parameter_struct *)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct *)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct *)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct *)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct *)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct *)p_struct)->working_mode = CAN_NORMAL_MODE; - break; - /* used for can_filter_init() */ - case CAN_FILTER_STRUCT: - ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; - ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; - ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; - ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; - ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct *)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct *)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct *)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct *)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct *)p_struct)->filter_number = 0U; - break; - /* used for can_message_transmit() */ - case CAN_TX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; - } + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_trasnmit_message_struct *)p_struct)->tx_data[i] = 0U; + } - ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; - ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; - ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; - ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; + ((can_trasnmit_message_struct *)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct *)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct *)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct *)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct *)p_struct)->tx_sfid = 0U; - break; - /* used for can_message_receive() */ - case CAN_RX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; - } + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_receive_message_struct *)p_struct)->rx_data[i] = 0U; + } - ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; - ((can_receive_message_struct*)p_struct)->rx_efid = 0U; - ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_receive_message_struct*)p_struct)->rx_fi = 0U; - ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; - ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; + ((can_receive_message_struct *)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct *)p_struct)->rx_efid = 0U; + ((can_receive_message_struct *)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct *)p_struct)->rx_fi = 0U; + ((can_receive_message_struct *)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct *)p_struct)->rx_sfid = 0U; - break; + break; - default: - CAN_ERROR_HANDLE("parameter is invalid \r\n"); + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); } } @@ -149,14 +155,14 @@ void can_struct_para_init(can_struct_type_enum type, void* p_struct) \arg time_triggered: ENABLE or DISABLE \arg auto_bus_off_recovery: ENABLE or DISABLE \arg auto_wake_up: ENABLE or DISABLE - \arg no_auto_retrans: ENABLE or DISABLE + \arg auto_retrans: ENABLE or DISABLE \arg rec_fifo_overwrite: ENABLE or DISABLE \arg trans_fifo_order: ENABLE or DISABLE \arg prescaler: 0x0001 - 0x0400 \param[out] none \retval ErrStatus: SUCCESS or ERROR */ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) { uint32_t timeout = CAN_TIMEOUT; ErrStatus flag = ERROR; @@ -166,64 +172,65 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init /* enable initialize mode */ CAN_CTL(can_periph) |= CAN_CTL_IWMOD; /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } /* check initialize working success */ - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { flag = ERROR; - }else{ + } else { /* set the bit timing register */ CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); + /* time trigger communication mode */ - if(ENABLE == can_parameter_init->time_triggered){ + if(ENABLE == can_parameter_init->time_triggered) { CAN_CTL(can_periph) |= CAN_CTL_TTC; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_TTC; } - /* automatic bus-off managment */ - if(ENABLE == can_parameter_init->auto_bus_off_recovery){ + /* automatic bus-off management */ + if(ENABLE == can_parameter_init->auto_bus_off_recovery) { CAN_CTL(can_periph) |= CAN_CTL_ABOR; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; } /* automatic wakeup mode */ - if(ENABLE == can_parameter_init->auto_wake_up){ + if(ENABLE == can_parameter_init->auto_wake_up) { CAN_CTL(can_periph) |= CAN_CTL_AWU; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_AWU; } - /* automatic retransmission mode disable*/ - if(ENABLE == can_parameter_init->no_auto_retrans){ - CAN_CTL(can_periph) |= CAN_CTL_ARD; - }else{ + /* automatic retransmission mode */ + if(ENABLE == can_parameter_init->auto_retrans) { CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } else { + CAN_CTL(can_periph) |= CAN_CTL_ARD; } - /* receive fifo overwrite mode */ - if(ENABLE == can_parameter_init->rec_fifo_overwrite){ - CAN_CTL(can_periph) |= CAN_CTL_RFOD; - }else{ + /* receive FIFO overwrite mode */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite) { CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; + } else { + CAN_CTL(can_periph) |= CAN_CTL_RFOD; } - /* transmit fifo order */ - if(ENABLE == can_parameter_init->trans_fifo_order){ + /* transmit FIFO order */ + if(ENABLE == can_parameter_init->trans_fifo_order) { CAN_CTL(can_periph) |= CAN_CTL_TFO; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_TFO; } /* disable initialize mode */ CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; timeout = CAN_TIMEOUT; /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } /* check exit initialize mode */ - if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + if(0U != timeout) { flag = SUCCESS; } } @@ -245,7 +252,7 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init \param[out] none \retval none */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init) { uint32_t val = 0U; @@ -256,54 +263,52 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) CAN_FW(CAN0) &= ~(uint32_t)val; /* filter 16 bits */ - if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ + if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits) { /* set filter 16 bits */ CAN_FSCFG(CAN0) &= ~(uint32_t)val; - /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ + /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); } /* filter 32 bits */ - if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ + if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits) { /* set filter 32 bits */ CAN_FSCFG(CAN0) |= (uint32_t)val; /* 32 bits list or first 32 bits list */ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); /* 32 bits mask or second 32 bits list */ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); } /* filter mode */ - if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ + if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode) { /* mask mode */ CAN_FMCFG(CAN0) &= ~(uint32_t)val; - }else{ + } else { /* list mode */ CAN_FMCFG(CAN0) |= (uint32_t)val; } /* filter FIFO */ - if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ + if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) { /* FIFO0 */ CAN_FAFIFO(CAN0) &= ~(uint32_t)val; - } - - if(CAN_FIFO1 == can_filter_parameter_init->filter_fifo_number){ + } else { /* FIFO1 */ CAN_FAFIFO(CAN0) |= (uint32_t)val; } /* filter working */ - if(ENABLE == can_filter_parameter_init->filter_enable){ + if(ENABLE == can_filter_parameter_init->filter_enable) { CAN_FW(CAN0) |= (uint32_t)val; } @@ -313,8 +318,9 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) } /*! - \brief set CAN1 fliter start bank number - \param[in] can1_start_bank_number + \brief set CAN1 filter start bank number + \param[in] start_bank: CAN1 start bank number + only one parameter can be selected which is shown as below: \arg (1..27) \param[out] none \retval none @@ -326,7 +332,7 @@ void can1_filter_start_bank(uint8_t start_bank) /* set CAN1 filter start number */ CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); - /* filter lock enaable */ + /* filter lock enable */ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; } @@ -339,8 +345,10 @@ void can1_filter_start_bank(uint8_t start_bank) */ void can_debug_freeze_enable(uint32_t can_periph) { + /* set DFZ bit */ CAN_CTL(can_periph) |= CAN_CTL_DFZ; - if(CAN0 == can_periph){ + + if(CAN0 == can_periph) { dbg_periph_enable(DBG_CAN0_HOLD); }else{ dbg_periph_enable(DBG_CAN1_HOLD); @@ -356,11 +364,13 @@ void can_debug_freeze_enable(uint32_t can_periph) */ void can_debug_freeze_disable(uint32_t can_periph) { + /* set DFZ bit */ CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; + if(CAN0 == can_periph){ dbg_periph_disable(DBG_CAN0_HOLD); }else{ - dbg_periph_disable(DBG_CAN0_HOLD); + dbg_periph_disable(DBG_CAN1_HOLD); } } @@ -375,10 +385,10 @@ void can_time_trigger_mode_enable(uint32_t can_periph) { uint8_t mailbox_number; - /* enable the tcc mode */ + /* enable the TTC mode */ CAN_CTL(can_periph) |= CAN_CTL_TTC; /* enable time stamp */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; } } @@ -394,16 +404,16 @@ void can_time_trigger_mode_disable(uint32_t can_periph) { uint8_t mailbox_number; - /* disable the TCC mode */ + /* disable the TTC mode */ CAN_CTL(can_periph) &= ~CAN_CTL_TTC; /* reset TSEN bits */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; } } /*! - \brief transmit CAN message + \brief transmit CAN message \param[in] can_periph \arg CANx(x=0,1) \param[in] transmit_message: struct for CAN transmit message @@ -416,49 +426,48 @@ void can_time_trigger_mode_disable(uint32_t can_periph) \param[out] none \retval mailbox_number */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message) { uint8_t mailbox_number = CAN_MAILBOX0; /* select one empty mailbox */ - if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ + if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)) { mailbox_number = CAN_MAILBOX0; - }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ + } else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)) { mailbox_number = CAN_MAILBOX1; - }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ + } else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)) { mailbox_number = CAN_MAILBOX2; - }else{ + } else { mailbox_number = CAN_NOMAILBOX; } /* return no mailbox empty */ - if(CAN_NOMAILBOX == mailbox_number){ + if(CAN_NOMAILBOX == mailbox_number) { return CAN_NOMAILBOX; } CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if(CAN_FF_STANDARD == transmit_message->tx_ff){ + if(CAN_FF_STANDARD == transmit_message->tx_ff) { /* set transmit mailbox standard identifier */ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - }else{ + transmit_message->tx_ft); + } else { /* set transmit mailbox extended identifier */ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); + transmit_message->tx_ff | \ + transmit_message->tx_ft); } /* set the data length */ - transmit_message->tx_dlen &= (uint8_t)(CAN_TMP_DLENC); - CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC); + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; /* set the data */ CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); /* enable transmission */ CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; @@ -481,7 +490,7 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox uint32_t val = 0U; /* check selected mailbox state */ - switch(mailbox_number){ + switch(mailbox_number) { /* mailbox0 */ case CAN_MAILBOX0: val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); @@ -499,34 +508,24 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox break; } - switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): + switch(val) { + /* transmit pending */ + case(CAN_STATE_PENDING): state = CAN_TRANSMIT_PENDING; break; - /* transmit failed */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_TME0): - state = CAN_TRANSMIT_FAILED; - break; - case (CAN_TSTAT_MTF1 | CAN_TSTAT_TME1): - state = CAN_TRANSMIT_FAILED; - break; - case (CAN_TSTAT_MTF2 | CAN_TSTAT_TME2): - state = CAN_TRANSMIT_FAILED; - break; - /* transmit succeeded */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + /* mailbox0 transmit succeeded */ + case(CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): state = CAN_TRANSMIT_OK; break; - /* mailbox1 transmit succeeded */ - case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + /* mailbox1 transmit succeeded */ + case(CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): state = CAN_TRANSMIT_OK; break; - /* mailbox2 transmit succeeded */ - case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + /* mailbox2 transmit succeeded */ + case(CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): state = CAN_TRANSMIT_OK; break; - /* transmit failed */ + /* transmit failed */ default: state = CAN_TRANSMIT_FAILED; break; @@ -546,19 +545,19 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox */ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) { - if(CAN_MAILBOX0 == mailbox_number){ + if(CAN_MAILBOX0 == mailbox_number) { CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) { } - }else if(CAN_MAILBOX1 == mailbox_number){ + } else if(CAN_MAILBOX1 == mailbox_number) { CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) { } - }else if(CAN_MAILBOX2 == mailbox_number){ + } else if(CAN_MAILBOX2 == mailbox_number) { CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) { } - }else{ + } else { /* illegal parameters */ } } @@ -579,14 +578,14 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) \arg rx_fi: 0 - 27 \retval none */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message) { /* get the frame format */ receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); - if(CAN_FF_STANDARD == receive_message->rx_ff){ + if(CAN_FF_STANDARD == receive_message->rx_ff) { /* get standard identifier */ receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); - }else{ + } else { /* get extended identifier */ receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); } @@ -595,7 +594,7 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); /* filtering index */ receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - /* get recevie data length */ + /* get receive data length */ receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); /* receive data */ @@ -609,15 +608,15 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); /* release FIFO */ - if(CAN_FIFO0 == fifo_number){ + if(CAN_FIFO0 == fifo_number) { CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else{ + } else { CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; } } /*! - \brief release FIFO0 + \brief release FIFO \param[in] can_periph \arg CANx(x=0,1) \param[in] fifo_number @@ -628,11 +627,11 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m */ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) { - if(CAN_FIFO0 == fifo_number){ + if(CAN_FIFO0 == fifo_number) { CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else if(CAN_FIFO1 == fifo_number){ + } else if(CAN_FIFO1 == fifo_number) { CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - }else{ + } else { /* illegal parameters */ CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); } @@ -652,13 +651,13 @@ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) { uint8_t val = 0U; - if(CAN_FIFO0 == fifo_number){ + if(CAN_FIFO0 == fifo_number) { /* FIFO0 */ val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); - }else if(CAN_FIFO1 == fifo_number){ + } else if(CAN_FIFO1 == fifo_number) { /* FIFO1 */ val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); - }else{ + } else { /* illegal parameters */ } return val; @@ -682,47 +681,47 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) /* timeout for IWS or also for SLPWS bits */ uint32_t timeout = CAN_TIMEOUT; - if(CAN_MODE_INITIALIZE == working_mode){ + if(CAN_MODE_INITIALIZE == working_mode) { /* disable sleep mode */ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); /* set initialize mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } - }else if(CAN_MODE_NORMAL == working_mode){ + } else if(CAN_MODE_NORMAL == working_mode) { /* enter normal mode */ CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) { timeout--; } - if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ + if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } - }else if(CAN_MODE_SLEEP == working_mode){ + } else if(CAN_MODE_SLEEP == working_mode) { /* disable initialize mode */ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); /* set sleep mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) { timeout--; } - if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } - }else{ + } else { flag = ERROR; } return flag; @@ -743,13 +742,13 @@ ErrStatus can_wakeup(uint32_t can_periph) /* wakeup */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)) { timeout--; } /* check state */ - if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } return flag; @@ -811,62 +810,6 @@ uint8_t can_transmit_error_number_get(uint32_t can_periph) return val; } -/*! - \brief enable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) |= interrupt; -} - -/*! - \brief disable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) &= ~interrupt; -} - /*! \brief get CAN flag state \param[in] can_periph @@ -882,9 +825,9 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) \arg CAN_FLAG_ERRIF: error flag \arg CAN_FLAG_SLPWS: sleep working state \arg CAN_FLAG_IWS: initial working state - \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in Tx FIFO - \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in Tx FIFO - \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in Tx FIFO + \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in TX FIFO + \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in TX FIFO + \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in TX FIFO \arg CAN_FLAG_TME2: transmit mailbox 2 empty \arg CAN_FLAG_TME1: transmit mailbox 1 empty \arg CAN_FLAG_TME0: transmit mailbox 0 empty @@ -913,9 +856,9 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) { /* get flag and interrupt enable state */ - if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ + if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) { return SET; - }else{ + } else { return RESET; } } @@ -953,6 +896,62 @@ void can_flag_clear(uint32_t can_periph, can_flag_enum flag) CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); } +/*! + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + /*! \brief get CAN interrupt flag state \param[in] can_periph @@ -983,28 +982,28 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f uint32_t ret1 = RESET; uint32_t ret2 = RESET; - /* get the staus of interrupt flag */ - if (flag == CAN_INT_FLAG_RFF0) { + /* get the status of interrupt flag */ + if(flag == CAN_INT_FLAG_RFL0) { ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0); - } else if (flag == CAN_INT_FLAG_RFF1) { + } else if(flag == CAN_INT_FLAG_RFL1) { ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1); - } else if (flag == CAN_INT_FLAG_ERRN) { + } else if(flag == CAN_INT_FLAG_ERRN) { ret1 = can_error_get(can_periph); } else { ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); } - /* get the staus of interrupt enale bit */ + /* get the status of interrupt enable bit */ ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); - if(ret1 && ret2){ + if(ret1 && ret2) { return SET; - }else{ + } else { return RESET; } } /*! \brief clear CAN interrupt flag state - \param[in] can_periph + \param[in] can_periph \arg CANx(x=0,1) \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c index bfe79cb9aa..24bf512870 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -38,6 +39,7 @@ OF SUCH DAMAGE. #define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) #define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) + /*! \brief deinit CRC calculation unit \param[in] none @@ -121,7 +123,7 @@ uint32_t crc_single_data_calculate(uint32_t sdata) uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) { uint32_t index; - for(index = 0U; index < size; index++){ + for(index = 0U; index < size; index++) { CRC_DATA = array[index]; } return (CRC_DATA); diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c index ab67c4ad73..4ae5ccde4e 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -45,7 +46,7 @@ OF SUCH DAMAGE. #define CTC_LIMIT_VALUE_OFFSET ((uint32_t)16U) /*! - \brief reset CTC clock trim controller + \brief reset CTC clock trim controller \param[in] none \param[out] none \retval none @@ -58,7 +59,7 @@ void ctc_deinit(void) } /*! - \brief enable CTC trim counter + \brief enable CTC trim counter \param[in] none \param[out] none \retval none @@ -69,7 +70,7 @@ void ctc_counter_enable(void) } /*! - \brief disable CTC trim counter + \brief disable CTC trim counter \param[in] none \param[out] none \retval none @@ -80,7 +81,7 @@ void ctc_counter_disable(void) } /*! - \brief configure the IRC48M trim value + \brief configure the IRC48M trim value \param[in] ctc_trim_value: 8-bit IRC48M trim value \arg 0x00 - 0x3F \param[out] none @@ -95,7 +96,7 @@ void ctc_irc48m_trim_value_config(uint8_t trim_value) } /*! - \brief generate software reference source sync pulse + \brief generate software reference source sync pulse \param[in] none \param[out] none \retval none @@ -106,7 +107,7 @@ void ctc_software_refsource_pulse_generate(void) } /*! - \brief configure hardware automatically trim mode + \brief configure hardware automatically trim mode \param[in] hardmode: only one parameter can be selected which is shown as below: \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable @@ -121,7 +122,7 @@ void ctc_hardware_trim_mode_config(uint32_t hardmode) } /*! - \brief configure reference signal source polarity + \brief configure reference signal source polarity \param[in] polarity: only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge @@ -136,26 +137,11 @@ void ctc_refsource_polarity_config(uint32_t polarity) } /*! - \brief select USBFS or USBHS SOF signal - \param[in] usbsof: - \arg CTC_USBSOFSEL_USBHS: USBHS SOF signal is selected - \arg CTC_USBSOFSEL_USBFS: USBFS SOF signal is selected - \param[out] none - \retval none -*/ -void ctc_usbsof_signal_select(uint32_t usbsof) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_USBSOFSEL); - CTC_CTL1 |= (uint32_t)usbsof; -} - -/*! - \brief select reference signal source + \brief select reference signal source \param[in] refs: only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_GPIO: GPIO is selected \arg CTC_REFSOURCE_LXTAL: LXTAL is selected - \arg CTC_REFSOURCE_USBSOF: USBSOF is selected \param[out] none \retval none */ @@ -166,7 +152,7 @@ void ctc_refsource_signal_select(uint32_t refs) } /*! - \brief configure reference signal source prescaler + \brief configure reference signal source prescaler \param[in] prescaler: only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided @@ -187,7 +173,7 @@ void ctc_refsource_prescaler_config(uint32_t prescaler) } /*! - \brief configure clock trim base limit value + \brief configure clock trim base limit value \param[in] limit_value: 8-bit clock trim base limit value \arg 0x00 - 0xFF \param[out] none @@ -200,7 +186,7 @@ void ctc_clock_limit_value_config(uint8_t limit_value) } /*! - \brief configure CTC counter reload value + \brief configure CTC counter reload value \param[in] reload_value: 16-bit CTC counter reload value \arg 0x0000 - 0xFFFF \param[out] none @@ -213,7 +199,7 @@ void ctc_counter_reload_value_config(uint16_t reload_value) } /*! - \brief read CTC counter capture value when reference sync pulse occurred + \brief read CTC counter capture value when reference sync pulse occurred \param[in] none \param[out] none \retval the 16-bit CTC counter capture value @@ -221,12 +207,12 @@ void ctc_counter_reload_value_config(uint16_t reload_value) uint16_t ctc_counter_capture_value_read(void) { uint16_t capture_value = 0U; - capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> CTC_REFCAP_OFFSET); + capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP) >> CTC_REFCAP_OFFSET); return (capture_value); } /*! - \brief read CTC trim counter direction when reference sync pulse occurred + \brief read CTC trim counter direction when reference sync pulse occurred \param[in] none \param[out] none \retval FlagStatus: SET or RESET @@ -235,15 +221,15 @@ uint16_t ctc_counter_capture_value_read(void) */ FlagStatus ctc_counter_direction_read(void) { - if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ + if(RESET != (CTC_STAT & CTC_STAT_REFDIR)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief read CTC counter reload value + \brief read CTC counter reload value \param[in] none \param[out] none \retval the 16-bit CTC counter reload value @@ -256,7 +242,7 @@ uint16_t ctc_counter_reload_value_read(void) } /*! - \brief read the IRC48M trim value + \brief read the IRC48M trim value \param[in] none \param[out] none \retval the 8-bit IRC48M trim value @@ -269,7 +255,7 @@ uint8_t ctc_irc48m_trim_value_read(void) } /*! - \brief enable the CTC interrupt + \brief enable the CTC interrupt \param[in] interrupt: CTC interrupt enable one or more parameters can be selected which are shown as below: \arg CTC_INT_CKOK: clock trim OK interrupt enable @@ -285,7 +271,7 @@ void ctc_interrupt_enable(uint32_t interrupt) } /*! - \brief disable the CTC interrupt + \brief disable the CTC interrupt \param[in] interrupt: CTC interrupt enable source one or more parameters can be selected which are shown as below: \arg CTC_INT_CKOK: clock trim OK interrupt enable @@ -301,7 +287,7 @@ void ctc_interrupt_disable(uint32_t interrupt) } /*! - \brief get CTC interrupt flag + \brief get CTC interrupt flag \param[in] int_flag: the CTC interrupt flag only one parameter can be selected which is shown as below: \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt @@ -319,24 +305,24 @@ FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) uint32_t interrupt_flag = 0U, intenable = 0U; /* check whether the interrupt is enabled */ - if(RESET != (int_flag & CTC_FLAG_MASK)){ + if(RESET != (int_flag & CTC_FLAG_MASK)) { intenable = CTC_CTL0 & CTC_CTL0_ERRIE; - }else{ + } else { intenable = CTC_CTL0 & int_flag; } /* get interrupt flag status */ interrupt_flag = CTC_STAT & int_flag; - if(interrupt_flag && intenable){ + if(interrupt_flag && intenable) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear CTC interrupt flag + \brief clear CTC interrupt flag \param[in] int_flag: the CTC interrupt flag only one parameter can be selected which is shown as below: \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt @@ -351,15 +337,15 @@ FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) */ void ctc_interrupt_flag_clear(uint32_t int_flag) { - if(RESET != (int_flag & CTC_FLAG_MASK)){ + if(RESET != (int_flag & CTC_FLAG_MASK)) { CTC_INTC |= CTC_INTC_ERRIC; - }else{ + } else { CTC_INTC |= int_flag; } } /*! - \brief get CTC flag + \brief get CTC flag \param[in] flag: the CTC flag only one parameter can be selected which is shown as below: \arg CTC_FLAG_CKOK: clock trim OK flag @@ -374,15 +360,15 @@ void ctc_interrupt_flag_clear(uint32_t int_flag) */ FlagStatus ctc_flag_get(uint32_t flag) { - if(RESET != (CTC_STAT & flag)){ + if(RESET != (CTC_STAT & flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear CTC flag + \brief clear CTC flag \param[in] flag: the CTC flag only one parameter can be selected which is shown as below: \arg CTC_FLAG_CKOK: clock trim OK flag @@ -397,9 +383,9 @@ FlagStatus ctc_flag_get(uint32_t flag) */ void ctc_flag_clear(uint32_t flag) { - if(RESET != (flag & CTC_FLAG_MASK)){ + if(RESET != (flag & CTC_FLAG_MASK)) { CTC_INTC |= CTC_INTC_ERRIC; - }else{ + } else { CTC_INTC |= flag; } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c index 3a5dd52cdd..e92ea25d32 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -61,9 +62,9 @@ void dac_deinit(void) */ void dac_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DEN0; - }else{ + } else { DAC_CTL |= DAC_CTL_DEN1; } } @@ -76,9 +77,9 @@ void dac_enable(uint32_t dac_periph) */ void dac_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DEN0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DEN1; } } @@ -91,9 +92,9 @@ void dac_disable(uint32_t dac_periph) */ void dac_dma_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DDMAEN0; - }else{ + } else { DAC_CTL |= DAC_CTL_DDMAEN1; } } @@ -106,9 +107,9 @@ void dac_dma_enable(uint32_t dac_periph) */ void dac_dma_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DDMAEN0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DDMAEN1; } } @@ -121,9 +122,9 @@ void dac_dma_disable(uint32_t dac_periph) */ void dac_output_buffer_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DBOFF0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DBOFF1; } } @@ -136,9 +137,9 @@ void dac_output_buffer_enable(uint32_t dac_periph) */ void dac_output_buffer_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DBOFF0; - }else{ + } else { DAC_CTL |= DAC_CTL_DBOFF1; } } @@ -152,10 +153,10 @@ void dac_output_buffer_disable(uint32_t dac_periph) uint16_t dac_output_value_get(uint32_t dac_periph) { uint16_t data = 0U; - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* store the DAC0 output value */ data = (uint16_t)DAC0_DO; - }else{ + } else { /* store the DAC1 output value */ data = (uint16_t)DAC1_DO; } @@ -176,8 +177,8 @@ uint16_t dac_output_value_get(uint32_t dac_periph) */ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) { - if(DAC0 == dac_periph){ - switch(dac_align){ + if(DAC0 == dac_periph) { + switch(dac_align) { /* data right 12 bit alignment */ case DAC_ALIGN_12B_R: DAC0_R12DH = data; @@ -193,8 +194,8 @@ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) default: break; } - }else{ - switch(dac_align){ + } else { + switch(dac_align) { /* data right 12 bit alignment */ case DAC_ALIGN_12B_R: DAC1_R12DH = data; @@ -221,9 +222,9 @@ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) */ void dac_trigger_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DTEN0; - }else{ + } else { DAC_CTL |= DAC_CTL_DTEN1; } } @@ -236,9 +237,9 @@ void dac_trigger_enable(uint32_t dac_periph) */ void dac_trigger_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DTEN0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DTEN1; } } @@ -259,13 +260,13 @@ void dac_trigger_disable(uint32_t dac_periph) \param[out] none \retval none */ -void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL0; DAC_CTL |= triggersource; - }else{ + } else { /* configure DAC1 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL1; DAC_CTL |= (triggersource << DAC1_REG_OFFSET); @@ -279,9 +280,9 @@ void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) */ void dac_software_trigger_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_SWT |= DAC_SWT_SWTR0; - }else{ + } else { DAC_SWT |= DAC_SWT_SWTR1; } } @@ -294,9 +295,9 @@ void dac_software_trigger_enable(uint32_t dac_periph) */ void dac_software_trigger_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ + } else { DAC_SWT &= ~DAC_SWT_SWTR1; } } @@ -314,11 +315,11 @@ void dac_software_trigger_disable(uint32_t dac_periph) */ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 wave mode */ DAC_CTL &= ~DAC_CTL_DWM0; DAC_CTL |= wave_mode; - }else{ + } else { /* configure DAC1 wave mode */ DAC_CTL &= ~DAC_CTL_DWM1; DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); @@ -347,11 +348,11 @@ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) */ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= bit_width; - }else{ + } else { /* configure DAC1 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (bit_width << DAC1_REG_OFFSET); @@ -380,11 +381,11 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) */ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= unmask_bits; - }else{ + } else { /* configure DAC1 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); @@ -413,11 +414,11 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) */ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= amplitude; - }else{ + } else { /* configure DAC1 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (amplitude << DAC1_REG_OFFSET); @@ -517,7 +518,7 @@ void dac_concurrent_output_buffer_disable(void) void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) { uint32_t data = 0U; - switch(dac_align){ + switch(dac_align) { /* data right 12b alignment */ case DAC_ALIGN_12B_R: data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; @@ -564,36 +565,6 @@ void dac_concurrent_interrupt_disable(void) DAC_CTL &= (~ctl); } -/*! - \brief enable DAC interrupt(DAC DMA underrun interrupt) - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_interrupt_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDUDRIE0; - }else{ - DAC_CTL |= DAC_CTL_DDUDRIE1; - } -} - -/*! - \brief disable DAC interrupt(DAC DMA underrun interrupt) - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_interrupt_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDUDRIE0; - }else{ - DAC_CTL &= ~DAC_CTL_DDUDRIE1; - } -} - /*! \brief get the specified DAC flag (DAC DMA underrun flag) \param[in] dac_periph: DACx(x = 0,1) @@ -603,14 +574,14 @@ void dac_interrupt_disable(uint32_t dac_periph) FlagStatus dac_flag_get(uint32_t dac_periph) { FlagStatus temp_flag = RESET; - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* check the DMA underrun flag */ - if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)){ + if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)) { temp_flag = SET; } - }else{ + } else { /* check the DMA underrun flag */ - if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)){ + if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)) { temp_flag = SET; } } @@ -625,13 +596,43 @@ FlagStatus dac_flag_get(uint32_t dac_periph) */ void dac_flag_clear(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_STAT |= DAC_STAT_DDUDR0; - }else{ + } else { DAC_STAT |= DAC_STAT_DDUDR1; } } +/*! + \brief enable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_interrupt_enable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DDUDRIE0; + } else { + DAC_CTL |= DAC_CTL_DDUDRIE1; + } +} + +/*! + \brief disable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none + \retval none +*/ +void dac_interrupt_disable(uint32_t dac_periph) +{ + if(DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DDUDRIE0; + } else { + DAC_CTL &= ~DAC_CTL_DDUDRIE1; + } +} + /*! \brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag) \param[in] dac_periph: DACx(x = 0,1) @@ -643,18 +644,18 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) FlagStatus temp_flag = RESET; uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0; ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0; - if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){ + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) { temp_flag = SET; } - }else{ + } else { /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ ddudr_flag = DAC_STAT & DAC_STAT_DDUDR1; ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE1; - if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){ + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) { temp_flag = SET; } } @@ -669,9 +670,9 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) */ void dac_interrupt_flag_clear(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_STAT |= DAC_STAT_DDUDR0; - }else{ + } else { DAC_STAT |= DAC_STAT_DDUDR1; } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c index a408136ea4..992dd592b7 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -39,7 +40,7 @@ OF SUCH DAMAGE. #define DBG_RESET_VAL 0x00000000U /*! - \brief deinitialize the DBG + \brief deinitialize the DBG \param[in] none \param[out] none \retval none @@ -51,7 +52,7 @@ void dbg_deinit(void) } /*! - \brief read DBG_ID code register + \brief read DBG_ID code register \param[in] none \param[out] none \retval DBG_ID code @@ -62,7 +63,7 @@ uint32_t dbg_id_get(void) } /*! - \brief enable low power behavior when the mcu is in debug mode + \brief enable low power behavior when the mcu is in debug mode \param[in] dbg_low_power: this parameter can be any combination of the following values: \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode @@ -77,7 +78,7 @@ void dbg_low_power_enable(uint32_t dbg_low_power) } /*! - \brief disable low power behavior when the mcu is in debug mode + \brief disable low power behavior when the mcu is in debug mode \param[in] dbg_low_power: this parameter can be any combination of the following values: \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode @@ -92,7 +93,7 @@ void dbg_low_power_disable(uint32_t dbg_low_power) } /*! - \brief enable peripheral behavior when the mcu is in debug mode + \brief enable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: dbg_periph_enum only one parameter can be selected which is shown as below: \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted @@ -117,7 +118,6 @@ void dbg_low_power_disable(uint32_t dbg_low_power) \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted - \arg \param[out] none \retval none */ void dbg_periph_enable(dbg_periph_enum dbg_periph) @@ -126,7 +126,7 @@ void dbg_periph_enable(dbg_periph_enum dbg_periph) } /*! - \brief disable peripheral behavior when the mcu is in debug mode + \brief disable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: dbg_periph_enum only one parameter can be selected which is shown as below: \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted @@ -160,7 +160,7 @@ void dbg_periph_disable(dbg_periph_enum dbg_periph) } /*! - \brief enable trace pin assignment + \brief enable trace pin assignment \param[in] none \param[out] none \retval none @@ -171,7 +171,7 @@ void dbg_trace_pin_enable(void) } /*! - \brief disable trace pin assignment + \brief disable trace pin assignment \param[in] none \param[out] none \retval none @@ -181,18 +181,3 @@ void dbg_trace_pin_disable(void) DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN; } -/*! - \brief trace pin mode selection - \param[in] trace_mode: - \arg TRACE_MODE_ASYNC: trace pin used for async mode - \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 - \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 - \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 - \param[out] none - \retval none -*/ -void dbg_trace_pin_mode_set(uint32_t trace_mode) -{ - DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE; - DBG_CTL0 |= trace_mode; -} diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c index a1ddcab384..730410ad2a 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,7 +38,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_dci.h" /*! - \brief DCI deinit + \brief DCI deinit \param[in] none \param[out] none \retval none @@ -49,7 +50,7 @@ void dci_deinit(void) } /*! - \brief initialize DCI registers + \brief initialize DCI registers \param[in] dci_struct: DCI parameter initialization structure members of the structure and the member values are shown as below: capture_mode : DCI_CAPTURE_MODE_CONTINUOUS, DCI_CAPTURE_MODE_SNAPSHOT @@ -62,7 +63,7 @@ void dci_deinit(void) \param[out] none \retval none */ -void dci_init(dci_parameter_struct* dci_struct) +void dci_init(dci_parameter_struct *dci_struct) { uint32_t reg = 0U; /* disable capture function and DCI */ @@ -79,7 +80,7 @@ void dci_init(dci_parameter_struct* dci_struct) } /*! - \brief enable DCI function + \brief enable DCI function \param[in] none \param[out] none \retval none @@ -90,7 +91,7 @@ void dci_enable(void) } /*! - \brief disable DCI function + \brief disable DCI function \param[in] none \param[out] none \retval none @@ -101,7 +102,7 @@ void dci_disable(void) } /*! - \brief enable DCI capture + \brief enable DCI capture \param[in] none \param[out] none \retval none @@ -112,7 +113,7 @@ void dci_capture_enable(void) } /*! - \brief disable DCI capture + \brief disable DCI capture \param[in] none \param[out] none \retval none @@ -123,7 +124,7 @@ void dci_capture_disable(void) } /*! - \brief enable DCI jpeg mode + \brief enable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -134,7 +135,7 @@ void dci_jpeg_enable(void) } /*! - \brief disable DCI jpeg mode + \brief disable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -145,7 +146,7 @@ void dci_jpeg_disable(void) } /*! - \brief enable cropping window function + \brief enable cropping window function \param[in] none \param[out] none \retval none @@ -156,7 +157,7 @@ void dci_crop_window_enable(void) } /*! - \brief disable cropping window function + \brief disable cropping window function \param[in] none \param[out] none \retval none @@ -167,7 +168,7 @@ void dci_crop_window_disable(void) } /*! - \brief configure DCI cropping window + \brief configure DCI cropping window \param[in] start_x: window horizontal start position \param[in] start_y: window vertical start position \param[in] size_width: window horizontal size @@ -177,12 +178,12 @@ void dci_crop_window_disable(void) */ void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height) { - DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y<<16)); - DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height<<16)); + DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y << 16)); + DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height << 16)); } /*! - \brief enable embedded synchronous mode + \brief enable embedded synchronous mode \param[in] none \param[out] none \retval none @@ -193,7 +194,7 @@ void dci_embedded_sync_enable(void) } /*! - \brief disble embedded synchronous mode + \brief disble embedded synchronous mode \param[in] none \param[out] none \retval none @@ -203,7 +204,7 @@ void dci_embedded_sync_disable(void) DCI_CTL &= ~DCI_CTL_ESM; } /*! - \brief config synchronous codes in embedded synchronous mode + \brief config synchronous codes in embedded synchronous mode \param[in] frame_start: frame start code in embedded synchronous mode \param[in] line_start: line start code in embedded synchronous mode \param[in] line_end: line end code in embedded synchronous mode @@ -213,11 +214,11 @@ void dci_embedded_sync_disable(void) */ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) { - DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); + DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); } /*! - \brief config synchronous codes unmask in embedded synchronous mode + \brief config synchronous codes unmask in embedded synchronous mode \param[in] frame_start: frame start code unmask bits in embedded synchronous mode \param[in] line_start: line start code unmask bits in embedded synchronous mode \param[in] line_end: line end code unmask bits in embedded synchronous mode @@ -227,11 +228,11 @@ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line */ void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) { - DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); + DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); } /*! - \brief read DCI data register + \brief read DCI data register \param[in] none \param[out] none \retval data @@ -242,7 +243,7 @@ uint32_t dci_data_read(void) } /*! - \brief get specified flag + \brief get specified flag \param[in] flag: \arg DCI_FLAG_HS: HS line status \arg DCI_FLAG_VS: VS line status @@ -259,23 +260,23 @@ FlagStatus dci_flag_get(uint32_t flag) { uint32_t stat = 0U; - if(flag >> 31){ + if(flag >> 31) { /* get flag status from DCI_STAT1 register */ stat = DCI_STAT1; - }else{ + } else { /* get flag status from DCI_STAT0 register */ stat = DCI_STAT0; } - if(flag & stat){ + if(flag & stat) { return SET; - }else{ + } else { return RESET; } } /*! - \brief enable specified DCI interrupt + \brief enable specified DCI interrupt \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt @@ -291,7 +292,7 @@ void dci_interrupt_enable(uint32_t interrupt) } /*! - \brief disable specified DCI interrupt + \brief disable specified DCI interrupt \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt @@ -307,7 +308,7 @@ void dci_interrupt_disable(uint32_t interrupt) } /*! - \brief clear specified interrupt flag + \brief clear specified interrupt flag \param[in] int_flag: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt @@ -323,7 +324,7 @@ void dci_interrupt_flag_clear(uint32_t int_flag) } /*! - \brief get specified interrupt flag + \brief get specified interrupt flag \param[in] int_flag: \arg DCI_INT_FLAG_EF: end of frame interrupt flag \arg DCI_INT_FLAG_OVR: FIFO overrun interrupt flag @@ -335,9 +336,9 @@ void dci_interrupt_flag_clear(uint32_t int_flag) */ FlagStatus dci_interrupt_flag_get(uint32_t int_flag) { - if(RESET == (DCI_INTF & int_flag)){ + if(RESET == (DCI_INTF & int_flag)) { return RESET; - }else{ + } else { return SET; } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c index d8bd7be2d7..9e528782d0 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c @@ -1,14 +1,14 @@ /*! \file gd32f4xx_dma.c \brief DMA driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -34,14 +34,13 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI OF SUCH DAMAGE. */ - #include "gd32f4xx_dma.h" /* DMA register bit offset */ #define CHXCTL_PERIEN_OFFSET ((uint32_t)25U) /*! - \brief deinitialize DMA a channel registers + \brief deinitialize DMA a channel registers \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel is deinitialized @@ -52,29 +51,29 @@ OF SUCH DAMAGE. void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) { /* disable DMA a channel */ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; /* reset DMA channel registers */ - DMA_CHCTL(dma_periph,channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(dma_periph,channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(dma_periph,channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHM0ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_CHM1ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_CHFCTL(dma_periph,channelx) = DMA_CHFCTL_RESET_VALUE; - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); - }else{ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHM0ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_CHM1ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_CHFCTL(dma_periph, channelx) = DMA_CHFCTL_RESET_VALUE; + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); + } else { channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); } } /*! - \brief initialize the DMA single data mode parameters struct with the default values + \brief initialize the DMA single data mode parameters struct with the default values \param[in] init_struct: the initialization data needed to initialize DMA channel \param[out] none \retval none */ -void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct) +void dma_single_data_para_struct_init(dma_single_data_parameter_struct *init_struct) { /* set the DMA struct with the default values */ init_struct->periph_addr = 0U; @@ -89,12 +88,12 @@ void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_str } /*! - \brief initialize the DMA multi data mode parameters struct with the default values + \brief initialize the DMA multi data mode parameters struct with the default values \param[in] init_struct: the initialization data needed to initialize DMA channel \param[out] none \retval none */ -void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct) +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct *init_struct) { /* set the DMA struct with the default values */ init_struct->periph_addr = 0U; @@ -112,7 +111,7 @@ void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struc } /*! - \brief initialize DMA single data mode + \brief initialize DMA single data mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel is initialized @@ -130,54 +129,54 @@ void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struc \param[out] none \retval none */ -void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct) +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct *init_struct) { uint32_t ctl; /* select single data mode */ - DMA_CHFCTL(dma_periph,channelx) &= ~DMA_CHXFCTL_MDMEN; + DMA_CHFCTL(dma_periph, channelx) &= ~DMA_CHXFCTL_MDMEN; /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; + DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr; /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct->number; + DMA_CHCNT(dma_periph, channelx) = init_struct->number; /* configure peripheral and memory transfer width,channel priotity,transfer mode */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM); ctl |= (init_struct->periph_memory_width | (init_struct->periph_memory_width << 2) | init_struct->priority | init_struct->direction); - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; } /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; } } /*! - \brief initialize DMA multi data mode + \brief initialize DMA multi data mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel is initialized @@ -199,54 +198,55 @@ void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, d \param[out] none \retval none */ -void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct) +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct *init_struct) { uint32_t ctl; /* select multi data mode and configure FIFO critical value */ - DMA_CHFCTL(dma_periph,channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value); + DMA_CHFCTL(dma_periph, channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value); /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; + DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; + DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr; /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct->number; + DMA_CHCNT(dma_periph, channelx) = init_struct->number; /* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST); - ctl |= (init_struct->periph_width | (init_struct->memory_width ) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | init_struct->periph_burst_width); - DMA_CHCTL(dma_periph,channelx) = ctl; + ctl |= (init_struct->periph_width | (init_struct->memory_width) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | + init_struct->periph_burst_width); + DMA_CHCTL(dma_periph, channelx) = ctl; /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; } /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; } } /*! - \brief set DMA peripheral base address + \brief set DMA peripheral base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set peripheral base address @@ -257,11 +257,11 @@ void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dm */ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { - DMA_CHPADDR(dma_periph,channelx) = address; + DMA_CHPADDR(dma_periph, channelx) = address; } /*! - \brief set DMA Memory0 base address + \brief set DMA Memory0 base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set Memory base address @@ -273,15 +273,15 @@ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, u */ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address) { - if(memory_flag){ - DMA_CHM1ADDR(dma_periph,channelx) = address; - }else{ - DMA_CHM0ADDR(dma_periph,channelx) = address; + if(memory_flag) { + DMA_CHM1ADDR(dma_periph, channelx) = address; + } else { + DMA_CHM0ADDR(dma_periph, channelx) = address; } } /*! - \brief set the number of remaining data to be transferred by the DMA + \brief set the number of remaining data to be transferred by the DMA \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set number @@ -292,11 +292,11 @@ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, u */ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) { - DMA_CHCNT(dma_periph,channelx) = number; + DMA_CHCNT(dma_periph, channelx) = number; } /*! - \brief get the number of remaining data to be transferred by the DMA + \brief get the number of remaining data to be transferred by the DMA \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set number @@ -306,11 +306,11 @@ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, */ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) { - return (uint32_t)DMA_CHCNT(dma_periph,channelx); + return (uint32_t)DMA_CHCNT(dma_periph, channelx); } /*! - \brief configure priority level of DMA channel + \brief configure priority level of DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -328,15 +328,15 @@ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_ { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PRIO; ctl |= priority; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief configure transfer burst beats of memory + \brief configure transfer burst beats of memory \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -349,19 +349,19 @@ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_ \param[out] none \retval none */ -void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat) +void dma_memory_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat) { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_MBURST; ctl |= mbeat; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief configure transfer burst beats of peripheral + \brief configure transfer burst beats of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -375,19 +375,19 @@ void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channe \param[out] none \retval none */ -void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat) +void dma_periph_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat) { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PBURST; ctl |= pbeat; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief configure transfer data size of memory + \brief configure transfer data size of memory \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -404,15 +404,15 @@ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_MWIDTH; ctl |= msize; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief configure transfer data size of peripheral + \brief configure transfer data size of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -425,19 +425,19 @@ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin \param[out] none \retval none */ -void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize) +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize) { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PWIDTH; ctl |= psize; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief configure memory address generation generation_algorithm + \brief configure memory address generation generation_algorithm \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -451,15 +451,15 @@ void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, ui */ void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) { - if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; + if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } } /*! - \brief configure peripheral address generation_algorithm + \brief configure peripheral address generation_algorithm \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -474,18 +474,18 @@ void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum */ void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) { - if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; + if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF; } } /*! - \brief enable DMA circulation mode + \brief enable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -495,11 +495,11 @@ void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_e */ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) { - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; } /*! - \brief disable DMA circulation mode + \brief disable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -509,11 +509,11 @@ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) */ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) { - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; } /*! - \brief enable DMA channel + \brief enable DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -523,11 +523,11 @@ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) */ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) { - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CHEN; + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; } /*! - \brief disable DMA channel + \brief disable DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -537,11 +537,11 @@ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) */ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) { - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; } /*! - \brief configure the direction of data transfer on the channel + \brief configure the direction of data transfer on the channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -558,16 +558,16 @@ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channel { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_TM; ctl |= direction; - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief DMA switch buffer mode config + \brief DMA switch buffer mode config \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -580,17 +580,17 @@ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channel void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select) { /* configure memory1 base address */ - DMA_CHM1ADDR(dma_periph,channelx) = memory1_addr; + DMA_CHM1ADDR(dma_periph, channelx) = memory1_addr; - if(DMA_MEMORY_0 == memory_select){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MBS; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MBS; + if(DMA_MEMORY_0 == memory_select) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MBS; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MBS; } } /*! - \brief DMA using memory get + \brief DMA using memory get \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -600,15 +600,15 @@ void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channel */ uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx) { - if((DMA_CHCTL(dma_periph,channelx)) & DMA_CHXCTL_MBS){ + if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS) { return DMA_MEMORY_1; - }else{ + } else { return DMA_MEMORY_0; } } /*! - \brief DMA channel peripheral select + \brief DMA channel peripheral select \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -622,16 +622,16 @@ void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum chan { uint32_t ctl; /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); + ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PERIEN; ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET); - DMA_CHCTL(dma_periph,channelx) = ctl; + DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief DMA flow controller configure + \brief DMA flow controller configure \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -645,15 +645,15 @@ void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum chan */ void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller) { - if(DMA_FLOW_CONTROLLER_DMA == controller){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_TFCS; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_TFCS; + if(DMA_FLOW_CONTROLLER_DMA == controller) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_TFCS; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_TFCS; } } /*! - \brief DMA switch buffer mode enable + \brief DMA switch buffer mode enable \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -664,17 +664,17 @@ void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, */ void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue) { - if(ENABLE == newvalue){ + if(ENABLE == newvalue) { /* switch buffer mode enable */ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_SBMEN; - }else{ + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_SBMEN; + } else { /* switch buffer mode disable */ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_SBMEN; + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_SBMEN; } } /*! - \brief DMA FIFO status get + \brief DMA FIFO status get \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel @@ -684,11 +684,11 @@ void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channel */ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx) { - return (DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FCNT); + return (DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FCNT); } /*! - \brief get DMA flag is set or not + \brief get DMA flag is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get flag @@ -705,24 +705,24 @@ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx) */ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { - if(channelx < DMA_CH4){ - if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ + if(channelx < DMA_CH4) { + if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { return SET; - }else{ + } else { return RESET; } - }else{ + } else { channelx -= (dma_channel_enum)4; - if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ + if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { return SET; - }else{ + } else { return RESET; } } } /*! - \brief clear DMA a channel flag + \brief clear DMA a channel flag \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get flag @@ -739,16 +739,66 @@ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t */ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag,channelx); - }else{ + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag, channelx); + } else { channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag,channelx); + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag, channelx); } } /*! - \brief get DMA interrupt flag is set or not + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to enbale + only one parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source) { + DMA_CHCTL(dma_periph, channelx) |= source; + } else { + DMA_CHFCTL(dma_periph, channelx) |= source; + } +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to disbale + only one parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source) { + DMA_CHCTL(dma_periph, channelx) &= ~source; + } else { + DMA_CHFCTL(dma_periph, channelx) &= ~source; + } +} + +/*! + \brief get DMA interrupt flag is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get interrupt flag @@ -765,70 +815,70 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla */ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) { - uint32_t interrupt_enable = 0U,interrupt_flag = 0U; + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; dma_channel_enum channel_flag_offset = channelx; - if(channelx < DMA_CH4){ - switch(interrupt){ + if(channelx < DMA_CH4) { + switch(interrupt) { case DMA_INTF_FEEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; break; case DMA_INTF_SDEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; break; case DMA_INTF_TAEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; break; case DMA_INTF_HTFIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; break; case DMA_INTF_FTFIF: - interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx)); - interrupt_enable = (DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE); + interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx)); + interrupt_enable = (DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE); break; default: break; } - }else{ + } else { channel_flag_offset -= (dma_channel_enum)4; - switch(interrupt){ + switch(interrupt) { case DMA_INTF_FEEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; break; case DMA_INTF_SDEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; break; case DMA_INTF_TAEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; break; case DMA_INTF_HTFIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; break; case DMA_INTF_FTFIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE; + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; break; default: break; } } - if(interrupt_flag && interrupt_enable){ + if(interrupt_flag && interrupt_enable) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear DMA a channel interrupt flag + \brief clear DMA a channel interrupt flag \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to clear interrupt flag @@ -845,61 +895,10 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx */ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) { - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); - }else{ + if(channelx < DMA_CH4) { + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx); + } else { channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx); } } - -/*! - \brief enable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] source: specify which interrupt to enbale - one or more parameters can be selected which are shown as below: - \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable - \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable - \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable - \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable - \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable - \param[out] none - \retval none -*/ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(DMA_CHXFCTL_FEEIE != source){ - DMA_CHCTL(dma_periph,channelx) |= source; - }else{ - DMA_CHFCTL(dma_periph,channelx) |= source; - } -} - -/*! - \brief disable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] source: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable - \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable - \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable - \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable - \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable - \param[out] none - \retval none -*/ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(DMA_CHXFCTL_FEEIE != source){ - DMA_CHCTL(dma_periph,channelx) &= ~source; - }else{ - DMA_CHFCTL(dma_periph,channelx) &= ~source; - } -} - diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c index 456e476fd8..ba17638266 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c @@ -5,11 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,10 +57,10 @@ uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive bu uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ #elif defined (__GNUC__) /* GNU Compiler */ -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */ -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */ -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */ -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__((aligned(4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__((aligned(4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET transmit buffer */ #endif /* __CC_ARM */ @@ -73,19 +73,20 @@ enet_descriptors_struct *dma_current_ptp_txdesc = NULL; enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; /* init structure parameters for ENET initialization */ -static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +static enet_initpara_struct enet_initpara = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static uint32_t enet_unknow_err = 0U; /* array of register offset for debug information get */ static const uint16_t enet_reg_tab[] = { -0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, -0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, + 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, + 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, + 0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, -0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, -0x104C, 0x1050, 0x1054}; + 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, + 0x104C, 0x1050, 0x1054 +}; /* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ static void enet_default_init(void); @@ -101,7 +102,7 @@ static void enet_delay(uint32_t ncount); /*! - \brief deinitialize the ENET, and reset structure parameters for ENET initialization + \brief deinitialize the ENET, and reset structure parameters for ENET initialization \param[in] none \param[out] none \retval none @@ -114,7 +115,7 @@ void enet_deinit(void) } /*! - \brief configure the parameters which are usually less cared for initialization + \brief configure the parameters which are usually less cared for initialization note -- this function must be called before enet_init(), otherwise configuration will be no effect \param[in] option: different function option, which is related to several parameters, refer to enet_option_enum @@ -183,7 +184,15 @@ void enet_deinit(void) ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; - - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . + - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE ; + - ENET_ACTIVE_THRESHOLD_256BYTES/ ENET_ACTIVE_THRESHOLD_512BYTES ; + - ENET_ACTIVE_THRESHOLD_768BYTES/ ENET_ACTIVE_THRESHOLD_1024BYTES ; + - ENET_ACTIVE_THRESHOLD_1280BYTES/ ENET_ACTIVE_THRESHOLD_1536BYTES ; + - ENET_ACTIVE_THRESHOLD_1792BYTES ; + - ENET_DEACTIVE_THRESHOLD_256BYTES/ ENET_DEACTIVE_THRESHOLD_512BYTES ; + - ENET_DEACTIVE_THRESHOLD_768BYTES/ ENET_DEACTIVE_THRESHOLD_1024BYTES ; + - ENET_DEACTIVE_THRESHOLD_1280BYTES/ ENET_DEACTIVE_THRESHOLD_1536BYTES ; + - ENET_DEACTIVE_THRESHOLD_1792BYTES . HASHH_OPTION related parameters: - 0x0~0xFFFF FFFFU HASHL_OPTION related parameters: @@ -218,7 +227,7 @@ void enet_deinit(void) */ void enet_initpara_config(enet_option_enum option, uint32_t para) { - switch(option){ + switch(option) { case FORWARD_OPTION: /* choose to configure forward_frame, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; @@ -300,7 +309,7 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) } /*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared + \brief initialize ENET peripheral with generally concerned parameters and the less cared parameters \param[in] mediamode: PHY mode and mac loopback configurations, refer to enet_mediamode_enum only one parameter can be selected which is shown as below @@ -327,16 +336,16 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) */ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) { - uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; + uint32_t reg_value = 0U, reg_temp = 0U, temp = 0U; uint32_t media_temp = 0U; uint32_t timeout = 0U; uint16_t phy_value = 0U; - ErrStatus phy_state= ERROR, enet_state = ERROR; + ErrStatus phy_state = ERROR, enet_state = ERROR; /* PHY interface configuration, configure SMI clock and reset PHY chip */ - if(ERROR == enet_phy_config()){ + if(ERROR == enet_phy_config()) { _ENET_DELAY_(PHY_RESETDELAY); - if(ERROR == enet_phy_config()){ + if(ERROR == enet_phy_config()) { return enet_state; } } @@ -346,15 +355,15 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* 1st, configure mediamode */ media_temp = (uint32_t)mediamode; /* if is PHY auto negotiation */ - if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ + if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp) { /* wait for PHY_LINKED_STATUS bit be set */ - do{ + do { enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); phy_value &= PHY_LINKED_STATUS; timeout++; - }while((RESET == phy_value) && (timeout < PHY_READ_TO)); + } while((RESET == phy_value) && (timeout < PHY_READ_TO)); /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ + if(PHY_READ_TO == timeout) { return enet_state; } /* reset timeout counter */ @@ -363,19 +372,19 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* enable auto-negotiation */ phy_value = PHY_AUTONEGOTIATION; phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ + if(!phy_state) { /* return ERROR due to write timeout */ return enet_state; } /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ - do{ + do { enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); phy_value &= PHY_AUTONEGO_COMPLETE; timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + } while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ + if(PHY_READ_TO == timeout) { return enet_state; } /* reset timeout counter */ @@ -384,22 +393,22 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* read the result of the auto-negotiation */ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); /* configure the duplex mode of MAC following the auto-negotiation result */ - if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ + if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)) { media_temp = ENET_MODE_FULLDUPLEX; - }else{ + } else { media_temp = ENET_MODE_HALFDUPLEX; } /* configure the communication speed of MAC following the auto-negotiation result */ - if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ + if((uint16_t)RESET != (phy_value & PHY_SPEED_STATUS)) { media_temp |= ENET_SPEEDMODE_10M; - }else{ + } else { media_temp |= ENET_SPEEDMODE_100M; } - }else{ + } else { phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ + if(!phy_state) { /* return ERROR due to write timeout */ return enet_state; } @@ -409,13 +418,13 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* after configuring the PHY, use mediamode to configure registers */ reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); + reg_value &= (~(ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM | ENET_MAC_CFG_LBM)); reg_value |= media_temp; ENET_MAC_CFG = reg_value; /* 2st, configure checksum */ - if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ + if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)) { ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; reg_value = ENET_DMA_CTL; @@ -430,13 +439,13 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* 4th, configure different function options */ /* configure forward_frame related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)) { reg_temp = enet_initpara.forward_frame; reg_value = ENET_MAC_CFG; temp = reg_temp; /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_TFCD |ENET_MAC_CFG_APCD)); + reg_value &= (~(ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD)); temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); reg_value |= temp; ENET_MAC_CFG = reg_value; @@ -444,37 +453,37 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum reg_value = ENET_DMA_CTL; temp = reg_temp; /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); - temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); + reg_value &= (~(ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)); + temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF) << 2); reg_value |= (temp >> 2); ENET_DMA_CTL = reg_value; } /* configure dmabus_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)) { temp = enet_initpara.dmabus_mode; reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ - |ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); + | ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); reg_value |= temp; ENET_DMA_BCTL = reg_value; } /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)) { temp = enet_initpara.dma_maxburst; reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value &= ~(ENET_DMA_BCTL_RXDP | ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); reg_value |= temp; ENET_DMA_BCTL = reg_value; } /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)) { temp = enet_initpara.dma_arbitration; reg_value = ENET_DMA_BCTL; @@ -485,24 +494,24 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)) { temp = enet_initpara.store_forward_mode; reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ - reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD | ENET_DMA_CTL_RTHC | ENET_DMA_CTL_TTHC); reg_value |= temp; ENET_DMA_CTL = reg_value; } /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)) { reg_temp = enet_initpara.dma_function; reg_value = ENET_DMA_CTL; temp = reg_temp; /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); + reg_value &= (~(ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF)); temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); reg_value |= temp; ENET_DMA_CTL = reg_value; @@ -517,7 +526,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)) { reg_temp = enet_initpara.vlan_config; reg_value = ENET_MAC_VLT; @@ -528,65 +537,65 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)) { reg_temp = enet_initpara.flow_control; reg_value = ENET_MAC_FCTL; temp = reg_temp; /* configure ENET_MAC_FCTL register */ - reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); + reg_value &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); reg_value |= temp; ENET_MAC_FCTL = reg_value; reg_value = ENET_MAC_FCTH; temp = reg_temp; /* configure ENET_MAC_FCTH register */ - reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); - temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); + reg_value &= ~(ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD) << 8); reg_value |= (temp >> 8); ENET_MAC_FCTH = reg_value; } /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)) { ENET_MAC_HLH = enet_initpara.hashtable_high; } /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)) { ENET_MAC_HLL = enet_initpara.hashtable_low; } /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)) { reg_temp = enet_initpara.framesfilter_mode; reg_value = ENET_MAC_FRMF; /* configure ENET_MAC_FRMF register */ reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ - | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ - | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); reg_value |= reg_temp; ENET_MAC_FRMF = reg_value; } /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)) { reg_temp = enet_initpara.halfduplex_param; reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ - | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); reg_value |= reg_temp; ENET_MAC_CFG = reg_value; } /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)) { reg_temp = enet_initpara.timer_config; reg_value = ENET_MAC_CFG; @@ -597,7 +606,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)) { reg_temp = enet_initpara.interframegap; reg_value = ENET_MAC_CFG; @@ -612,7 +621,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /*! - \brief reset all core internal registers located in CLK_TX and CLK_RX + \brief reset all core internal registers located in CLK_TX and CLK_RX \param[in] none \param[out] none \retval ErrStatus: SUCCESS or ERROR @@ -627,13 +636,13 @@ ErrStatus enet_software_reset(void) ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; /* wait for reset operation complete */ - do{ + do { dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); timeout++; - }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + } while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); /* reset operation complete */ - if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ + if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)) { enet_state = SUCCESS; } @@ -641,7 +650,7 @@ ErrStatus enet_software_reset(void) } /*! - \brief check receive frame valid and return frame size + \brief check receive frame valid and return frame size \param[in] none \param[out] none \retval size of received frame: 0x0 - 0x3FFF @@ -655,14 +664,14 @@ uint32_t enet_rxframe_size_get(void) status = dma_current_rxdesc->status; /* if the desciptor is owned by DMA */ - if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ + if((uint32_t)RESET != (status & ENET_RDES0_DAV)) { return 0U; } /* if has any error, or the frame uses two or more descriptors */ if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || - (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || - (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))) { /* drop current receive frame */ enet_rxframe_drop(); @@ -671,37 +680,37 @@ uint32_t enet_rxframe_size_get(void) #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE /* if is an ethernet-type frame, and IP frame payload error occurred */ if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && - ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)){ - /* drop current receive frame */ - enet_rxframe_drop(); + ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)) { + /* drop current receive frame */ + enet_rxframe_drop(); return 1U; } #else /* if is an ethernet-type frame, and IP frame payload error occurred */ if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && - (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ - /* drop current receive frame */ - enet_rxframe_drop(); + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))) { + /* drop current receive frame */ + enet_rxframe_drop(); return 1U; } #endif /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && - (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))) { /* get the size of the received data including CRC */ size = GET_RDES0_FRML(status); /* substract the CRC size */ size = size - 4U; /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))){ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))) { size = size + 4U; } - }else{ + } else { enet_unknow_err++; enet_rxframe_drop(); @@ -713,7 +722,7 @@ uint32_t enet_rxframe_size_get(void) } /*! - \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode + \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors @@ -729,7 +738,7 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) uint8_t *buf; /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; @@ -742,7 +751,7 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; @@ -763,7 +772,7 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) dma_current_ptp_txdesc = NULL; /* configure each descriptor */ - for(num=0U; num < count; num++){ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; @@ -773,10 +782,10 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ + } else { /* when it is the last descriptor, the next descriptor address equals to first descriptor address in descriptor table */ desc->buffer2_next_desc_addr = (uint32_t) desc_tab; @@ -785,7 +794,7 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) } /*! - \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode + \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors @@ -806,7 +815,7 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; @@ -816,7 +825,7 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; @@ -829,7 +838,7 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - /* configure DMA Rx descriptor table address register */ + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; } @@ -837,7 +846,7 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) dma_current_ptp_txdesc = NULL; /* configure each descriptor */ - for(num=0U; num < count; num++){ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; @@ -847,11 +856,11 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } @@ -860,7 +869,7 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) } /*! - \brief handle current received frame data to application buffer + \brief handle current received frame data to application buffer \param[in] bufsize: the size of buffer which is the parameter in function \param[out] buffer: pointer to the received frame data note -- if the input is NULL, user should copy data in application by himself @@ -871,37 +880,37 @@ ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) uint32_t offset = 0U, size = 0U; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { return ERROR; } /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* if no error occurs, and the frame uses only one descriptor */ if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status); size = size - 4U; /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { size = size + 4U; } /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ + if(size > bufsize) { return ERROR; } /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offsetbuffer1_addr) + offset)); + for(offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); } - }else{ + } else { /* return ERROR */ return ERROR; } @@ -910,7 +919,7 @@ ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) dma_current_rxdesc->status = ENET_RDES0_DAV; /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { /* clear RBU flag */ ENET_DMA_STAT = ENET_DMA_STAT_RBU; /* resume DMA reception by writing to the RPEN register*/ @@ -919,16 +928,16 @@ ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } } @@ -936,7 +945,7 @@ ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) } /*! - \brief handle application buffer data to transmit it + \brief handle application buffer data to transmit it \param[in] buffer: pointer to the frame data to be transmitted, note -- if the input is NULL, user should handle the data in application by himself \param[in] length: the length of frame data to be transmitted @@ -949,20 +958,20 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) uint32_t dma_tbu_flag, dma_tu_flag; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { return ERROR; } /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ + if(length > ENET_MAX_FRAME_SIZE) { return ERROR; } /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } @@ -977,7 +986,7 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ @@ -986,16 +995,16 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } } @@ -1003,7 +1012,7 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) } /*! - \brief configure the transmit IP frame checksum offload calculation and insertion + \brief configure the transmit IP frame checksum offload calculation and insertion \param[in] desc: the descriptor pointer which users want to configure, refer to enet_descriptors_struct \param[in] checksum: IP frame checksum configuration only one parameter can be selected which is shown as below @@ -1021,7 +1030,7 @@ void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t check } /*! - \brief ENET Tx and Rx function enable (include MAC and DMA module) + \brief ENET Tx and Rx function enable (include MAC and DMA module) \param[in] none \param[out] none \retval none @@ -1033,7 +1042,7 @@ void enet_enable(void) } /*! - \brief ENET Tx and Rx function disable (include MAC and DMA module) + \brief ENET Tx and Rx function disable (include MAC and DMA module) \param[in] none \param[out] none \retval none @@ -1045,7 +1054,7 @@ void enet_disable(void) } /*! - \brief configure MAC address + \brief configure MAC address \param[in] mac_addr: select which MAC address will be set, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: set MAC address 0 filter @@ -1064,7 +1073,7 @@ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get MAC address + \brief get MAC address \param[in] mac_addr: select which MAC address will be get, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: get MAC address 0 filter @@ -1086,7 +1095,7 @@ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get the ENET MAC/MSC/PTP/DMA status flag + \brief get the ENET MAC/MSC/PTP/DMA status flag \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, only one parameter can be selected which is shown as below \arg ENET_MAC_FLAG_MPKR: magic packet received flag @@ -1131,15 +1140,15 @@ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) */ FlagStatus enet_flag_get(enet_flag_enum enet_flag) { - if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ + if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear the ENET DMA status flag + \brief clear the ENET DMA status flag \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum only one parameter can be selected which is shown as below \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear @@ -1167,7 +1176,7 @@ void enet_flag_clear(enet_flag_clear_enum enet_flag) } /*! - \brief enable ENET MAC/MSC/DMA interrupt + \brief enable ENET MAC/MSC/DMA interrupt \param[in] enet_int: ENET interrupt,, refer to enet_int_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask @@ -1198,17 +1207,17 @@ void enet_flag_clear(enet_flag_clear_enum enet_flag) */ void enet_interrupt_enable(enet_int_enum enet_int) { - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { /* ENET_DMA_INTEN register interrupt */ ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - }else{ + } else { /* other INTMSK register interrupt */ ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); } } /*! - \brief disable ENET MAC/MSC/DMA interrupt + \brief disable ENET MAC/MSC/DMA interrupt \param[in] enet_int: ENET interrupt, refer to enet_int_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask @@ -1239,17 +1248,17 @@ void enet_interrupt_enable(enet_int_enum enet_int) */ void enet_interrupt_disable(enet_int_enum enet_int) { - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { /* ENET_DMA_INTEN register interrupt */ ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - }else{ + } else { /* other INTMSK register interrupt */ ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); } } /*! - \brief get ENET MAC/MSC/DMA interrupt flag + \brief get ENET MAC/MSC/DMA interrupt flag \param[in] int_flag: ENET interrupt flag, refer to enet_int_flag_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_FLAG_WUM: WUM status flag @@ -1286,15 +1295,15 @@ void enet_interrupt_disable(enet_int_enum enet_int) */ FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) { - if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ + if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear ENET DMA interrupt flag + \brief clear ENET DMA interrupt flag \param[in] int_flag_clear: clear ENET interrupt flag, refer to enet_int_flag_clear_enum only one parameter can be selected which is shown as below \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag @@ -1322,7 +1331,7 @@ void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) } /*! - \brief ENET Tx function enable (include MAC and DMA module) + \brief ENET Tx function enable (include MAC and DMA module) \param[in] none \param[out] none \retval none @@ -1335,7 +1344,7 @@ void enet_tx_enable(void) } /*! - \brief ENET Tx function disable (include MAC and DMA module) + \brief ENET Tx function disable (include MAC and DMA module) \param[in] none \param[out] none \retval none @@ -1348,7 +1357,7 @@ void enet_tx_disable(void) } /*! - \brief ENET Rx function enable (include MAC and DMA module) + \brief ENET Rx function enable (include MAC and DMA module) \param[in] none \param[out] none \retval none @@ -1360,7 +1369,7 @@ void enet_rx_enable(void) } /*! - \brief ENET Rx function disable (include MAC and DMA module) + \brief ENET Rx function disable (include MAC and DMA module) \param[in] none \param[out] none \retval none @@ -1372,7 +1381,7 @@ void enet_rx_disable(void) } /*! - \brief put registers value into the application buffer + \brief put registers value into the application buffer \param[in] type: register type which will be get, refer to enet_registers_type_enum, only one parameter can be selected which is shown as below \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH @@ -1389,14 +1398,14 @@ void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t offset = (uint32_t)type; max = (uint32_t)type + num; - limit = sizeof(enet_reg_tab)/sizeof(uint16_t); + limit = sizeof(enet_reg_tab) / sizeof(uint16_t); /* prevent element in this array is out of range */ - if(max > limit){ + if(max > limit) { max = limit; } - for(; offset < max; offset++){ + for(; offset < max; offset++) { /* get value of the corresponding register */ *preg = REG32((ENET) + enet_reg_tab[offset]); preg++; @@ -1404,7 +1413,7 @@ void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t } /*! - \brief get the enet debug status from the debug register + \brief get the enet debug status from the debug register \param[in] mac_debug: enet debug status only one parameter can be selected which is shown as below \arg ENET_MAC_RECEIVER_NOT_IDLE: MAC receiver is not in idle state @@ -1426,7 +1435,7 @@ uint32_t enet_debug_status_get(uint32_t mac_debug) { uint32_t temp_state = 0U; - switch(mac_debug){ + switch(mac_debug) { case ENET_RX_ASYNCHRONOUS_FIFO_STATE: temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); break; @@ -1443,7 +1452,7 @@ uint32_t enet_debug_status_get(uint32_t mac_debug) temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); break; default: - if(RESET != (ENET_MAC_DBG & mac_debug)){ + if(RESET != (ENET_MAC_DBG & mac_debug)) { temp_state = 0x1U; } break; @@ -1452,7 +1461,7 @@ uint32_t enet_debug_status_get(uint32_t mac_debug) } /*! - \brief enable the MAC address filter + \brief enable the MAC address filter \param[in] mac_addr: select which MAC address will be enable, refer to enet_macaddress_enum \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter @@ -1466,7 +1475,7 @@ void enet_address_filter_enable(enet_macaddress_enum mac_addr) } /*! - \brief disable the MAC address filter + \brief disable the MAC address filter \param[in] mac_addr: select which MAC address will be disable, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter @@ -1481,7 +1490,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) } /*! - \brief configure the MAC address filter + \brief configure the MAC address filter \param[in] mac_addr: select which MAC address will be configured, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter @@ -1516,7 +1525,7 @@ void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mas } /*! - \brief PHY interface configuration (configure SMI clock and reset PHY chip) + \brief PHY interface configuration (configure SMI clock and reset PHY chip) \param[in] none \param[out] none \retval ErrStatus: SUCCESS or ERROR @@ -1536,36 +1545,36 @@ ErrStatus enet_phy_config(void) ahbclk = rcu_clock_freq_get(CK_AHB); /* configure MDC clock according to HCLK frequency range */ - if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ + if(ENET_RANGE(ahbclk, 20000000U, 35000000U)) { reg |= ENET_MDC_HCLK_DIV16; - }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ + } else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)) { reg |= ENET_MDC_HCLK_DIV26; - }else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)){ + } else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)) { reg |= ENET_MDC_HCLK_DIV42; - }else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)){ + } else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)) { reg |= ENET_MDC_HCLK_DIV62; - }else if((ENET_RANGE(ahbclk, 150000000U, 200000000U))||(200000000U == ahbclk)){ + } else if((ENET_RANGE(ahbclk, 150000000U, 240000000U)) || (240000000U == ahbclk)) { reg |= ENET_MDC_HCLK_DIV102; - }else{ + } else { return enet_state; } ENET_MAC_PHY_CTL = reg; /* reset PHY */ phy_value = PHY_RESET; - if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { return enet_state; } /* PHY reset need some time */ _ENET_DELAY_(ENET_DELAY_TO); /* check whether PHY reset is complete */ - if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { return enet_state; } /* PHY reset complete */ - if(RESET == (phy_value & PHY_RESET)){ + if(RESET == (phy_value & PHY_RESET)) { enet_state = SUCCESS; } @@ -1573,7 +1582,7 @@ ErrStatus enet_phy_config(void) } /*! - \brief write to / read from a PHY register + \brief write to / read from a PHY register \param[in] direction: only one parameter can be selected which is shown as below, refer to enet_phydirection_enum \arg ENET_PHY_WRITE: write data to phy register \arg ENET_PHY_READ: read data from phy register @@ -1595,25 +1604,24 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); /* if do the write operation, write value to the register */ - if(ENET_PHY_WRITE == direction){ + if(ENET_PHY_WRITE == direction) { ENET_MAC_PHY_DATA = *pvalue; } /* do PHY write/read operation, and wait the operation complete */ ENET_MAC_PHY_CTL = reg; - do{ + do { phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); timeout++; - } - while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + } while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); /* write/read operation complete */ - if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ + if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) { enet_state = SUCCESS; } /* if do the read operation, get value from the register */ - if(ENET_PHY_READ == direction){ + if(ENET_PHY_READ == direction) { *pvalue = (uint16_t)ENET_MAC_PHY_DATA; } @@ -1621,7 +1629,7 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add } /*! - \brief enable the loopback function of PHY chip + \brief enable the loopback function of PHY chip \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -1644,7 +1652,7 @@ ErrStatus enet_phyloopback_enable(void) } /*! - \brief disable the loopback function of PHY chip + \brief disable the loopback function of PHY chip \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -1667,7 +1675,7 @@ ErrStatus enet_phyloopback_disable(void) } /*! - \brief enable ENET forward feature + \brief enable ENET forward feature \param[in] feature: the feature of ENET forward mode one or more parameters can be selected which are shown as below \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames @@ -1689,13 +1697,13 @@ void enet_forward_feature_enable(uint32_t feature) } /*! - \brief disable ENET forward feature + \brief disable ENET forward feature \param[in] feature: the feature of ENET forward mode one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function - \arg ENET_TYPEFRAME_CRC_DROP: the flow control operation in the MAC - \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames \param[out] none \retval none */ @@ -1730,7 +1738,7 @@ void enet_fliter_feature_enable(uint32_t feature) } /*! - \brief disable ENET fliter feature + \brief disable ENET fliter feature \param[in] feature: the feature of ENET fliter mode one or more parameters can be selected which are shown as below \arg ENET_SRC_FILTER: filter source address function @@ -1749,7 +1757,7 @@ void enet_fliter_feature_disable(uint32_t feature) } /*! - \brief generate the pause frame, ENET will send pause frame after enable transmit flow control + \brief generate the pause frame, ENET will send pause frame after enable transmit flow control this function only use in full-dulex mode \param[in] none \param[out] none @@ -1757,12 +1765,12 @@ void enet_fliter_feature_disable(uint32_t feature) */ ErrStatus enet_pauseframe_generate(void) { - ErrStatus enet_state =ERROR; + ErrStatus enet_state = ERROR; uint32_t temp = 0U; /* in full-duplex mode, must make sure this bit is 0 before writing register */ temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; - if(RESET == temp){ + if(RESET == temp) { ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; enet_state = SUCCESS; } @@ -1770,7 +1778,7 @@ ErrStatus enet_pauseframe_generate(void) } /*! - \brief configure the pause frame detect type + \brief configure the pause frame detect type \param[in] detect: pause frame detect type only one parameter can be selected which is shown as below \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also @@ -1787,7 +1795,7 @@ void enet_pauseframe_detect_config(uint32_t detect) } /*! - \brief configure the pause frame parameters + \brief configure the pause frame parameters \param[in] pausetime: pause time in transmit pause control frame \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically this value must make sure to be less than configured pause time @@ -1806,7 +1814,7 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) } /*! - \brief configure the threshold of the flow control(deactive and active threshold) + \brief configure the threshold of the flow control(deactive and active threshold) \param[in] deactive: the threshold of the deactive flow control this value should always be less than active flow control value only one parameter can be selected which is shown as below @@ -1835,7 +1843,7 @@ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) } /*! - \brief enable ENET flow control feature + \brief enable ENET flow control feature \param[in] feature: the feature of ENET flow control mode one or more parameters can be selected which are shown as below \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function @@ -1847,7 +1855,7 @@ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) */ void enet_flowcontrol_feature_enable(uint32_t feature) { - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; } feature &= ~ENET_ZERO_QUANTA_PAUSE; @@ -1855,7 +1863,7 @@ void enet_flowcontrol_feature_enable(uint32_t feature) } /*! - \brief disable ENET flow control feature + \brief disable ENET flow control feature \param[in] feature: the feature of ENET flow control mode one or more parameters can be selected which are shown as below \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function @@ -1867,7 +1875,7 @@ void enet_flowcontrol_feature_enable(uint32_t feature) */ void enet_flowcontrol_feature_disable(uint32_t feature) { - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; } feature &= ~ENET_ZERO_QUANTA_PAUSE; @@ -1875,7 +1883,7 @@ void enet_flowcontrol_feature_disable(uint32_t feature) } /*! - \brief get the dma transmit/receive process state + \brief get the dma transmit/receive process state \param[in] direction: choose the direction of dma process which users want to check, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: dma transmit process @@ -1895,7 +1903,7 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) } /*! - \brief poll the DMA transmission/reception enable by writing any value to the + \brief poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception \param[in] direction: choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below @@ -1906,15 +1914,15 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) */ void enet_dmaprocess_resume(enet_dmadirection_enum direction) { - if(ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { ENET_DMA_TPEN = 0U; - }else{ + } else { ENET_DMA_RPEN = 0U; } } /*! - \brief check and recover the Rx process + \brief check and recover the Rx process \param[in] none \param[out] none \retval none @@ -1930,13 +1938,13 @@ void enet_rxprocess_check_recovery(void) /* if current descriptor is owned by DMA, but the descriptor address mismatches with receive descriptor address pointer updated by RxDMA controller */ if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && - (ENET_RDES0_DAV == status)){ - dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; + (ENET_RDES0_DAV == status)) { + dma_current_rxdesc = (enet_descriptors_struct *)ENET_DMA_CRDADDR; } } /*! - \brief flush the ENET transmit FIFO, and wait until the flush operation completes + \brief flush the ENET transmit FIFO, and wait until the flush operation completes \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -1950,12 +1958,12 @@ ErrStatus enet_txfifo_flush(void) /* set the FTF bit for flushing transmit FIFO */ ENET_DMA_CTL |= ENET_DMA_CTL_FTF; /* wait until the flush operation completes */ - do{ + do { flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; timeout++; - }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(RESET == flush_state){ + if(RESET == flush_state) { enet_state = SUCCESS; } @@ -1963,7 +1971,7 @@ ErrStatus enet_txfifo_flush(void) } /*! - \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table + \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum only one parameter can be selected which is shown as below \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table @@ -1981,12 +1989,12 @@ uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) { uint32_t reval = 0U; - reval = REG32((ENET) +(uint32_t)addr_get); + reval = REG32((ENET) + (uint32_t)addr_get); return reval; } /*! - \brief get the Tx or Rx descriptor information + \brief get the Tx or Rx descriptor information \param[in] desc: the descriptor pointer which users want to get information \param[in] info_get: the descriptor information type which is selected, refer to enet_descstate_enum only one parameter can be selected which is shown as below @@ -2003,7 +2011,7 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate { uint32_t reval = 0xFFFFFFFFU; - switch(info_get){ + switch(info_get) { case RXDESC_BUFFER_1_SIZE: reval = GET_RDES1_RB1S(desc->control_buffer_size); break; @@ -2012,14 +2020,14 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate break; case RXDESC_FRAME_LENGTH: reval = GET_RDES0_FRML(desc->status); - if(reval > 4U){ + if(reval > 4U) { reval = reval - 4U; /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))) { reval = reval + 4U; } - }else{ + } else { reval = 0U; } @@ -2040,7 +2048,7 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate } /*! - \brief get the number of missed frames during receiving + \brief get the number of missed frames during receiving \param[in] none \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller @@ -2056,7 +2064,7 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) } /*! - \brief get the bit flag of ENET DMA descriptor + \brief get the bit flag of ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to get flag \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below @@ -2111,7 +2119,7 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) { FlagStatus enet_flag = RESET; - if ((uint32_t)RESET != (desc->status & desc_flag)){ + if((uint32_t)RESET != (desc->status & desc_flag)) { enet_flag = SET; } @@ -2119,7 +2127,7 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) } /*! - \brief set the bit flag of ENET DMA descriptor + \brief set the bit flag of ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to set flag \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below @@ -2144,7 +2152,7 @@ void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) } /*! - \brief clear the bit flag of ENET DMA descriptor + \brief clear the bit flag of ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to clear flag \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below @@ -2169,7 +2177,7 @@ void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set \param[in] desc: the descriptor pointer which users want to configure \param[out] none \retval none @@ -2180,7 +2188,7 @@ void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct * } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time \param[in] desc: the descriptor pointer which users want to configure \param[in] delay_time: delay a time of 256*delay_time HCLK(0x00000000 - 0x000000FF) \param[out] none @@ -2193,7 +2201,7 @@ void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc } /*! - \brief drop current receive frame + \brief drop current receive frame \param[in] none \param[out] none \retval none @@ -2204,33 +2212,33 @@ void enet_rxframe_drop(void) dma_current_rxdesc->status = ENET_RDES0_DAV; /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - if(NULL != dma_current_ptp_rxdesc){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + if(NULL != dma_current_ptp_rxdesc) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ + if(0U != dma_current_ptp_rxdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { /* ponter to the next ptp descriptor */ dma_current_ptp_rxdesc++; } - }else{ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + } else { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); } - }else{ + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + if(NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); } - }else{ + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - if(NULL != dma_current_ptp_rxdesc){ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if(NULL != dma_current_ptp_rxdesc) { dma_current_ptp_rxdesc++; } } @@ -2238,7 +2246,7 @@ void enet_rxframe_drop(void) } /*! - \brief enable DMA feature + \brief enable DMA feature \param[in] feature: the feature of DMA mode one or more parameters can be selected which are shown as below \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function @@ -2252,7 +2260,7 @@ void enet_dma_feature_enable(uint32_t feature) } /*! - \brief disable DMA feature + \brief disable DMA feature \param[in] feature: the feature of DMA mode one or more parameters can be selected which are shown as below \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function @@ -2267,7 +2275,7 @@ void enet_dma_feature_disable(uint32_t feature) #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE /*! - \brief get the bit of extended status flag in ENET DMA descriptor + \brief get the bit of extended status flag in ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to get the extended status flag \param[in] desc_status: the extended status want to get only one parameter can be selected which is shown as below @@ -2287,7 +2295,7 @@ uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_ { uint32_t reval = 0xFFFFFFFFU; - switch (desc_status){ + switch(desc_status) { case ENET_RDES4_IPPLDT: reval = GET_RDES4_IPPLDT(desc->extended_status); break; @@ -2295,9 +2303,9 @@ uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_ reval = GET_RDES4_PTPMT(desc->extended_status); break; default: - if ((uint32_t)RESET != (desc->extended_status & desc_status)){ + if((uint32_t)RESET != (desc->extended_status & desc_status)) { reval = 1U; - }else{ + } else { reval = 0U; } } @@ -2306,7 +2314,7 @@ uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_ } /*! - \brief configure descriptor to work in enhanced mode + \brief configure descriptor to work in enhanced mode \param[in] none \param[out] none \retval none @@ -2317,7 +2325,7 @@ void enet_desc_select_enhanced_mode(void) } /*! - \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors @@ -2333,7 +2341,7 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) uint8_t *buf; /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; @@ -2346,7 +2354,7 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; @@ -2365,7 +2373,7 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) } /* configuration each descriptor */ - for(num = 0U; num < count; num++){ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; @@ -2375,10 +2383,10 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ + } else { /* when it is the last descriptor, the next descriptor address equals to first descriptor address in descriptor table */ desc->buffer2_next_desc_addr = (uint32_t)desc_tab; @@ -2387,7 +2395,7 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) } /*! - \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors @@ -2408,7 +2416,7 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; @@ -2421,7 +2429,7 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; @@ -2434,13 +2442,13 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - /* configure DMA Rx descriptor table address register */ + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; } /* configure each descriptor */ - for(num=0U; num < count; num++){ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; @@ -2450,11 +2458,11 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } @@ -2463,7 +2471,7 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode \param[in] bufsize: the size of buffer which is the parameter in function \param[out] buffer: pointer to the application buffer note -- if the input is NULL, user should copy data in application by himself @@ -2478,49 +2486,49 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t rdes0_tsv_flag; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { return ERROR; } /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* if no error occurs, and the frame uses only one descriptor */ if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { size = size + 4U; } /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ + if(size > bufsize) { return ERROR; } /* copy data from Rx buffer to application buffer */ - for(offset = 0; offset < size; offset++){ + for(offset = 0; offset < size; offset++) { (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); } - }else{ + } else { return ERROR; } } /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ + if(NULL != timestamp) { /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and write to the RDES6 and RDES7 */ - do{ + do { rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); timeout++; - }while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); + } while((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { return ERROR; } @@ -2535,7 +2543,7 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, dma_current_rxdesc->status = ENET_RDES0_DAV; /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { /* Clear RBU flag */ ENET_DMA_STAT = ENET_DMA_STAT_RBU; /* resume DMA reception by writing to the RPEN register*/ @@ -2544,16 +2552,16 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_rxdesc = (enet_descriptors_struct *)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); } } @@ -2561,7 +2569,7 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted @@ -2577,19 +2585,19 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timeout = 0; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { return ERROR; } /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ + if(length > ENET_MAX_FRAME_SIZE) { return ERROR; } /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* copy frame data from application buffer to Tx buffer */ - for(offset = 0; offset < length; offset++){ + for(offset = 0; offset < length; offset++) { (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } @@ -2604,7 +2612,7 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { /* Clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ @@ -2612,15 +2620,15 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, } /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ + if(NULL != timestamp) { /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ + do { tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { return ERROR; } @@ -2633,16 +2641,16 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_txdesc = (enet_descriptors_struct *)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); } } @@ -2652,7 +2660,7 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, #else /*! - \brief configure descriptor to work in normal mode + \brief configure descriptor to work in normal mode \param[in] none \param[out] none \retval none @@ -2663,7 +2671,7 @@ void enet_desc_select_normal_mode(void) } /*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function + \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors @@ -2680,7 +2688,7 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en uint8_t *buf; /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; @@ -2694,7 +2702,7 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; dma_current_ptp_txdesc = desc_ptptab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; @@ -2714,7 +2722,7 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en } /* configure each descriptor */ - for(num = 0U; num < count; num++){ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; @@ -2724,10 +2732,10 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ + } else { /* when it is the last descriptor, the next descriptor address equals to first descriptor address in descriptor table */ desc->buffer2_next_desc_addr = (uint32_t)desc_tab; @@ -2738,11 +2746,11 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en } /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; } /*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function + \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors @@ -2763,7 +2771,7 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; @@ -2777,7 +2785,7 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; dma_current_ptp_txdesc = desc_ptptab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; @@ -2797,7 +2805,7 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene } /* configure each descriptor */ - for(num = 0U; num < count; num++){ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; @@ -2807,11 +2815,11 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } @@ -2822,11 +2830,11 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene } /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode \param[in] bufsize: the size of buffer which is the parameter in function \param[out] buffer: pointer to the application buffer note -- if the input is NULL, user should copy data in application by himself @@ -2838,35 +2846,35 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u uint32_t offset = 0U, size = 0U; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { return ERROR; } /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* if no error occurs, and the frame uses only one descriptor */ if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { size = size + 4U; } /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ + if(size > bufsize) { return ERROR; } /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offset < size; offset++){ + for(offset = 0U; offset < size; offset++) { (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); } - }else{ + } else { return ERROR; } } @@ -2881,7 +2889,7 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u dma_current_rxdesc->status = ENET_RDES0_DAV; /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { /* clear RBU flag */ ENET_DMA_STAT = ENET_DMA_STAT_RBU; /* resume DMA reception by writing to the RPEN register*/ @@ -2891,27 +2899,27 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ + if(0U != dma_current_ptp_rxdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { /* ponter to the next ptp descriptor */ dma_current_ptp_rxdesc++; } - }else{ + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); dma_current_ptp_rxdesc ++; } } @@ -2920,7 +2928,7 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted @@ -2934,20 +2942,20 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { return ERROR; } /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ + if(length > ENET_MAX_FRAME_SIZE) { return ERROR; } /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } /* set the frame length */ @@ -2961,7 +2969,7 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ @@ -2969,15 +2977,15 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u } /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ + if(NULL != timestamp) { /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ + do { tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { return ERROR; } @@ -2992,27 +3000,27 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ + if(0U != dma_current_ptp_txdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { /* ponter to the next ptp descriptor */ dma_current_ptp_txdesc++; } - }else{ + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with TxDMA descriptor */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); dma_current_ptp_txdesc ++; } } @@ -3022,7 +3030,7 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ /*! - \brief wakeup frame filter register pointer reset + \brief wakeup frame filter register pointer reset \param[in] none \param[out] none \retval none @@ -3033,7 +3041,7 @@ void enet_wum_filter_register_pointer_reset(void) } /*! - \brief set the remote wakeup frame registers + \brief set the remote wakeup frame registers \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) \param[out] none \retval none @@ -3043,13 +3051,13 @@ void enet_wum_filter_config(uint32_t pdata[]) uint32_t num = 0U; /* configure ENET_MAC_RWFF register */ - for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ + for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++) { ENET_MAC_RWFF = pdata[num]; } } /*! - \brief enable wakeup management features + \brief enable wakeup management features \param[in] feature: the wake up type which is selected one or more parameters can be selected which are shown as below \arg ENET_WUM_POWER_DOWN: power down mode @@ -3065,7 +3073,7 @@ void enet_wum_feature_enable(uint32_t feature) } /*! - \brief disable wakeup management features + \brief disable wakeup management features \param[in] feature: the wake up type which is selected one or more parameters can be selected which are shown as below \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception @@ -3080,7 +3088,7 @@ void enet_wum_feature_disable(uint32_t feature) } /*! - \brief reset the MAC statistics counters + \brief reset the MAC statistics counters \param[in] none \param[out] none \retval none @@ -3092,7 +3100,7 @@ void enet_msc_counters_reset(void) } /*! - \brief enable the MAC statistics counter features + \brief enable the MAC statistics counter features \param[in] feature: the feature of MAC statistics counter one or more parameters can be selected which are shown as below \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover @@ -3107,7 +3115,7 @@ void enet_msc_feature_enable(uint32_t feature) } /*! - \brief disable the MAC statistics counter features + \brief disable the MAC statistics counter features \param[in] feature: the feature of MAC statistics counter one or more parameters can be selected which are shown as below \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover @@ -3118,11 +3126,11 @@ void enet_msc_feature_enable(uint32_t feature) */ void enet_msc_feature_disable(uint32_t feature) { - ENET_MSC_CTL &= (~feature); + ENET_MSC_CTL &= (~feature); } /*! - \brief configure MAC statistics counters preset mode + \brief configure MAC statistics counters preset mode \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum only one parameter can be selected which is shown as below \arg ENET_MSC_PRESET_NONE: do not preset MSC counter @@ -3138,7 +3146,7 @@ void enet_msc_counters_preset_config(enet_msc_preset_enum mode) } /*! - \brief get MAC statistics counter + \brief get MAC statistics counter \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum only one parameter can be selected which is shown as below \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter @@ -3160,7 +3168,7 @@ uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) } /*! - \brief enable the PTP features + \brief enable the PTP features \param[in] feature: the feature of ENET PTP mode one or more parameters can be selected which are shown as below \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames @@ -3179,7 +3187,7 @@ void enet_ptp_feature_enable(uint32_t feature) } /*! - \brief disable the PTP features + \brief disable the PTP features \param[in] feature: the feature of ENET PTP mode one or more parameters can be selected which are shown as below \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames @@ -3198,7 +3206,7 @@ void enet_ptp_feature_disable(uint32_t feature) } /*! - \brief configure the PTP timestamp function + \brief configure the PTP timestamp function \param[in] func: the function of PTP timestamp only one parameter can be selected which is shown as below \arg ENET_CKNT_ORDINARY: type of ordinary clock node type for timestamp @@ -3228,7 +3236,7 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) uint32_t timeout = 0U; ErrStatus enet_state = SUCCESS; - switch(func){ + switch(func) { case ENET_CKNT_ORDINARY: case ENET_CKNT_BOUNDARY: case ENET_CKNT_END_TO_END: @@ -3238,48 +3246,48 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) break; case ENET_PTP_ADDEND_UPDATE: /* this bit must be read as zero before application set it */ - do{ + do { temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { enet_state = ERROR; - }else{ + } else { ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; } break; case ENET_PTP_SYSTIME_UPDATE: /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ - do{ + do { temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { enet_state = ERROR; - }else{ + } else { ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; } break; case ENET_PTP_SYSTIME_INIT: /* this bit must be read as zero before application set it */ - do{ + do { temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { enet_state = ERROR; - }else{ + } else { ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; } break; default: temp_config = (uint32_t)func & (~BIT(31)); - if(RESET != ((uint32_t)func & BIT(31))){ + if(RESET != ((uint32_t)func & BIT(31))) { ENET_PTP_TSCTL |= temp_config; - }else{ + } else { ENET_PTP_TSCTL &= ~temp_config; } break; @@ -3289,7 +3297,7 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) } /*! - \brief configure system time subsecond increment value + \brief configure system time subsecond increment value \param[in] subsecond: the value will be added to the subsecond value of system time(0x00000000 - 0x000000FF) \param[out] none \retval none @@ -3300,7 +3308,7 @@ void enet_ptp_subsecond_increment_config(uint32_t subsecond) } /*! - \brief adjusting the clock frequency only in fine update mode + \brief adjusting the clock frequency only in fine update mode \param[in] add: the value will be added to the accumulator register to achieve time synchronization \param[out] none \retval none @@ -3311,7 +3319,7 @@ void enet_ptp_timestamp_addend_config(uint32_t add) } /*! - \brief initialize or add/subtract to second of the system time + \brief initialize or add/subtract to second of the system time \param[in] sign: timestamp update positive or negative sign only one parameter can be selected which is shown as below \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time @@ -3329,7 +3337,7 @@ void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t s } /*! - \brief configure the expected target time + \brief configure the expected target time \param[in] second: the expected target second time \param[in] nanosecond: the expected target nanosecond time (signed) \param[out] none @@ -3342,7 +3350,7 @@ void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) } /*! - \brief get the current system time + \brief get the current system time \param[in] none \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time @@ -3367,7 +3375,7 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) } /*! - \brief configure the PPS output frequency + \brief configure the PPS output frequency \param[in] freq: PPS output frequency only one parameter can be selected which is shown as below \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency @@ -3395,7 +3403,7 @@ void enet_ptp_pps_output_frequency_config(uint32_t freq) } /*! - \brief reset the ENET initpara struct, call it before using enet_initpara_config() + \brief reset the ENET initpara struct, call it before using enet_initpara_config() \param[in] none \param[out] none \retval none @@ -3420,7 +3428,7 @@ void enet_initpara_reset(void) } /*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() \param[in] none \param[out] none \retval none @@ -3434,20 +3442,20 @@ static void enet_default_init(void) reg_value = ENET_MAC_CFG; reg_value &= MAC_CFG_MASK; reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ - | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ - | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ - | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ - | ENET_DEFERRALCHECK_DISABLE \ - | ENET_TYPEFRAME_CRC_DROP_DISABLE \ - | ENET_AUTO_PADCRC_DROP_DISABLE \ - | ENET_CHECKSUMOFFLOAD_DISABLE; + | ENET_SPEEDMODE_10M | ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_TYPEFRAME_CRC_DROP_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; ENET_MAC_CFG = reg_value; /* configure ENET_MAC_FRMF register */ - ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ - |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ - |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ - |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE | ENET_DEST_FILTER_INVERSE_DISABLE \ + | ENET_MULTICAST_FILTER_PERFECT | ENET_UNICAST_FILTER_PERFECT \ + | ENET_PCFRM_PREVENT_ALL | ENET_BROADCASTFRAMES_ENABLE \ + | ENET_PROMISCUOUS_DISABLE | ENET_RX_FILTER_ENABLE; /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ ENET_MAC_HLH = 0x0U; @@ -3457,40 +3465,37 @@ static void enet_default_init(void) /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ reg_value = ENET_MAC_FCTL; reg_value &= MAC_FCTL_MASK; - reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ - |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ - |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; + reg_value |= MAC_FCTL_PTM(0) | ENET_ZERO_QUANTA_PAUSE_DISABLE \ + | ENET_PAUSETIME_MINUS4 | ENET_UNIQUE_PAUSEDETECT \ + | ENET_RX_FLOWCONTROL_DISABLE | ENET_TX_FLOWCONTROL_DISABLE; ENET_MAC_FCTL = reg_value; - ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; - /* configure ENET_MAC_VLT register */ - ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT | MAC_VLT_VLTI(0); /* DMA */ /* configure ENET_DMA_CTL register */ reg_value = ENET_DMA_CTL; reg_value &= DMA_CTL_MASK; - reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ - |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ - |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ - |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ - |ENET_SECONDFRAME_OPT_DISABLE; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP | ENET_RX_MODE_STOREFORWARD \ + | ENET_FLUSH_RXFRAME_ENABLE | ENET_TX_MODE_STOREFORWARD \ + | ENET_TX_THRESHOLD_64BYTES | ENET_RX_THRESHOLD_64BYTES \ + | ENET_SECONDFRAME_OPT_DISABLE; ENET_DMA_CTL = reg_value; /* configure ENET_DMA_BCTL register */ reg_value = ENET_DMA_BCTL; reg_value &= DMA_BCTL_MASK; - reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ - |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ - |ENET_FIXED_BURST_ENABLE |ENET_MIXED_BURST_DISABLE \ - |ENET_NORMAL_DESCRIPTOR; + reg_value = ENET_ADDRESS_ALIGN_ENABLE | ENET_ARBITRATION_RXTX_2_1 \ + | ENET_RXDP_32BEAT | ENET_PGBL_32BEAT | ENET_RXTX_DIFFERENT_PGBL \ + | ENET_FIXED_BURST_ENABLE | ENET_MIXED_BURST_DISABLE \ + | ENET_NORMAL_DESCRIPTOR; ENET_DMA_BCTL = reg_value; } #ifndef USE_DELAY /*! - \brief insert a delay time + \brief insert a delay time \param[in] ncount: specifies the delay time length \param[out] none \param[out] none @@ -3499,7 +3504,7 @@ static void enet_delay(uint32_t ncount) { __IO uint32_t delay_time = 0U; - for(delay_time = ncount; delay_time != 0U; delay_time--){ + for(delay_time = ncount; delay_time != 0U; delay_time--) { } } #endif /* USE_DELAY */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c index e225258eb5..71d26c3a73 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c @@ -5,10 +5,12 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx + \version 2022-06-08, V3.0.1, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -112,9 +114,6 @@ OF SUCH DAMAGE. #define SDARI_ARINTV_OFFSET ((uint32_t)1U) -#define SDRSCTL_SSCR_OFFSET ((uint32_t)1U) -#define SDRSCTL_SDSC_OFFSET ((uint32_t)4U) - #define SDSTAT_STA0_OFFSET ((uint32_t)1U) #define SDSTAT_STA1_OFFSET ((uint32_t)3U) @@ -145,7 +144,7 @@ void exmc_norsram_deinit(uint32_t exmc_norsram_region) \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer \retval none */ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) { /* configure the structure with default values */ exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; @@ -171,7 +170,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - /* write timing configure, when extended mode is used */ + /* configure write timing, when extended mode is used */ exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; @@ -198,7 +197,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i read_write_timing: struct exmc_norsram_timing_parameter_struct set the time asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 - syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + syn_clk_division: EXMC_SYN_CLOCK_RATIO_DISABLE, EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 bus_latency: 0x0U~0xFU asyn_data_setuptime: 0x01U~0xFFU asyn_address_holdtime: 0x1U~0xFU @@ -214,53 +213,55 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i \param[out] none \retval none */ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) { - uint32_t snctl = 0x00000000U,sntcfg = 0x00000000U,snwtcfg = 0x00000000U; + uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; /* get the register value */ snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); /* clear relative bits */ snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | - EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | - EXMC_SNCTL_NRMUX )); + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WEN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWTEN | EXMC_SNCTL_SYNCWR | + EXMC_SNCTL_NRMUX)); + /* configure control bits */ snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + /* configure timing */ sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | - (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | - (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | - (exmc_norsram_init_struct->read_write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | - exmc_norsram_init_struct->read_write_timing->syn_clk_division | - exmc_norsram_init_struct->read_write_timing->syn_data_latency | - exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->read_write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ + /* enable nor flash access */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { snctl |= (uint32_t)EXMC_SNCTL_NREN; } - /* extended mode configure */ - if(ENABLE == exmc_norsram_init_struct->extended_mode){ + /* configure extended mode */ + if(ENABLE == exmc_norsram_init_struct->extended_mode) { snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | - (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET )| - (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | - (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | - exmc_norsram_init_struct->write_timing->asyn_access_mode; - }else{ + (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | + (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | + (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | + exmc_norsram_init_struct->write_timing->asyn_access_mode; + } else { snwtcfg = BANK0_SNWTCFG_RESET; } @@ -272,7 +273,7 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) /*! \brief enable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM bank only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none @@ -285,7 +286,7 @@ void exmc_norsram_enable(uint32_t exmc_norsram_region) /*! \brief disable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM Bank only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none @@ -319,7 +320,7 @@ void exmc_nand_deinit(uint32_t exmc_nand_bank) \param[out] the initialized struct exmc_norsram_parameter_struct pointer \retval none */ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +void exmc_nand_struct_para_init(exmc_nand_parameter_struct *exmc_nand_init_struct) { /* configure the structure with default values */ exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; @@ -362,29 +363,29 @@ void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struc \param[out] none \retval none */ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct) { uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; - npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| - EXMC_NPCTL_NDTP | - exmc_nand_init_struct->databus_width | - (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| - exmc_nand_init_struct->ecc_size | - exmc_nand_init_struct->ctr_latency | - exmc_nand_init_struct->atr_latency; + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NPCTL_NDTP | + exmc_nand_init_struct->databus_width | + (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET) | + exmc_nand_init_struct->ecc_size | + exmc_nand_init_struct->ctr_latency | + exmc_nand_init_struct->atr_latency; - npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); - npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ + /* initialize EXMC_BANK1_NAND or EXMC_BANK2_NAND */ EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; @@ -392,7 +393,7 @@ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) /*! \brief enable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank + \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none @@ -405,7 +406,7 @@ void exmc_nand_enable(uint32_t exmc_nand_bank) /*! \brief disable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank + \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none @@ -438,7 +439,7 @@ void exmc_pccard_deinit(void) \param[out] the initialized struct exmc_pccard_parameter_struct pointer \retval none */ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) { /* configure the structure with default values */ exmc_pccard_init_struct->wait_feature = DISABLE; @@ -482,31 +483,31 @@ void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init \param[out] none \retval none */ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) { /* configure the EXMC bank3 PC card control register */ EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | - EXMC_NAND_DATABUS_WIDTH_16B | - exmc_pccard_init_struct->ctr_latency | - exmc_pccard_init_struct->atr_latency ; + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; /* configure the EXMC bank3 PC card common space timing configuration register */ - EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); /* configure the EXMC bank3 PC card attribute space timing configuration register */ - EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - ((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + ((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); /* configure the EXMC bank3 PC card io space timing configuration register */ - EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | - (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | - ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD ) | - ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD) | + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ); } /*! @@ -528,7 +529,7 @@ void exmc_pccard_enable(void) */ void exmc_pccard_disable(void) { - EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; + EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; } /*! @@ -556,7 +557,7 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device) \param[out] the initialized struct exmc_pccard_parameter_struct pointer \retval none */ -void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) { /* configure the structure with default values */ exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; @@ -567,7 +568,7 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_st exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; exmc_sdram_init_struct->write_protection = ENABLE; exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; - exmc_sdram_init_struct->brust_read_switch = DISABLE; + exmc_sdram_init_struct->burst_read_switch = DISABLE; exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; @@ -584,7 +585,7 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_st \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1 pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2 - brust_read_switch: ENABLE or DISABLE + burst_read_switch: ENABLE or DISABLE sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK write_protection: ENABLE or DISABLE cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3 @@ -603,68 +604,83 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_st \param[out] none \retval none */ -void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) +void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) { uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; - /* configuration EXMC_SDCTL0 or EXMC_SDCTL1 */ - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device){ - /* configuration EXMC_SDCTL0 */ - EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)| - exmc_sdram_init_struct->sdclock_config | - (exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET)| - exmc_sdram_init_struct->pipeline_read_delay; - - /* configuration EXMC_SDTCFG0 */ - EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); - }else{ - /* configuration EXMC_SDCTL0 and EXMC_SDCTL1 */ + /* configure EXMC_SDCTL0 or EXMC_SDCTL1 */ + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) { + /* configure EXMC_SDCTL0 */ + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET) | + exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); + + /* configure EXMC_SDTCFG0 */ + EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET); + } else { + /* configure EXMC_SDCTL0 and EXMC_SDCTL1 */ /* some bits in the EXMC_SDCTL1 register are reserved */ - sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~( EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK )); + sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK)); - sdctl0 |= (uint32_t)exmc_sdram_init_struct->sdclock_config | - exmc_sdram_init_struct->brust_read_switch | - exmc_sdram_init_struct->pipeline_read_delay; - - sdctl1 = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - exmc_sdram_init_struct->write_protection ; + sdctl0 |= (uint32_t)(exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); + + sdctl1 = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)); EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; - /* configuration EXMC_SDTCFG0 and EXMC_SDTCFG1 */ + /* configure EXMC_SDTCFG0 and EXMC_SDTCFG1 */ /* some bits in the EXMC_SDTCFG1 register are reserved */ sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); - sdtcfg0 |= (uint32_t)(((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET); + sdtcfg0 |= (uint32_t)((((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET)); - sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); + sdtcfg1 = (uint32_t)(((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET)); EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; } } +/*! + \brief initialize exmc_sdram_struct_command_para_init with the default values + \param[in] none + \param[out] the initialized struct exmc_sdram_struct_command_para_init pointer + \retval none +*/ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) +{ + /* configure the structure with default value */ + exmc_sdram_command_init_struct->mode_register_content = 0U; + exmc_sdram_command_init_struct->auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; + exmc_sdram_command_init_struct->bank_select = EXMC_SDRAM_DEVICE0_SELECT; + exmc_sdram_command_init_struct->command = EXMC_SDRAM_NORMAL_OPERATION; +} + /*! \brief deinitialize exmc SQPIPSRAM \param[in] none @@ -687,7 +703,7 @@ void exmc_sqpipsram_deinit(void) \param[out] none \retval none */ -void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) { /* configure the structure with default values */ exmc_sqpipsram_init_struct->sample_polarity = EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE; @@ -706,18 +722,18 @@ void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpip \param[out] none \retval none */ -void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) { /* initialize SQPI controller */ EXMC_SINIT = (uint32_t)exmc_sqpipsram_init_struct->sample_polarity | - exmc_sqpipsram_init_struct->id_length | - exmc_sqpipsram_init_struct->address_bits | - exmc_sqpipsram_init_struct->command_bits; + exmc_sqpipsram_init_struct->id_length | + exmc_sqpipsram_init_struct->address_bits | + exmc_sqpipsram_init_struct->command_bits; } /*! \brief configure consecutive clock - \param[in] clock_mode: specifie when the clock is generated + \param[in] clock_mode: specify when the clock is generated only one parameter can be selected which is shown as below: \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access \arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally @@ -726,9 +742,9 @@ void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_st */ void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) { - if (EXMC_CLOCK_UNCONDITIONALLY == clock_mode){ + if(EXMC_CLOCK_UNCONDITIONALLY == clock_mode) { EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; - }else{ + } else { EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; } } @@ -759,7 +775,7 @@ void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_s /*! \brief enable or disable the EXMC NAND ECC function - \param[in] exmc_nand_bank: specifie the NAND bank + \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[in] newvalue: ENABLE or DISABLE @@ -768,10 +784,10 @@ void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_s */ void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) { - if (ENABLE == newvalue){ + if(ENABLE == newvalue) { /* enable the selected NAND bank ECC function */ EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; - }else{ + } else { /* disable the selected NAND bank ECC function */ EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; } @@ -779,7 +795,7 @@ void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) /*! \brief get the EXMC ECC value - \param[in] exmc_nand_bank: specifie the NAND bank + \param[in] exmc_nand_bank: specify the NAND bank only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none @@ -798,9 +814,9 @@ uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) */ void exmc_sdram_readsample_enable(ControlStatus newvalue) { - if (ENABLE == newvalue){ + if(ENABLE == newvalue) { EXMC_SDRSCTL |= EXMC_SDRSCTL_RSEN; - }else{ + } else { EXMC_SDRSCTL &= (uint32_t)(~EXMC_SDRSCTL_RSEN); } } @@ -823,8 +839,7 @@ void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) /* reset the bits */ sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR)); /* set the bits */ - sdrsctl |= (uint32_t)(delay_cell & EXMC_SDRSCTL_SDSC) | - ((extra_hclk << SDRSCTL_SSCR_OFFSET) & EXMC_SDRSCTL_SSCR); + sdrsctl |= (uint32_t)(delay_cell | extra_hclk); EXMC_SDRSCTL = sdrsctl; } @@ -840,13 +855,13 @@ void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) \param[out] none \retval none */ -void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct) +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) { /* configure command register */ EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | - (exmc_sdram_command_init_struct->bank_select) | - ((exmc_sdram_command_init_struct->auto_refresh_number)) | - ((exmc_sdram_command_init_struct->mode_register_content)<bank_select) | + ((exmc_sdram_command_init_struct->auto_refresh_number)) | + ((exmc_sdram_command_init_struct->mode_register_content) << SDCMD_MRC_OFFSET)); } /*! @@ -876,8 +891,8 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) } /*! - \brief config the write protection function - \param[in] exmc_sdram_device: specifie the SDRAM device + \brief configure the write protection function + \param[in] exmc_sdram_device: specify the SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0,1) \param[in] newvalue: ENABLE or DISABLE @@ -886,9 +901,9 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) */ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue) { - if (ENABLE == newvalue){ + if(ENABLE == newvalue) { EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN; - }else{ + } else { EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN); } @@ -896,7 +911,7 @@ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatu /*! \brief get the status of SDRAM device0 or device1 - \param[in] exmc_sdram_device: specifie the SDRAM device + \param[in] exmc_sdram_device: specify the SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0,1) \param[out] none @@ -906,9 +921,9 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) { uint32_t sdstat = 0U; - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device){ + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device) { sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET); - }else{ + } else { sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); } @@ -928,13 +943,13 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) \param[out] none \retval none */ -void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle, uint32_t read_command_code) +void exmc_sqpipsram_read_command_set(uint32_t read_command_mode, uint32_t read_wait_cycle, uint32_t read_command_code) { uint32_t srcmd; srcmd = (uint32_t) read_command_mode | - ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | - ((read_command_code & EXMC_SRCMD_RCMD)); + ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | + ((read_command_code & EXMC_SRCMD_RCMD)); EXMC_SRCMD = srcmd; } @@ -951,13 +966,13 @@ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wa \param[out] none \retval none */ -void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle, uint32_t write_command_code) +void exmc_sqpipsram_write_command_set(uint32_t write_command_mode, uint32_t write_wait_cycle, uint32_t write_command_code) { uint32_t swcmd; swcmd = (uint32_t) write_command_mode | - ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | - ((write_command_code & EXMC_SWCMD_WCMD)); + ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | + ((write_command_code & EXMC_SWCMD_WCMD)); EXMC_SWCMD = swcmd; } @@ -1018,17 +1033,17 @@ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) { uint32_t flag = 0x00000000U; - if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag){ + if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag) { flag = EXMC_SRCMD; - }else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag){ + } else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag) { flag = EXMC_SWCMD; - }else{ + } else { } - if (flag & send_command_flag){ + if(flag & send_command_flag) { /* flag is set */ return SET; - }else{ + } else { /* flag is reset */ return RESET; } @@ -1036,14 +1051,14 @@ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) /*! \brief enable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank,PC card bank or SDRAM device + \param[in] exmc_bank: specify the NAND bank,PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt: specify get which interrupt flag + \param[in] interrupt: specify EXMC interrupt flag only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag @@ -1054,10 +1069,10 @@ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) */ void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) { - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ EXMC_NPINTEN(exmc_bank) |= interrupt; - }else{ + } else { /* SDRAM device0 or device1 */ EXMC_SDARI |= EXMC_SDARI_REIE; } @@ -1065,14 +1080,14 @@ void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) /*! \brief disable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt: specify get which interrupt flag + \param[in] interrupt: specify EXMC interrupt flag only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag @@ -1083,10 +1098,10 @@ void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) */ void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) { - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ EXMC_NPINTEN(exmc_bank) &= ~interrupt; - }else{ + } else { /* SDRAM device0 or device1 */ EXMC_SDARI &= ~EXMC_SDARI_REIE; } @@ -1094,7 +1109,7 @@ void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) /*! \brief get EXMC flag status - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 @@ -1112,22 +1127,22 @@ void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) +FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag) { uint32_t status = 0x00000000U; - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(exmc_bank); - }else{ - /* SDRAM device0 or device1 */ + } else { + /* SDRAM device0 or device1 */ status = EXMC_SDSTAT; } - if ((status & flag) != (uint32_t)flag ){ + if((status & flag) != (uint32_t)flag) { /* flag is reset */ return RESET; - }else{ + } else { /* flag is set */ return SET; } @@ -1135,7 +1150,7 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) /*! \brief clear EXMC flag status - \param[in] exmc_bank: specifie the NAND bank , PCCARD bank or SDRAM device + \param[in] exmc_bank: specify the NAND bank , PCCARD bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 @@ -1155,10 +1170,10 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) */ void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) { - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ EXMC_NPINTEN(exmc_bank) &= ~flag; - }else{ + } else { /* SDRAM device0 or device1 */ EXMC_SDSTAT &= ~flag; } @@ -1166,7 +1181,7 @@ void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) /*! \brief get EXMC interrupt flag - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 @@ -1184,24 +1199,24 @@ void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) */ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) { - uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; + uint32_t status = 0x00000000U, interrupt_enable = 0x00000000U, interrupt_state = 0x00000000U; - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(exmc_bank); interrupt_state = (status & (interrupt >> INTEN_INTS_OFFSET)); - }else{ - /* SDRAM device0 or device1 */ + } else { + /* SDRAM device0 or device1 */ status = EXMC_SDARI; interrupt_state = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); } interrupt_enable = (status & interrupt); - if ((interrupt_enable) && (interrupt_state)){ + if((interrupt_enable) && (interrupt_state)) { /* interrupt flag is set */ return SET; - }else{ + } else { /* interrupt flag is reset */ return RESET; } @@ -1209,7 +1224,7 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) /*! \brief clear EXMC interrupt flag - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 @@ -1227,10 +1242,10 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) */ void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt) { - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)) { /* NAND bank1,bank2 or PC card bank3 */ EXMC_NPINTEN(exmc_bank) &= ~(interrupt >> INTEN_INTS_OFFSET); - }else{ + } else { /* SDRAM device0 or device1 */ EXMC_SDARI |= EXMC_SDARI_REC; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c index a3eacb0202..413dff9338 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c @@ -1,14 +1,14 @@ /*! \file gd32f4xx_exti.c \brief EXTI driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -36,8 +36,10 @@ OF SUCH DAMAGE. #include "gd32f4xx_exti.h" +#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) + /*! - \brief deinitialize the EXTI + \brief deinitialize the EXTI \param[in] none \param[out] none \retval none @@ -45,15 +47,15 @@ OF SUCH DAMAGE. void exti_deinit(void) { /* reset the value of all the EXTI registers */ - EXTI_INTEN = (uint32_t)0x00000000U; - EXTI_EVEN = (uint32_t)0x00000000U; - EXTI_RTEN = (uint32_t)0x00000000U; - EXTI_FTEN = (uint32_t)0x00000000U; - EXTI_SWIEV = (uint32_t)0x00000000U; + EXTI_INTEN = EXTI_REG_RESET_VALUE; + EXTI_EVEN = EXTI_REG_RESET_VALUE; + EXTI_RTEN = EXTI_REG_RESET_VALUE; + EXTI_FTEN = EXTI_REG_RESET_VALUE; + EXTI_SWIEV = EXTI_REG_RESET_VALUE; } /*! - \brief initialize the EXTI + \brief initialize the EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -71,8 +73,8 @@ void exti_deinit(void) \retval none */ void exti_init(exti_line_enum linex, \ - exti_mode_enum mode, \ - exti_trig_type_enum trig_type) + exti_mode_enum mode, \ + exti_trig_type_enum trig_type) { /* reset the EXTI line x */ EXTI_INTEN &= ~(uint32_t)linex; @@ -81,7 +83,7 @@ void exti_init(exti_line_enum linex, \ EXTI_FTEN &= ~(uint32_t)linex; /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode){ + switch(mode) { case EXTI_INTERRUPT: EXTI_INTEN |= (uint32_t)linex; break; @@ -93,7 +95,7 @@ void exti_init(exti_line_enum linex, \ } /* set the EXTI trigger type */ - switch(trig_type){ + switch(trig_type) { case EXTI_TRIG_RISING: EXTI_RTEN |= (uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex; @@ -113,7 +115,7 @@ void exti_init(exti_line_enum linex, \ } /*! - \brief enable the interrupts from EXTI line x + \brief enable the interrupts from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -126,7 +128,7 @@ void exti_interrupt_enable(exti_line_enum linex) } /*! - \brief disable the interrupt from EXTI line x + \brief disable the interrupt from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -139,7 +141,7 @@ void exti_interrupt_disable(exti_line_enum linex) } /*! - \brief enable the events from EXTI line x + \brief enable the events from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -152,7 +154,7 @@ void exti_event_enable(exti_line_enum linex) } /*! - \brief disable the events from EXTI line x + \brief disable the events from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -165,7 +167,7 @@ void exti_event_disable(exti_line_enum linex) } /*! - \brief enable EXTI software interrupt event + \brief enable the software interrupt event from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -178,7 +180,7 @@ void exti_software_interrupt_enable(exti_line_enum linex) } /*! - \brief disable EXTI software interrupt event + \brief disable the software interrupt event from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -191,7 +193,7 @@ void exti_software_interrupt_disable(exti_line_enum linex) } /*! - \brief get EXTI lines flag + \brief get EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -200,15 +202,15 @@ void exti_software_interrupt_disable(exti_line_enum linex) */ FlagStatus exti_flag_get(exti_line_enum linex) { - if(RESET != (EXTI_PD & (uint32_t)linex)){ + if(RESET != (EXTI_PD & (uint32_t)linex)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear EXTI lines pending flag + \brief clear EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -221,7 +223,7 @@ void exti_flag_clear(exti_line_enum linex) } /*! - \brief get EXTI lines flag when the interrupt flag is set + \brief get EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -230,20 +232,15 @@ void exti_flag_clear(exti_line_enum linex) */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex) { - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ + if(RESET != (EXTI_PD & (uint32_t)linex)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear EXTI lines pending flag + \brief clear EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x @@ -254,4 +251,3 @@ void exti_interrupt_flag_clear(exti_line_enum linex) { EXTI_PD = (uint32_t)linex; } - diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c index 4e2b0db9a5..9dfa1904f2 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -38,7 +39,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_fmc.h" /*! - \brief set the wait state counter value + \brief set the FMC wait state counter \param[in] wscnt: wait state counter value only one parameter can be selected which is shown as below: \arg WS_WSCNT_0: FMC 0 wait @@ -71,14 +72,14 @@ void fmc_wscnt_set(uint32_t wscnt) } /*! - \brief unlock the main FMC operation + \brief unlock the main FMC operation \param[in] none \param[out] none \retval none */ void fmc_unlock(void) { - if((RESET != (FMC_CTL & FMC_CTL_LK))){ + if((RESET != (FMC_CTL & FMC_CTL_LK))) { /* write the FMC key */ FMC_KEY = UNLOCK_KEY0; FMC_KEY = UNLOCK_KEY1; @@ -86,7 +87,7 @@ void fmc_unlock(void) } /*! - \brief lock the main FMC operation + \brief lock the main FMC operation \param[in] none \param[out] none \retval none @@ -97,8 +98,54 @@ void fmc_lock(void) FMC_CTL |= FMC_CTL_LK; } +#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470) + /*! - \brief erase sector + \brief FMC erase page + \param[in] page_addr: the page address to be erased. + \param[out] none + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_TOERR: timeout error +*/ +fmc_state_enum fmc_page_erase(uint32_t page_addr) +{ + fmc_state_enum fmc_state = FMC_READY; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* unlock page erase operation */ + FMC_PEKEY = UNLOCK_PE_KEY; + + /* start page erase */ + FMC_PECFG = FMC_PE_EN | page_addr; + FMC_CTL &= ~FMC_CTL_SN; + FMC_CTL |= FMC_CTL_SER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + FMC_PECFG &= ~FMC_PE_EN; + FMC_CTL &= ~FMC_CTL_SER; + } + + /* return the FMC state */ + return fmc_state; +} + +#endif + +/*! + \brief FMC erase sector \param[in] fmc_sector: select the sector to erase only one parameter can be selected which is shown as below: \arg CTL_SECTOR_NUMBER_0: sector 0 @@ -138,22 +185,22 @@ void fmc_lock(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error + \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start sector erase */ FMC_CTL &= ~FMC_CTL_SN; FMC_CTL |= (FMC_CTL_SER | fmc_sector); FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the SER bit */ FMC_CTL &= (~FMC_CTL_SER); @@ -165,7 +212,7 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) } /*! - \brief erase whole chip + \brief FMC erase whole chip \param[in] none \param[out] none \retval state of FMC @@ -176,21 +223,21 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error + \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_mass_erase(void) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start whole chip erase */ FMC_CTL |= (FMC_CTL_MER0 | FMC_CTL_MER1); FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the MER bits */ FMC_CTL &= ~(FMC_CTL_MER0 | FMC_CTL_MER1); @@ -201,7 +248,7 @@ fmc_state_enum fmc_mass_erase(void) } /*! - \brief erase all FMC sectors in bank0 + \brief FMC erase whole bank0 \param[in] none \param[out] none \retval state of FMC @@ -212,21 +259,21 @@ fmc_state_enum fmc_mass_erase(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error + \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_bank0_erase(void) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start FMC bank0 erase */ FMC_CTL |= FMC_CTL_MER0; FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the MER0 bit */ FMC_CTL &= (~FMC_CTL_MER0); @@ -237,7 +284,7 @@ fmc_state_enum fmc_bank0_erase(void) } /*! - \brief erase all FMC sectors in bank1 + \brief FMC erase whole bank1 \param[in] none \param[out] none \retval state of FMC @@ -248,21 +295,21 @@ fmc_state_enum fmc_bank0_erase(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error + \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_bank1_erase(void) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start FMC bank1 erase */ FMC_CTL |= FMC_CTL_MER1; FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the MER1 bit */ FMC_CTL &= (~FMC_CTL_MER1); @@ -273,7 +320,7 @@ fmc_state_enum fmc_bank1_erase(void) } /*! - \brief program a word at the corresponding address + \brief program a word at the corresponding address \param[in] address: address to program \param[in] data: word to program(0x00000000 - 0xFFFFFFFF) \param[out] none @@ -285,15 +332,15 @@ fmc_state_enum fmc_bank1_erase(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error + \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_WORD; @@ -302,7 +349,7 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) REG32(address) = data; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PG bit */ FMC_CTL &= ~FMC_CTL_PG; @@ -313,7 +360,7 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) } /*! - \brief program a half word at the corresponding address + \brief program a half word at the corresponding address \param[in] address: address to program \param[in] data: halfword to program(0x0000 - 0xFFFF) \param[out] none @@ -325,15 +372,15 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error + \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_HALF_WORD; @@ -342,7 +389,7 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) REG16(address) = data; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PG bit */ FMC_CTL &= ~FMC_CTL_PG; @@ -353,7 +400,7 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) } /*! - \brief program a byte at the corresponding address + \brief program a byte at the corresponding address \param[in] address: address to program \param[in] data: byte to program(0x00 - 0xFF) \param[out] none @@ -365,15 +412,15 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error + \arg FMC_TOERR: timeout error */ fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_BYTE; @@ -382,7 +429,7 @@ fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) REG8(address) = data; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PG bit */ FMC_CTL &= ~FMC_CTL_PG; @@ -393,14 +440,14 @@ fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) } /*! - \brief unlock the option byte operation + \brief unlock the option byte operation \param[in] none \param[out] none \retval none */ void ob_unlock(void) { - if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_OB_LK)){ + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_OB_LK)) { /* write the FMC key */ FMC_OBKEY = OB_UNLOCK_KEY0; FMC_OBKEY = OB_UNLOCK_KEY1; @@ -408,7 +455,7 @@ void ob_unlock(void) } /*! - \brief lock the option byte operation + \brief lock the option byte operation \param[in] none \param[out] none \retval none @@ -420,25 +467,19 @@ void ob_lock(void) } /*! - \brief send option byte change command + \brief send option byte change command \param[in] none \param[out] none \retval none */ void ob_start(void) { - fmc_state_enum fmc_state = FMC_READY; /* set the OB_START bit in OBCTL0 register */ FMC_OBCTL0 |= FMC_OBCTL0_OB_START; - fmc_state = fmc_ready_wait(); - if(FMC_READY != fmc_state){ - while(1){ - } - } } /*! - \brief erase option byte + \brief erase option byte \param[in] none \param[out] none \retval none @@ -448,11 +489,11 @@ void ob_erase(void) uint32_t reg, reg1; fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + reg = FMC_OBCTL0; + reg1 = FMC_OBCTL1; - if(FMC_READY == fmc_state){ - reg = FMC_OBCTL0; - reg1 = FMC_OBCTL1; + if(FMC_READY == fmc_state) { /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ reg |= (FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); @@ -476,67 +517,73 @@ void ob_erase(void) } /*! - \brief enable write protection + \brief enable write protection \param[in] ob_wp: specify sector to be write protected one or more parameters can be selected which are shown as below: \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) \arg OB_WP_23_27: sector23~27 \arg OB_WP_ALL: all sector \param[out] none - \retval none + \retval SUCCESS or ERROR */ -void ob_write_protection_enable(uint32_t ob_wp) +ErrStatus ob_write_protection_enable(uint32_t ob_wp) { uint32_t reg0 = FMC_OBCTL0; uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; - if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ - while(1){ - } + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) { + return ERROR; } /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - reg0 &= (~((uint32_t)ob_wp << 16)); + if(FMC_READY == fmc_state) { + reg0 &= (~((uint32_t)ob_wp << 16U)); reg1 &= (~(ob_wp & 0xFFFF0000U)); FMC_OBCTL0 = reg0; FMC_OBCTL1 = reg1; + + return SUCCESS; + } else { + return ERROR; } } /*! - \brief disable write protection + \brief disable write protection \param[in] ob_wp: specify sector to be write protected one or more parameters can be selected which are shown as below: \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) \arg OB_WP_23_27: sector23~27 \arg OB_WP_ALL: all sector \param[out] none - \retval none + \retval SUCCESS or ERROR */ -void ob_write_protection_disable(uint32_t ob_wp) +ErrStatus ob_write_protection_disable(uint32_t ob_wp) { uint32_t reg0 = FMC_OBCTL0; uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; - if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ - while(1){ - } + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) { + return ERROR; } /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - reg0 |= ((uint32_t)ob_wp << 16); + if(FMC_READY == fmc_state) { + reg0 |= ((uint32_t)ob_wp << 16U); reg1 |= (ob_wp & 0xFFFF0000U); FMC_OBCTL0 = reg0; FMC_OBCTL1 = reg1; + + return SUCCESS; + } else { + return ERROR; } } /*! - \brief enable erase/program protection and D-bus read protection + \brief enable erase/program protection and D-bus read protection \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector one or more parameters can be selected which are shown as below: \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) @@ -553,55 +600,63 @@ void ob_drp_enable(uint32_t ob_drp) uint32_t drp_state = FMC_OBCTL0 & FMC_OBCTL0_DRP; uint32_t wp0_state = FMC_OBCTL0 & FMC_OBCTL0_WP0; uint32_t wp1_state = FMC_OBCTL1 & FMC_OBCTL1_WP1; - /*disable write protection before enable D-bus read protection*/ - if((RESET != drp_state) && ((FMC_OBCTL0_WP0 != wp0_state) && (FMC_OBCTL1_WP1 != wp1_state))){ - while(1){ - } - } - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - if(FMC_READY == fmc_state){ - reg0 &= ~FMC_OBCTL0_WP0; - reg1 &= ~FMC_OBCTL1_WP1; - reg0 |= ((uint32_t)ob_drp << 16); + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + if(RESET == drp_state) { + reg0 &= ~FMC_OBCTL0_WP0; + reg1 &= ~FMC_OBCTL1_WP1; + } + reg0 |= ((uint32_t)ob_drp << 16U); + reg0 |= FMC_OBCTL0_DRP; reg1 |= ((uint32_t)ob_drp & 0xFFFF0000U); + FMC_OBCTL0 = reg0; FMC_OBCTL1 = reg1; - FMC_OBCTL0 |= FMC_OBCTL0_DRP; } } /*! - \brief disable erase/program protection and D-bus read protection - \param[in] ob_drp: disable the WPx bits used as erase/program protection and D-bus read protection of each sector - one or more parameters can be selected which are shown as below: - \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) - \arg OB_DRP_23_27: sector23~27 - \arg OB_DRP_ALL: all sector + \brief disable erase/program protection and D-bus read protection + \param[in] none \param[out] none \retval none */ -void ob_drp_disable(uint32_t ob_drp) +void ob_drp_disable(void) { uint32_t reg0 = FMC_OBCTL0; uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { + if(((uint8_t)(reg0 >> 8U)) == (uint8_t)FMC_NSPC) { + /* security protection should be set as low level protection before disable D-BUS read protection */ + reg0 &= ~FMC_OBCTL0_SPC; + reg0 |= ((uint32_t)FMC_LSPC << 8U); + FMC_OBCTL0 = reg0; + /* set the OB_START bit in OBCTL0 register */ + FMC_OBCTL0 |= FMC_OBCTL0_OB_START; + } + + /* it is necessary to disable the security protection at the same time when D-BUS read protection is disabled */ + reg0 &= ~FMC_OBCTL0_SPC; + reg0 |= ((uint32_t)FMC_NSPC << 8U); reg0 |= FMC_OBCTL0_WP0; reg0 &= (~FMC_OBCTL0_DRP); FMC_OBCTL0 = reg0; reg1 |= FMC_OBCTL1_WP1; FMC_OBCTL1 = reg1; + } } /*! - \brief configure security protection level + \brief configure security protection level \param[in] ob_spc: specify security protection level only one parameter can be selected which is shown as below: \arg FMC_NSPC: no security protection @@ -614,21 +669,21 @@ void ob_security_protection_config(uint8_t ob_spc) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { uint32_t reg; reg = FMC_OBCTL0; /* reset the OBCTL0_SPC, set according to ob_spc */ reg &= ~FMC_OBCTL0_SPC; - reg |= ((uint32_t)ob_spc << 8); + reg |= ((uint32_t)ob_spc << 8U); FMC_OBCTL0 = reg; } } /*! - \brief program the FMC user option byte + \brief program the FMC user option byte \param[in] ob_fwdgt: option byte watchdog value only one parameter can be selected which is shown as below: \arg OB_FWDGT_SW: software free watchdog @@ -649,9 +704,9 @@ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { uint32_t reg; reg = FMC_OBCTL0; @@ -662,7 +717,7 @@ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) } /*! - \brief program the option byte BOR threshold value + \brief program the option byte BOR threshold value \param[in] ob_bor_th: user option byte only one parameter can be selected which is shown as below: \arg OB_BOR_TH_VALUE3: BOR threshold value 3 @@ -683,7 +738,7 @@ void ob_user_bor_threshold(uint32_t ob_bor_th) } /*! - \brief configure the option byte boot bank value + \brief configure the option byte boot bank value \param[in] boot_mode: specifies the option byte boot bank value only one parameter can be selected which is shown as below: \arg OB_BB_DISABLE: boot from bank0 @@ -702,18 +757,18 @@ void ob_boot_mode_config(uint32_t boot_mode) } /*! - \brief get the FMC user option byte + \brief get the FMC user option byte \param[in] none \param[out] none \retval the FMC user option byte values: ob_fwdgt(Bit0), ob_deepsleep(Bit1), ob_stdby(Bit2) */ uint8_t ob_user_get(void) { - return (uint8_t)((uint8_t)(FMC_OBCTL0 >> 5) & (uint8_t)0x07); + return (uint8_t)((uint8_t)(FMC_OBCTL0 >> 5U) & 0x07U); } /*! - \brief get the FMC option byte write protection + \brief get the FMC option byte write protection \param[in] none \param[out] none \retval the FMC write protection option byte value @@ -721,11 +776,11 @@ uint8_t ob_user_get(void) uint16_t ob_write_protection0_get(void) { /* return the FMC write protection option byte value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16)) & (uint16_t)0x0FFF); + return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU); } /*! - \brief get the FMC option byte write protection + \brief get the FMC option byte write protection \param[in] none \param[out] none \retval the FMC write protection option byte value @@ -733,11 +788,11 @@ uint16_t ob_write_protection0_get(void) uint16_t ob_write_protection1_get(void) { /* return the the FMC write protection option byte value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16)) & (uint16_t)0x0FFF); + return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU); } /*! - \brief get the FMC D-bus read protection protection + \brief get the FMC erase/program protection and D-bus read protection option bytes value \param[in] none \param[out] none \retval the FMC erase/program protection and D-bus read protection option bytes value @@ -745,11 +800,15 @@ uint16_t ob_write_protection1_get(void) uint16_t ob_drp0_get(void) { /* return the FMC erase/program protection and D-bus read protection option bytes value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16)) & (uint16_t)0x0FFF); + if(FMC_OBCTL0 & FMC_OBCTL0_DRP) { + return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU); + } else { + return 0xF000U; + } } /*! - \brief get the FMC D-bus read protection protection + \brief get the FMC erase/program protection and D-bus read protection option bytes value \param[in] none \param[out] none \retval the FMC erase/program protection and D-bus read protection option bytes value @@ -757,11 +816,15 @@ uint16_t ob_drp0_get(void) uint16_t ob_drp1_get(void) { /* return the FMC erase/program protection and D-bus read protection option bytes value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16)) & (uint16_t)0x0FFF); + if(FMC_OBCTL0 & FMC_OBCTL0_DRP) { + return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU); + } else { + return 0xF000U; + } } /*! - \brief get the FMC option byte security protection + \brief get option byte security protection code value \param[in] none \param[out] none \retval FlagStatus: SET or RESET @@ -770,16 +833,16 @@ FlagStatus ob_spc_get(void) { FlagStatus spc_state = RESET; - if (((uint8_t)(FMC_OBCTL0 >> 8)) != (uint8_t)FMC_NSPC){ + if(((uint8_t)(FMC_OBCTL0 >> 8U)) != FMC_NSPC) { spc_state = SET; - }else{ + } else { spc_state = RESET; } return spc_state; } /*! - \brief get the FMC option byte BOR threshold value + \brief get the FMC option byte BOR threshold value \param[in] none \param[out] none \retval the FMC BOR threshold value:OB_BOR_TH_OFF,OB_BOR_TH_VALUE1,OB_BOR_TH_VALUE2,OB_BOR_TH_VALUE3 @@ -787,39 +850,11 @@ FlagStatus ob_spc_get(void) uint8_t ob_user_bor_threshold_get(void) { /* return the FMC BOR threshold value */ - return (uint8_t)((uint8_t)FMC_OBCTL0 & (uint8_t)0x0C); + return (uint8_t)((uint8_t)FMC_OBCTL0 & 0x0CU); } /*! - \brief enable FMC interrupt - \param[in] fmc_int: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_END: enable FMC end of program interrupt - \arg FMC_INT_ERR: enable FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t fmc_int) -{ - FMC_CTL |= fmc_int; -} - -/*! - \brief disable FMC interrupt - \param[in] fmc_int: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_END: disable FMC end of program interrupt - \arg FMC_INT_ERR: disable FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t fmc_int) -{ - FMC_CTL &= ~(uint32_t)fmc_int; -} - -/*! - \brief get flag set or reset + \brief get flag set or reset \param[in] fmc_flag: check FMC flag only one parameter can be selected which is shown as below: \arg FMC_FLAG_BUSY: FMC busy flag bit @@ -834,15 +869,15 @@ void fmc_interrupt_disable(uint32_t fmc_int) */ FlagStatus fmc_flag_get(uint32_t fmc_flag) { - if(FMC_STAT & fmc_flag){ - return SET; + if(FMC_STAT & fmc_flag) { + return SET; } /* return the state of corresponding FMC flag */ return RESET; } /*! - \brief clear the FMC pending flag + \brief clear the FMC pending flag \param[in] FMC_flag: clear FMC flag only one parameter can be selected which is shown as below: \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit @@ -861,7 +896,88 @@ void fmc_flag_clear(uint32_t fmc_flag) } /*! - \brief get the FMC state + \brief enable FMC interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: enable FMC end of program interrupt + \arg FMC_INT_ERR: enable FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t fmc_int) +{ + FMC_CTL |= fmc_int; +} + +/*! + \brief disable FMC interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: disable FMC end of program interrupt + \arg FMC_INT_ERR: disable FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t fmc_int) +{ + FMC_CTL &= ~(uint32_t)fmc_int; +} + +/*! + \brief get FMC interrupt flag set or reset + \param[in] fmc_int_flag: FMC interrupt flag + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag + \arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag + \arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag + \arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag + \arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag) +{ + if(FMC_FLAG_END == fmc_int_flag) { + /* end of operation interrupt flag */ + if(FMC_CTL & FMC_CTL_ENDIE) { + if(FMC_STAT & fmc_int_flag) { + return SET; + } + } + } else { + /* error interrupt flags */ + if(FMC_CTL & FMC_CTL_ERRIE) { + if(FMC_STAT & fmc_int_flag) { + return SET; + } + } + } + + return RESET; +} + +/*! + \brief clear the FMC interrupt flag + \param[in] fmc_int_flag: FMC interrupt flag + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag + \arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag + \arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag + \arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag + \arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag + \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(uint32_t fmc_int_flag) +{ + /* clear the interrupt flag */ + FMC_STAT = fmc_int_flag; +} + +/*! + \brief get the FMC state \param[in] none \param[out] none \retval state of FMC @@ -872,39 +988,34 @@ void fmc_flag_clear(uint32_t fmc_flag) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error */ fmc_state_enum fmc_state_get(void) { fmc_state_enum fmc_state = FMC_READY; + uint32_t temp_val = FMC_STAT; - if((FMC_STAT & FMC_FLAG_BUSY) == FMC_FLAG_BUSY){ + if(RESET != (temp_val & FMC_FLAG_BUSY)) { fmc_state = FMC_BUSY; - }else{ - if((FMC_STAT & FMC_FLAG_WPERR) != (uint32_t)0x00){ - fmc_state = FMC_WPERR; - }else{ - if((FMC_STAT & FMC_FLAG_RDDERR) != (uint32_t)0x00){ - fmc_state = FMC_RDDERR; - }else{ - if((FMC_STAT & (uint32_t)0xEF) != (uint32_t)0x00){ - fmc_state = FMC_PGERR; - }else{ - if((FMC_STAT & FMC_FLAG_OPERR) != (uint32_t)0x00){ - fmc_state = FMC_OPERR; - }else{ - fmc_state = FMC_READY; - } - } - } - } + } else if(RESET != (temp_val & FMC_FLAG_RDDERR)) { + fmc_state = FMC_RDDERR; + } else if(RESET != (temp_val & FMC_FLAG_PGSERR)) { + fmc_state = FMC_PGSERR; + } else if(RESET != (temp_val & FMC_FLAG_PGMERR)) { + fmc_state = FMC_PGMERR; + } else if(RESET != (temp_val & FMC_FLAG_WPERR)) { + fmc_state = FMC_WPERR; + } else if(RESET != (temp_val & FMC_FLAG_OPERR)) { + fmc_state = FMC_OPERR; + } else { + fmc_state = FMC_READY; } + /* return the FMC state */ return fmc_state; } /*! - \brief check whether FMC is ready or not + \brief check whether FMC is ready or not \param[in] none \param[out] none \retval state of FMC @@ -915,17 +1026,22 @@ fmc_state_enum fmc_state_get(void) \arg FMC_PGMERR: program size not match error \arg FMC_WPERR: erase/program protection error \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error + \arg FMC_TOERR: timeout error */ -fmc_state_enum fmc_ready_wait(void) +fmc_state_enum fmc_ready_wait(uint32_t timeout) { fmc_state_enum fmc_state = FMC_BUSY; /* wait for FMC ready */ - do{ + do { /* get FMC state */ fmc_state = fmc_state_get(); - }while(FMC_BUSY == fmc_state); + timeout--; + } while((FMC_BUSY == fmc_state) && (0U != timeout)); + + if(0U == timeout) { + fmc_state = FMC_TOERR; + } /* return the FMC state */ return fmc_state; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c index 04e2c5b99d..4240327bd8 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c @@ -5,44 +5,40 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f4xx_fwdgt.h" -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - /*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD + \brief enable write access to FWDGT_PSC and FWDGT_RLD \param[in] none \param[out] none \retval none @@ -53,7 +49,7 @@ void fwdgt_write_enable(void) } /*! - \brief disable write access to FWDGT_PSC and FWDGT_RLD + \brief disable write access to FWDGT_PSC and FWDGT_RLD \param[in] none \param[out] none \retval none @@ -64,7 +60,7 @@ void fwdgt_write_disable(void) } /*! - \brief start the free watchdog timer counter + \brief start the free watchdog timer counter \param[in] none \param[out] none \retval none @@ -75,7 +71,72 @@ void fwdgt_enable(void) } /*! - \brief reload the counter of FWDGT + \brief configure the free watchdog timer counter prescaler value + \param[in] prescaler_value: specify prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_value; + + return SUCCESS; +} + +/*! + \brief configure the free watchdog timer counter reload value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value) +{ + uint32_t timeout = FWDGT_RLD_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + return SUCCESS; +} + +/*! + \brief reload the counter of FWDGT \param[in] none \param[out] none \retval none @@ -86,7 +147,7 @@ void fwdgt_counter_reload(void) } /*! - \brief configure counter reload value, and prescaler divider value + \brief configure counter reload value, and prescaler divider value \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) \param[in] prescaler_div: FWDGT prescaler value only one parameter can be selected which is shown as below: @@ -104,15 +165,15 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) { uint32_t timeout = FWDGT_PSC_TIMEOUT; uint32_t flag_status = RESET; - + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - + /* wait until the PUD flag to be reset */ do{ flag_status = FWDGT_STAT & FWDGT_STAT_PUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - + if ((uint32_t)RESET != flag_status){ return ERROR; } @@ -125,13 +186,13 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) do{ flag_status = FWDGT_STAT & FWDGT_STAT_RUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - + if ((uint32_t)RESET != flag_status){ return ERROR; } - + FWDGT_RLD = RLD_RLD(reload_value); - + /* reload the counter */ FWDGT_CTL = FWDGT_KEY_RELOAD; @@ -139,8 +200,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) } /*! - \brief get flag state of FWDGT - \param[in] flag: flag to get + \brief get flag state of FWDGT + \param[in] flag: flag to get only one parameter can be selected which is shown as below: \arg FWDGT_STAT_PUD: a write operation to FWDGT_PSC register is on going \arg FWDGT_STAT_RUD: a write operation to FWDGT_RLD register is on going diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c index d3693abb17..f9dbc4d716 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -46,7 +47,7 @@ OF SUCH DAMAGE. */ void gpio_deinit(uint32_t gpio_periph) { - switch(gpio_periph){ + switch(gpio_periph) { case GPIOA: /* reset GPIOA */ rcu_periph_reset_enable(RCU_GPIOARST); @@ -125,8 +126,8 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u ctl = GPIO_CTL(gpio_periph); pupd = GPIO_PUD(gpio_periph); - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { /* clear the specified pin mode bits */ ctl &= ~GPIO_MODE_MASK(i); /* set the specified pin mode bits */ @@ -155,7 +156,7 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u \arg GPIO_OSPEED_2MHZ: output max speed 2MHz \arg GPIO_OSPEED_25MHZ: output max speed 25MHz \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \arg GPIO_OSPEED_200MHZ: output max speed 200MHz + \arg GPIO_OSPEED_MAX: output max speed more than 50MHz \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL @@ -167,28 +168,28 @@ void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed uint16_t i; uint32_t ospeedr; - if(GPIO_OTYPE_OD == otype){ + if(GPIO_OTYPE_OD == otype) { GPIO_OMODE(gpio_periph) |= (uint32_t)pin; - }else{ + } else { GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); } /* get the specified pin output speed bits value */ ospeedr = GPIO_OSPD(gpio_periph); - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { /* clear the specified pin output speed bits */ ospeedr &= ~GPIO_OSPEED_MASK(i); /* set the specified pin output speed bits */ - ospeedr |= GPIO_OSPEED_SET(i,speed); + ospeedr |= GPIO_OSPEED_SET(i, speed); } } GPIO_OSPD(gpio_periph) = ospeedr; } /*! - \brief set GPIO pin bit + \brief set GPIO pin bit \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) @@ -235,9 +236,9 @@ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) */ void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) { - if(RESET != bit_value){ + if(RESET != bit_value) { GPIO_BOP(gpio_periph) = (uint32_t)pin; - }else{ + } else { GPIO_BC(gpio_periph) = (uint32_t)pin; } } @@ -269,9 +270,9 @@ void gpio_port_write(uint32_t gpio_periph, uint16_t data) */ FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) { - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { return SET; - }else{ + } else { return RESET; } } @@ -302,15 +303,15 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph) */ FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) { - if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ + if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief get GPIO all pins output status + \brief get GPIO port output status \param[in] gpio_periph: GPIO port only one parameter can be selected which is shown as below: \arg GPIOx(x = A,B,C,D,E,F,G,H,I) @@ -334,10 +335,10 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) \arg GPIO_AF_3: TIMER7, TIMER8, TIMER9, TIMER10 \arg GPIO_AF_4: I2C0, I2C1, I2C2 \arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5 - \arg GPIO_AF_6: SPI1, SPI2, SAI0 - \arg GPIO_AF_7: USART0, USART1, USART2 + \arg GPIO_AF_6: SPI2, SPI3, SPI4 + \arg GPIO_AF_7: USART0, USART1, USART2, SPI1, SPI2 \arg GPIO_AF_8: UART3, UART4, USART5, UART6, UART7 - \arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13 + \arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13, I2C1, I2C2, CTC \arg GPIO_AF_10: USB_FS, USB_HS \arg GPIO_AF_11: ENET \arg GPIO_AF_12: EXMC, SDIO, USB_HS @@ -358,19 +359,19 @@ void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) afrl = GPIO_AFSEL0(gpio_periph); afrh = GPIO_AFSEL1(gpio_periph); - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ + for(i = 0U; i < 8U; i++) { + if((1U << i) & pin) { /* clear the specified pin alternate function bits */ afrl &= ~GPIO_AFR_MASK(i); - afrl |= GPIO_AFR_SET(i,alt_func_num); + afrl |= GPIO_AFR_SET(i, alt_func_num); } } - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ + for(i = 8U; i < 16U; i++) { + if((1U << i) & pin) { /* clear the specified pin alternate function bits */ afrh &= ~GPIO_AFR_MASK(i - 8U); - afrh |= GPIO_AFR_SET(i - 8U,alt_func_num); + afrh |= GPIO_AFR_SET(i - 8U, alt_func_num); } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c index c3ac50c178..97988e8c3d 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c @@ -6,10 +6,11 @@ \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2019-04-16, V2.0.2, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -38,14 +39,14 @@ OF SUCH DAMAGE. #include "gd32f4xx_i2c.h" /* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x00000032U) /*!< i2cclk maximum value */ +#define I2CCLK_MAX ((uint32_t)0x0000003CU) /*!< i2cclk maximum value */ #define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ #define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ #define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ #define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ /* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ +#define STAT1_PECV_OFFSET ((uint32_t)0x00000008U) /* bit offset of PECV in I2C_STAT1 */ /*! \brief reset I2C @@ -55,7 +56,7 @@ OF SUCH DAMAGE. */ void i2c_deinit(uint32_t i2c_periph) { - switch(i2c_periph){ + switch(i2c_periph) { case I2C0: /* reset I2C0 */ rcu_periph_reset_enable(RCU_I2C0RST); @@ -82,8 +83,8 @@ void i2c_deinit(uint32_t i2c_periph) \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) \param[in] dutycyc: duty cycle in fast mode only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \arg I2C_DTCY_2: T_low/T_high = 2 in fast mode + \arg I2C_DTCY_16_9: T_low/T_high = 16/9 in fast mode \param[out] none \retval none */ @@ -94,8 +95,8 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) pclk1 = rcu_clock_freq_get(CK_APB1); /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1/1000000U); - if(freq >= I2CCLK_MAX){ + freq = (uint32_t)(pclk1 / 1000000U); + if(freq >= I2CCLK_MAX) { freq = I2CCLK_MAX; } temp = I2C_CTL1(i2c_periph); @@ -104,41 +105,43 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) I2C_CTL1(i2c_periph) = temp; - if(100000U >= clkspeed){ + if(100000U >= clkspeed) { /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1/1000000U)+1U); - if(risetime >= I2CCLK_MAX){ + risetime = (uint32_t)((pclk1 / 1000000U) + 1U); + if(risetime >= I2CCLK_MAX) { I2C_RT(i2c_periph) = I2CCLK_MAX; - }else{ + } else if(risetime <= I2CCLK_MIN) { + I2C_RT(i2c_periph) = I2CCLK_MIN; + } else { I2C_RT(i2c_periph) = risetime; } - clkc = (uint32_t)(pclk1/(clkspeed*2U)); - if(clkc < 0x04U){ + clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); + if(clkc < 0x04U) { /* the CLKC in standard mode minmum value is 4 */ clkc = 0x04U; } I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - }else if(400000U >= clkspeed){ + } else if(400000U >= clkspeed) { /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); + if(I2C_DTCY_2 == dutycyc) { /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ + } else { /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; } - if(0U == (clkc & I2C_CKCFG_CLKC)){ + if(0U == (clkc & I2C_CKCFG_CLKC)) { /* the CLKC in fast mode minmum value is 1 */ clkc |= 0x0001U; } I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; I2C_CKCFG(i2c_periph) |= clkc; - }else{ + } else { } } @@ -151,8 +154,8 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) \arg I2C_SMBUSMODE_ENABLE: SMBus mode \param[in] addformat: 7bits or 10bits only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits + \arg I2C_ADDFORMAT_7BITS: address format is 7 bits + \arg I2C_ADDFORMAT_10BITS: address format is 10 bits \param[in] addr: I2C address \param[out] none \retval none @@ -172,20 +175,20 @@ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat } /*! - \brief SMBus type selection + \brief select SMBus type \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] type: only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host + \arg I2C_SMBUS_DEVICE: SMBus mode device type + \arg I2C_SMBUS_HOST: SMBus mode host type \param[out] none \retval none */ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) { - if(I2C_SMBUS_HOST == type){ + if(I2C_SMBUS_HOST == type) { I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - }else{ + } else { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); } } @@ -202,11 +205,12 @@ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) */ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) { - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ACKEN); + ctl |= ack; + I2C_CTL0(i2c_periph) = ctl; } /*! @@ -214,19 +218,19 @@ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pos: only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \arg I2C_ACKPOS_CURRENT: ACKEN bit decides whether or not to send ACK or not for the current byte + \arg I2C_ACKPOS_NEXT: ACKEN bit decides whether or not to send ACK for the next byte \param[out] none \retval none */ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) { + uint32_t ctl = 0U; /* configure I2C POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_POAP); + ctl |= pos; + I2C_CTL0(i2c_periph) = ctl; } /*! @@ -236,16 +240,16 @@ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) \param[in] trandirection: transmitter or receiver only one parameter can be selected which is shown as below: \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver + \arg I2C_RECEIVER: receiver \param[out] none \retval none */ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) { /* master is a transmitter or a receiver */ - if(I2C_TRANSMITTER == trandirection){ + if(I2C_TRANSMITTER == trandirection) { addr = addr & I2C_TRANSMITTER; - }else{ + } else { addr = addr | I2C_RECEIVER; } /* send slave address */ @@ -345,16 +349,16 @@ uint8_t i2c_data_receive(uint32_t i2c_periph) } /*! - \brief enable I2C DMA mode + \brief configure I2C DMA mode \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] dmastate: only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable + \arg I2C_DMA_ON: enable DMA mode + \arg I2C_DMA_OFF: disable DMA mode \param[out] none \retval none */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate) { /* configure I2C DMA function */ uint32_t ctl = 0U; @@ -391,14 +395,14 @@ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] stretchpara: only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \arg I2C_SCLSTRETCH_ENABLE: enable SCL stretching + \arg I2C_SCLSTRETCH_DISABLE: disable SCL stretching \param[out] none \retval none */ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) { - /* configure I2C SCL strerching enable or disable */ + /* configure I2C SCL strerching */ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); @@ -429,7 +433,7 @@ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) } /*! - \brief software reset I2C + \brief configure software reset of I2C \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] sreset: only one parameter can be selected which is shown as below: @@ -450,7 +454,7 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) } /*! - \brief I2C PEC calculation on or off + \brief configure I2C PEC calculation \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pecstate: only one parameter can be selected which is shown as below: @@ -459,7 +463,7 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) \param[out] none \retval none */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate) { /* on/off PEC calculation */ uint32_t ctl = 0U; @@ -471,16 +475,16 @@ void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) } /*! - \brief I2C whether to transfer PEC value + \brief configure whether to transfer PEC value \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pecpara: only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC + \arg I2C_PECTRANS_ENABLE: transfer PEC value + \arg I2C_PECTRANS_DISABLE: not transfer PEC value \param[out] none \retval none */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara) { /* whether to transfer PEC */ uint32_t ctl = 0U; @@ -499,11 +503,11 @@ void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) */ uint8_t i2c_pec_value_get(uint32_t i2c_periph) { - return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET); + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); } /*! - \brief I2C issue alert through SMBA pin + \brief configure I2C alert through SMBA pin \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] smbuspara: only one parameter can be selected which is shown as below: @@ -512,9 +516,9 @@ uint8_t i2c_pec_value_get(uint32_t i2c_periph) \param[out] none \retval none */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara) { - /* issue alert through SMBA pin configure*/ + /* configure smubus alert through SMBA pin */ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); @@ -524,7 +528,7 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) } /*! - \brief enable or disable I2C ARP protocol in SMBus switch + \brief configure I2C ARP protocol in SMBus \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] arpstate: only one parameter can be selected which is shown as below: @@ -533,7 +537,7 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) \param[out] none \retval none */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate) { /* enable or disable I2C ARP protocol*/ uint32_t ctl = 0U; @@ -545,7 +549,7 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) } /*! - \brief analog noise filter disable + \brief disable analog noise filter \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none @@ -556,7 +560,7 @@ void i2c_analog_noise_filter_disable(uint32_t i2c_periph) } /*! - \brief analog noise filter enable + \brief enable analog noise filter \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none @@ -567,13 +571,30 @@ void i2c_analog_noise_filter_enable(uint32_t i2c_periph) } /*! - \brief digital noise filter configuration + \brief configure digital noise filter \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dfilterpara: refer to enum i2c_digital_filter_enum + \param[in] dfilterpara: refer to i2c_digital_filter_enum + only one parameter can be selected which is shown as below: + \arg I2C_DF_DISABLE: disable digital noise filter + \arg I2C_DF_1PCLK: enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 + \arg I2C_DF_2PCLK: enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 + \arg I2C_DF_3PCLK: enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 + \arg I2C_DF_4PCLK: enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 + \arg I2C_DF_5PCLK: enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 + \arg I2C_DF_6PCLK: enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 + \arg I2C_DF_7PCLK: enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 + \arg I2C_DF_8PCLK: enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 + \arg I2C_DF_9PCLK: enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 + \arg I2C_DF_10PCLK: enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 + \arg I2C_DF_11CLK: enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 + \arg I2C_DF_12CLK: enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 + \arg I2C_DF_13PCLK: enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 + \arg I2C_DF_14PCLK: enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 + \arg I2C_DF_15PCLK: enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 \param[out] none \retval none */ -void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara) +void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara) { I2C_FCTL(i2c_periph) |= dfilterpara; } @@ -623,27 +644,27 @@ void i2c_sam_timeout_disable(uint32_t i2c_periph) } /*! - \brief check I2C flag is set or not + \brief get I2C flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] flag: I2C flags, refer to i2c_flag_enum only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_SBSEND: start condition sent out in master mode \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode \arg I2C_FLAG_BTC: byte transmission finishes \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus \arg I2C_FLAG_LOSTARB: arbitration lost in master mode \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode \arg I2C_FLAG_PECERR: PEC error when receiving data \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode \arg I2C_FLAG_SMBALT: SMBus alert status \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver \arg I2C_FLAG_RXGC: general call address (00h) received \arg I2C_FLAG_DEFSMB: default address of SMBus device \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode @@ -657,26 +678,26 @@ void i2c_sam_timeout_disable(uint32_t i2c_periph) */ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) { - if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear I2C flag + \brief clear I2C flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] flag: I2C flags, refer to i2c_flag_enum only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBALT: SMBus alert status \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode \arg I2C_FLAG_PECERR: PEC error when receiving data \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode \arg I2C_FLAG_AERR: acknowledge error \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode \arg I2C_FLAG_TFF: txframe fall flag \arg I2C_FLAG_TFR: txframe rise flag \arg I2C_FLAG_RFF: rxframe fall flag @@ -686,11 +707,11 @@ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) */ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) { - if(I2C_FLAG_ADDSEND == flag){ + if(I2C_FLAG_ADDSEND == flag) { /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ I2C_STAT0(i2c_periph); I2C_STAT1(i2c_periph); - }else{ + } else { I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); } } @@ -700,13 +721,13 @@ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt \param[out] none \retval none */ @@ -718,15 +739,15 @@ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) /*! \brief disable I2C interrupt \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt \param[out] none \retval none */ @@ -736,15 +757,15 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) } /*! - \brief check I2C interrupt flag + \brief get I2C interrupt flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_BTC: byte transmission finishes interrupt flag \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag @@ -753,7 +774,7 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag @@ -773,22 +794,22 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i /* get the corresponding flag bit status */ flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ - if(intenable && bufie){ + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { + if(intenable && bufie) { intenable = 1U; - }else{ + } else { intenable = 0U; } } - if((0U != flagstatus) && (0U != intenable)){ + if((0U != flagstatus) && (0U != intenable)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear I2C interrupt flag + \brief clear I2C interrupt flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum only one parameter can be selected which is shown as below: @@ -799,7 +820,7 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag @@ -809,11 +830,11 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i */ void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { - if(I2C_INT_FLAG_ADDSEND == int_flag){ + if(I2C_INT_FLAG_ADDSEND == int_flag) { /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ I2C_STAT0(i2c_periph); I2C_STAT1(i2c_periph); - }else{ + } else { I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c index 5afcc48e0d..afee8e5947 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -39,7 +40,7 @@ OF SUCH DAMAGE. #define IPA_DEFAULT_VALUE 0x00000000U /*! - \brief deinitialize IPA registers + \brief deinitialize IPA registers \param[in] none \param[out] none \retval none @@ -51,7 +52,7 @@ void ipa_deinit(void) } /*! - \brief enable IPA transfer + \brief enable IPA transfer \param[in] none \param[out] none \retval none @@ -62,7 +63,7 @@ void ipa_transfer_enable(void) } /*! - \brief enable IPA transfer hang up + \brief enable IPA transfer hang up \param[in] none \param[out] none \retval none @@ -73,7 +74,7 @@ void ipa_transfer_hangup_enable(void) } /*! - \brief disable IPA transfer hang up + \brief disable IPA transfer hang up \param[in] none \param[out] none \retval none @@ -84,7 +85,7 @@ void ipa_transfer_hangup_disable(void) } /*! - \brief enable IPA transfer stop + \brief enable IPA transfer stop \param[in] none \param[out] none \retval none @@ -95,7 +96,7 @@ void ipa_transfer_stop_enable(void) } /*! - \brief disable IPA transfer stop + \brief disable IPA transfer stop \param[in] none \param[out] none \retval none @@ -105,7 +106,7 @@ void ipa_transfer_stop_disable(void) IPA_CTL &= ~(IPA_CTL_TST); } /*! - \brief enable IPA foreground LUT loading + \brief enable IPA foreground LUT loading \param[in] none \param[out] none \retval none @@ -116,7 +117,7 @@ void ipa_foreground_lut_loading_enable(void) } /*! - \brief enable IPA background LUT loading + \brief enable IPA background LUT loading \param[in] none \param[out] none \retval none @@ -127,7 +128,7 @@ void ipa_background_lut_loading_enable(void) } /*! - \brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled + \brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled \param[in] pfcm: pixel format convert mode only one parameter can be selected which is shown as below: \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert @@ -139,11 +140,12 @@ void ipa_background_lut_loading_enable(void) */ void ipa_pixel_format_convert_mode_set(uint32_t pfcm) { + IPA_CTL &= ~(IPA_CTL_PFCM); IPA_CTL |= pfcm; } /*! - \brief initialize the structure of IPA foreground parameter struct with the default values, it is + \brief initialize the structure of IPA foreground parameter struct with the default values, it is suggested that call this function after an ipa_foreground_parameter_struct structure is defined \param[in] none \param[out] foreground_struct: the data needed to initialize foreground @@ -159,7 +161,7 @@ void ipa_pixel_format_convert_mode_set(uint32_t pfcm) foreground_preblue: foreground pre-defined blue value \retval none */ -void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct) +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct) { /* initialize the struct parameters with default values */ foreground_struct->foreground_memaddr = IPA_DEFAULT_VALUE; @@ -173,7 +175,7 @@ void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground } /*! - \brief initialize foreground parameters + \brief initialize foreground parameters \param[in] foreground_struct: the data needed to initialize foreground foreground_memaddr: foreground memory base address foreground_lineoff: foreground line offset @@ -188,10 +190,10 @@ void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground \param[out] none \retval none */ -void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) +void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct) { FlagStatus tempflag = RESET; - if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { tempflag = SET; /* reset the TEN in order to configure the following bits */ IPA_CTL &= ~IPA_CTL_TEN; @@ -204,23 +206,23 @@ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) IPA_FLOFF &= ~(IPA_FLOFF_FLOFF); IPA_FLOFF = foreground_struct->foreground_lineoff; /* foreground pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_FPCTL &= ~(IPA_FPCTL_FPDAV|IPA_FPCTL_FAVCA|IPA_FPCTL_FPF); - IPA_FPCTL |= (foreground_struct->foreground_prealpha<<24U); + IPA_FPCTL &= ~(IPA_FPCTL_FPDAV | IPA_FPCTL_FAVCA | IPA_FPCTL_FPF); + IPA_FPCTL |= (foreground_struct->foreground_prealpha << 24U); IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm; IPA_FPCTL |= foreground_struct->foreground_pf; /* foreground pre-defined red green blue configuration */ - IPA_FPV &= ~(IPA_FPV_FPDRV|IPA_FPV_FPDGV|IPA_FPV_FPDBV); - IPA_FPV |= ((foreground_struct->foreground_prered<<16U)|(foreground_struct->foreground_pregreen<<8U) - |(foreground_struct->foreground_preblue)); + IPA_FPV &= ~(IPA_FPV_FPDRV | IPA_FPV_FPDGV | IPA_FPV_FPDBV); + IPA_FPV |= ((foreground_struct->foreground_prered << 16U) | (foreground_struct->foreground_pregreen << 8U) + | (foreground_struct->foreground_preblue)); - if(SET == tempflag){ + if(SET == tempflag) { /* restore the state of TEN */ IPA_CTL |= IPA_CTL_TEN; } } /*! - \brief initialize the structure of IPA background parameter struct with the default values, it is + \brief initialize the structure of IPA background parameter struct with the default values, it is suggested that call this function after an ipa_background_parameter_struct structure is defined \param[in] none \param[out] background_struct: the data needed to initialize background @@ -236,7 +238,7 @@ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) background_preblue: background pre-defined blue value \retval none */ -void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct) +void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct) { /* initialize the struct parameters with default values */ background_struct->background_memaddr = IPA_DEFAULT_VALUE; @@ -250,7 +252,7 @@ void ipa_background_struct_para_init(ipa_background_parameter_struct* background } /*! - \brief initialize background parameters + \brief initialize background parameters \param[in] background_struct: the data needed to initialize background background_memaddr: background memory base address background_lineoff: background line offset @@ -265,10 +267,10 @@ void ipa_background_struct_para_init(ipa_background_parameter_struct* background \param[out] none \retval none */ -void ipa_background_init(ipa_background_parameter_struct* background_struct) +void ipa_background_init(ipa_background_parameter_struct *background_struct) { FlagStatus tempflag = RESET; - if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { tempflag = SET; /* reset the TEN in order to configure the following bits */ IPA_CTL &= ~IPA_CTL_TEN; @@ -281,23 +283,23 @@ void ipa_background_init(ipa_background_parameter_struct* background_struct) IPA_BLOFF &= ~(IPA_BLOFF_BLOFF); IPA_BLOFF = background_struct->background_lineoff; /* background pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_BPCTL &= ~(IPA_BPCTL_BPDAV|IPA_BPCTL_BAVCA|IPA_BPCTL_BPF); - IPA_BPCTL |= (background_struct->background_prealpha<<24U); + IPA_BPCTL &= ~(IPA_BPCTL_BPDAV | IPA_BPCTL_BAVCA | IPA_BPCTL_BPF); + IPA_BPCTL |= (background_struct->background_prealpha << 24U); IPA_BPCTL |= background_struct->background_alpha_algorithm; IPA_BPCTL |= background_struct->background_pf; /* background pre-defined red green blue configuration */ - IPA_BPV &= ~(IPA_BPV_BPDRV|IPA_BPV_BPDGV|IPA_BPV_BPDBV); - IPA_BPV |= ((background_struct->background_prered<<16U)|(background_struct->background_pregreen<<8U) - |(background_struct->background_preblue)); + IPA_BPV &= ~(IPA_BPV_BPDRV | IPA_BPV_BPDGV | IPA_BPV_BPDBV); + IPA_BPV |= ((background_struct->background_prered << 16U) | (background_struct->background_pregreen << 8U) + | (background_struct->background_preblue)); - if(SET == tempflag){ + if(SET == tempflag) { /* restore the state of TEN */ IPA_CTL |= IPA_CTL_TEN; } } /*! - \brief initialize the structure of IPA destination parameter struct with the default values, it is + \brief initialize the structure of IPA destination parameter struct with the default values, it is suggested that call this function after an ipa_destination_parameter_struct structure is defined \param[in] none \param[out] destination_struct: the data needed to initialize destination parameter @@ -313,7 +315,7 @@ void ipa_background_init(ipa_background_parameter_struct* background_struct) image_height: height of the image to be processed \retval none */ -void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct) +void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct) { /* initialize the struct parameters with default values */ destination_struct->destination_pf = IPA_DPF_ARGB8888; @@ -328,7 +330,7 @@ void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destinat } /*! - \brief initialize destination parameters + \brief initialize destination parameters \param[in] destination_struct: the data needed to initialize destination parameters destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, IPA_DPF_ARGB4444,refer to ipa_dpf_enum @@ -343,11 +345,11 @@ void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destinat \param[out] none \retval none */ -void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) +void ipa_destination_init(ipa_destination_parameter_struct *destination_struct) { uint32_t destination_pixelformat; FlagStatus tempflag = RESET; - if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + if(RESET != (IPA_CTL & IPA_CTL_TEN)) { tempflag = SET; /* reset the TEN in order to configure the following bits */ IPA_CTL &= ~IPA_CTL_TEN; @@ -358,38 +360,38 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) IPA_DPCTL = destination_struct->destination_pf; destination_pixelformat = destination_struct->destination_pf; /* destination pixel format ARGB8888 */ - switch(destination_pixelformat){ + switch(destination_pixelformat) { case IPA_DPF_ARGB8888: - IPA_DPV &= ~(IPA_DPV_DPDBV_0|(IPA_DPV_DPDGV_0)|(IPA_DPV_DPDRV_0)|(IPA_DPV_DPDAV_0)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<8U) - |(destination_struct->destination_prered<<16U) - |(destination_struct->destination_prealpha<<24U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_0 | (IPA_DPV_DPDGV_0) | (IPA_DPV_DPDRV_0) | (IPA_DPV_DPDAV_0)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U) + | (destination_struct->destination_prered << 16U) + | (destination_struct->destination_prealpha << 24U)); break; /* destination pixel format RGB888 */ case IPA_DPF_RGB888: - IPA_DPV &= ~(IPA_DPV_DPDBV_1|(IPA_DPV_DPDGV_1)|(IPA_DPV_DPDRV_1)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<8U) - |(destination_struct->destination_prered<<16U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_1 | (IPA_DPV_DPDGV_1) | (IPA_DPV_DPDRV_1)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U) + | (destination_struct->destination_prered << 16U)); break; /* destination pixel format RGB565 */ case IPA_DPF_RGB565: - IPA_DPV &= ~(IPA_DPV_DPDBV_2|(IPA_DPV_DPDGV_2)|(IPA_DPV_DPDRV_2)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<5U) - |(destination_struct->destination_prered<<11U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_2 | (IPA_DPV_DPDGV_2) | (IPA_DPV_DPDRV_2)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 5U) + | (destination_struct->destination_prered << 11U)); break; /* destination pixel format ARGB1555 */ case IPA_DPF_ARGB1555: - IPA_DPV &= ~(IPA_DPV_DPDBV_3|(IPA_DPV_DPDGV_3)|(IPA_DPV_DPDRV_3)|(IPA_DPV_DPDAV_3)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<5U) - |(destination_struct->destination_prered<<10U) - |(destination_struct->destination_prealpha<<15U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_3 | (IPA_DPV_DPDGV_3) | (IPA_DPV_DPDRV_3) | (IPA_DPV_DPDAV_3)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 5U) + | (destination_struct->destination_prered << 10U) + | (destination_struct->destination_prealpha << 15U)); break; /* destination pixel format ARGB4444 */ case IPA_DPF_ARGB4444: - IPA_DPV &= ~(IPA_DPV_DPDBV_4|(IPA_DPV_DPDGV_4)|(IPA_DPV_DPDRV_4)|(IPA_DPV_DPDAV_4)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<4U) - |(destination_struct->destination_prered<<8U) - |(destination_struct->destination_prealpha<<12U)); + IPA_DPV &= ~(IPA_DPV_DPDBV_4 | (IPA_DPV_DPDGV_4) | (IPA_DPV_DPDRV_4) | (IPA_DPV_DPDAV_4)); + IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 4U) + | (destination_struct->destination_prered << 8U) + | (destination_struct->destination_prealpha << 12U)); break; default: break; @@ -399,19 +401,19 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) IPA_DMADDR = destination_struct->destination_memaddr; /* destination line offset configuration */ IPA_DLOFF &= ~(IPA_DLOFF_DLOFF); - IPA_DLOFF =destination_struct->destination_lineoff; + IPA_DLOFF = destination_struct->destination_lineoff; /* image size configuration */ - IPA_IMS &= ~(IPA_IMS_HEIGHT|IPA_IMS_WIDTH); - IPA_IMS |= ((destination_struct->image_width<<16U)|(destination_struct->image_height)); + IPA_IMS &= ~(IPA_IMS_HEIGHT | IPA_IMS_WIDTH); + IPA_IMS |= ((destination_struct->image_width << 16U) | (destination_struct->image_height)); - if(SET == tempflag){ + if(SET == tempflag) { /* restore the state of TEN */ IPA_CTL |= IPA_CTL_TEN; } } /*! - \brief initialize IPA foreground LUT parameters + \brief initialize IPA foreground LUT parameters \param[in] fg_lut_num: foreground LUT number of pixel \param[in] fg_lut_pf: foreground LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) \param[in] fg_lut_addr: foreground LUT memory base address @@ -421,32 +423,32 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr) { FlagStatus tempflag = RESET; - if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)){ + if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)) { tempflag = SET; /* reset the FLLEN in order to configure the following bits */ IPA_FPCTL &= ~IPA_FPCTL_FLLEN; } /* foreground LUT number of pixel configuration */ - IPA_FPCTL |= ((uint32_t)fg_lut_num<<8U); + IPA_FPCTL |= ((uint32_t)fg_lut_num << 8U); /* foreground LUT pixel format configuration */ - if(IPA_LUT_PF_RGB888 == fg_lut_pf){ + if(IPA_LUT_PF_RGB888 == fg_lut_pf) { IPA_FPCTL |= IPA_FPCTL_FLPF; - }else{ + } else { IPA_FPCTL &= ~(IPA_FPCTL_FLPF); } /* foreground LUT memory base address configuration */ IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR); IPA_FLMADDR = fg_lut_addr; - if(SET == tempflag){ + if(SET == tempflag) { /* restore the state of FLLEN */ IPA_FPCTL |= IPA_FPCTL_FLLEN; } } /*! - \brief initialize IPA background LUT parameters + \brief initialize IPA background LUT parameters \param[in] bg_lut_num: background LUT number of pixel \param[in] bg_lut_pf: background LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) \param[in] bg_lut_addr: background LUT memory base address @@ -456,32 +458,32 @@ void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_ void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr) { FlagStatus tempflag = RESET; - if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)){ + if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)) { tempflag = SET; /* reset the BLLEN in order to configure the following bits */ IPA_BPCTL &= ~IPA_BPCTL_BLLEN; } /* background LUT number of pixel configuration */ - IPA_BPCTL |= ((uint32_t)bg_lut_num<<8U); + IPA_BPCTL |= ((uint32_t)bg_lut_num << 8U); /* background LUT pixel format configuration */ - if(IPA_LUT_PF_RGB888 == bg_lut_pf){ + if(IPA_LUT_PF_RGB888 == bg_lut_pf) { IPA_BPCTL |= IPA_BPCTL_BLPF; - }else{ + } else { IPA_BPCTL &= ~(IPA_BPCTL_BLPF); } /* background LUT memory base address configuration */ IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR); IPA_BLMADDR = bg_lut_addr; - if(SET == tempflag){ + if(SET == tempflag) { /* restore the state of BLLEN */ IPA_BPCTL |= IPA_BPCTL_BLLEN; } } /*! - \brief configure IPA line mark + \brief configure IPA line mark \param[in] line_num: line number \param[out] none \retval none @@ -493,22 +495,22 @@ void ipa_line_mark_config(uint16_t line_num) } /*! - \brief inter-timer enable or disable + \brief inter-timer enable or disable \param[in] timer_cfg: IPA_INTER_TIMER_ENABLE,IPA_INTER_TIMER_DISABLE \param[out] none \retval none */ void ipa_inter_timer_config(uint8_t timer_cfg) { - if(IPA_INTER_TIMER_ENABLE == timer_cfg){ + if(IPA_INTER_TIMER_ENABLE == timer_cfg) { IPA_ITCTL |= IPA_ITCTL_ITEN; - }else{ + } else { IPA_ITCTL &= ~(IPA_ITCTL_ITEN); } } /*! - \brief configure the number of clock cycles interval + \brief configure the number of clock cycles interval \param[in] clk_num: the number of clock cycles \param[out] none \retval none @@ -517,11 +519,11 @@ void ipa_interval_clock_num_config(uint8_t clk_num) { /* NCCI[7:0] bits have no meaning if ITEN is '0' */ IPA_ITCTL &= ~(IPA_ITCTL_NCCI); - IPA_ITCTL |= ((uint32_t)clk_num<<8U); + IPA_ITCTL |= ((uint32_t)clk_num << 8U); } /*! - \brief get IPA flag status in IPA_INTF register + \brief get IPA flag status in IPA_INTF register \param[in] flag: IPA flags one or more parameters can be selected which are shown as below: \arg IPA_FLAG_TAE: transfer access error interrupt flag @@ -535,15 +537,15 @@ void ipa_interval_clock_num_config(uint8_t clk_num) */ FlagStatus ipa_flag_get(uint32_t flag) { - if(RESET != (IPA_INTF & flag)){ + if(RESET != (IPA_INTF & flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear IPA flag in IPA_INTF register + \brief clear IPA flag in IPA_INTF register \param[in] flag: IPA flags one or more parameters can be selected which are shown as below: \arg IPA_FLAG_TAE: transfer access error interrupt flag @@ -561,7 +563,7 @@ void ipa_flag_clear(uint32_t flag) } /*! - \brief enable IPA interrupt + \brief enable IPA interrupt \param[in] int_flag: IPA interrupt flags one or more parameters can be selected which are shown as below: \arg IPA_INT_TAE: transfer access error interrupt @@ -579,7 +581,7 @@ void ipa_interrupt_enable(uint32_t int_flag) } /*! - \brief disable IPA interrupt + \brief disable IPA interrupt \param[in] int_flag: IPA interrupt flags one or more parameters can be selected which are shown as below: \arg IPA_INT_TAE: transfer access error interrupt @@ -597,7 +599,7 @@ void ipa_interrupt_disable(uint32_t int_flag) } /*! - \brief get IPA interrupt flag + \brief get IPA interrupt flag \param[in] int_flag: IPA interrupt flag flags one or more parameters can be selected which are shown as below: \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag @@ -611,15 +613,15 @@ void ipa_interrupt_disable(uint32_t int_flag) */ FlagStatus ipa_interrupt_flag_get(uint32_t int_flag) { - if(0U != (IPA_INTF & int_flag)){ + if(0U != (IPA_INTF & int_flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear IPA interrupt flag + \brief clear IPA interrupt flag \param[in] int_flag: IPA interrupt flag flags one or more parameters can be selected which are shown as below: \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c index 218a070ef4..8702da387a 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,7 +38,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_iref.h" /*! - \brief deinit IREF + \brief deinitialize IREF \param[in] none \param[out] none \retval none @@ -49,7 +50,7 @@ void iref_deinit(void) } /*! - \brief enable IREF + \brief enable IREF \param[in] none \param[out] none \retval none diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c index c826722f13..b35db88d88 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c @@ -1,14 +1,14 @@ /*! \file gd32f4xx_misc.c \brief MISC driver - \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,7 +37,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_misc.h" /*! - \brief set the priority group + \brief set the priority group \param[in] nvic_prigroup: the NVIC priority group \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority @@ -54,7 +54,7 @@ void nvic_priority_group_set(uint32_t nvic_prigroup) } /*! - \brief enable NVIC request + \brief enable NVIC request \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set \param[in] nvic_irq_sub_priority: the subpriority needed to set @@ -66,29 +66,29 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, { uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; /* use the priority group value to get the temp_pre and the temp_sub */ - if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){ - temp_pre=0U; - temp_sub=0x4U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){ - temp_pre=1U; - temp_sub=0x3U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){ - temp_pre=2U; - temp_sub=0x2U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){ - temp_pre=3U; - temp_sub=0x1U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){ - temp_pre=4U; - temp_sub=0x0U; - }else{ + if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE0_SUB4) { + temp_pre = 0U; + temp_sub = 0x4U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE1_SUB3) { + temp_pre = 1U; + temp_sub = 0x3U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE2_SUB2) { + temp_pre = 2U; + temp_sub = 0x2U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE3_SUB1) { + temp_pre = 3U; + temp_sub = 0x1U; + } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE4_SUB0) { + temp_pre = 4U; + temp_sub = 0x0U; + } else { nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); - temp_pre=2U; - temp_sub=0x2U; + temp_pre = 2U; + temp_sub = 0x2U; } /* get the temp_priority to fill the NVIC->IP register */ temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); + temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub)); temp_priority = temp_priority << 0x04U; NVIC->IP[nvic_irq] = (uint8_t)temp_priority; /* enable the selected IRQ */ @@ -96,7 +96,7 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, } /*! - \brief disable NVIC request + \brief disable NVIC request \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type \param[out] none \retval none @@ -108,7 +108,7 @@ void nvic_irq_disable(uint8_t nvic_irq) } /*! - \brief set the NVIC vector table base address + \brief set the NVIC vector table base address \param[in] nvic_vict_tab: the RAM or FLASH base address \arg NVIC_VECTTAB_RAM: RAM base address \are NVIC_VECTTAB_FLASH: Flash base address @@ -119,10 +119,11 @@ void nvic_irq_disable(uint8_t nvic_irq) void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) { SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); + __DSB(); } /*! - \brief set the state of the low power mode + \brief set the state of the low power mode \param[in] lowpower_mode: the low power mode state \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power mode by exiting from ISR @@ -138,7 +139,7 @@ void system_lowpower_set(uint8_t lowpower_mode) } /*! - \brief reset the state of the low power mode + \brief reset the state of the low power mode \param[in] lowpower_mode: the low power mode state \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power mode by exiting from ISR @@ -154,7 +155,7 @@ void system_lowpower_reset(uint8_t lowpower_mode) } /*! - \brief set the systick clock source + \brief set the systick clock source \param[in] systick_clksource: the systick clock source needed to choose \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 @@ -164,10 +165,10 @@ void system_lowpower_reset(uint8_t lowpower_mode) void systick_clksource_set(uint32_t systick_clksource) { - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) { /* set the systick clock source from HCLK */ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - }else{ + } else { /* set the systick clock source from HCLK/8 */ SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c index 05f4cd7c3a..50086e72ca 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -36,8 +37,9 @@ OF SUCH DAMAGE. #include "gd32f4xx_pmu.h" #include "core_cm4.h" + /*! - \brief reset PMU register + \brief reset PMU registers \param[in] none \param[out] none \retval none @@ -75,6 +77,18 @@ void pmu_lvd_select(uint32_t lvdt_n) PMU_CTL |= PMU_CTL_LVDEN; } +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + /*! \brief select LDO output voltage this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL @@ -91,38 +105,6 @@ void pmu_ldo_output_select(uint32_t ldo_output) PMU_CTL |= ldo_output; } -/*! - \brief enable low-driver mode in deep-sleep mode - \param[in] lowdr_mode: - \arg PMU_LOWDRIVER_ENABLE: enable low-driver mode in deep-sleep mode - \arg PMU_LOWDRIVER_DISABLE: disable low-driver mode in deep-sleep mode - \param[out] none - \retval none -*/ -void pmu_low_driver_mode_enable(uint32_t lowdr_mode) -{ - PMU_CTL &= ~PMU_CTL_LDEN; - PMU_CTL |= lowdr_mode; -} - -/*! - \brief switch high-driver mode - this bit set by software only when IRC16M or HXTAL used as system clock - \param[in] highdr_switch: - \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch - \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch - \param[out] none - \retval none -*/ -void pmu_highdriver_switch_select(uint32_t highdr_switch) -{ - /* wait for HDRF flag set */ - while(SET != pmu_flag_get(PMU_FLAG_HDRF)){ - } - PMU_CTL &= ~PMU_CTL_HDS; - PMU_CTL |= highdr_switch; -} - /*! \brief enable high-driver mode this bit set by software only when IRC16M or HXTAL used as system clock @@ -147,47 +129,75 @@ void pmu_highdriver_mode_disable(void) } /*! - \brief disable PMU lvd + \brief switch high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] highdr_switch: + \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch + \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch + \param[out] none + \retval none +*/ +void pmu_highdriver_switch_select(uint32_t highdr_switch) +{ + /* wait for HDRF flag set */ + while(SET != pmu_flag_get(PMU_FLAG_HDRF)) { + } + PMU_CTL &= ~PMU_CTL_HDS; + PMU_CTL |= highdr_switch; +} + +/*! + \brief enable low-driver mode in deep-sleep \param[in] none \param[out] none \retval none */ -void pmu_lvd_disable(void) +void pmu_lowdriver_mode_enable(void) { - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; + PMU_CTL |= PMU_CTL_LDEN; } /*! - \brief low-driver mode when use low power LDO + \brief disable low-driver mode in deep-sleep + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; +} + +/*! + \brief in deep-sleep mode, driver mode when use low power LDO \param[in] mode: \arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO \param[out] none \retval none */ -void pmu_lowdriver_lowpower_config(uint32_t mode) +void pmu_lowpower_driver_config(uint32_t mode) { PMU_CTL &= ~PMU_CTL_LDLP; PMU_CTL |= mode; } /*! - \brief low-driver mode when use normal power LDO + \brief in deep-sleep mode, driver mode when use normal power LDO \param[in] mode: \arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO \param[out] none \retval none */ -void pmu_lowdriver_normalpower_config(uint32_t mode) +void pmu_normalpower_driver_config(uint32_t mode) { PMU_CTL &= ~PMU_CTL_LDNP; PMU_CTL |= mode; } /*! - \brief PMU work at sleep mode + \brief PMU work in sleep mode \param[in] sleepmodecmd: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command @@ -200,89 +210,122 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ + if(WFI_CMD == sleepmodecmd) { __WFI(); - }else{ + } else { __WFE(); } } /*! - \brief PMU work at deepsleep mode + \brief PMU work in deep-sleep mode \param[in] ldo - \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode + \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deep-sleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deep-sleep mode + \param[in] lowdrive: + only one parameter can be selected which is shown as below: + \arg PMU_LOWDRIVER_DISABLE: Low-driver mode disable in deep-sleep mode + \arg PMU_LOWDRIVER_ENABLE: Low-driver mode enable in deep-sleep mode \param[in] deepsleepmodecmd: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command \param[out] none \retval none */ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd) { - static uint32_t reg_snap[ 4 ]; + static uint32_t reg_snap[4]; /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP | PMU_CTL_LDEN | PMU_CTL_LDNP | PMU_CTL_LDLP)); /* set ldolp bit according to pmu_ldo */ PMU_CTL |= ldo; + /* configure low drive mode in deep-sleep mode */ + if(PMU_LOWDRIVER_ENABLE == lowdrive) { + if(PMU_LDO_NORMAL == ldo) { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDNP); + } else { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDLP); + } + } /* set sleepdeep bit of Cortex-M4 system control register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - reg_snap[ 0 ] = REG32( 0xE000E010U ); - reg_snap[ 1 ] = REG32( 0xE000E100U ); - reg_snap[ 2 ] = REG32( 0xE000E104U ); - reg_snap[ 3 ] = REG32( 0xE000E108U ); + reg_snap[0] = REG32(0xE000E010U); + reg_snap[1] = REG32(0xE000E100U); + reg_snap[2] = REG32(0xE000E104U); + reg_snap[3] = REG32(0xE000E108U); - REG32( 0xE000E010U ) &= 0x00010004U; - REG32( 0xE000E180U ) = 0XFF7FF831U; - REG32( 0xE000E184U ) = 0XBFFFF8FFU; - REG32( 0xE000E188U ) = 0xFFFFEFFFU; + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFF7FF831U; + REG32(0xE000E184U) = 0XBFFFF8FFU; + REG32(0xE000E188U) = 0xFFFFEFFFU; - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ + /* select WFI or WFE command to enter deep-sleep mode */ + if(WFI_CMD == deepsleepmodecmd) { __WFI(); - }else{ + } else { __SEV(); __WFE(); __WFE(); } - REG32( 0xE000E010U ) = reg_snap[ 0 ] ; - REG32( 0xE000E100U ) = reg_snap[ 1 ] ; - REG32( 0xE000E104U ) = reg_snap[ 2 ] ; - REG32( 0xE000E108U ) = reg_snap[ 3 ] ; + REG32(0xE000E010U) = reg_snap[0]; + REG32(0xE000E100U) = reg_snap[1]; + REG32(0xE000E104U) = reg_snap[2]; + REG32(0xE000E108U) = reg_snap[3]; /* reset sleepdeep bit of Cortex-M4 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); } /*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command + \brief pmu work in standby mode + \param[in] none \param[out] none \retval none */ -void pmu_to_standbymode(uint8_t standbymodecmd) +void pmu_to_standbymode(void) { - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - /* set stbmod bit */ PMU_CTL |= PMU_CTL_STBMOD; /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - __WFE(); - } + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFFFFFFF7U; + REG32(0xE000E184U) = 0XFFFFFDFFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + + /* select WFI command to enter standby mode */ + __WFI(); +} + +/*! + \brief enable PMU wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(void) +{ + PMU_CS |= PMU_CS_WUPEN; +} + +/*! + \brief disable PMU wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(void) +{ + PMU_CS &= ~PMU_CS_WUPEN; } /*! @@ -300,16 +343,61 @@ void pmu_backup_ldo_config(uint32_t bkp_ldo) } /*! - \brief reset flag bit - \param[in] flag_reset: + \brief enable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable write access to the registers in backup domain + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief get flag state + \param[in] flag: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag + \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag + \arg PMU_FLAG_HDRF: high-driver ready flag + \arg PMU_FLAG_HDSRF: high-driver switch ready flag + \arg PMU_FLAG_LDRF: low-driver mode ready flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + if(PMU_CS & flag) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear flag bit + \param[in] flag: \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag \arg PMU_FLAG_RESET_STANDBY: reset standby flag \param[out] none \retval none */ -void pmu_flag_reset(uint32_t flag_reset) +void pmu_flag_clear(uint32_t flag) { - switch(flag_reset){ + switch(flag) { case PMU_FLAG_RESET_WAKEUP: /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; @@ -322,70 +410,3 @@ void pmu_flag_reset(uint32_t flag_reset) break; } } - -/*! - \brief get flag state - \param[in] pmu_flag: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag - \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag - \arg PMU_FLAG_HDRF: high-driver ready flag - \arg PMU_FLAG_HDSRF: high-driver switch ready flag - \arg PMU_FLAG_LDRF: low-driver mode ready flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t pmu_flag) -{ - if(PMU_CS & pmu_flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief enable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief enable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(void) -{ - PMU_CS |= PMU_CS_WUPEN; -} - -/*! - \brief disable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(void) -{ - PMU_CS &= ~PMU_CS_WUPEN; -} diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c index aecc895a09..42b8aaec80 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -49,7 +50,7 @@ OF SUCH DAMAGE. #define RCU_IRC16M_ADJUST_OFFSET ((uint32_t)3U) /*! - \brief deinitialize the RCU + \brief deinitialize the RCU \param[in] none \param[out] none \retval none @@ -59,14 +60,16 @@ void rcu_deinit(void) /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; rcu_osci_stab_wait(RCU_IRC16M); - /* reset CFG0 register */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_RTCDIV | RCU_CFG0_CKOUT0SEL | RCU_CFG0_I2SSEL | RCU_CFG0_CKOUT0DIV | - RCU_CFG0_CKOUT1DIV | RCU_CFG0_CKOUT1SEL); + RCU_CFG0 &= ~RCU_CFG0_SCS; + /* reset CTL register */ RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN | RCU_CTL_PLLSAIEN); RCU_CTL &= ~(RCU_CTL_HXTALBPS); + /* reset CFG0 register */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_RTCDIV | RCU_CFG0_CKOUT0SEL | RCU_CFG0_I2SSEL | RCU_CFG0_CKOUT0DIV | + RCU_CFG0_CKOUT1DIV | RCU_CFG0_CKOUT1SEL); /* reset PLL register */ RCU_PLL = 0x24003010U; /* reset PLLI2S register */ @@ -80,10 +83,10 @@ void rcu_deinit(void) } /*! - \brief enable the peripherals clock + \brief enable the peripherals clock \param[in] periph: RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC: CRC clock \arg RCU_BKPSRAM: BKPSRAM clock \arg RCU_TCMSRAM: TCMSRAM clock @@ -99,17 +102,17 @@ void rcu_deinit(void) \arg RCU_TRNG: TRNG clock \arg RCU_USBFS: USBFS clock \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx (x=0,1,2,5): USART clock - \arg RCU_UARTx (x=3,4,6,7): UART clock - \arg RCU_I2Cx (x=0,1,2): I2C clock - \arg RCU_CANx (x=0,1): CAN clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock \arg RCU_PMU: PMU clock \arg RCU_DAC: DAC clock \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2): ADC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock \arg RCU_SDIO: SDIO clock \arg RCU_SYSCFG: SYSCFG clock \arg RCU_TLI: TLI clock @@ -124,10 +127,10 @@ void rcu_periph_clock_enable(rcu_periph_enum periph) } /*! - \brief disable the peripherals clock + \brief disable the peripherals clock \param[in] periph: RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC: CRC clock \arg RCU_BKPSRAM: BKPSRAM clock \arg RCU_TCMSRAM: TCMSRAM clock @@ -143,17 +146,17 @@ void rcu_periph_clock_enable(rcu_periph_enum periph) \arg RCU_TRNG: TRNG clock \arg RCU_USBFS: USBFS clock \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx (x=0,1,2,5): USART clock - \arg RCU_UARTx (x=3,4,6,7): UART clock - \arg RCU_I2Cx (x=0,1,2): I2C clock - \arg RCU_CANx (x=0,1): CAN clock + \arg RCU_SPIx (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx (x = 0, 1, 2): I2C clock + \arg RCU_CANx (x = 0, 1): CAN clock \arg RCU_PMU: PMU clock \arg RCU_DAC: DAC clock \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2): ADC clock + \arg RCU_ADCx (x = 0, 1, 2): ADC clock \arg RCU_SDIO: SDIO clock \arg RCU_SYSCFG: SYSCFG clock \arg RCU_TLI: TLI clock @@ -168,10 +171,10 @@ void rcu_periph_clock_disable(rcu_periph_enum periph) } /*! - \brief enable the peripherals clock when sleep mode + \brief enable the peripherals clock when sleep mode \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx_SLP (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC_SLP: CRC clock \arg RCU_FMC_SLP: FMC clock \arg RCU_SRAM0_SLP: SRAM0 clock @@ -190,17 +193,17 @@ void rcu_periph_clock_disable(rcu_periph_enum periph) \arg RCU_TRNG_SLP: TRNG clock \arg RCU_USBFS_SLP: USBFS clock \arg RCU_EXMC_SLP: EXMC clock - \arg RCU_TIMERx_SLP (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT_SLP: WWDGT clock - \arg RCU_SPIx_SLP (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx_SLP (x=0,1,2,5): USART clock - \arg RCU_UARTx_SLP (x=3,4,6,7): UART clock - \arg RCU_I2Cx_SLP (x=0,1,2): I2C clock - \arg RCU_CANx_SLP (x=0,1): CAN clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock \arg RCU_PMU_SLP: PMU clock \arg RCU_DAC_SLP: DAC clock \arg RCU_RTC_SLP: RTC clock - \arg RCU_ADCx_SLP (x=0,1,2): ADC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock \arg RCU_SDIO_SLP: SDIO clock \arg RCU_SYSCFG_SLP: SYSCFG clock \arg RCU_TLI_SLP: TLI clock @@ -215,10 +218,10 @@ void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) } /*! - \brief disable the peripherals clock when sleep mode + \brief disable the peripherals clock when sleep mode \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOx_SLP (x=A,B,C,D,E,F,G,H,I): GPIO ports clock + \arg RCU_GPIOx_SLP (x = A, B, C, D, E, F, G, H, I): GPIO ports clock \arg RCU_CRC_SLP: CRC clock \arg RCU_FMC_SLP: FMC clock \arg RCU_SRAM0_SLP: SRAM0 clock @@ -237,17 +240,17 @@ void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) \arg RCU_TRNG_SLP: TRNG clock \arg RCU_USBFS_SLP: USBFS clock \arg RCU_EXMC_SLP: EXMC clock - \arg RCU_TIMERx_SLP (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock + \arg RCU_TIMERx_SLP (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): TIMER clock \arg RCU_WWDGT_SLP: WWDGT clock - \arg RCU_SPIx_SLP (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx_SLP (x=0,1,2,5): USART clock - \arg RCU_UARTx_SLP (x=3,4,6,7): UART clock - \arg RCU_I2Cx_SLP (x=0,1,2): I2C clock - \arg RCU_CANx_SLP (x=0,1): CAN clock + \arg RCU_SPIx_SLP (x = 0, 1, 2, 3, 4, 5): SPI clock + \arg RCU_USARTx_SLP (x = 0, 1, 2, 5): USART clock + \arg RCU_UARTx_SLP (x = 3, 4, 6, 7): UART clock + \arg RCU_I2Cx_SLP (x = 0, 1, 2): I2C clock + \arg RCU_CANx_SLP (x = 0, 1): CAN clock \arg RCU_PMU_SLP: PMU clock \arg RCU_DAC_SLP: DAC clock \arg RCU_RTC_SLP: RTC clock - \arg RCU_ADCx_SLP (x=0,1,2): ADC clock + \arg RCU_ADCx_SLP (x = 0, 1, 2): ADC clock \arg RCU_SDIO_SLP: SDIO clock \arg RCU_SYSCFG_SLP: SYSCFG clock \arg RCU_TLI_SLP: TLI clock @@ -262,10 +265,10 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) } /*! - \brief reset the peripherals + \brief reset the peripherals \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA \arg RCU_IPARST: reset IPA @@ -275,16 +278,16 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) \arg RCU_TRNGRST: reset TRNG \arg RCU_USBFSRST: reset USBFS \arg RCU_EXMCRST: reset EXMC - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2,3,4,5): reset SPI - \arg RCU_USARTxRST (x=0,1,2,5): reset USART - \arg RCU_UARTxRST (x=3,4,6,7): reset UART - \arg RCU_I2CxRST (x=0,1,2): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC \arg RCU_SDIORST: reset SDIO \arg RCU_SYSCFGRST: reset SYSCFG \arg RCU_TLIRST: reset TLI @@ -299,10 +302,10 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) } /*! - \brief disable reset the peripheral + \brief disable reset the peripheral \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports + \arg RCU_GPIOxRST (x = A, B, C, D, E, F, G, H, I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA \arg RCU_IPARST: reset IPA @@ -312,16 +315,16 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) \arg RCU_TRNGRST: reset TRNG \arg RCU_USBFSRST: reset USBFS \arg RCU_EXMCRST: reset EXMC - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER + \arg RCU_TIMERxRST (x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13): reset TIMER \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2,3,4,5): reset SPI - \arg RCU_USARTxRST (x=0,1,2,5): reset USART - \arg RCU_UARTxRST (x=3,4,6,7): reset UART - \arg RCU_I2CxRST (x=0,1,2): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN + \arg RCU_SPIxRST (x = 0, 1, 2, 3, 4, 5): reset SPI + \arg RCU_USARTxRST (x = 0, 1, 2, 5): reset USART + \arg RCU_UARTxRST (x = 3, 4, 6, 7): reset UART + \arg RCU_I2CxRST (x = 0, 1, 2): reset I2C + \arg RCU_CANxRST (x = 0, 1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC + \arg RCU_ADCRST (x = 0, 1, 2): reset ADC \arg RCU_SDIORST: reset SDIO \arg RCU_SYSCFGRST: reset SYSCFG \arg RCU_TLIRST: reset TLI @@ -336,7 +339,7 @@ void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) } /*! - \brief reset the BKP + \brief reset the BKP \param[in] none \param[out] none \retval none @@ -347,7 +350,7 @@ void rcu_bkp_reset_enable(void) } /*! - \brief disable the BKP reset + \brief disable the BKP reset \param[in] none \param[out] none \retval none @@ -358,7 +361,7 @@ void rcu_bkp_reset_disable(void) } /*! - \brief configure the system clock source + \brief configure the system clock source \param[in] ck_sys: system clock source select only one parameter can be selected which is shown as below: \arg RCU_CKSYSSRC_IRC16M: select CK_IRC16M as the CK_SYS source @@ -378,7 +381,7 @@ void rcu_system_clock_source_config(uint32_t ck_sys) } /*! - \brief get the system clock source + \brief get the system clock source \param[in] none \param[out] none \retval which clock is selected as CK_SYS source @@ -392,10 +395,10 @@ uint32_t rcu_system_clock_source_get(void) } /*! - \brief configure the AHB clock prescaler selection + \brief configure the AHB clock prescaler selection \param[in] ck_ahb: AHB clock prescaler selection only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \arg RCU_AHB_CKSYS_DIVx (x = 1, 2, 4, 8, 16, 64, 128, 256, 512): select CK_SYS / x as CK_AHB \param[out] none \retval none */ @@ -410,14 +413,14 @@ void rcu_ahb_clock_config(uint32_t ck_ahb) } /*! - \brief configure the APB1 clock prescaler selection + \brief configure the APB1 clock prescaler selection \param[in] ck_apb1: APB1 clock prescaler selection only one parameter can be selected which is shown as below: \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB / 2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB / 4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB / 8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB / 16 as CK_APB1 \param[out] none \retval none */ @@ -432,14 +435,14 @@ void rcu_apb1_clock_config(uint32_t ck_apb1) } /*! - \brief configure the APB2 clock prescaler selection + \brief configure the APB2 clock prescaler selection \param[in] ck_apb2: APB2 clock prescaler selection only one parameter can be selected which is shown as below: \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB / 2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB / 4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB / 8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB / 16 as CK_APB2 \param[out] none \retval none */ @@ -454,7 +457,7 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) } /*! - \brief configure the CK_OUT0 clock source and divider + \brief configure the CK_OUT0 clock source and divider \param[in] ckout0_src: CK_OUT0 clock source selection only one parameter can be selected which is shown as below: \arg RCU_CKOUT0SRC_IRC16M: IRC16M selected @@ -462,7 +465,7 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected \arg RCU_CKOUT0SRC_PLLP: PLLP selected \param[in] ckout0_div: CK_OUT0 divider - \arg RCU_CKOUT0_DIVx(x=1,2,3,4,5): CK_OUT0 is divided by x + \arg RCU_CKOUT0_DIVx(x = 1, 2, 3, 4, 5): CK_OUT0 is divided by x \param[out] none \retval none */ @@ -472,12 +475,12 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) reg = RCU_CFG0; /* reset the CKOUT0SRC, CKOUT0DIV and set according to ckout0_src and ckout0_div */ - reg &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV ); + reg &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV); RCU_CFG0 = (reg | ckout0_src | ckout0_div); } /*! - \brief configure the CK_OUT1 clock source and divider + \brief configure the CK_OUT1 clock source and divider \param[in] ckout1_src: CK_OUT1 clock source selection only one parameter can be selected which is shown as below: \arg RCU_CKOUT1SRC_SYSTEMCLOCK: system clock selected @@ -485,7 +488,7 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected \arg RCU_CKOUT1SRC_PLLP: PLLP selected \param[in] ckout1_div: CK_OUT1 divider - \arg RCU_CKOUT1_DIVx(x=1,2,3,4,5): CK_OUT1 is divided by x + \arg RCU_CKOUT1_DIVx(x = 1, 2, 3, 4, 5): CK_OUT1 is divided by x \param[out] none \retval none */ @@ -500,7 +503,7 @@ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) } /*! - \brief configure the main PLL clock + \brief configure the main PLL clock \param[in] pll_src: PLL clock source selection \arg RCU_PLLSRC_IRC16M: select IRC16M as PLL source clock \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock @@ -524,20 +527,20 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin ss_modulation_reg = RCU_PLLSSCTL; /* calculate the minimum factor of PLLN */ - if((ss_modulation_reg & RCU_PLLSSCTL_SSCGON) == RCU_PLLSSCTL_SSCGON){ - if((ss_modulation_reg & RCU_SS_TYPE_DOWN) == RCU_SS_TYPE_DOWN){ + if((ss_modulation_reg & RCU_PLLSSCTL_SSCGON) == RCU_PLLSSCTL_SSCGON) { + if((ss_modulation_reg & RCU_SS_TYPE_DOWN) == RCU_SS_TYPE_DOWN) { ss_modulation_inc += RCU_SS_MODULATION_DOWN_INC; - }else{ + } else { ss_modulation_inc += RCU_SS_MODULATION_CENTER_INC; } } /* check the function parameter */ - if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n,ss_modulation_inc) && - CHECK_PLL_P_VALID(pll_p) && CHECK_PLL_Q_VALID(pll_q)){ - RCU_PLL = pll_psc | (pll_n << 6) | (((pll_p >> 1) - 1U) << 16) | - (pll_src) | (pll_q << 24); - }else{ + if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n, ss_modulation_inc) && + CHECK_PLL_P_VALID(pll_p) && CHECK_PLL_Q_VALID(pll_q)) { + RCU_PLL = pll_psc | (pll_n << 6) | (((pll_p >> 1) - 1U) << 16) | + (pll_src) | (pll_q << 24); + } else { /* return status */ return ERROR; } @@ -547,7 +550,7 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin } /*! - \brief configure the PLLI2S clock + \brief configure the PLLI2S clock \param[in] plli2s_n: the PLLI2S VCO clock multi factor \arg this parameter should be selected between 50 and 500 \param[in] plli2s_r: the PLLI2S R output frequency division factor from PLLI2S VCO clock @@ -558,9 +561,9 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) { /* check the function parameter */ - if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_R_VALID(plli2s_r)){ + if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_R_VALID(plli2s_r)) { RCU_PLLI2S = (plli2s_n << 6) | (plli2s_r << 28); - }else{ + } else { /* return status */ return ERROR; } @@ -570,7 +573,7 @@ ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) } /*! - \brief configure the PLLSAI clock + \brief configure the PLLSAI clock \param[in] pllsai_n: the PLLSAI VCO clock multi factor \arg this parameter should be selected between 50 and 500 \param[in] pllsai_p: the PLLSAI P output frequency division factor from PLL VCO clock @@ -583,9 +586,9 @@ ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r) { /* check the function parameter */ - if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && CHECK_PLLSAI_R_VALID(pllsai_r)){ + if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && CHECK_PLLSAI_R_VALID(pllsai_r)) { RCU_PLLSAI = (pllsai_n << 6U) | (((pllsai_p >> 1U) - 1U) << 16U) | (pllsai_r << 28U); - }else{ + } else { /* return status */ return ERROR; } @@ -595,13 +598,13 @@ ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsa } /*! - \brief configure the RTC clock source selection + \brief configure the RTC clock source selection \param[in] rtc_clock_source: RTC clock source selection only one parameter can be selected which is shown as below: \arg RCU_RTCSRC_NONE: no clock selected \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock \arg RCU_RTCSRC_IRC32K: CK_IRC32K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_RTCDIV: CK_HXTAL/RTCDIV selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_RTCDIV: CK_HXTAL / RTCDIV selected as RTC source clock \param[out] none \retval none */ @@ -616,11 +619,11 @@ void rcu_rtc_clock_config(uint32_t rtc_clock_source) } /*! - \brief configure the frequency division of RTC clock when HXTAL was selected as its clock source + \brief configure the frequency division of RTC clock when HXTAL was selected as its clock source \param[in] rtc_div: RTC clock frequency division only one parameter can be selected which is shown as below: \arg RCU_RTC_HXTAL_NONE: no clock for RTC - \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL/x, x = 2....31 + \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL / x, x = 2....31 \param[out] none \retval none */ @@ -636,7 +639,7 @@ void rcu_rtc_div_config(uint32_t rtc_div) /*! - \brief configure the I2S clock source selection + \brief configure the I2S clock source selection \param[in] i2s_clock_source: I2S clock source selection only one parameter can be selected which is shown as below: \arg RCU_I2SSRC_PLLI2S: CK_PLLI2S selected as I2S source clock @@ -655,7 +658,7 @@ void rcu_i2s_clock_config(uint32_t i2s_clock_source) } /*! - \brief configure the CK48M clock source selection + \brief configure the CK48M clock source selection \param[in] ck48m_clock_source: CK48M clock source selection only one parameter can be selected which is shown as below: \arg RCU_CK48MSRC_PLL48M: CK_PLL48M selected as CK48M source clock @@ -674,7 +677,7 @@ void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) } /*! - \brief configure the PLL48M clock source selection + \brief configure the PLL48M clock source selection \param[in] pll48m_clock_source: PLL48M clock source selection only one parameter can be selected which is shown as below: \arg RCU_PLL48MSRC_PLLQ: CK_PLLQ selected as PLL48M source clock @@ -693,7 +696,7 @@ void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) } /*! - \brief configure the TIMER clock prescaler selection + \brief configure the TIMER clock prescaler selection \param[in] timer_clock_prescaler: TIMER clock selection only one parameter can be selected which is shown as below: \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) @@ -710,15 +713,15 @@ void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler) { /* configure the TIMERSEL bit and select the TIMER clock prescaler */ - if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2){ + if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2) { RCU_CFG1 &= timer_clock_prescaler; - }else{ + } else { RCU_CFG1 |= timer_clock_prescaler; } } /*! - \brief configure the PLLSAIR divider used as input of TLI + \brief configure the PLLSAIR divider used as input of TLI \param[in] pllsai_r_div: PLLSAIR divider used as input of TLI only one parameter can be selected which is shown as below: \arg RCU_PLLSAIR_DIVx(x=2,4,8,16): PLLSAIR divided x used as input of TLI @@ -736,138 +739,7 @@ void rcu_tli_clock_div_config(uint32_t pllsai_r_div) } /*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag - \arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag - \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag - \arg RCU_FLAG_BORRST: BOR reset flags - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: Power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval none -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) -{ - RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable - \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum interrupt) -{ - RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); -} - - -/*! - \brief disable the stabilization interrupt - \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable - \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable - \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable - \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum interrupt) -{ - RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); -} - -/*! - \brief configure the LXTAL drive capability + \brief configure the LXTAL drive capability \param[in] lxtal_dricap: drive capability of LXTAL only one parameter can be selected which is shown as below: \arg RCU_LXTALDRI_LOWER_DRIVE: lower driving capability @@ -887,7 +759,7 @@ void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) } /*! - \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout + \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: HXTAL @@ -907,100 +779,100 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) ErrStatus reval = ERROR; FlagStatus osci_stat = RESET; - switch(osci){ + switch(osci) { /* wait HXTAL stable */ case RCU_HXTAL: - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); stb_cnt++; } /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { reval = SUCCESS; } break; /* wait LXTAL stable */ case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); stb_cnt++; } /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { reval = SUCCESS; } break; /* wait IRC16M stable */ case RCU_IRC16M: - while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC16MSTB); stb_cnt++; } /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC16MSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_IRC16MSTB)) { reval = SUCCESS; } break; /* wait IRC48M stable */ case RCU_IRC48M: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); stb_cnt++; } /* check whether flag is set */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) { reval = SUCCESS; } break; /* wait IRC32K stable */ case RCU_IRC32K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB); stb_cnt++; } /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)) { reval = SUCCESS; } break; /* wait PLL stable */ case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); stb_cnt++; } /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { reval = SUCCESS; } break; /* wait PLLI2S stable */ case RCU_PLLI2S_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLLI2SSTB); stb_cnt++; } /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLI2SSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLLI2SSTB)) { reval = SUCCESS; } break; /* wait PLLSAI stable */ case RCU_PLLSAI_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLLSAISTB); stb_cnt++; } /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSAISTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSAISTB)) { reval = SUCCESS; } break; @@ -1014,7 +886,7 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) } /*! - \brief turn on the oscillator + \brief turn on the oscillator \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: HXTAL @@ -1034,7 +906,7 @@ void rcu_osci_on(rcu_osci_type_enum osci) } /*! - \brief turn off the oscillator + \brief turn off the oscillator \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: HXTAL @@ -1054,7 +926,7 @@ void rcu_osci_off(rcu_osci_type_enum osci) } /*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) @@ -1066,7 +938,7 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) { uint32_t reg; - switch(osci){ + switch(osci) { /* enable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; @@ -1092,7 +964,7 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) } /*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) @@ -1104,7 +976,7 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) { uint32_t reg; - switch(osci){ + switch(osci) { /* disable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; @@ -1130,30 +1002,7 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) } /*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - -/*! - \brief set the IRC16M adjust value + \brief set the IRC16M adjust value \param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F \arg 0x00 - 0x1F \param[out] none @@ -1170,35 +1019,7 @@ void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval) } /*! - \brief unlock the voltage key - \param[in] none - \param[out] none - \retval none -*/ -void rcu_voltage_key_unlock(void) -{ - RCU_VKEY = RCU_VKEY_UNLOCK; -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V - \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - -/*! - \brief configure the spread spectrum modulation for the main PLL clock + \brief configure the spread spectrum modulation for the main PLL clock \param[in] spread_spectrum_type: PLL spread spectrum modulation type select \arg RCU_SS_TYPE_CENTER: center spread type is selected \arg RCU_SS_TYPE_DOWN: down spread type is selected @@ -1220,7 +1041,7 @@ void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, } /*! - \brief enable the PLL spread spectrum modulation + \brief enable the PLL spread spectrum modulation \param[in] none \param[out] none \retval none @@ -1231,7 +1052,7 @@ void rcu_spread_spectrum_enable(void) } /*! - \brief disable the PLL spread spectrum modulation + \brief disable the PLL spread spectrum modulation \param[in] none \param[out] none \retval none @@ -1242,7 +1063,58 @@ void rcu_spread_spectrum_disable(void) } /*! - \brief get the system clock, bus and peripheral clock frequency + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief unlock the voltage key + \param[in] none + \param[out] none + \retval none +*/ +void rcu_voltage_key_unlock(void) +{ + RCU_VKEY = RCU_VKEY_UNLOCK; +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_0: the core voltage is default value + \arg RCU_DEEPSLEEP_V_1: the core voltage is (default value-0.1)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_2: the core voltage is (default value-0.2)V(customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_3: the core voltage is (default value-0.3)V(customers are not recommended to use it) + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency \param[in] clock: the clock frequency which to get only one parameter can be selected which is shown as below: \arg CK_SYS: system clock frequency @@ -1264,7 +1136,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ + switch(sws) { /* IRC16M is selected as CK_SYS */ case SEL_IRC16M: cksys_freq = IRC16M_VALUE; @@ -1281,12 +1153,12 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; /* PLL clock source selection, HXTAL or IRC16M/2 */ pllsel = (RCU_PLL & RCU_PLL_PLLSEL); - if (RCU_PLLSRC_HXTAL == pllsel) { + if(RCU_PLLSRC_HXTAL == pllsel) { ck_src = HXTAL_VALUE; } else { ck_src = IRC16M_VALUE; } - cksys_freq = ((ck_src / pllpsc) * plln)/pllp; + cksys_freq = ((ck_src / pllpsc) * plln) / pllp; break; /* IRC16M is selected as CK_SYS */ default: @@ -1309,7 +1181,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) apb2_freq = ahb_freq >> clk_exp; /* return the clocks frequency */ - switch(clock){ + switch(clock) { case CK_SYS: ck_freq = cksys_freq; break; @@ -1327,3 +1199,134 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) } return ck_freq; } + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag + \arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag + \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag + \arg RCU_FLAG_BORRST: BOR reset flags + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: Power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval none +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) +{ + RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); +} + + +/*! + \brief disable the stabilization interrupt + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable + \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable + \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable + \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum interrupt) +{ + RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); +} diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c index 12ee6c3207..8003e92c2d 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -45,9 +46,8 @@ OF SUCH DAMAGE. #define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ #define RTC_ALRMXWF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ - /*! - \brief reset most of the RTC registers + \brief reset most of the RTC registers \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -67,7 +67,7 @@ ErrStatus rtc_deinit(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { /* reset RTC_CTL register, but RTC_CTL[2��0] */ RTC_CTL &= (RTC_REGISTER_RESET | RTC_CTL_WTCS); /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. @@ -78,13 +78,13 @@ ErrStatus rtc_deinit(void) RTC_PSC = RTC_PSC_RESET; /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ /* wait until the WTWF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + do { + flag_status = RTC_STAT & RTC_STAT_WTWF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET == flag_status){ + if((uint32_t)RESET == flag_status) { error_status = ERROR; - }else{ + } else { RTC_CTL &= RTC_REGISTER_RESET; RTC_WUT = RTC_WUT_RESET; RTC_COSC = RTC_REGISTER_RESET; @@ -110,7 +110,7 @@ ErrStatus rtc_deinit(void) } /*! - \brief initialize RTC registers + \brief initialize RTC registers \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: @@ -130,7 +130,7 @@ ErrStatus rtc_deinit(void) \param[out] none \retval ErrStatus: ERROR or SUCCESS */ -ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) +ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct) { ErrStatus error_status = ERROR; uint32_t reg_time = 0U, reg_date = 0U; @@ -140,7 +140,7 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) DATE_MON(rtc_initpara_struct->month) | \ DATE_DAY(rtc_initpara_struct->date)); - reg_time = (rtc_initpara_struct->am_pm| \ + reg_time = (rtc_initpara_struct->am_pm | \ TIME_HR(rtc_initpara_struct->hour) | \ TIME_MN(rtc_initpara_struct->minute) | \ TIME_SC(rtc_initpara_struct->second)); @@ -152,8 +152,8 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) /* 2nd: enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ - RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn)| \ + if(ERROR != error_status) { + RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn) | \ PSC_FACTOR_S(rtc_initpara_struct->factor_syn)); RTC_TIME = (uint32_t)reg_time; @@ -176,7 +176,7 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) } /*! - \brief enter RTC init mode + \brief enter RTC init mode \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -188,25 +188,25 @@ ErrStatus rtc_init_mode_enter(void) ErrStatus error_status = ERROR; /* check whether it has been in init mode */ - if ((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){ + if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) { RTC_STAT |= RTC_STAT_INITM; /* wait until the INITF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_INITF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + do { + flag_status = RTC_STAT & RTC_STAT_INITF; + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET != flag_status){ + if((uint32_t)RESET != flag_status) { error_status = SUCCESS; } - }else{ + } else { error_status = SUCCESS; } return error_status; } /*! - \brief exit RTC init mode + \brief exit RTC init mode \param[in] none \param[out] none \retval none @@ -217,7 +217,7 @@ void rtc_init_mode_exit(void) } /*! - \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow + \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated \param[in] none \param[out] none @@ -229,7 +229,7 @@ ErrStatus rtc_register_sync_wait(void) uint32_t flag_status = RESET; ErrStatus error_status = ERROR; - if ((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){ + if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -238,17 +238,17 @@ ErrStatus rtc_register_sync_wait(void) RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); /* wait until RSYNF flag to be set */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_RSYNF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET != flag_status){ + if((uint32_t)RESET != flag_status) { error_status = SUCCESS; } /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - }else{ + } else { error_status = SUCCESS; } @@ -256,7 +256,7 @@ ErrStatus rtc_register_sync_wait(void) } /*! - \brief get current time and date + \brief get current time and date \param[in] none \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral @@ -276,7 +276,7 @@ ErrStatus rtc_register_sync_wait(void) display_format: RTC_24HOUR, RTC_12HOUR \retval none */ -void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct) +void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct) { uint32_t temp_tr = 0U, temp_dr = 0U, temp_pscr = 0U, temp_ctlr = 0U; @@ -295,12 +295,12 @@ void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct) rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr); rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); - rtc_initpara_struct->am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); + rtc_initpara_struct->am_pm = (uint32_t)(temp_tr & RTC_TIME_PM); rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); } /*! - \brief get current subsecond value + \brief get current subsecond value \param[in] none \param[out] none \retval current subsecond value @@ -311,13 +311,13 @@ uint32_t rtc_subsecond_get(void) /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ reg = (uint32_t)RTC_SS; /* read RTC_DATE to unlock the 3 shadow registers */ - (void) (RTC_DATE); + (void)(RTC_DATE); return reg; } /*! - \brief configure RTC alarm + \brief configure RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration @@ -335,26 +335,26 @@ uint32_t rtc_subsecond_get(void) \param[out] none \retval none */ -void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) +void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time) { uint32_t reg_alrmtd = 0U; - reg_alrmtd =(rtc_alarm_time->alarm_mask | \ - rtc_alarm_time->weekday_or_date | \ - rtc_alarm_time->am_pm | \ - ALRMTD_DAY(rtc_alarm_time->alarm_day) | \ - ALRMTD_HR(rtc_alarm_time->alarm_hour) | \ - ALRMTD_MN(rtc_alarm_time->alarm_minute) | \ - ALRMTD_SC(rtc_alarm_time->alarm_second)); + reg_alrmtd = (rtc_alarm_time->alarm_mask | \ + rtc_alarm_time->weekday_or_date | \ + rtc_alarm_time->am_pm | \ + ALRMTD_DAY(rtc_alarm_time->alarm_day) | \ + ALRMTD_HR(rtc_alarm_time->alarm_hour) | \ + ALRMTD_MN(rtc_alarm_time->alarm_minute) | \ + ALRMTD_SC(rtc_alarm_time->alarm_second)); /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { RTC_ALRM0TD = (uint32_t)reg_alrmtd; - }else{ + } else { RTC_ALRM1TD = (uint32_t)reg_alrmtd; } /* enable the write protection */ @@ -362,7 +362,7 @@ void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) } /*! - \brief configure subsecond of RTC alarm + \brief configure subsecond of RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 \param[in] mask_subsecond: alarm subsecond mask \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration @@ -391,9 +391,9 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { RTC_ALRM0SS = mask_subsecond | subsecond; - }else{ + } else { RTC_ALRM1SS = mask_subsecond | subsecond; } /* enable the write protection */ @@ -401,7 +401,7 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint } /*! - \brief get RTC alarm + \brief get RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration @@ -418,14 +418,14 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint am_pm: RTC_AM, RTC_PM \retval none */ -void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) +void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time) { uint32_t reg_alrmtd = 0U; /* get the value of RTC_ALRM0TD register */ - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { reg_alrmtd = RTC_ALRM0TD; - }else{ + } else { reg_alrmtd = RTC_ALRM1TD; } /* get alarm parameters and construct the rtc_alarm_struct structure */ @@ -439,22 +439,22 @@ void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) } /*! - \brief get RTC alarm subsecond + \brief get RTC alarm subsecond \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 \param[out] none \retval RTC alarm subsecond value */ uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm) { - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); - }else{ + } else { return ((uint32_t)(RTC_ALRM1SS & RTC_ALRM1SS_SSC)); } } /*! - \brief enable RTC alarm + \brief enable RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 \param[out] none \retval none @@ -465,9 +465,9 @@ void rtc_alarm_enable(uint8_t rtc_alarm) RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { RTC_CTL |= RTC_CTL_ALRM0EN; - }else{ + } else { RTC_CTL |= RTC_CTL_ALRM1EN; } /* enable the write protection */ @@ -475,7 +475,7 @@ void rtc_alarm_enable(uint8_t rtc_alarm) } /*! - \brief disable RTC alarm + \brief disable RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -491,21 +491,21 @@ ErrStatus rtc_alarm_disable(uint8_t rtc_alarm) RTC_WPK = RTC_UNLOCK_KEY2; /* clear the state of alarm */ - if(RTC_ALARM0 == rtc_alarm){ + if(RTC_ALARM0 == rtc_alarm) { RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); /* wait until ALRM0WF flag to be set after the alarm is disabled */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_ALRM0WF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - }else{ + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } else { RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); /* wait until ALRM1WF flag to be set after the alarm is disabled */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_ALRM1WF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } - if ((uint32_t)RESET != flag_status){ + if((uint32_t)RESET != flag_status) { error_status = SUCCESS; } @@ -516,7 +516,7 @@ ErrStatus rtc_alarm_disable(uint8_t rtc_alarm) } /*! - \brief enable RTC time-stamp + \brief enable RTC time-stamp \param[in] edge: specify which edge to detect of time-stamp \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event @@ -544,7 +544,7 @@ void rtc_timestamp_enable(uint32_t edge) } /*! - \brief disable RTC time-stamp + \brief disable RTC time-stamp \param[in] none \param[out] none \retval none @@ -563,7 +563,7 @@ void rtc_timestamp_disable(void) } /*! - \brief get RTC timestamp time and date + \brief get RTC timestamp time and date \param[in] none \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains parameters for RTC time-stamp configuration @@ -579,7 +579,7 @@ void rtc_timestamp_disable(void) am_pm: RTC_AM, RTC_PM \retval none */ -void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp) +void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp) { uint32_t temp_tts = 0U, temp_dts = 0U; @@ -598,7 +598,7 @@ void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp) } /*! - \brief get RTC time-stamp subsecond + \brief get RTC time-stamp subsecond \param[in] none \param[out] none \retval RTC time-stamp subsecond value @@ -609,7 +609,7 @@ uint32_t rtc_timestamp_subsecond_get(void) } /*! - \brief RTC time-stamp mapping + \brief RTC time-stamp mapping \param[in] rtc_af: \arg RTC_AF0_TIMESTAMP: RTC_AF0 use for timestamp \arg RTC_AF1_TIMESTAMP: RTC_AF1 use for timestamp @@ -623,7 +623,7 @@ void rtc_timestamp_pin_map(uint32_t rtc_af) } /*! - \brief enable RTC tamper + \brief enable RTC tamper \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains parameters for RTC tamper configuration members of the structure and the member values are shown as below: @@ -646,7 +646,7 @@ void rtc_timestamp_pin_map(uint32_t rtc_af) \param[out] none \retval none */ -void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) +void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper) { /* disable tamper */ RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); @@ -655,13 +655,13 @@ void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; /* the tamper source is voltage level detection */ - if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE ){ + if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE) { RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); /* check if the tamper pin need precharge, if need, then configure the precharge time */ - if(DISABLE == rtc_tamper->tamper_precharge_enable){ - RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; - }else{ + if(DISABLE == rtc_tamper->tamper_precharge_enable) { + RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; + } else { RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time); } @@ -670,29 +670,29 @@ void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) /* configure the tamper trigger */ RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); + if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); } - }else{ + } else { /* configure the tamper trigger */ RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); + if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); } } RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; - if(DISABLE != rtc_tamper->tamper_with_timestamp){ + if(DISABLE != rtc_tamper->tamper_with_timestamp) { /* the tamper event also cause a time-stamp event */ RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; } /* enable tamper */ - RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); } /*! - \brief disable RTC tamper + \brief disable RTC tamper \param[in] source: specify which tamper source to be disabled \arg RTC_TAMPER0 \arg RTC_TAMPER1 @@ -707,7 +707,7 @@ void rtc_tamper_disable(uint32_t source) } /*! - \brief RTC tamper0 mapping + \brief RTC tamper0 mapping \param[in] rtc_af: \arg RTC_AF0_TAMPER0: RTC_AF0 use for tamper0 \arg RTC_AF1_TAMPER0: RTC_AF1 use for tamper0 @@ -721,7 +721,7 @@ void rtc_tamper0_pin_map(uint32_t rtc_af) } /*! - \brief enable specified RTC interrupt + \brief enable specified RTC interrupt \param[in] interrupt: specify which interrupt source to be enabled \arg RTC_INT_TIMESTAMP: timestamp interrupt \arg RTC_INT_ALARM0: alarm0 interrupt @@ -747,7 +747,7 @@ void rtc_interrupt_enable(uint32_t interrupt) } /*! - \brief disble specified RTC interrupt + \brief disble specified RTC interrupt \param[in] interrupt: specify which interrupt source to be disabled \arg RTC_INT_TIMESTAMP: timestamp interrupt \arg RTC_INT_ALARM0: alarm interrupt @@ -773,15 +773,15 @@ void rtc_interrupt_disable(uint32_t interrupt) } /*! - \brief check specified flag + \brief check specified flag \param[in] flag: specify which flag to check \arg RTC_STAT_SCP: smooth calibration pending flag \arg RTC_FLAG_TP1: RTC tamper 1 detected flag \arg RTC_FLAG_TP0: RTC tamper 0 detected flag \arg RTC_FLAG_TSOVR: time-stamp overflow flag \arg RTC_FLAG_TS: time-stamp flag - \arg RTC_FLAG_ALARM0: alarm0 occurs flag - \arg RTC_FLAG_ALARM1: alarm1 occurs flag + \arg RTC_FLAG_ALRM0: alarm0 occurs flag + \arg RTC_FLAG_ALRM1: alarm1 occurs flag \arg RTC_FLAG_WT: wakeup timer occurs flag \arg RTC_FLAG_INIT: initialization state flag \arg RTC_FLAG_RSYN: register synchronization flag @@ -797,14 +797,14 @@ FlagStatus rtc_flag_get(uint32_t flag) { FlagStatus flag_state = RESET; - if ((uint32_t)RESET != (RTC_STAT & flag)){ + if((uint32_t)RESET != (RTC_STAT & flag)) { flag_state = SET; } return flag_state; } /*! - \brief clear specified flag + \brief clear specified flag \arg RTC_FLAG_TP1: RTC tamper 1 detected flag \arg RTC_FLAG_TP0: RTC tamper 0 detected flag \arg RTC_FLAG_TSOVR: time-stamp overflow flag @@ -822,7 +822,7 @@ void rtc_flag_clear(uint32_t flag) } /*! - \brief configure rtc alarm output source + \brief configure rtc alarm output source \param[in] source: specify signal to output \arg RTC_ALARM0_HIGH: when the alarm0 flag is set, the output pin is high \arg RTC_ALARM0_LOW: when the alarm0 flag is set, the output pin is low @@ -854,7 +854,7 @@ void rtc_alarm_output_config(uint32_t source, uint32_t mode) } /*! - \brief configure rtc calibration output source + \brief configure rtc calibration output source \param[in] source: specify signal to output \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC is the default value, output 512Hz signal @@ -876,9 +876,8 @@ void rtc_calibration_output_config(uint32_t source) RTC_WPK = RTC_LOCK_KEY; } - /*! - \brief adjust the daylight saving time by adding or substracting one hour from the current time + \brief adjust the daylight saving time by adding or substracting one hour from the current time \param[in] operation: hour adjustment operation \arg RTC_CTL_A1H: add one hour \arg RTC_CTL_S1H: substract one hour @@ -898,7 +897,7 @@ void rtc_hour_adjust(uint32_t operation) } /*! - \brief adjust RTC second or subsecond value of current time + \brief adjust RTC second or subsecond value of current time \param[in] add: add 1s to current time or not \arg RTC_SHIFT_ADD1S_RESET: no effect \arg RTC_SHIFT_ADD1S_SET: add 1s to current time @@ -911,19 +910,19 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) volatile uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; ErrStatus error_status = ERROR; uint32_t flag_status = RESET; - uint32_t temp=0U; + uint32_t temp = 0U; /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; /* check if a shift operation is ongoing */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_SOPF; - }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); /* check if the function of reference clock detection is disabled */ temp = RTC_CTL & RTC_CTL_REFEN; - if((RESET == flag_status) && (RESET == temp)){ + if((RESET == flag_status) && (RESET == temp)) { RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); error_status = rtc_register_sync_wait(); } @@ -935,7 +934,7 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) } /*! - \brief enable RTC bypass shadow registers function + \brief enable RTC bypass shadow registers function \param[in] none \param[out] none \retval none @@ -953,7 +952,7 @@ void rtc_bypass_shadow_enable(void) } /*! - \brief disable RTC bypass shadow registers function + \brief disable RTC bypass shadow registers function \param[in] none \param[out] none \retval none @@ -971,7 +970,7 @@ void rtc_bypass_shadow_disable(void) } /*! - \brief enable RTC reference clock detection function + \brief enable RTC reference clock detection function \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -987,7 +986,7 @@ ErrStatus rtc_refclock_detection_enable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { RTC_CTL |= (uint32_t)RTC_CTL_REFEN; /* exit init mode */ rtc_init_mode_exit(); @@ -1000,7 +999,7 @@ ErrStatus rtc_refclock_detection_enable(void) } /*! - \brief disable RTC reference clock detection function + \brief disable RTC reference clock detection function \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -1016,7 +1015,7 @@ ErrStatus rtc_refclock_detection_disable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; /* exit init mode */ rtc_init_mode_exit(); @@ -1029,7 +1028,7 @@ ErrStatus rtc_refclock_detection_disable(void) } /*! - \brief enable RTC auto wakeup function + \brief enable RTC auto wakeup function \param[in] none \param[out] none \retval none @@ -1047,7 +1046,7 @@ void rtc_wakeup_enable(void) } /*! - \brief disable RTC auto wakeup function + \brief disable RTC auto wakeup function \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -1062,13 +1061,13 @@ ErrStatus rtc_wakeup_disable(void) RTC_WPK = RTC_UNLOCK_KEY2; RTC_CTL &= ~RTC_CTL_WTEN; /* wait until the WTWF flag to be set */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET == flag_status){ + if((uint32_t)RESET == flag_status) { error_status = ERROR; - }else{ + } else { error_status = SUCCESS; } /* enable the write protection */ @@ -1077,7 +1076,7 @@ ErrStatus rtc_wakeup_disable(void) } /*! - \brief set RTC auto wakeup timer clock + \brief set RTC auto wakeup timer clock \param[in] wakeup_clock: \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 @@ -1098,13 +1097,13 @@ ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) RTC_WPK = RTC_UNLOCK_KEY2; /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ /* wait until the WTWF flag to be set */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET == flag_status){ + if((uint32_t)RESET == flag_status) { error_status = ERROR; - }else{ + } else { RTC_CTL &= (uint32_t)~ RTC_CTL_WTCS; RTC_CTL |= (uint32_t)wakeup_clock; error_status = SUCCESS; @@ -1116,7 +1115,7 @@ ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) } /*! - \brief set wakeup timer value + \brief set wakeup timer value \param[in] wakeup_timer: 0x0000-0xffff \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -1130,13 +1129,13 @@ ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer) RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; /* wait until the WTWF flag to be set */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET == flag_status){ + if((uint32_t)RESET == flag_status) { error_status = ERROR; - }else{ + } else { RTC_WUT = (uint32_t)wakeup_timer; error_status = SUCCESS; } @@ -1146,18 +1145,18 @@ ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer) } /*! - \brief get wakeup timer value + \brief get wakeup timer value \param[in] none \param[out] none \retval wakeup timer value */ - uint16_t rtc_wakeup_timer_get(void) +uint16_t rtc_wakeup_timer_get(void) { return (uint16_t)RTC_WUT; } /*! - \brief configure RTC smooth calibration + \brief configure RTC smooth calibration \param[in] window: select calibration window \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz @@ -1180,11 +1179,11 @@ ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t RTC_WPK = RTC_UNLOCK_KEY2; /* check if a smooth calibration operation is ongoing */ - do{ + do { flag_status = RTC_STAT & RTC_STAT_SCPF; - }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); + } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - if((uint32_t)RESET == flag_status){ + if((uint32_t)RESET == flag_status) { RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); error_status = SUCCESS; } @@ -1196,7 +1195,7 @@ ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t } /*! - \brief enable RTC coarse calibration + \brief enable RTC coarse calibration \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -1210,7 +1209,7 @@ ErrStatus rtc_coarse_calibration_enable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { RTC_CTL |= (uint32_t)RTC_CTL_CCEN; /* exit init mode */ rtc_init_mode_exit(); @@ -1222,7 +1221,7 @@ ErrStatus rtc_coarse_calibration_enable(void) } /*! - \brief disable RTC coarse calibration + \brief disable RTC coarse calibration \param[in] none \param[out] none \retval ErrStatus: ERROR or SUCCESS @@ -1236,7 +1235,7 @@ ErrStatus rtc_coarse_calibration_disable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status) { RTC_CTL &= (uint32_t)~RTC_CTL_CCEN; /* exit init mode */ rtc_init_mode_exit(); @@ -1248,7 +1247,7 @@ ErrStatus rtc_coarse_calibration_disable(void) } /*! - \brief config coarse calibration direction and step + \brief config coarse calibration direction and step \param[in] direction: CALIB_INCREASE or CALIB_DECREASE \param[in] step: 0x00-0x1F COSD=0: @@ -1276,10 +1275,10 @@ ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ - if(CALIB_DECREASE == direction){ + if(ERROR != error_status) { + if(CALIB_DECREASE == direction) { RTC_COSC |= (uint32_t)RTC_COSC_COSD; - }else{ + } else { RTC_COSC &= (uint32_t)~RTC_COSC_COSD; } RTC_COSC &= ~RTC_COSC_COSS; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c index d1d0a0be32..17b4ea96fe 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.1, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,7 +38,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_sdio.h" /*! - \brief deinitialize the SDIO + \brief deinitialize the SDIO \param[in] none \param[out] none \retval none @@ -49,7 +50,7 @@ void sdio_deinit(void) } /*! - \brief configure the SDIO clock + \brief configure the SDIO clock \param[in] clock_edge: SDIO_CLK clock edge only one parameter can be selected which is shown as below: \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK @@ -73,7 +74,7 @@ void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t cloc /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); /* if the clock division is greater or equal to 256, set the DIV[8] */ - if(clock_division >= 256U){ + if(clock_division >= 256U) { clock_config |= SDIO_CLKCTL_DIV8; clock_division -= 256U; } @@ -83,7 +84,7 @@ void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t cloc } /*! - \brief enable hardware clock control + \brief enable hardware clock control \param[in] none \param[out] none \retval none @@ -94,7 +95,7 @@ void sdio_hardware_clock_enable(void) } /*! - \brief disable hardware clock control + \brief disable hardware clock control \param[in] none \param[out] none \retval none @@ -105,7 +106,7 @@ void sdio_hardware_clock_disable(void) } /*! - \brief set different SDIO card bus mode + \brief set different SDIO card bus mode \param[in] bus_mode: SDIO card bus mode only one parameter can be selected which is shown as below: \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode @@ -122,7 +123,7 @@ void sdio_bus_mode_set(uint32_t bus_mode) } /*! - \brief set the SDIO power state + \brief set the SDIO power state \param[in] power_state: SDIO power state only one parameter can be selected which is shown as below: \arg SDIO_POWER_ON: SDIO power on @@ -136,7 +137,7 @@ void sdio_power_state_set(uint32_t power_state) } /*! - \brief get the SDIO power state + \brief get the SDIO power state \param[in] none \param[out] none \retval SDIO power state @@ -149,7 +150,7 @@ uint32_t sdio_power_state_get(void) } /*! - \brief enable SDIO_CLK clock output + \brief enable SDIO_CLK clock output \param[in] none \param[out] none \retval none @@ -160,7 +161,7 @@ void sdio_clock_enable(void) } /*! - \brief disable SDIO_CLK clock output + \brief disable SDIO_CLK clock output \param[in] none \param[out] none \retval none @@ -171,7 +172,7 @@ void sdio_clock_disable(void) } /*! - \brief configure the command and response + \brief configure the command and response \param[in] cmd_index: command index, refer to the related specifications \param[in] cmd_argument: command argument, refer to the related specifications \param[in] response_type: response type @@ -198,7 +199,7 @@ void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uin } /*! - \brief set the command state machine wait type + \brief set the command state machine wait type \param[in] wait_type: wait type only one parameter can be selected which is shown as below: \arg SDIO_WAITTYPE_NO: not wait interrupt @@ -216,7 +217,7 @@ void sdio_wait_type_set(uint32_t wait_type) } /*! - \brief enable the CSM(command state machine) + \brief enable the CSM(command state machine) \param[in] none \param[out] none \retval none @@ -227,7 +228,7 @@ void sdio_csm_enable(void) } /*! - \brief disable the CSM(command state machine) + \brief disable the CSM(command state machine) \param[in] none \param[out] none \retval none @@ -238,7 +239,7 @@ void sdio_csm_disable(void) } /*! - \brief get the last response command index + \brief get the last response command index \param[in] none \param[out] none \retval last response command index @@ -249,7 +250,7 @@ uint8_t sdio_command_index_get(void) } /*! - \brief get the response for the last received command + \brief get the response for the last received command \param[in] sdio_responsex: SDIO response only one parameter can be selected which is shown as below: \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] @@ -262,7 +263,7 @@ uint8_t sdio_command_index_get(void) uint32_t sdio_response_get(uint32_t sdio_responsex) { uint32_t resp_content = 0U; - switch(sdio_responsex){ + switch(sdio_responsex) { case SDIO_RESPONSE0: resp_content = SDIO_RESP0; break; @@ -282,7 +283,7 @@ uint32_t sdio_response_get(uint32_t sdio_responsex) } /*! - \brief configure the data timeout, data length and data block size + \brief configure the data timeout, data length and data block size \param[in] data_timeout: data timeout period in card bus clock periods \param[in] data_length: number of data bytes to be transferred \param[in] data_blocksize: size of data block for block transfer @@ -318,7 +319,7 @@ void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data } /*! - \brief configure the data transfer mode and direction + \brief configure the data transfer mode and direction \param[in] transfer_mode: mode of data transfer only one parameter can be selected which is shown as below: \arg SDIO_TRANSMODE_BLOCK: block transfer @@ -341,7 +342,7 @@ void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_directi } /*! - \brief enable the DSM(data state machine) for data transfer + \brief enable the DSM(data state machine) for data transfer \param[in] none \param[out] none \retval none @@ -352,7 +353,7 @@ void sdio_dsm_enable(void) } /*! - \brief disable the DSM(data state machine) + \brief disable the DSM(data state machine) \param[in] none \param[out] none \retval none @@ -363,7 +364,7 @@ void sdio_dsm_disable(void) } /*! - \brief write data(one word) to the transmit FIFO + \brief write data(one word) to the transmit FIFO \param[in] data: 32-bit data write to card \param[out] none \retval none @@ -374,7 +375,7 @@ void sdio_data_write(uint32_t data) } /*! - \brief read data(one word) from the receive FIFO + \brief read data(one word) from the receive FIFO \param[in] none \param[out] none \retval received data @@ -385,7 +386,7 @@ uint32_t sdio_data_read(void) } /*! - \brief get the number of remaining data bytes to be transferred to card + \brief get the number of remaining data bytes to be transferred to card \param[in] none \param[out] none \retval number of remaining data bytes to be transferred @@ -396,7 +397,7 @@ uint32_t sdio_data_counter_get(void) } /*! - \brief get the number of words remaining to be written or read from FIFO + \brief get the number of words remaining to be written or read from FIFO \param[in] none \param[out] none \retval remaining number of words @@ -407,7 +408,7 @@ uint32_t sdio_fifo_counter_get(void) } /*! - \brief enable the DMA request for SDIO + \brief enable the DMA request for SDIO \param[in] none \param[out] none \retval none @@ -418,7 +419,7 @@ void sdio_dma_enable(void) } /*! - \brief disable the DMA request for SDIO + \brief disable the DMA request for SDIO \param[in] none \param[out] none \retval none @@ -429,7 +430,7 @@ void sdio_dma_disable(void) } /*! - \brief get the flags state of SDIO + \brief get the flags state of SDIO \param[in] flag: flags state of SDIO one or more parameters can be selected which are shown as below: \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag @@ -462,14 +463,14 @@ void sdio_dma_disable(void) FlagStatus sdio_flag_get(uint32_t flag) { FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & flag)){ + if(RESET != (SDIO_STAT & flag)) { temp_flag = SET; } return temp_flag; } /*! - \brief clear the pending flags of SDIO + \brief clear the pending flags of SDIO \param[in] flag: flags state of SDIO one or more parameters can be selected which are shown as below: \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag @@ -494,7 +495,7 @@ void sdio_flag_clear(uint32_t flag) } /*! - \brief enable the SDIO interrupt + \brief enable the SDIO interrupt \param[in] int_flag: interrupt flags state of SDIO one or more parameters can be selected which are shown as below: \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt @@ -530,7 +531,7 @@ void sdio_interrupt_enable(uint32_t int_flag) } /*! - \brief disable the SDIO interrupt + \brief disable the SDIO interrupt \param[in] int_flag: interrupt flags state of SDIO one or more parameters can be selected which are shown as below: \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt @@ -566,7 +567,7 @@ void sdio_interrupt_disable(uint32_t int_flag) } /*! - \brief get the interrupt flags state of SDIO + \brief get the interrupt flags state of SDIO \param[in] int_flag: interrupt flags state of SDIO one or more parameters can be selected which are shown as below: \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt flag @@ -599,14 +600,14 @@ void sdio_interrupt_disable(uint32_t int_flag) FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) { FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & int_flag)){ + if(RESET != (SDIO_STAT & int_flag)) { temp_flag = SET; } return temp_flag; } /*! - \brief clear the interrupt pending flags of SDIO + \brief clear the interrupt pending flags of SDIO \param[in] int_flag: interrupt flags state of SDIO one or more parameters can be selected which are shown as below: \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag @@ -631,7 +632,7 @@ void sdio_interrupt_flag_clear(uint32_t int_flag) } /*! - \brief enable the read wait mode(SD I/O only) + \brief enable the read wait mode(SD I/O only) \param[in] none \param[out] none \retval none @@ -642,7 +643,7 @@ void sdio_readwait_enable(void) } /*! - \brief disable the read wait mode(SD I/O only) + \brief disable the read wait mode(SD I/O only) \param[in] none \param[out] none \retval none @@ -653,7 +654,7 @@ void sdio_readwait_disable(void) } /*! - \brief enable the function that stop the read wait process(SD I/O only) + \brief enable the function that stop the read wait process(SD I/O only) \param[in] none \param[out] none \retval none @@ -664,7 +665,7 @@ void sdio_stop_readwait_enable(void) } /*! - \brief disable the function that stop the read wait process(SD I/O only) + \brief disable the function that stop the read wait process(SD I/O only) \param[in] none \param[out] none \retval none @@ -675,7 +676,7 @@ void sdio_stop_readwait_disable(void) } /*! - \brief set the read wait type(SD I/O only) + \brief set the read wait type(SD I/O only) \param[in] readwait_type: SD I/O read wait type only one parameter can be selected which is shown as below: \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK @@ -685,15 +686,15 @@ void sdio_stop_readwait_disable(void) */ void sdio_readwait_type_set(uint32_t readwait_type) { - if(SDIO_READWAITTYPE_CLK == readwait_type){ + if(SDIO_READWAITTYPE_CLK == readwait_type) { SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; - }else{ + } else { SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; } } /*! - \brief enable the SD I/O mode specific operation(SD I/O only) + \brief enable the SD I/O mode specific operation(SD I/O only) \param[in] none \param[out] none \retval none @@ -704,7 +705,7 @@ void sdio_operation_enable(void) } /*! - \brief disable the SD I/O mode specific operation(SD I/O only) + \brief disable the SD I/O mode specific operation(SD I/O only) \param[in] none \param[out] none \retval none @@ -715,7 +716,7 @@ void sdio_operation_disable(void) } /*! - \brief enable the SD I/O suspend operation(SD I/O only) + \brief enable the SD I/O suspend operation(SD I/O only) \param[in] none \param[out] none \retval none @@ -726,7 +727,7 @@ void sdio_suspend_enable(void) } /*! - \brief disable the SD I/O suspend operation(SD I/O only) + \brief disable the SD I/O suspend operation(SD I/O only) \param[in] none \param[out] none \retval none @@ -737,7 +738,7 @@ void sdio_suspend_disable(void) } /*! - \brief enable the CE-ATA command(CE-ATA only) + \brief enable the CE-ATA command(CE-ATA only) \param[in] none \param[out] none \retval none @@ -748,7 +749,7 @@ void sdio_ceata_command_enable(void) } /*! - \brief disable the CE-ATA command(CE-ATA only) + \brief disable the CE-ATA command(CE-ATA only) \param[in] none \param[out] none \retval none @@ -759,7 +760,7 @@ void sdio_ceata_command_disable(void) } /*! - \brief enable the CE-ATA interrupt(CE-ATA only) + \brief enable the CE-ATA interrupt(CE-ATA only) \param[in] none \param[out] none \retval none @@ -770,7 +771,7 @@ void sdio_ceata_interrupt_enable(void) } /*! - \brief disable the CE-ATA interrupt(CE-ATA only) + \brief disable the CE-ATA interrupt(CE-ATA only) \param[in] none \param[out] none \retval none @@ -781,7 +782,7 @@ void sdio_ceata_interrupt_disable(void) } /*! - \brief enable the CE-ATA command completion signal(CE-ATA only) + \brief enable the CE-ATA command completion signal(CE-ATA only) \param[in] none \param[out] none \retval none @@ -792,7 +793,7 @@ void sdio_ceata_command_completion_enable(void) } /*! - \brief disable the CE-ATA command completion signal(CE-ATA only) + \brief disable the CE-ATA command completion signal(CE-ATA only) \param[in] none \param[out] none \retval none diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c index 3f842251fc..c2fe7c1c07 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -54,7 +55,7 @@ OF SUCH DAMAGE. */ void spi_i2s_deinit(uint32_t spi_periph) { - switch(spi_periph){ + switch(spi_periph) { case SPI0: /* reset SPI0 */ rcu_periph_reset_enable(RCU_SPI0RST); @@ -124,7 +125,7 @@ void spi_struct_para_init(spi_parameter_struct *spi_struct) \param[out] none \retval none */ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) { uint32_t reg = 0U; reg = SPI_CTL0(spi_periph); @@ -198,7 +199,7 @@ void spi_disable(uint32_t spi_periph) */ void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) { - uint32_t reg= 0U; + uint32_t reg = 0U; reg = SPI_I2SCTL(spi_periph); reg &= I2S_INIT_MASK; @@ -249,7 +250,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ uint32_t i2sclock = 0U; #ifndef I2S_EXTERNAL_CLOCK_IN - uint32_t plli2sm = 0U, plli2sn = 0U, plli2sr = 0U; + uint32_t plli2sm = 0U, plli2sn = 0U, plli2sr = 0U; #endif /* I2S_EXTERNAL_CLOCK_IN */ /* deinit SPI_I2SPSC register */ @@ -280,25 +281,23 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ /* get the RCU_PLLI2S_PLLI2SR value */ plli2sr = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SR) >> 28); - if((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL) - { - /* get the I2S source clock value */ - i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr); - } - else - { /* get the I2S source clock value */ - i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr); + if((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL) { + /* get the I2S source clock value */ + i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr); + } else { + /* get the I2S source clock value */ + i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr); } #endif /* I2S_EXTERNAL_CLOCK_IN */ /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == i2s_mckout){ + if(I2S_MCKOUT_ENABLE == i2s_mckout) { clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample); + } else { + if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat) { + clks = (uint32_t)(((i2sclock / 32U) * 10U) / i2s_audiosample); + } else { + clks = (uint32_t)(((i2sclock / 64U) * 10U) / i2s_audiosample); } } /* remove the floating point */ @@ -308,7 +307,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ i2sof = (i2sof << 8U); /* set the default values */ - if((i2sdiv< 2U) || (i2sdiv > 255U)){ + if((i2sdiv < 2U) || (i2sdiv > 255U)) { i2sdiv = 2U; i2sof = 0U; } @@ -317,7 +316,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout); /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN|SPI_I2SCTL_CHLEN)); + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); /* configure data frame format */ SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat; } @@ -400,9 +399,9 @@ void spi_nss_internal_low(uint32_t spi_periph) */ void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) { - if(SPI_DMA_TRANSMIT == spi_dma){ + if(SPI_DMA_TRANSMIT == spi_dma) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ + } else { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; } } @@ -419,9 +418,9 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) */ void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) { - if(SPI_DMA_TRANSMIT == spi_dma){ + if(SPI_DMA_TRANSMIT == spi_dma) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ + } else { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); } } @@ -478,116 +477,15 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph) */ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) { - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { /* set the transmit only mode */ SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ + } else { /* set the receive only mode */ SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; } } -/*! - \brief set SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} - -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_crc: SPI crc value - only one parameter can be selected which is shown as below: - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc) -{ - if(SPI_CRC_TX == spi_crc){ - return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief enable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_ti_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; -} - -/*! - \brief disable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_ti_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); -} - /*! \brief configure i2s full duplex mode \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) @@ -622,9 +520,9 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin reg &= I2S_FULL_DUPLEX_MASK; /* get the mode of the extra I2S module I2Sx_ADD */ - if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)){ + if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)) { tmp = I2S_MODE_SLAVERX; - }else{ + } else { tmp = I2S_MODE_SLAVETX; } @@ -643,13 +541,136 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg; } +/*! + \brief clear SPI/I2S format error flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] flag: SPI/I2S frame format error flag + \arg SPI_FLAG_FERR: only for SPI work in TI mode + \arg I2S_FLAG_FERR: for I2S + \param[out] none + \retval none +*/ +void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag) +{ + SPI_STAT(spi_periph) = (uint32_t)(~flag); +} + +/*! + \brief set SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) +{ + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief turn on SPI CRC function + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off SPI CRC function + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_crc: SPI crc value + only one parameter can be selected which is shown as below: + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc) +{ + if(SPI_CRC_TX == spi_crc) { + return ((uint16_t)(SPI_TCRC(spi_periph))); + } else { + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) = (uint32_t)(~SPI_FLAG_CRCERR); +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + /*! \brief enable quad wire SPI \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none */ -void qspi_enable(uint32_t spi_periph) +void spi_quad_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; } @@ -660,7 +681,7 @@ void qspi_enable(uint32_t spi_periph) \param[out] none \retval none */ -void qspi_disable(uint32_t spi_periph) +void spi_quad_disable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); } @@ -671,7 +692,7 @@ void qspi_disable(uint32_t spi_periph) \param[out] none \retval none */ -void qspi_write_enable(uint32_t spi_periph) +void spi_quad_write_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); } @@ -682,7 +703,7 @@ void qspi_write_enable(uint32_t spi_periph) \param[out] none \retval none */ -void qspi_read_enable(uint32_t spi_periph) +void spi_quad_read_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; } @@ -693,22 +714,53 @@ void qspi_read_enable(uint32_t spi_periph) \param[out] none \retval none */ -void qspi_io23_output_enable(uint32_t spi_periph) +void spi_quad_io23_output_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; } - /*! - \brief disable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=5) - \param[out] none - \retval none +/*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=5) + \param[out] none + \retval none */ - void qspi_io23_output_disable(uint32_t spi_periph) +void spi_quad_io23_output_disable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); } +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_flag: SPI/I2S flag status + only one parameter can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(SPI_STAT(spi_periph) & flag) { + return SET; + } else { + return RESET; + } +} + /*! \brief enable SPI and I2S interrupt \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) @@ -721,9 +773,9 @@ void qspi_io23_output_enable(uint32_t spi_periph) \param[out] none \retval none */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) { - switch(spi_i2s_int){ + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_TBE: SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; @@ -753,9 +805,9 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) \param[out] none \retval none */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) { - switch(spi_i2s_int){ + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_TBE : SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); @@ -777,6 +829,7 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) \brief get SPI and I2S interrupt flag status \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_i2s_int: SPI/I2S interrupt flag status + only one parameter can be selected which are shown as below: \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag @@ -787,12 +840,12 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) { uint32_t reg1 = SPI_STAT(spi_periph); uint32_t reg2 = SPI_CTL1(spi_periph); - switch(spi_i2s_int){ + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_FLAG_TBE : reg1 = reg1 & SPI_STAT_TBE; @@ -832,51 +885,9 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) break; } /*get SPI/I2S interrupt flag status */ - if(reg1 && reg2){ + if(reg1 && reg2) { return SET; - }else{ + } else { return RESET; } } - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_flag: SPI/I2S flag status - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) -{ - if(SPI_STAT(spi_periph) & spi_i2s_flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} - diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c index 6fa0a776d0..3c13fcd8bc 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,7 +38,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_syscfg.h" /*! - \brief reset the SYSCFG registers + \brief reset the SYSCFG registers \param[in] none \param[out] none \retval none @@ -49,7 +50,7 @@ void syscfg_deinit(void) } /*! - \brief configure the boot mode + \brief configure the boot mode \param[in] syscfg_bootmode: selects the memory remapping only one parameter can be selected which is shown as below: \arg SYSCFG_BOOTMODE_FLASH: main flash memory (0x08000000~0x083BFFFF) is mapped at address 0x00000000 @@ -68,7 +69,7 @@ void syscfg_bootmode_config(uint8_t syscfg_bootmode) } /*! - \brief FMC memory mapping swap + \brief FMC memory mapping swap \param[in] syscfg_fmc_swap: selects the interal flash bank swapping only one parameter can be selected which is shown as below: \arg SYSCFG_FMC_SWP_BANK0: bank 0 is mapped at address 0x08000000 and bank 1 is mapped at address 0x08100000 @@ -86,7 +87,7 @@ void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap) } /*! - \brief EXMC memory mapping swap + \brief EXMC memory mapping swap \param[in] syscfg_exmc_swap: selects the memories in EXMC swapping only one parameter can be selected which is shown as below: \arg SYSCFG_EXMC_SWP_ENABLE: SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card @@ -105,7 +106,7 @@ void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap) } /*! - \brief configure the GPIO pin as EXTI Line + \brief configure the GPIO pin as EXTI Line \param[in] exti_port: specify the GPIO port used in EXTI only one parameter can be selected which is shown as below: \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,E,F,G,H,I): EXTI GPIO port @@ -120,7 +121,7 @@ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); - switch(exti_pin/EXTI_SS_JSTEP){ + switch(exti_pin / EXTI_SS_JSTEP) { case EXTISS0: /* clear EXTI source line(0..3) */ SYSCFG_EXTISS0 &= clear_exti_mask; @@ -151,7 +152,7 @@ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) } /*! - \brief configure the PHY interface for the ethernet MAC + \brief configure the PHY interface for the ethernet MAC \param[in] syscfg_enet_phy_interface: specifies the media interface mode. only one parameter can be selected which is shown as below: \arg SYSCFG_ENET_PHY_MII: MII mode is selected @@ -170,7 +171,7 @@ void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) } /*! - \brief configure the I/O compensation cell + \brief configure the I/O compensation cell \param[in] syscfg_compensation: specifies the I/O compensation cell mode only one parameter can be selected which is shown as below: \arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled @@ -189,16 +190,16 @@ void syscfg_compensation_config(uint32_t syscfg_compensation) } /*! - \brief checks whether the I/O compensation cell ready flag is set or not + \brief checks whether the I/O compensation cell ready flag is set or not \param[in] none \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus syscfg_flag_get(void) { - if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){ + if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)) { return SET; - }else{ + } else { return RESET; } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c index e312680222..0fc34e3e05 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -45,7 +46,7 @@ OF SUCH DAMAGE. */ void timer_deinit(uint32_t timer_periph) { - switch(timer_periph){ + switch(timer_periph) { case TIMER0: /* reset TIMER0 */ rcu_periph_reset_enable(RCU_TIMER0RST); @@ -127,7 +128,7 @@ void timer_deinit(uint32_t timer_periph) \param[out] none \retval none */ -void timer_struct_para_init(timer_parameter_struct* initpara) +void timer_struct_para_init(timer_parameter_struct *initpara) { /* initialize the init parameter struct member with the default value */ initpara->prescaler = 0U; @@ -151,15 +152,15 @@ void timer_struct_para_init(timer_parameter_struct* initpara) \param[out] none \retval none */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) { /* configure the counter prescaler value */ TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; /* configure the counter direction and aligned mode */ if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) - || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); + || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM); TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; } @@ -167,13 +168,13 @@ void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) /* configure the autoreload value */ TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) { /* reset the CKDIV bit */ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; } - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* configure the repetition counter value */ TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; } @@ -303,7 +304,7 @@ void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t p { TIMER_PSC(timer_periph) = (uint32_t)prescaler; - if(TIMER_PSC_RELOAD_NOW == pscreload){ + if(TIMER_PSC_RELOAD_NOW == pscreload) { TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; } } @@ -327,7 +328,7 @@ void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) \param[out] none \retval none */ -void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload) +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) { TIMER_CAR(timer_periph) = (uint32_t)autoreload; } @@ -339,7 +340,7 @@ void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload) \param[out] none \retval none */ -void timer_counter_value_config(uint32_t timer_periph , uint32_t counter) +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) { TIMER_CNT(timer_periph) = (uint32_t)counter; } @@ -382,11 +383,11 @@ uint16_t timer_prescaler_read(uint32_t timer_periph) */ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) { - if(TIMER_SP_MODE_SINGLE == spmode){ + if(TIMER_SP_MODE_SINGLE == spmode) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ + } else if(TIMER_SP_MODE_REPETITIVE == spmode) { TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ + } else { /* illegal parameters */ } } @@ -403,159 +404,15 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) */ void timer_update_source_config(uint32_t timer_periph, uint32_t update) { - if(TIMER_UPDATE_SRC_REGULAR == update){ + if(TIMER_UPDATE_SRC_REGULAR == update) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(TIMER_UPDATE_SRC_GLOBAL == update){ + } else if(TIMER_UPDATE_SRC_GLOBAL == update) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ + } else { /* illegal parameters */ } } -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt enable source - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt source enable - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)flag); -} - /*! \brief enable the TIMER DMA \param[in] timer_periph: please refer to the following parameters @@ -608,11 +465,11 @@ void timer_dma_disable(uint32_t timer_periph, uint16_t dma) */ void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) { - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ + } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ + } else { /* illegal parameters */ } } @@ -676,12 +533,12 @@ void timer_event_software_generate(uint32_t timer_periph, uint16_t event) } /*! - \brief initialize TIMER break parameter struct with a default value + \brief initialize TIMER break parameter struct \param[in] breakpara: TIMER break parameter struct \param[out] none \retval none */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) { /* initialize the break parameter struct member with the default value */ breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; @@ -707,14 +564,14 @@ void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) \param[out] none \retval none */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) { - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| - ((uint32_t)(breakpara->ideloffstate))| - ((uint32_t)(breakpara->deadtime))| - ((uint32_t)(breakpara->breakpolarity))| + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode))| + ((uint32_t)(breakpara->protectmode)) | ((uint32_t)(breakpara->breakstate))) ; } @@ -771,9 +628,9 @@ void timer_automatic_output_disable(uint32_t timer_periph) */ void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) { - if(ENABLE == newvalue){ + if(ENABLE == newvalue) { TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ + } else { TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); } } @@ -787,9 +644,9 @@ void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) */ void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) { - if(ENABLE == newvalue){ + if(ENABLE == newvalue) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ + } else { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); } } @@ -806,11 +663,11 @@ void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus ne */ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) { - if(TIMER_UPDATECTL_CCU == ccuctl){ + if(TIMER_UPDATECTL_CCU == ccuctl) { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ + } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ + } else { /* illegal parameters */ } } @@ -821,7 +678,7 @@ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t c \param[out] none \retval none */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) { /* initialize the channel output parameter struct member with the default value */ ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; @@ -851,9 +708,9 @@ void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) \param[out] none \retval none */ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ @@ -866,7 +723,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* set the CH0P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the CH0NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); /* set the CH0NEN bit */ @@ -897,7 +754,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* set the CH1P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the CH1NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); /* set the CH1NEN bit */ @@ -928,7 +785,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* set the CH2P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the CH2NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); /* set the CH2NEN bit */ @@ -950,7 +807,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* configure TIMER_CH_3 */ case TIMER_CH_3: /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; /* set the CH3EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); @@ -959,7 +816,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* set the CH3P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the ISO3 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); /* set the ISO3 bit */ @@ -995,7 +852,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ */ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); @@ -1036,7 +893,7 @@ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, u */ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CH0CV(timer_periph) = (uint32_t)pulse; @@ -1051,7 +908,7 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t cha break; /* configure TIMER_CH_3 */ case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; break; default: break; @@ -1076,7 +933,7 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t cha */ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); @@ -1120,7 +977,7 @@ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, */ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); @@ -1164,7 +1021,7 @@ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, u */ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); @@ -1208,7 +1065,7 @@ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, */ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); @@ -1251,7 +1108,7 @@ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channe */ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); @@ -1290,7 +1147,7 @@ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, u */ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); @@ -1333,7 +1190,7 @@ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, */ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); @@ -1355,12 +1212,12 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint } /*! - \brief initialize TIMER channel input parameter struct with a default value + \brief initialize TIMER channel input parameter struct \param[in] icpara: TIMER channel intput parameter struct \param[out] none \retval none */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) { /* initialize the channel input parameter struct member with the default value */ icpara->icpolarity = TIMER_IC_POLARITY_RISING; @@ -1386,9 +1243,9 @@ void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) \param[out] none \retval none */ -void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara) +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ @@ -1432,7 +1289,7 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); /* reset the CH2MS bit */ @@ -1493,7 +1350,7 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic */ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); @@ -1535,7 +1392,7 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16 { uint32_t count_value = 0U; - switch(channel){ + switch(channel) { /* read TIMER channel 0 capture compare register value */ case TIMER_CH_0: count_value = TIMER_CH0CV(timer_periph); @@ -1573,30 +1430,30 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16 \param[out] none \retval none */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) { uint16_t icpolarity = 0x0U; uint16_t icselection = 0x0U; /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ + } else { icpolarity = TIMER_IC_POLARITY_RISING; } /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ + } else { icselection = TIMER_IC_SELECTION_DIRECTTI; } - if(TIMER_CH_0 == channel){ + if(TIMER_CH_0 == channel) { /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); /* reset the CH0MS bit */ @@ -1610,12 +1467,12 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); /* reset the CH1MS bit */ @@ -1629,12 +1486,12 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - }else{ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + } else { /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); /* reset the CH1MS bit */ @@ -1653,7 +1510,7 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; /* reset the CH0MS bit */ @@ -1683,11 +1540,11 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim */ void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) { - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ + if(TIMER_HALLINTERFACE_ENABLE == hallmode) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ + } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) { TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ + } else { /* illegal parameters */ } } @@ -1742,9 +1599,9 @@ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t o \param[in] slavemode: only one parameter can be selected which is shown as below: \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11)) - \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7)) - \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7)) - \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7)) + \arg TIMER_QUAD_DECODER_MODE0: quadrature decoder mode 0(TIMERx(x=0..4,7)) + \arg TIMER_QUAD_DECODER_MODE1: quadrature decoder mode 1(TIMERx(x=0..4,7)) + \arg TIMER_QUAD_DECODER_MODE2: quadrature decoder mode 2(TIMERx(x=0..4,7)) \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11)) \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11)) \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11)) @@ -1772,11 +1629,11 @@ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) */ void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) { - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ + } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ + } else { /* illegal parameters */ } } @@ -1808,12 +1665,12 @@ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, /*! \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] timer_periph: TIMERx(x=0..4,7) \param[in] decomode: only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \arg TIMER_QUAD_DECODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_QUAD_DECODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_QUAD_DECODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input \param[in] ic0polarity: only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge @@ -1826,17 +1683,17 @@ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, \retval none */ void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, - uint16_t ic0polarity, uint16_t ic1polarity) + uint16_t ic0polarity, uint16_t ic1polarity) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); } /*! @@ -1886,13 +1743,13 @@ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint \retval none */ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, - uint16_t extpolarity, uint32_t extfilter) + uint16_t extpolarity, uint32_t extfilter) { - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1NP bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); /* reset the CH1MS bit */ @@ -1905,11 +1762,11 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ + } else { /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; /* reset the CH0MS bit */ @@ -1924,7 +1781,7 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; } /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,extrigger); + timer_input_trigger_source_select(timer_periph, extrigger); /* reset the SMC bit */ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); /* set the SMC bit */ @@ -2032,11 +1889,11 @@ void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) */ void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) { - if(TIMER_CHVSEL_ENABLE == ccsel){ + if(TIMER_CHVSEL_ENABLE == ccsel) { TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - }else if(TIMER_CHVSEL_DISABLE == ccsel){ + } else if(TIMER_CHVSEL_DISABLE == ccsel) { TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; - }else{ + } else { /* illegal parameters */ } } @@ -2053,11 +1910,155 @@ void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) */ void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) { - if(TIMER_OUTSEL_ENABLE == outsel){ + if(TIMER_OUTSEL_ENABLE == outsel) { TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - }else if(TIMER_OUTSEL_DISABLE == outsel){ + } else if(TIMER_OUTSEL_DISABLE == outsel) { TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; - }else{ + } else { /* illegal parameters */ } } + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source enable + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); +} diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c index 9d719bb29b..2e4fad1fc4 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,7 +41,7 @@ OF SUCH DAMAGE. #define TLI_OPAQUE_VALUE 0x000000FFU /*! - \brief deinitialize TLI registers + \brief deinitialize TLI registers \param[in] none \param[out] none \retval none @@ -52,7 +53,7 @@ void tli_deinit(void) } /*! - \brief initialize the parameters of TLI parameter structure with the default values, it is suggested + \brief initialize the parameters of TLI parameter structure with the default values, it is suggested that call this function after a tli_parameter_struct structure is defined \param[in] none \param[out] tli_struct: the data needed to initialize TLI @@ -94,7 +95,7 @@ void tli_struct_para_init(tli_parameter_struct *tli_struct) } /*! - \brief initialize TLI display timing parameters + \brief initialize TLI display timing parameters \param[in] tli_struct: the data needed to initialize TLI synpsz_vpsz: size of the vertical synchronous pulse synpsz_hpsz: size of the horizontal synchronous pulse @@ -117,28 +118,28 @@ void tli_struct_para_init(tli_parameter_struct *tli_struct) void tli_init(tli_parameter_struct *tli_struct) { /* synchronous pulse size configuration */ - TLI_SPSZ &= ~(TLI_SPSZ_VPSZ|TLI_SPSZ_HPSZ); - TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz|((uint32_t)tli_struct->synpsz_hpsz<<16U)); + TLI_SPSZ &= ~(TLI_SPSZ_VPSZ | TLI_SPSZ_HPSZ); + TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz | ((uint32_t)tli_struct->synpsz_hpsz << 16U)); /* back-porch size configuration */ - TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ|TLI_BPSZ_HBPSZ); - TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz|((uint32_t)tli_struct->backpsz_hbpsz<<16U)); + TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ | TLI_BPSZ_HBPSZ); + TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz | ((uint32_t)tli_struct->backpsz_hbpsz << 16U)); /* active size configuration */ - TLI_ASZ &= ~(TLI_ASZ_VASZ|TLI_ASZ_HASZ); - TLI_ASZ = (tli_struct->activesz_vasz|(tli_struct->activesz_hasz<<16U)); + TLI_ASZ &= ~(TLI_ASZ_VASZ | TLI_ASZ_HASZ); + TLI_ASZ = (tli_struct->activesz_vasz | (tli_struct->activesz_hasz << 16U)); /* total size configuration */ - TLI_TSZ &= ~(TLI_TSZ_VTSZ|TLI_TSZ_HTSZ); - TLI_TSZ = (tli_struct->totalsz_vtsz|(tli_struct->totalsz_htsz<<16U)); + TLI_TSZ &= ~(TLI_TSZ_VTSZ | TLI_TSZ_HTSZ); + TLI_TSZ = (tli_struct->totalsz_vtsz | (tli_struct->totalsz_htsz << 16U)); /* background color configuration */ - TLI_BGC &= ~(TLI_BGC_BVB|(TLI_BGC_BVG)|(TLI_BGC_BVR)); - TLI_BGC = (tli_struct->backcolor_blue|(tli_struct->backcolor_green<<8U)|(tli_struct->backcolor_red<<16U)); - TLI_CTL &= ~(TLI_CTL_HPPS|TLI_CTL_VPPS|TLI_CTL_DEPS|TLI_CTL_CLKPS); - TLI_CTL |= (tli_struct->signalpolarity_hs|tli_struct->signalpolarity_vs|\ - tli_struct->signalpolarity_de|tli_struct->signalpolarity_pixelck); + TLI_BGC &= ~(TLI_BGC_BVB | (TLI_BGC_BVG) | (TLI_BGC_BVR)); + TLI_BGC = (tli_struct->backcolor_blue | (tli_struct->backcolor_green << 8U) | (tli_struct->backcolor_red << 16U)); + TLI_CTL &= ~(TLI_CTL_HPPS | TLI_CTL_VPPS | TLI_CTL_DEPS | TLI_CTL_CLKPS); + TLI_CTL |= (tli_struct->signalpolarity_hs | tli_struct->signalpolarity_vs | \ + tli_struct->signalpolarity_de | tli_struct->signalpolarity_pixelck); } /*! - \brief configure TLI dither function + \brief configure TLI dither function \param[in] dither_stat only one parameter can be selected which is shown as below: \arg TLI_DITHER_ENABLE @@ -148,15 +149,15 @@ void tli_init(tli_parameter_struct *tli_struct) */ void tli_dither_config(uint8_t dither_stat) { - if(TLI_DITHER_ENABLE == dither_stat){ + if(TLI_DITHER_ENABLE == dither_stat) { TLI_CTL |= TLI_CTL_DFEN; - }else{ + } else { TLI_CTL &= ~(TLI_CTL_DFEN); } } /*! - \brief enable TLI + \brief enable TLI \param[in] none \param[out] none \retval none @@ -167,7 +168,7 @@ void tli_enable(void) } /*! - \brief disable TLI + \brief disable TLI \param[in] none \param[out] none \retval none @@ -178,7 +179,7 @@ void tli_disable(void) } /*! - \brief configure TLI reload mode + \brief configure TLI reload mode \param[in] reload_mod only one parameter can be selected which is shown as below: \arg TLI_FRAME_BLANK_RELOAD_EN @@ -188,17 +189,17 @@ void tli_disable(void) */ void tli_reload_config(uint8_t reload_mod) { - if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod){ + if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod) { /* the layer configuration will be reloaded at frame blank */ TLI_RL |= TLI_RL_FBR; - }else{ + } else { /* the layer configuration will be reloaded after this bit sets */ TLI_RL |= TLI_RL_RQR; } } /*! - \brief initialize the parameters of TLI layer structure with the default values, it is suggested + \brief initialize the parameters of TLI layer structure with the default values, it is suggested that call this function after a tli_layer_parameter_struct structure is defined \param[in] none \param[out] layer_struct: TLI Layer parameter struct @@ -244,7 +245,7 @@ void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) } /*! - \brief initialize TLI layer + \brief initialize TLI layer \param[in] layerx: LAYERx(x=0,1) \param[in] layer_struct: TLI Layer parameter struct layer_window_rightpos: window right position @@ -268,14 +269,14 @@ void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) \param[out] none \retval none */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct) { /* configure layer window horizontal position */ - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos|((uint32_t)layer_struct->layer_window_rightpos<<16U)); + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos | ((uint32_t)layer_struct->layer_window_rightpos << 16U)); /* configure layer window vertical position */ - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos|((uint32_t)layer_struct->layer_window_bottompos<<16U)); + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos | ((uint32_t)layer_struct->layer_window_bottompos << 16U)); /* configure layer packeted pixel format */ TLI_LxPPF(layerx) &= ~(TLI_LxPPF_PPF); TLI_LxPPF(layerx) = layer_struct->layer_ppf; @@ -283,20 +284,20 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) TLI_LxSA(layerx) &= ~(TLI_LxSA_SA); TLI_LxSA(layerx) = layer_struct->layer_sa; /* configure layer default color */ - TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB|(TLI_LxDC_DCG)|(TLI_LxDC_DCR)|(TLI_LxDC_DCA)); - TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue|((uint32_t)layer_struct->layer_default_green<<8U) - |((uint32_t)layer_struct->layer_default_red<<16U) - |((uint32_t)layer_struct->layer_default_alpha<<24U)); + TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB | (TLI_LxDC_DCG) | (TLI_LxDC_DCR) | (TLI_LxDC_DCA)); + TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue | ((uint32_t)layer_struct->layer_default_green << 8U) + | ((uint32_t)layer_struct->layer_default_red << 16U) + | ((uint32_t)layer_struct->layer_default_alpha << 24U)); /* configure layer alpha calculation factors */ - TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2|(TLI_LxBLEND_ACF1)); - TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2)|(layer_struct->layer_acf1)); + TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2 | (TLI_LxBLEND_ACF1)); + TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2) | (layer_struct->layer_acf1)); /* configure layer frame buffer base address */ TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); /* configure layer frame line length */ - TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL|(TLI_LxFLLEN_STDOFF)); - TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length|((uint32_t)layer_struct->layer_frame_buf_stride_offset<<16U)); + TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL | (TLI_LxFLLEN_STDOFF)); + TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length | ((uint32_t)layer_struct->layer_frame_buf_stride_offset << 16U)); /* configure layer frame total line number */ TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); TLI_LxFTLN(layerx) = (uint32_t)(layer_struct->layer_frame_total_line_number); @@ -304,56 +305,56 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) } /*! - \brief reconfigure window position + \brief reconfigure window position \param[in] layerx: LAYERx(x=0,1) \param[in] offset_x: new horizontal offset \param[in] offset_y: new vertical offset \param[out] none \retval none */ -void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y) +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y) { /* configure window start position */ uint32_t layer_ppf, line_num, hstart, vstart; uint32_t line_length = 0U; - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - hstart = (uint32_t)offset_x+(((TLI_BPSZ & TLI_BPSZ_HBPSZ)>>16U)+1U); - vstart = (uint32_t)offset_y+((TLI_BPSZ & TLI_BPSZ_VBPSZ)+1U); + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + hstart = (uint32_t)offset_x + (((TLI_BPSZ & TLI_BPSZ_HBPSZ) >> 16U) + 1U); + vstart = (uint32_t)offset_y + ((TLI_BPSZ & TLI_BPSZ_VBPSZ) + 1U); line_num = (TLI_LxFTLN(layerx) & TLI_LxFTLN_FTLN); layer_ppf = (TLI_LxPPF(layerx) & TLI_LxPPF_PPF); /* the bytes of a line equal TLI_LxFLLEN_FLL bits value minus 3 */ - switch(layer_ppf){ + switch(layer_ppf) { case LAYER_PPF_ARGB8888: /* each pixel includes 4bytes, when pixel format is ARGB8888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/4U); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 4U); break; case LAYER_PPF_RGB888: /* each pixel includes 3bytes, when pixel format is RGB888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/3U); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 3U); break; case LAYER_PPF_RGB565: case LAYER_PPF_ARGB1555: case LAYER_PPF_ARGB4444: case LAYER_PPF_AL88: /* each pixel includes 2bytes, when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/2U); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 2U); break; case LAYER_PPF_L8: case LAYER_PPF_AL44: /* each pixel includes 1byte, when pixel format is L8 or AL44 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U)); break; default: break; } /* reconfigure window position */ - TLI_LxHPOS(layerx) = (hstart|((hstart+line_length-1U)<<16U)); - TLI_LxVPOS(layerx) = (vstart|((vstart+line_num-1U)<<16U)); + TLI_LxHPOS(layerx) = (hstart | ((hstart + line_length - 1U) << 16U)); + TLI_LxVPOS(layerx) = (vstart | ((vstart + line_num - 1U) << 16U)); } /*! - \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested + \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested that call this function after a tli_layer_lut_parameter_struct structure is defined \param[in] none \param[out] lut_struct: TLI layer LUT parameter struct @@ -373,7 +374,7 @@ void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) } /*! - \brief initialize TLI layer LUT + \brief initialize TLI layer LUT \param[in] layerx: LAYERx(x=0,1) \param[in] lut_struct: TLI layer LUT parameter struct layer_table_addr: look up table write address @@ -383,16 +384,15 @@ void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) \param[out] none \retval none */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct) +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct) { - TLI_LxLUT(layerx) &= ~(TLI_LxLUT_TB|TLI_LxLUT_TG|TLI_LxLUT_TR|TLI_LxLUT_TADD); - TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue)|((uint32_t)lut_struct->layer_lut_channel_green<<8U) - |((uint32_t)lut_struct->layer_lut_channel_red<<16U - |((uint32_t)lut_struct->layer_table_addr<<24U))); + TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue) | ((uint32_t)lut_struct->layer_lut_channel_green << 8U) + | ((uint32_t)lut_struct->layer_lut_channel_red << 16U + | ((uint32_t)lut_struct->layer_table_addr << 24U))); } /*! - \brief initialize TLI layer color key + \brief initialize TLI layer color key \param[in] layerx: LAYERx(x=0,1) \param[in] redkey: color key red \param[in] greenkey: color key green @@ -400,13 +400,13 @@ void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct) \param[out] none \retval none */ -void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey) +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey) { - TLI_LxCKEY(layerx) = (((uint32_t)bluekey)|((uint32_t)greenkey<<8U)|((uint32_t)redkey<<16U)); + TLI_LxCKEY(layerx) = (((uint32_t)bluekey) | ((uint32_t)greenkey << 8U) | ((uint32_t)redkey << 16U)); } /*! - \brief enable TLI layer + \brief enable TLI layer \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -417,7 +417,7 @@ void tli_layer_enable(uint32_t layerx) } /*! - \brief disable TLI layer + \brief disable TLI layer \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -428,7 +428,7 @@ void tli_layer_disable(uint32_t layerx) } /*! - \brief enable TLI layer color keying + \brief enable TLI layer color keying \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -439,7 +439,7 @@ void tli_color_key_enable(uint32_t layerx) } /*! - \brief disable TLI layer color keying + \brief disable TLI layer color keying \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -450,7 +450,7 @@ void tli_color_key_disable(uint32_t layerx) } /*! - \brief enable TLI layer LUT + \brief enable TLI layer LUT \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -461,7 +461,7 @@ void tli_lut_enable(uint32_t layerx) } /*! - \brief disable TLI layer LUT + \brief disable TLI layer LUT \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none @@ -472,7 +472,7 @@ void tli_lut_disable(uint32_t layerx) } /*! - \brief set line mark value + \brief set line mark value \param[in] line_num: line number \param[out] none \retval none @@ -484,7 +484,7 @@ void tli_line_mark_set(uint16_t line_num) } /*! - \brief get current displayed position + \brief get current displayed position \param[in] none \param[out] none \retval position of current pixel @@ -495,7 +495,7 @@ uint32_t tli_current_pos_get(void) } /*! - \brief enable TLI interrupt + \brief enable TLI interrupt \param[in] int_flag: TLI interrupt flags one or more parameters can be selected which are shown as below: \arg TLI_INT_LM: line mark interrupt @@ -511,7 +511,7 @@ void tli_interrupt_enable(uint32_t int_flag) } /*! - \brief disable TLI interrupt + \brief disable TLI interrupt \param[in] int_flag: TLI interrupt flags one or more parameters can be selected which are shown as below: \arg TLI_INT_LM: line mark interrupt @@ -527,7 +527,7 @@ void tli_interrupt_disable(uint32_t int_flag) } /*! - \brief get TLI interrupt flag + \brief get TLI interrupt flag \param[in] int_flag: TLI interrupt flags one or more parameters can be selected which are shown as below: \arg TLI_INT_FLAG_LM: line mark interrupt flag @@ -541,9 +541,9 @@ FlagStatus tli_interrupt_flag_get(uint32_t int_flag) { uint32_t state; state = TLI_INTF; - if(state & int_flag){ + if(state & int_flag) { state = TLI_INTEN; - if(state & int_flag){ + if(state & int_flag) { return SET; } } @@ -551,7 +551,7 @@ FlagStatus tli_interrupt_flag_get(uint32_t int_flag) } /*! - \brief clear TLI interrupt flag + \brief clear TLI interrupt flag \param[in] int_flag: TLI interrupt flags one or more parameters can be selected which are shown as below: \arg TLI_INT_FLAG_LM: line mark interrupt flag @@ -567,7 +567,7 @@ void tli_interrupt_flag_clear(uint32_t int_flag) } /*! - \brief get TLI flag or state in TLI_INTF register or TLI_STAT register + \brief get TLI flag or state in TLI_INTF register or TLI_STAT register \param[in] flag: TLI flags or states only one parameter can be selected which is shown as below: \arg TLI_FLAG_VDE: current VDE state @@ -585,14 +585,14 @@ FlagStatus tli_flag_get(uint32_t flag) { uint32_t stat; /* choose which register to get flag or state */ - if(flag >> 31U){ + if(flag >> 31U) { stat = TLI_INTF; - }else{ + } else { stat = TLI_STAT; } - if(flag & stat){ + if(flag & stat) { return SET; - }else{ + } else { return RESET; } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c index 8c86bb832e..862432ca4e 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,7 +38,7 @@ OF SUCH DAMAGE. #include "gd32f4xx_trng.h" /*! - \brief deinitialize the TRNG + \brief reset TRNG \param[in] none \param[out] none \retval none @@ -49,7 +50,7 @@ void trng_deinit(void) } /*! - \brief enable the TRNG interface + \brief enable TRNG \param[in] none \param[out] none \retval none @@ -60,7 +61,7 @@ void trng_enable(void) } /*! - \brief disable the TRNG interface + \brief disable TRNG \param[in] none \param[out] none \retval none @@ -74,7 +75,7 @@ void trng_disable(void) \brief get the true random data \param[in] none \param[out] none - \retval the generated random data + \retval uint32_t: 0x0-0xFFFFFFFF */ uint32_t trng_get_true_random_data(void) { @@ -82,70 +83,70 @@ uint32_t trng_get_true_random_data(void) } /*! - \brief enable the TRNG interrupt + \brief enable TRNG interrupt \param[in] none \param[out] none \retval none */ void trng_interrupt_enable(void) { - TRNG_CTL |= TRNG_CTL_IE; + TRNG_CTL |= TRNG_CTL_TRNGIE; } /*! - \brief disable the TRNG interrupt + \brief disable TRNG interrupt \param[in] none \param[out] none \retval none */ void trng_interrupt_disable(void) { - TRNG_CTL &= ~TRNG_CTL_IE; + TRNG_CTL &= ~TRNG_CTL_TRNGIE; } /*! - \brief get the trng status flags - \param[in] flag: trng status flag, refer to trng_flag_enum + \brief get TRNG flag status + \param[in] flag: TRNG flag only one parameter can be selected which is shown as below: - \arg TRNG_FLAG_DRDY: Random Data ready status - \arg TRNG_FLAG_CECS: Clock error current status - \arg TRNG_FLAG_SECS: Seed error current status + \arg TRNG_FLAG_DRDY: random Data ready status + \arg TRNG_FLAG_CECS: clock error current status + \arg TRNG_FLAG_SECS: seed error current status \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus trng_flag_get(trng_flag_enum flag) { - if(RESET != (TRNG_STAT & flag)){ + if(RESET != (TRNG_STAT & flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief get the trng interrupt flags - \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum + \brief get TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag only one parameter can be selected which is shown as below: \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag - \arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag) { - if(RESET != (TRNG_STAT & int_flag)){ + if(RESET != (TRNG_STAT & int_flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear the trng interrupt flags - \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum + \brief clear TRNG interrupt flag status + \param[in] int_flag: TRNG interrupt flag only one parameter can be selected which is shown as below: \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag - \arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag + \arg TRNG_INT_FLAG_SEIF: seed error interrupt flag \param[out] none \retval none */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c index 1b864e3b96..e54929d941 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c @@ -5,10 +5,11 @@ \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx + \version 2022-03-09, V3.0.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -34,7 +35,6 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI OF SUCH DAMAGE. */ - #include "gd32f4xx_usart.h" /* USART register bit offset */ @@ -43,14 +43,14 @@ OF SUCH DAMAGE. #define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ /*! - \brief reset USART/UART + \brief reset USART/UART \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none */ void usart_deinit(uint32_t usart_periph) { - switch(usart_periph){ + switch(usart_periph) { case USART0: rcu_periph_reset_enable(RCU_USART0RST); rcu_periph_reset_disable(RCU_USART0RST); @@ -89,7 +89,7 @@ void usart_deinit(uint32_t usart_periph) } /*! - \brief configure USART baud rate value + \brief configure USART baud rate value \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] baudval: baud rate value \param[out] none @@ -97,45 +97,45 @@ void usart_deinit(uint32_t usart_periph) */ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) { - uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; - switch(usart_periph){ - /* get clock frequency */ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch(usart_periph) { + /* get clock frequency */ case USART0: - uclk=rcu_clock_freq_get(CK_APB2); - break; + uclk = rcu_clock_freq_get(CK_APB2); + break; case USART5: - uclk=rcu_clock_freq_get(CK_APB2); - break; + uclk = rcu_clock_freq_get(CK_APB2); + break; case USART1: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case USART2: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART3: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART4: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART6: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART7: - uclk=rcu_clock_freq_get(CK_APB1); - break; + uclk = rcu_clock_freq_get(CK_APB1); + break; default: - break; + break; } - if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){ + if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD) { /* when oversampling by 8, configure the value of USART_BAUD */ - udiv = ((2U*uclk) + baudval/2U)/baudval; + udiv = ((2U * uclk) + baudval / 2U) / baudval; intdiv = udiv & 0xfff0U; - fradiv = (udiv>>1U) & 0x7U; + fradiv = (udiv >> 1U) & 0x7U; USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - }else{ + } else { /* when oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; + udiv = (uclk + baudval / 2U) / baudval; intdiv = udiv & 0xfff0U; fradiv = udiv & 0xfU; USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); @@ -143,7 +143,7 @@ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) } /*! - \brief configure USART parity function + \brief configure USART parity function \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] paritycfg: configure USART parity only one parameter can be selected which is shown as below: @@ -157,12 +157,12 @@ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) { /* clear USART_CTL0 PM,PCEN Bits */ USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ + /* configure USART parity mode */ USART_CTL0(usart_periph) |= paritycfg ; } /*! - \brief configure USART word length + \brief configure USART word length \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] wlen: USART word length configure only one parameter can be selected which is shown as below: @@ -180,7 +180,7 @@ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) } /*! - \brief configure USART stop bit length + \brief configure USART stop bit length \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] stblen: USART stop bit configure only one parameter can be selected which is shown as below: @@ -199,7 +199,7 @@ void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) USART_CTL1(usart_periph) |= stblen; } /*! - \brief enable USART + \brief enable USART \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -210,7 +210,7 @@ void usart_enable(uint32_t usart_periph) } /*! - \brief disable USART + \brief disable USART \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -221,7 +221,7 @@ void usart_disable(uint32_t usart_periph) } /*! - \brief configure USART transmitter + \brief configure USART transmitter \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] txconfig: enable or disable USART transmitter only one parameter can be selected which is shown as below: @@ -242,7 +242,7 @@ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) } /*! - \brief configure USART receiver + \brief configure USART receiver \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] rxconfig: enable or disable USART receiver only one parameter can be selected which is shown as below: @@ -263,7 +263,7 @@ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) } /*! - \brief data is transmitted/received with the LSB/MSB first + \brief data is transmitted/received with the LSB/MSB first \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] msbf: LSB/MSB only one parameter can be selected which is shown as below: @@ -284,7 +284,7 @@ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) } /*! - \brief configure USART inversion + \brief configure USART inversion \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] invertpara: refer to enum USART_INVERT_CONFIG only one parameter can be selected which is shown as below: @@ -300,7 +300,7 @@ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) { /* inverted or not the specified siginal */ - switch(invertpara){ + switch(invertpara) { case USART_DINV_ENABLE: USART_CTL3(usart_periph) |= USART_CTL3_DINV; break; @@ -325,7 +325,7 @@ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) } /*! - \brief configure the USART oversample mode + \brief configure the USART oversample mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] oversamp: oversample value only one parameter can be selected which is shown as below: @@ -342,7 +342,7 @@ void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) } /*! - \brief configure sample bit method + \brief configure sample bit method \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] obsm: sample bit only one parameter can be selected which is shown as below: @@ -358,7 +358,7 @@ void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm) } /*! - \brief enable receiver timeout of USART + \brief enable receiver timeout of USART \param[in] usart_periph: USARTx(x=0,1,2,5) \param[out] none \retval none @@ -369,7 +369,7 @@ void usart_receiver_timeout_enable(uint32_t usart_periph) } /*! - \brief disable receiver timeout of USART + \brief disable receiver timeout of USART \param[in] usart_periph: USARTx(x=0,1,2,5) \param[out] none \retval none @@ -380,7 +380,7 @@ void usart_receiver_timeout_disable(uint32_t usart_periph) } /*! - \brief set the receiver timeout threshold of USART + \brief set the receiver timeout threshold of USART \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] rtimeout: 0-0x00FFFFFF \param[out] none @@ -393,19 +393,19 @@ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rti } /*! - \brief USART transmit data function + \brief USART transmit data function \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] data: data of transmission \param[out] none \retval none */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) +void usart_data_transmit(uint32_t usart_periph, uint16_t data) { - USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); + USART_DATA(usart_periph) = USART_DATA_DATA & (uint32_t)data; } /*! - \brief USART receive data function + \brief USART receive data function \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval data of received @@ -416,7 +416,7 @@ uint16_t usart_data_receive(uint32_t usart_periph) } /*! - \brief configure the address of the USART in wake up by address match mode + \brief configure the address of the USART in wake up by address match mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] addr: address of USART/UART \param[out] none @@ -425,11 +425,11 @@ uint16_t usart_data_receive(uint32_t usart_periph) void usart_address_config(uint32_t usart_periph, uint8_t addr) { USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (uint32_t)addr); } /*! - \brief enable mute mode + \brief enable mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -440,7 +440,7 @@ void usart_mute_mode_enable(uint32_t usart_periph) } /*! - \brief disable mute mode + \brief disable mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -451,7 +451,7 @@ void usart_mute_mode_disable(uint32_t usart_periph) } /*! - \brief configure wakeup method in mute mode + \brief configure wakeup method in mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] wmehtod: two method be used to enter or exit the mute mode only one parameter can be selected which is shown as below: @@ -467,7 +467,7 @@ void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod) } /*! - \brief enable LIN mode + \brief enable LIN mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -478,7 +478,7 @@ void usart_lin_mode_enable(uint32_t usart_periph) } /*! - \brief disable LIN mode + \brief disable LIN mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -489,7 +489,7 @@ void usart_lin_mode_disable(uint32_t usart_periph) } /*! - \brief configure lin break frame length + \brief configure lin break frame length \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] lblen: lin break frame length only one parameter can be selected which is shown as below: @@ -505,7 +505,7 @@ void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lbl } /*! - \brief send break frame + \brief send break frame \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -516,7 +516,7 @@ void usart_send_break(uint32_t usart_periph) } /*! - \brief enable half duplex mode + \brief enable half duplex mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -527,7 +527,7 @@ void usart_halfduplex_enable(uint32_t usart_periph) } /*! - \brief disable half duplex mode + \brief disable half duplex mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -538,7 +538,7 @@ void usart_halfduplex_disable(uint32_t usart_periph) } /*! - \brief enable CK pin in synchronous mode + \brief enable CK pin in synchronous mode \param[in] usart_periph: USARTx(x=0,1,2,5) \param[out] none \retval none @@ -549,7 +549,7 @@ void usart_synchronous_clock_enable(uint32_t usart_periph) } /*! - \brief disable CK pin in synchronous mode + \brief disable CK pin in synchronous mode \param[in] usart_periph: USARTx(x=0,1,2,5) \param[out] none \retval none @@ -560,7 +560,7 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) } /*! - \brief configure USART synchronous mode parameters + \brief configure USART synchronous mode parameters \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] clen: CK length only one parameter can be selected which is shown as below: @@ -579,32 +579,25 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) */ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) { - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) = ctl; + USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + USART_CTL1(usart_periph) = (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); } /*! - \brief configure guard time value in smartcard mode + \brief configure guard time value in smartcard mode \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] guat: guard time value, 0-0xFF \param[out] none \retval none */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) +void usart_guard_time_config(uint32_t usart_periph, uint8_t guat) { USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)<> 8U);(uint8_t)(x >> 16U) +#define FORMAT_24BIT(x) (uint8_t)(x);(uint8_t)((x) >> 8U);(uint8_t)((x) >> 16U) /* number of sub-packets in the audio transfer buffer. you can modify this value but always make sure that it is an even number and higher than 3 */ -#define OUT_PACKET_NUM 4U +#define OUT_PACKET_NUM 200U /* total size of the audio transfer buffer */ -#define OUT_BUF_MARGIN 4U -#define TOTAL_OUT_BUF_SIZE ((uint32_t)((SPEAKER_OUT_PACKET + OUT_BUF_MARGIN) * OUT_PACKET_NUM)) +#define OUT_BUF_MARGIN 0U +#define TOTAL_OUT_BUF_SIZE ((uint32_t)((SPEAKER_OUT_PACKET + OUT_BUF_MARGIN) * OUT_PACKET_NUM)) -#define AUDIO_CONFIG_DESC_SET_LEN (sizeof(usb_desc_config_set)) -#define AUDIO_INTERFACE_DESC_SIZE 9U +#define AD_CONFIG_DESC_SET_LEN (sizeof(usb_desc_config_set)) +#define AD_INTERFACE_DESC_SIZE 9U -#define USB_AUDIO_DESC_SIZ 0x09U -#define AUDIO_STANDARD_EP_DESC_SIZE 0x09U -#define AUDIO_STREAMING_EP_DESC_SIZE 0x07U +#define USB_AD_DESC_SIZ 0x09U +#define AD_STANDARD_EP_DESC_SIZE 0x09U +#define AD_STREAMING_EP_DESC_SIZE 0x07U /* audio interface class code */ -#define USB_CLASS_AUDIO 0x01U +#define USB_CLASS_AUDIO 0x01U /* audio interface subclass codes */ -#define AUDIO_SUBCLASS_CONTROL 0x01U -#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02U -#define AUDIO_SUBCLASS_MIDISTREAMING 0x03U +#define AD_SUBCLASS_CONTROL 0x01U +#define AD_SUBCLASS_AUDIOSTREAMING 0x02U +#define AD_SUBCLASS_MIDISTREAMING 0x03U /* audio interface protocol codes */ -#define AUDIO_PROTOCOL_UNDEFINED 0x00U -#define AUDIO_STREAMING_GENERAL 0x01U -#define AUDIO_STREAMING_FORMAT_TYPE 0x02U +#define AD_PROTOCOL_UNDEFINED 0x00U +#define AD_STREAMING_GENERAL 0x01U +#define AD_STREAMING_FORMAT_TYPE 0x02U /* audio class-specific descriptor types */ -#define AUDIO_DESCTYPE_UNDEFINED 0x20U -#define AUDIO_DESCTYPE_DEVICE 0x21U -#define AUDIO_DESCTYPE_CONFIGURATION 0x22U -#define AUDIO_DESCTYPE_STRING 0x23U -#define AUDIO_DESCTYPE_INTERFACE 0x24U -#define AUDIO_DESCTYPE_ENDPOINT 0x25U +#define AD_DESCTYPE_UNDEFINED 0x20U +#define AD_DESCTYPE_DEVICE 0x21U +#define AD_DESCTYPE_CONFIGURATION 0x22U +#define AD_DESCTYPE_STRING 0x23U +#define AD_DESCTYPE_INTERFACE 0x24U +#define AD_DESCTYPE_ENDPOINT 0x25U /* audio control interface descriptor subtypes */ -#define AUDIO_CONTROL_HEADER 0x01U -#define AUDIO_CONTROL_INPUT_TERMINAL 0x02U -#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03U -#define AUDIO_CONTROL_MIXER_UNIT 0x04U -#define AUDIO_CONTROL_SELECTOR_UNIT 0x05U -#define AUDIO_CONTROL_FEATURE_UNIT 0x06U -#define AUDIO_CONTROL_PROCESSING_UNIT 0x07U -#define AUDIO_CONTROL_EXTENSION_UNIT 0x08U +#define AD_CONTROL_HEADER 0x01U +#define AD_CONTROL_INPUT_TERMINAL 0x02U +#define AD_CONTROL_OUTPUT_TERMINAL 0x03U +#define AD_CONTROL_MIXER_UNIT 0x04U +#define AD_CONTROL_SELECTOR_UNIT 0x05U +#define AD_CONTROL_FEATURE_UNIT 0x06U +#define AD_CONTROL_PROCESSING_UNIT 0x07U +#define AD_CONTROL_EXTENSION_UNIT 0x08U -#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0CU -#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09U -#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07U +#define AD_INPUT_TERMINAL_DESC_SIZE 0x0CU +#define AD_OUTPUT_TERMINAL_DESC_SIZE 0x09U +#define AD_STREAMING_INTERFACE_DESC_SIZE 0x07U -#define AUDIO_CONTROL_MUTE 0x01U -#define AUDIO_CONTROL_VOLUME 0x02U +#define AD_CONTROL_MUTE 0x01U +#define AD_CONTROL_VOLUME 0x02U -#define AUDIO_FORMAT_TYPE_I 0x01U -#define AUDIO_FORMAT_TYPE_III 0x03U +#define AD_FORMAT_TYPE_I 0x01U +#define AD_FORMAT_TYPE_III 0x03U -#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01U -#define AUDIO_ENDPOINT_GENERAL 0x01U +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01U +#define AD_ENDPOINT_GENERAL 0x01U -#define AUDIO_REQ_UNDEFINED 0x00U -#define AUDIO_REQ_SET_CUR 0x01U -#define AUDIO_REQ_GET_CUR 0x81U -#define AUDIO_REQ_SET_MIN 0x02U -#define AUDIO_REQ_GET_MIN 0x82U -#define AUDIO_REQ_SET_MAX 0x03U -#define AUDIO_REQ_GET_MAX 0x83U -#define AUDIO_REQ_SET_RES 0x04U -#define AUDIO_REQ_GET_RES 0x84U -#define AUDIO_REQ_SET_MEM 0x05U -#define AUDIO_REQ_GET_MEM 0x85U -#define AUDIO_REQ_GET_STAT 0xFFU +#define AD_REQ_UNDEFINED 0x00U +#define AD_REQ_SET_CUR 0x01U +#define AD_REQ_GET_CUR 0x81U +#define AD_REQ_SET_MIN 0x02U +#define AD_REQ_GET_MIN 0x82U +#define AD_REQ_SET_MAX 0x03U +#define AD_REQ_GET_MAX 0x83U +#define AD_REQ_SET_RES 0x04U +#define AD_REQ_GET_RES 0x84U +#define AD_REQ_SET_MEM 0x05U +#define AD_REQ_GET_MEM 0x85U +#define AD_REQ_GET_STAT 0xFFU -#define AUDIO_OUT_STREAMING_CTRL 0x05U -#define AUDIO_IN_STREAMING_CTRL 0x02U +#define AD_OUT_STREAMING_CTRL 0x05U +#define AD_IN_STREAMING_CTRL 0x02U /* audio stream interface number */ enum { -#ifdef USE_USB_AUDIO_MICPHONE +#ifdef USE_USB_AD_MICPHONE MIC_INTERFACE_COUNT, -#endif -#ifdef USE_USB_AUDIO_SPEAKER +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER SPEAK_INTERFACE_COUNT, -#endif +#endif /* USE_USB_AD_SPEAKER */ CONFIG_DESC_AS_ITF_COUNT, }; -#define AC_ITF_TOTAL_LEN (sizeof(usb_desc_AC_itf) + CONFIG_DESC_AS_ITF_COUNT*(sizeof(usb_desc_input_terminal) + \ +#define AC_ITF_TOTAL_LEN (sizeof(usb_desc_AC_itf) + CONFIG_DESC_AS_ITF_COUNT*(sizeof(usb_desc_input_terminal) + \ sizeof(usb_desc_mono_feature_unit) + sizeof(usb_desc_output_terminal))) #pragma pack(1) @@ -138,13 +141,13 @@ typedef struct uint16_t bcdADC; /*!< audio device class specification release number in binary-coded decimal */ uint16_t wTotalLength; /*!< total number of bytes */ uint8_t bInCollection; /*!< the number of the streaming interfaces */ -#ifdef USE_USB_AUDIO_MICPHONE +#ifdef USE_USB_AD_MICPHONE uint8_t baInterfaceNr0; /*!< interface number of the streaming interfaces */ -#endif +#endif /* USE_USB_AD_MICPHONE */ -#ifdef USE_USB_AUDIO_SPEAKER +#ifdef USE_USB_AD_SPEAKER uint8_t baInterfaceNr1; /*!< interface number of the streaming interfaces */ -#endif +#endif /* USE_USB_AD_SPEAKER */ } usb_desc_AC_itf; typedef struct @@ -237,64 +240,83 @@ typedef struct uint16_t wLockDelay; /*!< indicates the time it takes this endpoint to reliably lock its internal clock recovery circuitry */ } usb_desc_AS_ep; +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bEndpointAddress; /*!< EP_GENERAL descriptor subtype */ + uint8_t bmAttributes; /*!< transfer type and synchronization type */ + uint16_t wMaxPacketSize; /*!< maximum packet size this endpoint is capable of sending or receiving */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ + uint8_t Refresh; /*!< bRefresh 1~9, power of 2 */ + uint8_t bSynchAddress; /* bSynchAddress */ +} usb_desc_FeedBack_ep; + #pragma pack() /* USB configuration descriptor structure */ typedef struct { - usb_desc_config config; - usb_desc_itf std_itf; - usb_desc_AC_itf ac_itf; + usb_desc_config config; + usb_desc_itf std_itf; + usb_desc_AC_itf ac_itf; -#ifdef USE_USB_AUDIO_MICPHONE - usb_desc_input_terminal mic_in_terminal; - usb_desc_mono_feature_unit mic_feature_unit; - usb_desc_output_terminal mic_out_terminal; +#ifdef USE_USB_AD_MICPHONE + usb_desc_input_terminal mic_in_terminal; + usb_desc_mono_feature_unit mic_feature_unit; + usb_desc_output_terminal mic_out_terminal; #endif -#ifdef USE_USB_AUDIO_SPEAKER +#ifdef USE_USB_AD_SPEAKER usb_desc_input_terminal speak_in_terminal; usb_desc_mono_feature_unit speak_feature_unit; usb_desc_output_terminal speak_out_terminal; -#endif +#endif /* USE_USB_AD_SPEAKER */ -#ifdef USE_USB_AUDIO_MICPHONE - usb_desc_itf mic_std_as_itf_zeroband; - usb_desc_itf mic_std_as_itf_opera; - usb_desc_AS_itf mic_as_itf; - usb_desc_format_type mic_format_typeI; - usb_desc_std_ep mic_std_endpoint; - usb_desc_AS_ep mic_as_endpoint; -#endif +#ifdef USE_USB_AD_MICPHONE + usb_desc_itf mic_std_as_itf_zeroband; + usb_desc_itf mic_std_as_itf_opera; + usb_desc_AS_itf mic_as_itf; + usb_desc_format_type mic_format_typeI; + usb_desc_std_ep mic_std_endpoint; + usb_desc_AS_ep mic_as_endpoint; +#endif /* USE_USB_AD_MICPHONE */ -#ifdef USE_USB_AUDIO_SPEAKER +#ifdef USE_USB_AD_SPEAKER usb_desc_itf speak_std_as_itf_zeroband; usb_desc_itf speak_std_as_itf_opera; usb_desc_AS_itf speak_as_itf; usb_desc_format_type speak_format_typeI; usb_desc_std_ep speak_std_endpoint; usb_desc_AS_ep speak_as_endpoint; -#endif + usb_desc_FeedBack_ep speak_feedback_endpoint; +#endif /* USE_USB_AD_SPEAKER */ } usb_desc_config_set; typedef struct { /* main buffer for audio data out transfers and its relative pointers */ - uint8_t isoc_out_buff[TOTAL_OUT_BUF_SIZE * 2U]; + uint8_t isoc_out_buff[TOTAL_OUT_BUF_SIZE]; uint8_t* isoc_out_wrptr; uint8_t* isoc_out_rdptr; + uint16_t buf_free_size; + uint16_t dam_tx_len; + + __IO uint32_t actual_freq; + __IO uint8_t play_flag; + uint8_t feedback_freq[3]; + uint32_t cur_sam_freq; + + /* usb receive buffer */ + uint8_t usb_rx_buffer[SPEAKER_OUT_MAX_PACKET]; /* main buffer for audio control requests transfers and its relative variables */ uint8_t audioctl[64]; uint8_t audioctl_unit; uint32_t audioctl_len; - -#ifdef USE_USB_AUDIO_SPEAKER - uint32_t play_flag; -#endif /* USE_USB_AUDIO_SPEAKER */ } usbd_audio_handler; extern usb_desc audio_desc; extern usb_class_core usbd_audio_cb; +extern usbd_audio_handler audio_handler; #endif /* __AUDIO_CORE_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Include/audio_out_itf.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Include/audio_out_itf.h index b143c5fa44..f4bfc56b10 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Include/audio_out_itf.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Include/audio_out_itf.h @@ -3,32 +3,34 @@ \brief audio OUT (playback) interface header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -36,39 +38,12 @@ OF SUCH DAMAGE. #define __AUDIO_OUT_ITF_H #include "usbd_conf.h" - -/* audio commands enumeration */ -typedef enum -{ - AUDIO_CMD_PLAY = 1U, - AUDIO_CMD_PAUSE, - AUDIO_CMD_STOP, -}audio_cmd_enum; - -/* mute commands */ -#define AUDIO_MUTE 0x01U -#define AUDIO_UNMUTE 0x00U - -/* functions return value */ -#define AUDIO_OK 0x00U -#define AUDIO_FAIL 0xFFU - -/* audio machine states */ -#define AUDIO_STATE_INACTIVE 0x00U -#define AUDIO_STATE_ACTIVE 0x01U -#define AUDIO_STATE_PLAYING 0x02U -#define AUDIO_STATE_PAUSED 0x03U -#define AUDIO_STATE_STOPPED 0x04U -#define AUDIO_STATE_ERROR 0x05U +#include "string.h" typedef struct { - uint8_t (*audio_init) (uint32_t audio_freq, uint32_t volume, uint32_t options); - uint8_t (*audio_deinit) (uint32_t options); + uint8_t (*audio_init) (uint32_t audio_freq, uint32_t volume); + uint8_t (*audio_deinit) (void); uint8_t (*audio_cmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd); - uint8_t (*audio_volume_ctl) (uint8_t vol); - uint8_t (*audio_mute_ctl) (uint8_t cmd); - uint8_t (*audio_periodic_tc) (uint8_t cmd); - uint8_t (*audio_state_get) (void); } audio_fops_struct; extern audio_fops_struct audio_out_fops; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Source/audio_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Source/audio_core.c index 6f686aec70..92f6861b47 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Source/audio_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Source/audio_core.c @@ -3,77 +3,92 @@ \brief USB audio device class core functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "audio_out_itf.h" #include "audio_core.h" #include +#include #define USBD_VID 0x28E9U #define USBD_PID 0x9574U -#ifdef USE_USB_AUDIO_MICPHONE +#define VOL_MIN 0U /* volume Minimum Value */ +#define VOL_MAX 100U /* volume Maximum Value */ +#define VOL_RES 1U /* volume Resolution */ +#define VOL_0dB 70U /* 0dB is in the middle of VOL_MIN and VOL_MAX */ + +#ifdef USE_USB_AD_MICPHONE extern volatile uint32_t count_data; extern const char wavetestdata[]; #define LENGTH_DATA (1747 * 32) -#endif +#endif /* USE_USB_AD_MICPHONE */ + +__ALIGN_BEGIN usbd_audio_handler audio_handler __ALIGN_END; /* local function prototypes ('static') */ static uint8_t audio_init (usb_dev *udev, uint8_t config_index); static uint8_t audio_deinit (usb_dev *udev, uint8_t config_index); static uint8_t audio_req_handler (usb_dev *udev, usb_req *req); +static uint8_t audio_set_intf (usb_dev *udev, usb_req *req); +static uint8_t audio_ctlx_out (usb_dev *udev); static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num); static uint8_t audio_data_out (usb_dev *udev, uint8_t ep_num); -static uint8_t usbd_audio_sof (usb_dev *udev); +static uint8_t audio_sof (usb_dev *udev); +static uint8_t audio_iso_in_incomplete (usb_dev *udev); +static uint8_t audio_iso_out_incomplete (usb_dev *udev); +static uint32_t usbd_audio_spk_get_feedback(usb_dev *udev); +static void get_feedback_fs_rate(uint32_t rate, uint8_t *buf); usb_class_core usbd_audio_cb = { .init = audio_init, .deinit = audio_deinit, .req_proc = audio_req_handler, + .set_intf = audio_set_intf, + .ctlx_out = audio_ctlx_out, .data_in = audio_data_in, .data_out = audio_data_out, - .SOF = usbd_audio_sof + .SOF = audio_sof, + .incomplete_isoc_in = audio_iso_in_incomplete, + .incomplete_isoc_out = audio_iso_out_incomplete }; -#define VOL_MIN 0U /* volume Minimum Value */ -#define VOL_MAX 100U /* volume Maximum Value */ -#define VOL_RES 1U /* volume Resolution */ -#define VOL_0dB 70U /* 0dB is in the middle of VOL_MIN and VOL_MAX */ - /* note:it should use the c99 standard when compiling the below codes */ /* USB standard device descriptor */ __ALIGN_BEGIN const usb_desc_dev audio_dev_desc __ALIGN_END = { - .header = + .header = { - .bLength = USB_DEV_DESC_LEN, + .bLength = USB_DEV_DESC_LEN, .bDescriptorType = USB_DESCTYPE_DEV }, .bcdUSB = 0x0200U, @@ -91,16 +106,16 @@ __ALIGN_BEGIN const usb_desc_dev audio_dev_desc __ALIGN_END = }; /* USB device configuration descriptor */ -__ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END = +__ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END = { - .config = + .config = { - .header = + .header = { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG }, - .wTotalLength = AUDIO_CONFIG_DESC_SET_LEN, + .wTotalLength = AD_CONFIG_DESC_SET_LEN, .bNumInterfaces = 0x01U + CONFIG_DESC_AS_ITF_COUNT, .bConfigurationValue = 0x01U, .iConfiguration = 0x00U, @@ -108,48 +123,49 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END = .bMaxPower = 0x32U }, - .std_itf = + .std_itf = { - .header = + .header = { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x00U, .bInterfaceClass = USB_CLASS_AUDIO, - .bInterfaceSubClass = AUDIO_SUBCLASS_CONTROL, - .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .bInterfaceSubClass = AD_SUBCLASS_CONTROL, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, .iInterface = 0x00U }, - .ac_itf = + .ac_itf = { - .header = + .header = { - .bLength = sizeof(usb_desc_AC_itf), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_AC_itf), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, .bDescriptorSubtype = 0x01U, .bcdADC = 0x0100U, .wTotalLength = AC_ITF_TOTAL_LEN, .bInCollection = CONFIG_DESC_AS_ITF_COUNT, -#ifdef USE_USB_AUDIO_MICPHONE +#ifdef USE_USB_AD_MICPHONE .baInterfaceNr0 = 0x01U, -#endif -#ifdef USE_USB_AUDIO_SPEAKER +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER .baInterfaceNr1 = 0x02U -#endif +#endif /* USE_USB_AD_SPEAKER */ }, -#ifdef USE_USB_AUDIO_MICPHONE - .mic_in_terminal = +#ifdef USE_USB_AD_MICPHONE + .mic_in_terminal = { - .header = + .header = { - .bLength = sizeof(usb_desc_input_terminal), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_input_terminal), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, .bDescriptorSubtype = 0x02U, .bTerminalID = 0x01U, @@ -161,47 +177,47 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END = .iTerminal = 0x00U }, - .mic_feature_unit = + .mic_feature_unit = { - .header = + .header = { - .bLength = sizeof(usb_desc_mono_feature_unit), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_mono_feature_unit), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, - .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, - .bUnitID = AUDIO_IN_STREAMING_CTRL, + .bDescriptorSubtype = AD_CONTROL_FEATURE_UNIT, + .bUnitID = AD_IN_STREAMING_CTRL, .bSourceID = 0x01U, .bControlSize = 0x01U, - .bmaControls0 = AUDIO_CONTROL_MUTE, - .bmaControls1 = AUDIO_CONTROL_VOLUME, + .bmaControls0 = AD_CONTROL_MUTE | AD_CONTROL_VOLUME, + .bmaControls1 = 0x00U, .iFeature = 0x00U }, - .mic_out_terminal = + .mic_out_terminal = { - .header = + .header = { - .bLength = sizeof(usb_desc_output_terminal), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_output_terminal), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, - .bDescriptorSubtype = AUDIO_CONTROL_OUTPUT_TERMINAL, + .bDescriptorSubtype = AD_CONTROL_OUTPUT_TERMINAL, .bTerminalID = 0x03U, .wTerminalType = 0x0101U, .bAssocTerminal = 0x00U, .bSourceID = 0x02U, .iTerminal = 0x00U }, -#endif +#endif /* USE_USB_AD_MICPHONE */ -#ifdef USE_USB_AUDIO_SPEAKER - .speak_in_terminal = +#ifdef USE_USB_AD_SPEAKER + .speak_in_terminal = { - .header = + .header = { - .bLength = sizeof(usb_desc_input_terminal), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_input_terminal), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, - .bDescriptorSubtype = AUDIO_CONTROL_INPUT_TERMINAL, + .bDescriptorSubtype = AD_CONTROL_INPUT_TERMINAL, .bTerminalID = 0x04U, .wTerminalType = 0x0101U, .bAssocTerminal = 0x00U, @@ -211,93 +227,93 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END = .iTerminal = 0x00U }, - .speak_feature_unit = + .speak_feature_unit = { - .header = + .header = { - .bLength = sizeof(usb_desc_mono_feature_unit), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_mono_feature_unit), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, - .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, - .bUnitID = AUDIO_OUT_STREAMING_CTRL, + .bDescriptorSubtype = AD_CONTROL_FEATURE_UNIT, + .bUnitID = AD_OUT_STREAMING_CTRL, .bSourceID = 0x04U, .bControlSize = 0x01U, - .bmaControls0 = AUDIO_CONTROL_MUTE, - .bmaControls1 = AUDIO_CONTROL_VOLUME, + .bmaControls0 = AD_CONTROL_MUTE | AD_CONTROL_VOLUME, + .bmaControls1 = 0x00U, .iFeature = 0x00U }, - .speak_out_terminal = + .speak_out_terminal = { - .header = + .header = { - .bLength = sizeof(usb_desc_output_terminal), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_output_terminal), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, - .bDescriptorSubtype = AUDIO_CONTROL_OUTPUT_TERMINAL, + .bDescriptorSubtype = AD_CONTROL_OUTPUT_TERMINAL, .bTerminalID = 0x06U, .wTerminalType = 0x0301U, .bAssocTerminal = 0x00U, .bSourceID = 0x05U, .iTerminal = 0x00U }, -#endif +#endif /* USE_USB_AD_SPEAKER */ -#ifdef USE_USB_AUDIO_MICPHONE - .mic_std_as_itf_zeroband = +#ifdef USE_USB_AD_MICPHONE + .mic_std_as_itf_zeroband = { - .header = + .header = { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF }, .bInterfaceNumber = 0x01U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x00U, .bInterfaceClass = USB_CLASS_AUDIO, - .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, - .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .bInterfaceSubClass = AD_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, .iInterface = 0x00U }, - .mic_std_as_itf_opera = + .mic_std_as_itf_opera = { - .header = + .header = { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF }, .bInterfaceNumber = 0x01U, .bAlternateSetting = 0x01U, .bNumEndpoints = 0x01U, .bInterfaceClass = USB_CLASS_AUDIO, - .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, - .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .bInterfaceSubClass = AD_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, .iInterface = 0x00U }, - .mic_as_itf = + .mic_as_itf = { - .header = + .header = { - .bLength = sizeof(usb_desc_AS_itf), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_AS_itf), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, - .bDescriptorSubtype = AUDIO_STREAMING_GENERAL, + .bDescriptorSubtype = AD_STREAMING_GENERAL, .bTerminalLink = 0x03U, .bDelay = 0x01U, .wFormatTag = 0x0001U, }, - .mic_format_typeI = + .mic_format_typeI = { - .header = + .header = { - .bLength = sizeof(usb_desc_format_type), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_format_type), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, - .bDescriptorSubtype = AUDIO_STREAMING_FORMAT_TYPE, - .bFormatType = AUDIO_FORMAT_TYPE_I, + .bDescriptorSubtype = AD_STREAMING_FORMAT_TYPE, + .bFormatType = AD_FORMAT_TYPE_I, .bNrChannels = MIC_IN_CHANNEL_NBR, .bSubFrameSize = 0x02U, .bBitResolution = MIC_IN_BIT_RESOLUTION, @@ -307,14 +323,14 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END = .bSamFreq[2] = USBD_MIC_FREQ >> 16U }, - .mic_std_endpoint = + .mic_std_endpoint = { - .header = + .header = { - .bLength = sizeof(usb_desc_std_ep), - .bDescriptorType = USB_DESCTYPE_EP + .bLength = sizeof(usb_desc_std_ep), + .bDescriptorType = USB_DESCTYPE_EP }, - .bEndpointAddress = AUDIO_IN_EP, + .bEndpointAddress = AD_IN_EP, .bmAttributes = USB_ENDPOINT_TYPE_ISOCHRONOUS, .wMaxPacketSize = MIC_IN_PACKET, .bInterval = 0x01U, @@ -322,75 +338,75 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END = .bSynchAddress = 0x00U }, - .mic_as_endpoint = + .mic_as_endpoint = { - .header = + .header = { - .bLength = sizeof(usb_desc_AS_ep), - .bDescriptorType = AUDIO_DESCTYPE_ENDPOINT + .bLength = sizeof(usb_desc_AS_ep), + .bDescriptorType = AD_DESCTYPE_ENDPOINT }, - .bDescriptorSubtype = AUDIO_ENDPOINT_GENERAL, + .bDescriptorSubtype = AD_ENDPOINT_GENERAL, .bmAttributes = 0x00U, .bLockDelayUnits = 0x00U, .wLockDelay = 0x0000U, }, -#endif +#endif /* USE_USB_AD_MICPHONE */ -#ifdef USE_USB_AUDIO_SPEAKER - .speak_std_as_itf_zeroband = +#ifdef USE_USB_AD_SPEAKER + .speak_std_as_itf_zeroband = { - .header = + .header = { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF }, .bInterfaceNumber = 0x02U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x00U, .bInterfaceClass = USB_CLASS_AUDIO, - .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, - .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .bInterfaceSubClass = AD_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, .iInterface = 0x00U }, - .speak_std_as_itf_opera = + .speak_std_as_itf_opera = { - .header = + .header = { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF }, .bInterfaceNumber = 0x02U, .bAlternateSetting = 0x01U, - .bNumEndpoints = 0x01U, + .bNumEndpoints = 0x02U, .bInterfaceClass = USB_CLASS_AUDIO, - .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, - .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .bInterfaceSubClass = AD_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, .iInterface = 0x00U }, - .speak_as_itf = + .speak_as_itf = { - .header = + .header = { - .bLength = sizeof(usb_desc_AS_itf), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_AS_itf), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, - .bDescriptorSubtype = AUDIO_STREAMING_GENERAL, + .bDescriptorSubtype = AD_STREAMING_GENERAL, .bTerminalLink = 0x04U, .bDelay = 0x01U, .wFormatTag = 0x0001U, }, - .speak_format_typeI = + .speak_format_typeI = { - .header = + .header = { - .bLength = sizeof(usb_desc_format_type), - .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + .bLength = sizeof(usb_desc_format_type), + .bDescriptorType = AD_DESCTYPE_INTERFACE }, - .bDescriptorSubtype = AUDIO_STREAMING_FORMAT_TYPE, - .bFormatType = AUDIO_FORMAT_TYPE_I, + .bDescriptorSubtype = AD_STREAMING_FORMAT_TYPE, + .bFormatType = AD_FORMAT_TYPE_I, .bNrChannels = SPEAKER_OUT_CHANNEL_NBR, .bSubFrameSize = 0x02U, .bBitResolution = SPEAKER_OUT_BIT_RESOLUTION, @@ -400,42 +416,57 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END = .bSamFreq[2] = USBD_SPEAKER_FREQ >> 16U }, - .speak_std_endpoint = + .speak_std_endpoint = { - .header = + .header = { - .bLength = sizeof(usb_desc_std_ep), - .bDescriptorType = USB_DESCTYPE_EP + .bLength = sizeof(usb_desc_std_ep), + .bDescriptorType = USB_DESCTYPE_EP }, - .bEndpointAddress = AUDIO_OUT_EP, - .bmAttributes = USB_ENDPOINT_TYPE_ISOCHRONOUS, + .bEndpointAddress = AD_OUT_EP, + .bmAttributes = USB_EP_ATTR_ISO | USB_EP_ATTR_ASYNC, .wMaxPacketSize = SPEAKER_OUT_PACKET, .bInterval = 0x01U, .bRefresh = 0x00U, - .bSynchAddress = 0x00U + .bSynchAddress = AD_FEEDBACK_IN_EP, }, - .speak_as_endpoint = + .speak_as_endpoint = { - .header = + .header = { - .bLength = sizeof(usb_desc_AS_ep), - .bDescriptorType = AUDIO_DESCTYPE_ENDPOINT + .bLength = sizeof(usb_desc_AS_ep), + .bDescriptorType = AD_DESCTYPE_ENDPOINT }, - .bDescriptorSubtype = AUDIO_ENDPOINT_GENERAL, + .bDescriptorSubtype = AD_ENDPOINT_GENERAL, .bmAttributes = 0x00U, .bLockDelayUnits = 0x00U, .wLockDelay = 0x0000U, - } -#endif + }, + + .speak_feedback_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_FeedBack_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = AD_FEEDBACK_IN_EP, + .bmAttributes = USB_EP_ATTR_ISO | USB_EP_ATTR_ASYNC | USB_EP_ATTR_FEEDBACK, + .wMaxPacketSize = FEEDBACK_IN_PACKET, + .bInterval = 0x01U, + .Refresh = FEEDBACK_IN_INTERVAL, /* refresh every 32(2^5) ms */ + .bSynchAddress = 0x00U, + }, +#endif /* USE_USB_AD_SPEAKER */ }; /* USB language ID descriptor */ -static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { - .header = + .header = { - .bLength = sizeof(usb_desc_LANGID), + .bLength = sizeof(usb_desc_LANGID), .bDescriptorType = USB_DESCTYPE_STR }, @@ -443,39 +474,39 @@ static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = }; /* USB manufacture string */ -static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { - .header = + .header = { - .bLength = USB_STRING_LEN(10), + .bLength = USB_STRING_LEN(10), .bDescriptorType = USB_DESCTYPE_STR, }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ -static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { - .header = + .header = { - .bLength = USB_STRING_LEN(14), + .bLength = USB_STRING_LEN(14), .bDescriptorType = USB_DESCTYPE_STR, }, .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'A', 'u', 'd', 'i', 'o'} }; /* USBD serial string */ -static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { - .header = + .header = { - .bLength = USB_STRING_LEN(12), + .bLength = USB_STRING_LEN(12), .bDescriptorType = USB_DESCTYPE_STR, } }; /* USB string descriptor */ -void *const usbd_audio_strings[] = +void *const usbd_audio_strings[] = { [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, @@ -483,6 +514,7 @@ void *const usbd_audio_strings[] = [STR_IDX_SERIAL] = (uint8_t *)&serial_string }; +/* USB descriptor configure */ usb_desc audio_desc = { .dev_desc = (uint8_t *)&audio_dev_desc, .config_desc = (uint8_t *)&audio_config_set, @@ -498,11 +530,9 @@ usb_desc audio_desc = { */ static uint8_t audio_init (usb_dev *udev, uint8_t config_index) { - static __ALIGN_BEGIN usbd_audio_handler audio_handler __ALIGN_END; - memset((void *)&audio_handler, 0, sizeof(usbd_audio_handler)); -#ifdef USE_USB_AUDIO_MICPHONE +#ifdef USE_USB_AD_MICPHONE { usb_desc_std_ep std_ep = audio_config_set.mic_std_endpoint; @@ -511,43 +541,54 @@ static uint8_t audio_init (usb_dev *udev, uint8_t config_index) .bEndpointAddress = std_ep.bEndpointAddress, .bmAttributes = std_ep.bmAttributes, .wMaxPacketSize = std_ep.wMaxPacketSize, - .bInterval = std_ep.bInterval + .bInterval = std_ep.bInterval }; /* initialize TX endpoint */ usbd_ep_setup (udev, &ep); } -#endif +#endif /* USE_USB_AD_MICPHONE */ -#ifdef USE_USB_AUDIO_SPEAKER +#ifdef USE_USB_AD_SPEAKER { audio_handler.isoc_out_rdptr = audio_handler.isoc_out_buff; audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; usb_desc_std_ep std_ep = audio_config_set.speak_std_endpoint; - usb_desc_ep ep = { + usb_desc_ep ep1 = { .header = std_ep.header, .bEndpointAddress = std_ep.bEndpointAddress, .bmAttributes = std_ep.bmAttributes, - .wMaxPacketSize = std_ep.wMaxPacketSize, - .bInterval = std_ep.bInterval + .wMaxPacketSize = SPEAKER_OUT_MAX_PACKET, + .bInterval = std_ep.bInterval }; /* initialize RX endpoint */ - usbd_ep_setup (udev, &ep); + usbd_ep_setup (udev, &ep1); + + /* prepare out endpoint to receive next audio packet */ + usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET); /* initialize the audio output hardware layer */ - if (USBD_OK != audio_out_fops.audio_init(USBD_AUDIO_FREQ_16K, DEFAULT_VOLUME, 0U)) { + if (USBD_OK != audio_out_fops.audio_init(USBD_SPEAKER_FREQ, DEFAULT_VOLUME)) { return USBD_FAIL; } - /* prepare OUT endpoint to receive audio data */ - usbd_ep_recev (udev, AUDIO_OUT_EP, (uint8_t*)audio_handler.isoc_out_buff, SPEAKER_OUT_PACKET); -} -#endif + usb_desc_FeedBack_ep feedback_ep = audio_config_set.speak_feedback_endpoint; - udev->dev.class_data[USBD_AUDIO_INTERFACE] = (void *)&audio_handler; + usb_desc_ep ep2 = { + .header = feedback_ep.header, + .bEndpointAddress = feedback_ep.bEndpointAddress, + .bmAttributes = feedback_ep.bmAttributes, + .wMaxPacketSize = feedback_ep.wMaxPacketSize, + .bInterval = feedback_ep.bInterval + }; + + /* initialize Tx endpoint */ + usbd_ep_setup (udev, &ep2); +} +#endif /* USE_USB_AD_SPEAKER */ return USBD_OK; } @@ -561,20 +602,23 @@ static uint8_t audio_init (usb_dev *udev, uint8_t config_index) */ static uint8_t audio_deinit (usb_dev *udev, uint8_t config_index) { -#ifdef USE_USB_AUDIO_MICPHONE +#ifdef USE_USB_AD_MICPHONE /* deinitialize AUDIO endpoints */ - usbd_ep_clear(udev, AUDIO_IN_EP); -#endif + usbd_ep_clear(udev, AD_IN_EP); +#endif /* USE_USB_AD_MICPHONE */ -#ifdef USE_USB_AUDIO_SPEAKER +#ifdef USE_USB_AD_SPEAKER /* deinitialize AUDIO endpoints */ - usbd_ep_clear(udev, AUDIO_OUT_EP); + usbd_ep_clear(udev, AD_OUT_EP); /* deinitialize the audio output hardware layer */ - if (USBD_OK != audio_out_fops.audio_deinit(0U)) { + if (USBD_OK != audio_out_fops.audio_deinit()) { return USBD_FAIL; } -#endif + + /* deinitialize AUDIO endpoints */ + usbd_ep_clear(udev, AD_FEEDBACK_IN_EP); +#endif /* USE_USB_AD_SPEAKER */ return USBD_OK; } @@ -590,50 +634,48 @@ static uint8_t audio_req_handler (usb_dev *udev, usb_req *req) { uint8_t status = REQ_NOTSUPP; - usbd_audio_handler *audio = (usbd_audio_handler *)udev->dev.class_data[USBD_AUDIO_INTERFACE]; - usb_transc *transc_in = &udev->dev.transc_in[0]; usb_transc *transc_out = &udev->dev.transc_out[0]; switch (req->bRequest) { - case AUDIO_REQ_GET_CUR: - transc_in->xfer_buf = audio->audioctl; + case AD_REQ_GET_CUR: + transc_in->xfer_buf = audio_handler.audioctl; transc_in->remain_len = req->wLength; status = REQ_SUPP; break; - case AUDIO_REQ_SET_CUR: + case AD_REQ_SET_CUR: if (req->wLength) { - transc_out->xfer_buf = audio->audioctl; + transc_out->xfer_buf = audio_handler.audioctl; transc_out->remain_len = req->wLength; - udev->dev.class_core->command = AUDIO_REQ_SET_CUR; + udev->dev.class_core->command = AD_REQ_SET_CUR; - audio->audioctl_len = req->wLength; - audio->audioctl_unit = BYTE_HIGH(req->wIndex); + audio_handler.audioctl_len = req->wLength; + audio_handler.audioctl_unit = BYTE_HIGH(req->wIndex); status = REQ_SUPP; } break; - case AUDIO_REQ_GET_MIN: - *((uint16_t *)audio->audioctl) = VOL_MIN; - transc_in->xfer_buf = audio->audioctl; + case AD_REQ_GET_MIN: + *((uint16_t *)audio_handler.audioctl) = VOL_MIN; + transc_in->xfer_buf = audio_handler.audioctl; transc_in->remain_len = req->wLength; status = REQ_SUPP; break; - case AUDIO_REQ_GET_MAX: - *((uint16_t *)audio->audioctl) = VOL_MAX; - transc_in->xfer_buf = audio->audioctl; + case AD_REQ_GET_MAX: + *((uint16_t *)audio_handler.audioctl) = VOL_MAX; + transc_in->xfer_buf = audio_handler.audioctl; transc_in->remain_len = req->wLength; status = REQ_SUPP; break; - case AUDIO_REQ_GET_RES: - *((uint16_t *)audio->audioctl) = VOL_RES; - transc_in->xfer_buf = audio->audioctl; + case AD_REQ_GET_RES: + *((uint16_t *)audio_handler.audioctl) = VOL_RES; + transc_in->xfer_buf = audio_handler.audioctl; transc_in->remain_len = req->wLength; status = REQ_SUPP; break; @@ -645,6 +687,78 @@ static uint8_t audio_req_handler (usb_dev *udev, usb_req *req) return status; } +/*! + \brief handle the AUDIO set interface requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_set_intf(usb_dev *udev, usb_req *req) +{ + udev->dev.class_core->alter_set = req->wValue; + + if(0xFF != req->wValue){ + if (req->wValue != 0){ + /* deinit audio handler */ + memset((void *)&audio_handler, 0, sizeof(usbd_audio_handler)); + + audio_handler.play_flag = 0; + audio_handler.isoc_out_rdptr = audio_handler.isoc_out_buff; + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; + + /* feedback calculate sample freq */ + audio_handler.actual_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ); + get_feedback_fs_rate(audio_handler.actual_freq, audio_handler.feedback_freq); + + /* send feedback data of estimated frequence*/ + usbd_ep_send(udev, AD_FEEDBACK_IN_EP, audio_handler.feedback_freq, FEEDBACK_IN_PACKET); + } else { + /* stop audio output */ + audio_out_fops.audio_cmd(audio_handler.isoc_out_rdptr, SPEAKER_OUT_PACKET/2, AD_CMD_STOP); + + audio_handler.play_flag = 0; + audio_handler.isoc_out_rdptr = audio_handler.isoc_out_buff; + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; + + usbd_fifo_flush (udev, AD_IN_EP); + usbd_fifo_flush (udev, AD_FEEDBACK_IN_EP); + usbd_fifo_flush (udev, AD_OUT_EP); + } + } + + return 0; +} + +/*! + \brief handles the control transfer OUT callback + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_ctlx_out (usb_dev *udev) +{ +#ifdef USE_USB_AD_SPEAKER + /* handles audio control requests data */ + /* check if an audio_control request has been issued */ + if (AD_REQ_SET_CUR == udev->dev.class_core->command) { + /* in this driver, to simplify code, only SET_CUR request is managed */ + + /* check for which addressed unit the audio_control request has been issued */ + if (AD_OUT_STREAMING_CTRL == audio_handler.audioctl_unit) { + /* in this driver, to simplify code, only one unit is manage */ + + /* reset the audioctl_cmd variable to prevent re-entering this function */ + udev->dev.class_core->command = 0U; + + audio_handler.audioctl_len = 0U; + } + } +#endif /* USE_USB_AD_SPEAKER */ + + return USBD_OK; +} + /*! \brief handles the audio IN data stage \param[in] udev: pointer to USB device instance @@ -654,16 +768,28 @@ static uint8_t audio_req_handler (usb_dev *udev, usb_req *req) */ static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num) { -#ifdef USE_USB_AUDIO_MICPHONE +#ifdef USE_USB_AD_MICPHONE + if(ep_num == EP_ID(AD_IN_EP)){ if(count_data < LENGTH_DATA){ /* Prepare next buffer to be sent: dummy data */ - usbd_ep_send(udev, AUDIO_IN_EP,(uint8_t*)&wavetestdata[count_data],MIC_IN_PACKET); + usbd_ep_send(udev, AD_IN_EP,(uint8_t*)&wavetestdata[count_data],MIC_IN_PACKET); count_data += MIC_IN_PACKET; } else { - usbd_ep_send(udev, AUDIO_IN_EP,(uint8_t*)wavetestdata,MIC_IN_PACKET); + usbd_ep_send(udev, AD_IN_EP,(uint8_t*)wavetestdata,MIC_IN_PACKET); count_data = MIC_IN_PACKET; } -#endif + } +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER + if(ep_num == EP_ID(AD_FEEDBACK_IN_EP)){ + /* calculate feedback actual freq */ + audio_handler.actual_freq = usbd_audio_spk_get_feedback(udev); + get_feedback_fs_rate(audio_handler.actual_freq, audio_handler.feedback_freq); + + usbd_ep_send(udev, AD_FEEDBACK_IN_EP, audio_handler.feedback_freq, FEEDBACK_IN_PACKET); + } +#endif /* USE_USB_AD_SPEAKER */ return USBD_OK; } @@ -677,52 +803,73 @@ static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num) */ static uint8_t audio_data_out (usb_dev *udev, uint8_t ep_num) { -#ifdef USE_USB_AUDIO_SPEAKER - usbd_audio_handler *audio = (usbd_audio_handler *)udev->dev.class_data[USBD_AUDIO_INTERFACE]; + uint16_t usb_rx_length, tail_len; - if (AUDIO_OUT_EP == ep_num) { - /* increment the Buffer pointer or roll it back when all buffers are full */ - if (audio->isoc_out_wrptr >= (audio->isoc_out_buff + (SPEAKER_OUT_PACKET * OUT_PACKET_NUM))) { - /* all buffers are full: roll back */ - audio->isoc_out_wrptr = audio->isoc_out_buff; - } else { - /* increment the buffer pointer */ - audio->isoc_out_wrptr += SPEAKER_OUT_PACKET; - } + /* get receive length */ + usb_rx_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count; - /* Toggle the frame index */ - udev->dev.transc_out[ep_num].frame_num = - (udev->dev.transc_out[ep_num].frame_num)? 0U:1U; + if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ + audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + }else{ + audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + } - /* prepare out endpoint to receive next audio packet */ - usbd_ep_recev (udev, AUDIO_OUT_EP, (uint8_t*)(audio->isoc_out_wrptr), SPEAKER_OUT_PACKET); + /* free buffer enough to save rx data */ + if(audio_handler.buf_free_size > usb_rx_length){ + if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ + tail_len = audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE - audio_handler.isoc_out_wrptr; - /* trigger the start of streaming only when half buffer is full */ - if ((0U == audio->play_flag) && (audio->isoc_out_wrptr >= (audio->isoc_out_buff + ((SPEAKER_OUT_PACKET * OUT_PACKET_NUM) / 2U)))) { - /* enable start of streaming */ - audio->play_flag = 1U; - } - } else { - /* handles audio control requests data */ - /* check if an audio_control request has been issued */ - if (AUDIO_REQ_SET_CUR == udev->dev.class_core->command) { - /* in this driver, to simplify code, only SET_CUR request is managed */ + if(tail_len >= usb_rx_length){ + memcpy(audio_handler.isoc_out_wrptr, audio_handler.usb_rx_buffer, usb_rx_length); - /* check for which addressed unit the audio_control request has been issued */ - if (AUDIO_OUT_STREAMING_CTRL == audio->audioctl_unit) { - /* in this driver, to simplify code, only one unit is manage */ + /* increment the buffer pointer */ + audio_handler.isoc_out_wrptr += usb_rx_length; - /* call the audio interface mute function */ - audio_out_fops.audio_mute_ctl(audio->audioctl[0]); + /* increment the Buffer pointer or roll it back when all buffers are full */ + if(audio_handler.isoc_out_wrptr >= (audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE)){ + /* all buffers are full: roll back */ + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; + } + }else{ + memcpy(audio_handler.isoc_out_wrptr, audio_handler.usb_rx_buffer, tail_len); + /* adjust write pointer */ + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; - /* reset the audioctl_cmd variable to prevent re-entering this function */ - udev->dev.class_core->command = 0U; - - audio->audioctl_len = 0U; + memcpy(audio_handler.isoc_out_wrptr, &audio_handler.usb_rx_buffer[tail_len], usb_rx_length - tail_len); + /* adjust write pointer */ + audio_handler.isoc_out_wrptr += usb_rx_length - tail_len; } + }else{ + memcpy(audio_handler.isoc_out_wrptr, audio_handler.usb_rx_buffer, usb_rx_length); + + /* increment the buffer pointer */ + audio_handler.isoc_out_wrptr += usb_rx_length; } } -#endif + + /* Toggle the frame index */ + udev->dev.transc_out[ep_num].frame_num = (udev->dev.transc_out[ep_num].frame_num)? 0U:1U; + + /* prepare out endpoint to receive next audio packet */ + usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET); + + if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ + audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + }else{ + audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + } + + if ((0U == audio_handler.play_flag) && (audio_handler.buf_free_size < TOTAL_OUT_BUF_SIZE/2)) { + /* enable start of streaming */ + audio_handler.play_flag = 1U; + + /* initialize the audio output hardware layer */ + if (USBD_OK != audio_out_fops.audio_cmd(audio_handler.isoc_out_rdptr, SPEAKER_OUT_MAX_PACKET/2, AD_CMD_PLAY)) { + return USBD_FAIL; + } + + audio_handler.dam_tx_len = SPEAKER_OUT_MAX_PACKET; + } return USBD_OK; } @@ -733,45 +880,82 @@ static uint8_t audio_data_out (usb_dev *udev, uint8_t ep_num) \param[out] none \retval USB device operation status */ -static uint8_t usbd_audio_sof (usb_dev *udev) +static uint8_t audio_sof (usb_dev *udev) { -#ifdef USE_USB_AUDIO_SPEAKER - usbd_audio_handler *audio = (usbd_audio_handler *)udev->dev.class_data[USBD_AUDIO_INTERFACE]; + return USBD_OK; +} - /* check if there are available data in stream buffer. - in this function, a single variable (play_flag) is used to avoid software delays. - the play operation must be executed as soon as possible after the SOF detection. */ - if (audio->play_flag) { - /* start playing received packet */ - audio_out_fops.audio_cmd((uint8_t*)(audio->isoc_out_rdptr), /* samples buffer pointer */ - SPEAKER_OUT_PACKET, /* number of samples in Bytes */ - AUDIO_CMD_PLAY); /* command to be processed */ +/*! + \brief handles the audio ISO IN Incomplete event + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_iso_in_incomplete (usb_dev *udev) +{ + (void)usb_txfifo_flush (&udev->regs, EP_ID(AD_FEEDBACK_IN_EP)); - /* increment the Buffer pointer or roll it back when all buffers all full */ - if (audio->isoc_out_rdptr >= (audio->isoc_out_buff + (SPEAKER_OUT_PACKET * OUT_PACKET_NUM))) { - /* roll back to the start of buffer */ - audio->isoc_out_rdptr = audio->isoc_out_buff; - } else { - /* increment to the next sub-buffer */ - audio->isoc_out_rdptr += SPEAKER_OUT_PACKET; - } + audio_handler.actual_freq = usbd_audio_spk_get_feedback(udev); + get_feedback_fs_rate(audio_handler.actual_freq, audio_handler.feedback_freq); - /* if all available buffers have been consumed, stop playing */ - if (audio->isoc_out_rdptr == audio->isoc_out_wrptr) { - /* Pause the audio stream */ - audio_out_fops.audio_cmd((uint8_t*)(audio->isoc_out_buff), /* samples buffer pointer */ - SPEAKER_OUT_PACKET, /* number of samples in Bytes */ - AUDIO_CMD_PAUSE); /* command to be processed */ - - /* stop entering play loop */ - audio->play_flag = 0U; - - /* reset buffer pointers */ - audio->isoc_out_rdptr = audio->isoc_out_buff; - audio->isoc_out_wrptr = audio->isoc_out_buff; - } - } -#endif + /* send feedback data of estimated frequence*/ + usbd_ep_send(udev, AD_FEEDBACK_IN_EP, audio_handler.feedback_freq, FEEDBACK_IN_PACKET); return USBD_OK; } + +/*! + \brief handles the audio ISO OUT Incomplete event + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_iso_out_incomplete (usb_dev *udev) +{ + return USBD_OK; +} + +/*! + \brief calculate feedback sample frequency + \param[in] udev: pointer to USB device instance + \param[out] none + \retval feedback frequency value +*/ +static uint32_t usbd_audio_spk_get_feedback(usb_dev *udev) +{ + static uint32_t fb_freq; + + /* calculate buffer free size */ + if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ + audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + }else{ + audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + } + + /* calculate feedback frequency */ + if(audio_handler.buf_free_size <= (TOTAL_OUT_BUF_SIZE/4)){ + fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) - FEEDBACK_FREQ_OFFSET; + }else if(audio_handler.buf_free_size >= (TOTAL_OUT_BUF_SIZE*3/4)){ + fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) + FEEDBACK_FREQ_OFFSET; + }else{ + fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ); + } + + return fb_freq; +} + +/*! + \brief get feedback value from rate in USB full speed + \param[in] rate: sample frequence + \param[in] buf: pointer to result buffer + \param[out] none + \retval USB device operation status +*/ +static void get_feedback_fs_rate(uint32_t rate, uint8_t *buf) +{ + rate = ((rate / 1000) << 14) | ((rate % 1000) << 4); + + buf[0] = rate; + buf[1] = rate >> 8; + buf[2] = rate >> 16; +} diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Source/audio_out_itf.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Source/audio_out_itf.c index fbe56d907b..cfbc580ca3 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Source/audio_out_itf.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/audio/Source/audio_out_itf.c @@ -3,102 +3,99 @@ \brief audio OUT (playback) interface functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "audio_core.h" #include "audio_out_itf.h" -static uint8_t init (uint32_t audiofreq, uint32_t volume, uint32_t options); -static uint8_t deinit (uint32_t options); -static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd); -static uint8_t volume_ctl (uint8_t vol); -static uint8_t mute_ctl (uint8_t cmd); -static uint8_t periodic_tc (uint8_t cmd); -static uint8_t get_state (void); +/* local function prototypes ('static') */ +static uint8_t init (uint32_t audio_freq, uint32_t volume); +static uint8_t deinit (void); +static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd); -audio_fops_struct audio_out_fops = +/* local variable defines */ +static uint8_t audio_state = AD_STATE_INACTIVE; + +audio_fops_struct audio_out_fops = { - init, - deinit, - audio_cmd, - volume_ctl, - mute_ctl, - periodic_tc, - get_state + .audio_init = init, + .audio_deinit = deinit, + .audio_cmd = audio_cmd, }; -static uint8_t audio_state = AUDIO_STATE_INACTIVE; - /*! - \brief initialize and configures all required resources for audio play function + \brief initialize and configures all required resources \param[in] audio_freq: statrt_up audio frequency \param[in] volume: start_up volume to be set - \param[in] options: specific options passed to low layer function \param[out] none - \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else + \retval AD_OK if all operations succeed, otherwise, AD_FAIL. */ -static uint8_t init (uint32_t audio_freq, uint32_t volume, uint32_t options) +static uint8_t init (uint32_t audio_freq, uint32_t volume) { static uint32_t initialized = 0U; /* check if the low layer has already been initialized */ if (0U == initialized) { - /* call low layer function */ - if (0U != eval_audio_init(OUTPUT_DEVICE_AUTO, (uint8_t)volume, audio_freq)) { - audio_state = AUDIO_STATE_ERROR; + /* initialize GPIO */ + codec_gpio_init(); - return AUDIO_FAIL; - } + /* initialize i2s */ + codec_audio_interface_init(audio_freq); - /* set the initialization flag to prevent reinitializing the interface again */ + /* initialize DMA */ + codec_i2s_dma_init(); + + /* prevent reinitializing the interface again */ initialized = 1U; } /* update the audio state machine */ - audio_state = AUDIO_STATE_ACTIVE; + audio_state = AD_STATE_ACTIVE; - return AUDIO_OK; + return AD_OK; } /*! \brief free all resources used by low layer and stops audio-play function - \param[in] options: specific options passed to low layer function + \param[in] none \param[out] none - \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else + \retval AD_OK if all operations succeed, otherwise, AD_FAIL. */ -static uint8_t deinit (uint32_t options) +static uint8_t deinit (void) { /* update the audio state machine */ - audio_state = AUDIO_STATE_INACTIVE; + audio_state = AD_STATE_INACTIVE; - return AUDIO_OK; + return AD_OK; } /*! @@ -106,123 +103,68 @@ static uint8_t deinit (uint32_t options) \param[in] pbuf: address from which file should be played \param[in] size: size of the current buffer/file \param[in] cmd: command to be executed, can be: - \arg AUDIO_CMD_PLAY - \arg AUDIO_CMD_PAUSE - \arg AUDIO_CMD_RESUME - \arg AUDIO_CMD_STOP + \arg AD_CMD_PLAY + \arg AD_CMD_PAUSE + \arg AD_CMD_RESUME + \arg AD_CMD_STOP \param[out] none - \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else + \retval AD_OK if all operations succeed, otherwise, AD_FAIL. */ static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd) { /* check the current state */ - if ((AUDIO_STATE_INACTIVE == audio_state) || (AUDIO_STATE_ERROR == audio_state)) { - audio_state = AUDIO_STATE_ERROR; + if ((AD_STATE_INACTIVE == audio_state) || (AD_STATE_ERROR == audio_state)) { + audio_state = AD_STATE_ERROR; - return AUDIO_FAIL; + return AD_FAIL; } switch (cmd) { /* process the play command */ - case AUDIO_CMD_PLAY: + case AD_CMD_PLAY: /* if current state is active or stopped */ - if ((AUDIO_STATE_ACTIVE == audio_state) || \ - (AUDIO_STATE_STOPPED == audio_state) || \ - (AUDIO_STATE_PLAYING == audio_state)) { - audio_mal_play((uint32_t)pbuf, size); - audio_state = AUDIO_STATE_PLAYING; + if ((AD_STATE_ACTIVE == audio_state) || \ + (AD_STATE_STOPPED == audio_state) || \ + (AD_STATE_PLAYING == audio_state)) { + audio_play((uint32_t)pbuf, size); + audio_state = AD_STATE_PLAYING; - return AUDIO_OK; - } else if (AUDIO_STATE_PAUSED == audio_state) { - if (eval_audio_pause_resume(AUDIO_RESUME, (uint32_t)pbuf, (size / 2U))) { - audio_state = AUDIO_STATE_ERROR; + return AD_OK; + } else if (AD_STATE_PAUSED == audio_state) { + audio_pause_resume(AD_RESUME, (uint32_t)pbuf, (size/2)); + audio_state = AD_STATE_PLAYING; - return AUDIO_FAIL; - } else { - audio_state = AUDIO_STATE_PLAYING; - - return AUDIO_OK; - } + return AD_OK; } else { - return AUDIO_FAIL; + return AD_FAIL; } /* process the stop command */ - case AUDIO_CMD_STOP: - if (AUDIO_STATE_PLAYING != audio_state) { + case AD_CMD_STOP: + if (AD_STATE_PLAYING != audio_state) { /* unsupported command */ - return AUDIO_FAIL; - } else if (eval_audio_stop(CODEC_PDWN_SW)) { - audio_state = AUDIO_STATE_ERROR; - - return AUDIO_FAIL; + return AD_FAIL; } else { - audio_state = AUDIO_STATE_STOPPED; + audio_stop(); + audio_state = AD_STATE_STOPPED; - return AUDIO_OK; + return AD_OK; } /* process the pause command */ - case AUDIO_CMD_PAUSE: - if (AUDIO_STATE_PLAYING != audio_state) { + case AD_CMD_PAUSE: + if (AD_STATE_PLAYING != audio_state) { /* unsupported command */ - return AUDIO_FAIL; - } else if (eval_audio_pause_resume(AUDIO_PAUSE, (uint32_t)pbuf, (size / 2U))) { - audio_state = AUDIO_STATE_ERROR; - - return AUDIO_FAIL; + return AD_FAIL; } else { - audio_state = AUDIO_STATE_PAUSED; + audio_pause_resume(AD_PAUSE, (uint32_t)pbuf, (size/2)); + audio_state = AD_STATE_PAUSED; - return AUDIO_OK; + return AD_OK; } /* unsupported command */ default: - return AUDIO_FAIL; + return AD_FAIL; } } - -/*! - \brief set the volume level - \param[in] vol: volume level to be set in % (from 0% to 100%) - \param[out] none - \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else -*/ -static uint8_t volume_ctl (uint8_t vol) -{ - return AUDIO_OK; -} - -/*! - \brief mute or unmute the audio current output - \param[in] cmd: can be 0 to unmute, or 1 to mute - \param[out] none - \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else -*/ -static uint8_t mute_ctl (uint8_t cmd) -{ - return AUDIO_OK; -} - -/*! - \brief periodic transfer control - \param[in] cmd: command - \param[out] none - \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else -*/ -static uint8_t periodic_tc (uint8_t cmd) -{ - return AUDIO_OK; -} - -/*! - \brief return the current state of the audio machine - \param[in] none - \param[out] none - \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else -*/ -static uint8_t get_state (void) -{ - return audio_state; -} diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/cdc/Include/cdc_acm_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/cdc/Include/cdc_acm_core.h index c1a2bc8f80..3c967f5f1d 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/cdc/Include/cdc_acm_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/cdc/Include/cdc_acm_core.h @@ -3,32 +3,34 @@ \brief the header file of cdc acm driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -38,15 +40,15 @@ OF SUCH DAMAGE. #include "usbd_enum.h" #include "usb_cdc.h" -#define USB_CDC_RX_LEN 64 +#define USB_CDC_RX_LEN USB_CDC_DATA_PACKET_SIZE typedef struct { - uint8_t data[USB_CDC_RX_LEN]; - uint8_t cmd[USB_CDC_CMD_PACKET_SIZE]; - uint8_t packet_sent; uint8_t packet_receive; + uint8_t data[USB_CDC_RX_LEN]; + uint8_t cmd[USB_CDC_CMD_PACKET_SIZE]; + uint32_t receive_length; acm_line line_coding; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/cdc/Source/cdc_acm_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/cdc/Source/cdc_acm_core.c index a950c091c8..7049467550 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/cdc/Source/cdc_acm_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/cdc/Source/cdc_acm_core.c @@ -3,32 +3,34 @@ \brief CDC ACM driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,9 +43,9 @@ OF SUCH DAMAGE. /* USB standard device descriptor */ __ALIGN_BEGIN const usb_desc_dev cdc_dev_desc __ALIGN_END = { - .header = + .header = { - .bLength = USB_DEV_DESC_LEN, + .bLength = USB_DEV_DESC_LEN, .bDescriptorType = USB_DESCTYPE_DEV, }, .bcdUSB = 0x0200U, @@ -61,15 +63,15 @@ __ALIGN_BEGIN const usb_desc_dev cdc_dev_desc __ALIGN_END = }; /* USB device configuration descriptor */ -__ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = +__ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = { - .config = + .config = { .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG, - }, + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG, + }, .wTotalLength = USB_CDC_ACM_CONFIG_DESC_SIZE, .bNumInterfaces = 0x02U, .bConfigurationValue = 0x01U, @@ -78,13 +80,13 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = .bMaxPower = 0x32U }, - .cmd_itf = + .cmd_itf = { .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x01U, @@ -97,10 +99,10 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = .cdc_header = { .header = - { + { .bLength = sizeof(usb_desc_header_func), .bDescriptorType = USB_DESCTYPE_CS_INTERFACE - }, + }, .bDescriptorSubtype = 0x00U, .bcdCDC = 0x0110U }, @@ -108,10 +110,10 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = .cdc_call_managment = { .header = - { + { .bLength = sizeof(usb_desc_call_managment_func), .bDescriptorType = USB_DESCTYPE_CS_INTERFACE - }, + }, .bDescriptorSubtype = 0x01U, .bmCapabilities = 0x00U, .bDataInterface = 0x01U @@ -120,10 +122,10 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = .cdc_acm = { .header = - { + { .bLength = sizeof(usb_desc_acm_func), .bDescriptorType = USB_DESCTYPE_CS_INTERFACE - }, + }, .bDescriptorSubtype = 0x02U, .bmCapabilities = 0x02U, }, @@ -131,10 +133,10 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = .cdc_union = { .header = - { + { .bLength = sizeof(usb_desc_union_func), .bDescriptorType = USB_DESCTYPE_CS_INTERFACE - }, + }, .bDescriptorSubtype = 0x06U, .bMasterInterface = 0x00U, .bSlaveInterface0 = 0x01U, @@ -143,10 +145,10 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = .cdc_cmd_endpoint = { .header = - { + { .bLength = sizeof(usb_desc_ep), .bDescriptorType = USB_DESCTYPE_EP, - }, + }, .bEndpointAddress = CDC_CMD_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = USB_CDC_CMD_PACKET_SIZE, @@ -156,10 +158,10 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = .cdc_data_interface = { .header = - { + { .bLength = sizeof(usb_desc_itf), .bDescriptorType = USB_DESCTYPE_ITF, - }, + }, .bInterfaceNumber = 0x01U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x02U, @@ -172,10 +174,10 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = .cdc_out_endpoint = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP, - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP, + }, .bEndpointAddress = CDC_DATA_OUT_EP, .bmAttributes = USB_EP_ATTR_BULK, .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, @@ -185,10 +187,10 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = .cdc_in_endpoint = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = CDC_DATA_IN_EP, .bmAttributes = USB_EP_ATTR_BULK, .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, @@ -197,70 +199,71 @@ __ALIGN_BEGIN const usb_cdc_desc_config_set cdc_config_desc __ALIGN_END = }; /* USB language ID Descriptor */ -static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR, + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ -static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(10), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(10), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ -static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(12), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(12), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'C', 'D', 'C', '_', 'A', 'C', 'M'} }; /* USBD serial string */ -static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(12), - .bDescriptorType = USB_DESCTYPE_STR, - } + { + .bLength = USB_STRING_LEN(12), + .bDescriptorType = USB_DESCTYPE_STR, + } }; /* USB string descriptor set */ -void *const usbd_cdc_strings[] = +void *const usbd_cdc_strings[] = { - [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, - [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, - [STR_IDX_PRODUCT] = (uint8_t *)&product_string, - [STR_IDX_SERIAL] = (uint8_t *)&serial_string + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string }; -usb_desc cdc_desc = +usb_desc cdc_desc = { - .dev_desc = (uint8_t *)&cdc_dev_desc, - .config_desc = (uint8_t *)&cdc_config_desc, + .dev_desc = (uint8_t *) &cdc_dev_desc, + .config_desc = (uint8_t *) &cdc_config_desc, .strings = usbd_cdc_strings }; /* local function prototypes ('static') */ -static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index); -static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index); -static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req); -static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num); -static uint8_t cdc_acm_out (usb_dev *udev, uint8_t ep_num); +static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req); +static uint8_t cdc_acm_ctlx_out (usb_dev *udev); +static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num); +static uint8_t cdc_acm_out (usb_dev *udev, uint8_t ep_num); /* USB CDC device class callbacks structure */ usb_class_core cdc_class = @@ -270,9 +273,8 @@ usb_class_core cdc_class = .init = cdc_acm_init, .deinit = cdc_acm_deinit, - .req_proc = cdc_acm_req, - + .ctlx_out = cdc_acm_ctlx_out, .data_in = cdc_acm_in, .data_out = cdc_acm_out }; @@ -328,7 +330,7 @@ void cdc_acm_data_receive (usb_dev *udev) cdc->packet_receive = 0U; cdc->packet_sent = 0U; - usbd_ep_recev(udev, CDC_DATA_OUT_EP, (uint8_t*)(cdc->data), USB_CDC_DATA_PACKET_SIZE); + usbd_ep_recev (udev, CDC_DATA_OUT_EP, (uint8_t*)(cdc->data), USB_CDC_DATA_PACKET_SIZE); } /*! @@ -342,13 +344,13 @@ static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index) { static __ALIGN_BEGIN usb_cdc_handler cdc_handler __ALIGN_END; - /* initialize the data TX endpoint */ + /* initialize the data Tx endpoint */ usbd_ep_setup (udev, &(cdc_config_desc.cdc_in_endpoint)); - /* initialize the data RX endpoint */ + /* initialize the data Rx endpoint */ usbd_ep_setup (udev, &(cdc_config_desc.cdc_out_endpoint)); - /* initialize the command TX endpoint */ + /* initialize the command Tx endpoint */ usbd_ep_setup (udev, &(cdc_config_desc.cdc_cmd_endpoint)); /* initialize CDC handler structure */ @@ -357,10 +359,10 @@ static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index) cdc_handler.receive_length = 0U; cdc_handler.line_coding = (acm_line){ - .dwDTERate = 115200, - .bCharFormat = 0, - .bParityType = 0, - .bDataBits = 0x08 + .dwDTERate = 115200U, + .bCharFormat = 0U, + .bParityType = 0U, + .bDataBits = 0x08U }; udev->dev.class_data[CDC_COM_INTERFACE] = (void *)&cdc_handler; @@ -369,7 +371,7 @@ static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index) } /*! - \brief de-initialize the CDC ACM device + \brief deinitialize the CDC ACM device \param[in] udev: pointer to USB device instance \param[in] config_index: configuration index \param[out] none @@ -377,11 +379,11 @@ static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index) */ static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index) { - /* deinitialize the data TX/RX endpoint */ + /* deinitialize the data Tx/Rx endpoint */ usbd_ep_clear (udev, CDC_DATA_IN_EP); usbd_ep_clear (udev, CDC_DATA_OUT_EP); - /* deinitialize the command TX endpoint */ + /* deinitialize the command Tx endpoint */ usbd_ep_clear (udev, CDC_CMD_EP); return USBD_OK; @@ -398,7 +400,7 @@ static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req) { usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; - usb_transc *transc = &udev->dev.transc_in[0]; + usb_transc *transc = NULL; switch (req->bRequest) { case SEND_ENCAPSULATED_COMMAND: @@ -422,6 +424,8 @@ static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req) break; case SET_LINE_CODING: + transc = &udev->dev.transc_out[0]; + /* set the value of the current command to be processed */ udev->dev.class_core->alter_set = req->bRequest; @@ -431,6 +435,8 @@ static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req) break; case GET_LINE_CODING: + transc = &udev->dev.transc_in[0]; + cdc->cmd[0] = (uint8_t)(cdc->line_coding.dwDTERate); cdc->cmd[1] = (uint8_t)(cdc->line_coding.dwDTERate >> 8); cdc->cmd[2] = (uint8_t)(cdc->line_coding.dwDTERate >> 16); @@ -459,7 +465,34 @@ static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req) } /*! - \brief handle CDC ACM data + \brief command data received on control endpoint + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_ctlx_out (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if (udev->dev.class_core->alter_set != NO_CMD) { + /* process the command data */ + cdc->line_coding.dwDTERate = (uint32_t)((uint32_t)cdc->cmd[0] | + ((uint32_t)cdc->cmd[1] << 8U) | + ((uint32_t)cdc->cmd[2] << 16U) | + ((uint32_t)cdc->cmd[3] << 24U)); + + cdc->line_coding.bCharFormat = cdc->cmd[4]; + cdc->line_coding.bParityType = cdc->cmd[5]; + cdc->line_coding.bDataBits = cdc->cmd[6]; + + udev->dev.class_core->alter_set = NO_CMD; + } + + return USBD_OK; +} + +/*! + \brief handle CDC ACM data in \param[in] udev: pointer to USB device instance \param[in] ep_num: endpoint identifier \param[out] none @@ -481,7 +514,7 @@ static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num) } /*! - \brief handle CDC ACM data + \brief handle CDC ACM data out \param[in] udev: pointer to USB device instance \param[in] ep_num: endpoint identifier \param[out] none @@ -491,25 +524,8 @@ static uint8_t cdc_acm_out (usb_dev *udev, uint8_t ep_num) { usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; - if (0U == ep_num) { - if (udev->dev.class_core->alter_set != NO_CMD) - { - /* process the command data */ - cdc->line_coding.dwDTERate = (uint32_t)((uint32_t)cdc->cmd[0] | - ((uint32_t)cdc->cmd[1] << 8U) | - ((uint32_t)cdc->cmd[2] << 16U) | - ((uint32_t)cdc->cmd[3] << 24U)); - - cdc->line_coding.bCharFormat = cdc->cmd[4]; - cdc->line_coding.bParityType = cdc->cmd[5]; - cdc->line_coding.bDataBits = cdc->cmd[6]; - - udev->dev.class_core->alter_set = NO_CMD; - } - } else { - cdc->packet_receive = 1U; - cdc->receive_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count; - } + cdc->packet_receive = 1U; + cdc->receive_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count; return USBD_OK; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Include/dfu_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Include/dfu_core.h index e62dd75cf2..9b9c3c090d 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Include/dfu_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Include/dfu_core.h @@ -3,32 +3,34 @@ \brief the header file of USB DFU device class core functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -76,10 +78,6 @@ OF SUCH DAMAGE. /* bit detach capable = bit 3 in bmAttributes field */ #define DFU_DETACH_MASK (uint8_t)(0x10U) -#define USB_SERIAL_STR_LEN 0x06U - -#define USB_DFU_CONFIG_DESC_SIZE 27U - #define DFU_DESC_TYPE 0x21U /* DFU device state defines */ @@ -136,9 +134,9 @@ typedef struct { usb_desc_header header; /*!< descriptor header, including type and size */ uint8_t bmAttributes; /*!< DFU attributes */ - uint16_t wDetachTimeOut; /*!< time, in milliseconds, that the device will wait after receipt of the DFU_DETACH request. If */ + uint16_t wDetachTimeOut; /*!< time, in milliseconds, that the device will wait after receipt of the DFU_DETACH request. If */ uint16_t wTransferSize; /*!< maximum number of bytes that the device can accept per control-write transaction */ - uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU Specification release. */ + uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU specification release. */ } usb_desc_dfu_func; #pragma pack() @@ -147,10 +145,13 @@ typedef struct typedef struct { usb_desc_config config; - usb_desc_itf dfu_itf; + usb_desc_itf dfu_itf0; + usb_desc_itf dfu_itf1; + usb_desc_itf dfu_itf2; usb_desc_dfu_func dfu_func; } usb_dfu_desc_config_set; +/* USB DFU handler structure */ typedef struct { uint8_t bStatus; @@ -173,4 +174,4 @@ typedef void (*app_func) (void); extern usb_desc dfu_desc; extern usb_class_core dfu_class; -#endif /* DFU_CORE_H */ +#endif /* DFU_CORE_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Include/dfu_mem.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Include/dfu_mem.h new file mode 100644 index 0000000000..3f74af9a5e --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Include/dfu_mem.h @@ -0,0 +1,85 @@ +/*! + \file dfu_mem.h + \brief USB DFU device media access layer header file + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DFU_MEM_H +#define __DFU_MEM_H + +#include "usb_conf.h" + +typedef struct _dfu_mem_prop +{ + const uint8_t* pstr_desc; + + uint8_t (*mem_init) (void); + uint8_t (*mem_deinit) (void); + uint8_t (*mem_erase) (uint32_t addr); + uint8_t (*mem_write) (uint8_t *buf, uint32_t addr, uint32_t len); + uint8_t* (*mem_read) (uint8_t *buf, uint32_t addr, uint32_t len); + uint8_t (*mem_checkaddr) (uint32_t addr); + + const uint32_t erase_timeout; + const uint32_t write_timeout; +} dfu_mem_prop; + +typedef enum +{ + MEM_OK = 0, + MEM_FAIL +} mem_status; + +#define _1ST_BYTE(x) (uint8_t)((x) & 0xFF) /*!< addressing cycle 1st byte */ +#define _2ND_BYTE(x) (uint8_t)(((x) & 0xFF00) >> 8) /*!< addressing cycle 2nd byte */ +#define _3RD_BYTE(x) (uint8_t)(((x) & 0xFF0000) >> 16) /*!< addressing cycle 3rd byte */ + +#define POLLING_TIMEOUT_SET(x) buffer[0] = _1ST_BYTE(x);\ + buffer[1] = _2ND_BYTE(x);\ + buffer[2] = _3RD_BYTE(x); + +/* function declarations */ +/* initialize the memory media on the GD32 */ +uint8_t dfu_mem_init(void); +/* deinitialize the memory media on the GD32 */ +uint8_t dfu_mem_deinit(void); +/* erase a memory sector */ +uint8_t dfu_mem_erase(uint32_t addr); +/* write data to sectors of memory */ +uint8_t dfu_mem_write(uint8_t *buf, uint32_t addr, uint32_t len); +/* read data from sectors of memory */ +uint8_t* dfu_mem_read(uint8_t *buf, uint32_t addr, uint32_t len); +/* get the status of a given memory and store in buffer */ +uint8_t dfu_mem_getstatus(uint32_t addr, uint8_t cmd, uint8_t *buffer); + +#endif /* __DFU_MEM_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Source/dfu_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Source/dfu_core.c index 676a8cda78..8786e0e154 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Source/dfu_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Source/dfu_core.c @@ -3,39 +3,40 @@ \brief USB DFU device class core functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "dfu_core.h" +#include "dfu_mem.h" #include "drv_usb_hw.h" -#include "dfu_mal.h" -#include "flash_if.h" #include #define USBD_VID 0x28E9U @@ -45,7 +46,12 @@ OF SUCH DAMAGE. static uint8_t dfu_init(usb_dev *udev, uint8_t config_index); static uint8_t dfu_deinit(usb_dev *udev, uint8_t config_index); static uint8_t dfu_req_handler(usb_dev *udev, usb_req *req); -static uint8_t dfu_data_in(usb_dev *udev, uint8_t ep_num); +static uint8_t dfu_ctlx_in(usb_dev *udev); + +static void dfu_mode_leave(usb_dev *udev); +static uint8_t dfu_getstatus_complete (usb_dev *udev); + +/* DFU requests management functions */ static void dfu_detach(usb_dev *udev, usb_req *req); static void dfu_dnload(usb_dev *udev, usb_req *req); static void dfu_upload(usb_dev *udev, usb_req *req); @@ -53,10 +59,10 @@ static void dfu_getstatus(usb_dev *udev, usb_req *req); static void dfu_clrstatus(usb_dev *udev, usb_req *req); static void dfu_getstate(usb_dev *udev, usb_req *req); static void dfu_abort(usb_dev *udev, usb_req *req); -static void dfu_mode_leave(usb_dev *udev); -static uint8_t dfu_getstatus_complete (usb_dev *udev); -static void (*dfu_request_process[])(usb_dev *udev, usb_req *req) = +static void string_to_unicode (uint8_t *str, uint16_t *pbuf); + +static void (*dfu_request_process[])(usb_dev *udev, usb_req *req) = { [DFU_DETACH] = dfu_detach, [DFU_DNLOAD] = dfu_dnload, @@ -71,9 +77,9 @@ static void (*dfu_request_process[])(usb_dev *udev, usb_req *req) = /* USB standard device descriptor */ __ALIGN_BEGIN const usb_desc_dev dfu_dev_desc __ALIGN_END = { - .header = + .header = { - .bLength = USB_DEV_DESC_LEN, + .bLength = USB_DEV_DESC_LEN, .bDescriptorType = USB_DESCTYPE_DEV }, .bcdUSB = 0x0200U, @@ -91,16 +97,16 @@ __ALIGN_BEGIN const usb_desc_dev dfu_dev_desc __ALIGN_END = }; /* USB device configuration descriptor */ -__ALIGN_BEGIN const usb_dfu_desc_config_set dfu_config_desc __ALIGN_END = +__ALIGN_BEGIN const usb_dfu_desc_config_set dfu_config_desc __ALIGN_END = { - .config = + .config = { - .header = + .header = { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG }, - .wTotalLength = USB_DFU_CONFIG_DESC_SIZE, + .wTotalLength = sizeof(usb_dfu_desc_config_set), .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, .iConfiguration = 0x00U, @@ -108,12 +114,12 @@ __ALIGN_BEGIN const usb_dfu_desc_config_set dfu_config_desc __ALIGN_END = .bMaxPower = 0x32U }, - .dfu_itf = + .dfu_itf0 = { - .header = + .header = { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, @@ -121,95 +127,149 @@ __ALIGN_BEGIN const usb_dfu_desc_config_set dfu_config_desc __ALIGN_END = .bInterfaceClass = USB_DFU_CLASS, .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, - .iInterface = 0x05U + .iInterface = STR_IDX_ALT_ITF0 }, - .dfu_func = + .dfu_itf1 = { - .header = + .header = { - .bLength = sizeof(usb_desc_dfu_func), - .bDescriptorType = DFU_DESC_TYPE + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x01U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_DFU_CLASS, + .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, + .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, + .iInterface = STR_IDX_ALT_ITF1 + }, + + .dfu_itf2 = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x02U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_DFU_CLASS, + .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, + .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, + .iInterface = STR_IDX_ALT_ITF2 + }, + + .dfu_func= + { + .header = + { + .bLength = sizeof(usb_desc_dfu_func), + .bDescriptorType = DFU_DESC_TYPE }, .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_CAN_UPLOAD | USB_DFU_WILL_DETACH, .wDetachTimeOut = 0x00FFU, .wTransferSize = TRANSFER_SIZE, - .bcdDFUVersion = 0x011AU, + .bcdDFUVersion = 0x0110U, }, }; -/* USB language ID Descriptor */ -static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +/* USB language ID descriptor */ +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { - .header = { - .bLength = sizeof(usb_desc_LANGID), + .header = + { + .bLength = sizeof(usb_desc_LANGID), .bDescriptorType = USB_DESCTYPE_STR - }, + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ -static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(10U), + .header = + { + .bLength = USB_STRING_LEN(10U), .bDescriptorType = USB_DESCTYPE_STR, }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ -static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(12U), + .header = + { + .bLength = USB_STRING_LEN(12U), .bDescriptorType = USB_DESCTYPE_STR, - }, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'D', 'F', 'U'} }; -/* USBD serial string */ -static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +/* USB serial string */ +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(2U), + .header = + { + .bLength = USB_STRING_LEN(2U), .bDescriptorType = USB_DESCTYPE_STR, - } + } }; /* USB configure string */ -static __ALIGN_BEGIN const usb_desc_str config_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str config_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(15U), + .header = + { + .bLength = USB_STRING_LEN(15U), .bDescriptorType = USB_DESCTYPE_STR, - }, + }, .unicode_string = {'G', 'D', '3', '2', ' ', 'U', 'S', 'B', ' ', 'C', 'O', 'N', 'F', 'I', 'G'} }; -static __ALIGN_BEGIN const usb_desc_str interface_string __ALIGN_END = +/* alternate interface 0 string */ +static __ALIGN_BEGIN usb_desc_str interface_string0 __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(44U), + .header = + { + .bLength = USB_STRING_LEN(2U), .bDescriptorType = USB_DESCTYPE_STR, - }, - .unicode_string = {'@', 'I', 'n', 't', 'e', 'r', 'n', 'a', 'l', 'F', 'l', 'a', 's', 'h', ' ', '/', '0', 'x', '0', '8', '0', '0', - '0', '0', '0', '0', '/', '1', '6', '*', '0', '0', '1', 'K', 'a', ',', '4', '8', '*', '0', '0', '1', 'K', 'g'} + }, }; -void *const usbd_dfu_strings[] = +/* alternate interface 1 string */ +static __ALIGN_BEGIN usb_desc_str interface_string1 __ALIGN_END = { - [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, - [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, - [STR_IDX_PRODUCT] = (uint8_t *)&product_string, - [STR_IDX_SERIAL] = (uint8_t *)&serial_string, - [STR_IDX_CONFIG] = (uint8_t *)&config_string, - [STR_IDX_ITF] = (uint8_t *)&interface_string + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + }, +}; + +/* alternate interface 2 string */ +static __ALIGN_BEGIN usb_desc_str interface_string2 __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + }, +}; + +void *const usbd_dfu_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *)&product_string, + [STR_IDX_SERIAL] = (uint8_t *)&serial_string, + [STR_IDX_CONFIG] = (uint8_t *)&config_string, + [STR_IDX_ALT_ITF0] = (uint8_t *)&interface_string0, + [STR_IDX_ALT_ITF1] = (uint8_t *)&interface_string1, + [STR_IDX_ALT_ITF2] = (uint8_t *)&interface_string2, }; usb_desc dfu_desc = { @@ -222,7 +282,7 @@ usb_class_core dfu_class = { .init = dfu_init, .deinit = dfu_deinit, .req_proc = dfu_req_handler, - .data_in = dfu_data_in + .ctlx_in = dfu_ctlx_in }; /*! @@ -237,22 +297,26 @@ static uint8_t dfu_init (usb_dev *udev, uint8_t config_index) static __ALIGN_BEGIN usbd_dfu_handler dfu_handler __ALIGN_END; /* unlock the internal flash */ - dfu_mal_init(); + dfu_mem_init(); memset((void *)&dfu_handler, 0, sizeof(usbd_dfu_handler)); - dfu_handler.base_addr = APP_LOADED_ADDR; dfu_handler.manifest_state = MANIFEST_COMPLETE; dfu_handler.bState = STATE_DFU_IDLE; dfu_handler.bStatus = STATUS_OK; udev->dev.class_data[USBD_DFU_INTERFACE] = (void *)&dfu_handler; + /* create interface string */ + string_to_unicode((uint8_t *)dfu_inter_flash_cb.pstr_desc, udev->dev.desc->strings[STR_IDX_ALT_ITF0]); + string_to_unicode((uint8_t *)dfu_nor_flash_cb.pstr_desc, udev->dev.desc->strings[STR_IDX_ALT_ITF1]); + string_to_unicode((uint8_t *)dfu_nand_flash_cb.pstr_desc, udev->dev.desc->strings[STR_IDX_ALT_ITF2]); + return USBD_OK; } /*! - \brief de-initialize the DFU device + \brief deinitialize the DFU device \param[in] udev: pointer to USB device instance \param[in] config_index: configuration index \param[out] none @@ -268,8 +332,8 @@ static uint8_t dfu_deinit (usb_dev *udev, uint8_t config_index) dfu->bState = STATE_DFU_IDLE; dfu->bStatus = STATUS_OK; - /* lock the internal flash */ - dfu_mal_deinit(); + /* deinit the memory */ + dfu_mem_deinit(); return USBD_OK; } @@ -293,17 +357,14 @@ static uint8_t dfu_req_handler (usb_dev *udev, usb_req *req) } /*! - \brief handle data Stage + \brief handle data stage \param[in] udev: pointer to USB device instance - \param[in] ep_num: the endpoint number \param[out] none \retval USB device operation status */ -static uint8_t dfu_data_in (usb_dev *udev, uint8_t ep_num) +static uint8_t dfu_ctlx_in (usb_dev *udev) { - if (0U == ep_num) { - dfu_getstatus_complete(udev); - } + dfu_getstatus_complete(udev); return USBD_OK; } @@ -325,8 +386,8 @@ static void dfu_mode_leave (usb_dev *udev) } else { dfu->bState = STATE_DFU_MANIFEST_WAIT_RESET; - /* lock the internal flash */ - dfu_mal_deinit(); + /* deinit the memory */ + dfu_mem_deinit(); /* generate system reset to allow jumping to the user code */ NVIC_SystemReset(); @@ -359,7 +420,7 @@ static uint8_t dfu_getstatus_complete (usb_dev *udev) } else if (ERASE == dfu->buf[0]) { dfu->base_addr = *(uint32_t *)(dfu->buf + 1U); - dfu_mal_erase(dfu->base_addr); + dfu_mem_erase(dfu->base_addr); } else { /* no operation */ } @@ -370,7 +431,7 @@ static uint8_t dfu_getstatus_complete (usb_dev *udev) /* decode the required address */ addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr; - dfu_mal_write (dfu->buf, addr, dfu->data_len); + dfu_mem_write (dfu->buf, addr, dfu->data_len); dfu->block_num = 0U; } else { @@ -417,7 +478,7 @@ static void dfu_detach(usb_dev *udev, usb_req *req) dfu->block_num = 0U; dfu->data_len = 0U; break; - + default: break; } @@ -515,7 +576,7 @@ static void dfu_upload (usb_dev *udev, usb_req *req) addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr; /* return the physical address where data are stored */ - phy_addr = dfu_mal_read (dfu->buf, addr, dfu->data_len); + phy_addr = dfu_mem_read (dfu->buf, addr, dfu->data_len); /* send the status data over EP0 */ transc->xfer_buf = phy_addr; @@ -539,11 +600,10 @@ static void dfu_upload (usb_dev *udev, usb_req *req) \param[out] none \retval none */ -static void dfu_getstatus (usb_dev *udev, usb_req *req) +static void dfu_getstatus (usb_dev *udev, usb_req *req) { - usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; - usb_transc *transc = &udev->dev.transc_in[0]; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; switch (dfu->bState) { case STATE_DFU_DNLOAD_SYNC: @@ -552,9 +612,9 @@ static void dfu_getstatus (usb_dev *udev, usb_req *req) if (0U == dfu->block_num) { if (ERASE == dfu->buf[0]) { - dfu_mal_getstatus (dfu->base_addr, CMD_ERASE, (uint8_t *)&dfu->bwPollTimeout0); + dfu_mem_getstatus (dfu->base_addr, CMD_ERASE, (uint8_t *)&dfu->bwPollTimeout0); } else { - dfu_mal_getstatus (dfu->base_addr, CMD_WRITE, (uint8_t *)&dfu->bwPollTimeout0); + dfu_mem_getstatus (dfu->base_addr, CMD_WRITE, (uint8_t *)&dfu->bwPollTimeout0); } } } else { @@ -586,7 +646,8 @@ static void dfu_getstatus (usb_dev *udev, usb_req *req) /*! \brief handle the DFU_CLRSTATUS request - \param udev: pointer to USB device instance + \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request \param[out] none \retval none */ @@ -609,14 +670,14 @@ static void dfu_clrstatus (usb_dev *udev, usb_req *req) /*! \brief handle the DFU_GETSTATE request \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request \param[out] none \retval none */ static void dfu_getstate (usb_dev *udev, usb_req *req) { - usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; - usb_transc *transc = &udev->dev.transc_in[0]; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; /* send the current state of the DFU interface to host */ transc->xfer_buf = &(dfu->bState); @@ -626,6 +687,7 @@ static void dfu_getstate (usb_dev *udev, usb_req *req) /*! \brief handle the DFU_ABORT request \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request \param[out] none \retval none */ @@ -651,3 +713,23 @@ static void dfu_abort (usb_dev *udev, usb_req *req) break; } } + +/*! + \brief convert string value into unicode char + \param[in] str: pointer to plain string + \param[in] pbuf: buffer pointer to store unicode char + \param[out] none + \retval none +*/ +static void string_to_unicode (uint8_t *str, uint16_t *pbuf) +{ + uint8_t index = 0; + + if (str != NULL) { + pbuf[index++] = ((strlen((const char *)str) * 2U + 2U) & 0x00FFU) | ((USB_DESCTYPE_STR << 8U) & 0xFF00); + + while (*str != '\0') { + pbuf[index++] = *str++; + } + } +} diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Source/dfu_mem.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Source/dfu_mem.c new file mode 100644 index 0000000000..b5c1a040ce --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/dfu/Source/dfu_mem.c @@ -0,0 +1,245 @@ +/*! + \file dfu_mem.c + \brief USB DFU device media access layer functions + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "dfu_mem.h" +#include "drv_usb_hw.h" +#include "usbd_transc.h" + +extern usb_core_driver usb_dfu_dev; + +extern struct { + uint8_t buf[TRANSFER_SIZE]; + uint16_t data_len; + uint16_t block_num; + uint32_t base_addr; +} prog; + +dfu_mem_prop* mem_tab[MAX_USED_MEMORY_MEDIA] = { + &dfu_inter_flash_cb, + &dfu_nor_flash_cb, + &dfu_nand_flash_cb, +}; + +/* The list of memory interface string descriptor pointers. This list + can be updated whenever a memory has to be added or removed */ +const uint8_t* USBD_DFU_StringDesc[MAX_USED_MEMORY_MEDIA] = +{ + (const uint8_t *)INTER_FLASH_IF_STR, + (const uint8_t *)NOR_FLASH_IF_STR, + (const uint8_t *)NAND_FLASH_IF_STR +}; + +static uint8_t dfu_mem_checkaddr (uint32_t addr); + +/*! + \brief initialize the memory media on the GD32 + \param[in] none + \param[out] none + \retval MEM_OK +*/ +uint8_t dfu_mem_init (void) +{ + uint32_t mem_index = 0U; + + /* initialize all supported memory medias */ + for (mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { + /* check if the memory media exists */ + if (NULL != mem_tab[mem_index]->mem_init) { + mem_tab[mem_index]->mem_init(); + } + } + + return MEM_OK; +} + +/*! + \brief deinitialize the memory media on the GD32 + \param[in] none + \param[out] none + \retval MEM_OK +*/ +uint8_t dfu_mem_deinit (void) +{ + uint32_t mem_index = 0U; + + /* deinitialize all supported memory medias */ + for (mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { + /* check if the memory media exists */ + if (NULL != mem_tab[mem_index]->mem_deinit) { + mem_tab[mem_index]->mem_deinit(); + } + } + + return MEM_OK; +} + +/*! + \brief erase a memory sector + \param[in] addr: memory sector address/code + \param[out] none + \retval MEM_OK +*/ +uint8_t dfu_mem_erase (uint32_t addr) +{ + uint32_t mem_index = dfu_mem_checkaddr(addr); + + /* check if the address is in protected area */ + if (IS_PROTECTED_AREA(addr)) { + return MEM_FAIL; + } + + if (mem_index < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if (NULL != mem_tab[mem_index]->mem_erase) { + return mem_tab[mem_index]->mem_erase(addr); + } else { + return MEM_FAIL; + } + } else { + return MEM_FAIL; + } +} + +/*! + \brief write data to sectors of memory + \param[in] buf: the data buffer to be write + \param[in] addr: memory sector address/code + \param[in] len: data length + \param[out] none + \retval MEM_OK +*/ +uint8_t dfu_mem_write (uint8_t *buf, uint32_t addr, uint32_t len) +{ + uint32_t mem_index = dfu_mem_checkaddr(addr); + + /* check if the address is in protected area */ + if (IS_PROTECTED_AREA(addr)) { + return MEM_FAIL; + } + + if ((addr & MAL_MASK_OB) == OB_RDPT0) { + option_byte_write(addr, buf); + NVIC_SystemReset(); + + return MEM_OK; + } + + if (mem_index < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if (NULL != mem_tab[mem_index]->mem_write) { + return mem_tab[mem_index]->mem_write(buf, addr, len); + } else { + return MEM_FAIL; + } + } else { + return MEM_FAIL; + } +} + +/*! + \brief read data from sectors of memory + \param[in] buf: the data buffer to be write + \param[in] addr: memory sector address/code + \param[in] len: data length + \param[out] none + \retval pointer to buffer +*/ +uint8_t* dfu_mem_read (uint8_t *buf, uint32_t addr, uint32_t len) +{ + uint32_t mem_index = 0U; + + if ((OB_RDPT0 != addr) && (OB_RDPT1 != addr)) { + mem_index = dfu_mem_checkaddr(addr); + } + + if (mem_index < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if (NULL != mem_tab[mem_index]->mem_read) { + return mem_tab[mem_index]->mem_read(buf, addr, len); + } else { + return buf; + } + } else { + return buf; + } +} + +/*! + \brief get the status of a given memory and store in buffer + \param[in] addr: memory sector address/code + \param[in] cmd: 0 for erase and 1 for write + \param[in] buffer: pointer to the buffer where the status data will be stored + \param[out] none + \retval MEM_OK if all operations are OK, MEM_FAIL else +*/ +uint8_t dfu_mem_getstatus (uint32_t addr, uint8_t cmd, uint8_t *buffer) +{ + uint32_t mem_index = dfu_mem_checkaddr(addr); + + if (mem_index < MAX_USED_MEMORY_MEDIA) { + if (cmd & 0x01U) { + POLLING_TIMEOUT_SET(mem_tab[mem_index]->write_timeout); + } else { + POLLING_TIMEOUT_SET(mem_tab[mem_index]->erase_timeout); + } + + return MEM_OK; + } else { + return MEM_FAIL; + } +} + +/*! + \brief check the address is supported + \param[in] addr: memory sector address/code + \param[out] none + \retval index of the addressed memory +*/ +static uint8_t dfu_mem_checkaddr (uint32_t addr) +{ + uint8_t mem_index = 0U; + + /* check with all supported memories */ + for (mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { + /* if the check address is supported, return the memory index */ + if (MEM_OK == mem_tab[mem_index]->mem_checkaddr(addr)) { + return mem_index; + } + } + + /* if there is no memory found, return MAX_USED_MEMORY_MEDIA */ + return (MAX_USED_MEMORY_MEDIA); +} diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Include/custom_hid_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Include/custom_hid_core.h index f320f77e40..aa0f207663 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Include/custom_hid_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Include/custom_hid_core.h @@ -3,32 +3,34 @@ \brief definitions for HID core \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Include/standard_hid_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Include/standard_hid_core.h index 773470d67f..8f83cf99db 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Include/standard_hid_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Include/standard_hid_core.h @@ -3,32 +3,34 @@ \brief definitions for HID core \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -39,7 +41,7 @@ OF SUCH DAMAGE. #include "usb_hid.h" #define USB_HID_CONFIG_DESC_LEN 0x22U -#define USB_HID_REPORT_DESC_LEN 0x29U +#define USB_HID_REPORT_DESC_LEN 0x2EU #define NO_CMD 0xFFU diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Source/custom_hid_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Source/custom_hid_core.c index fd4c9ccca7..13b9ac51de 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Source/custom_hid_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Source/custom_hid_core.c @@ -3,32 +3,34 @@ \brief custom HID class driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -44,10 +46,10 @@ OF SUCH DAMAGE. __ALIGN_BEGIN const usb_desc_dev custom_hid_dev_desc __ALIGN_END = { .header = - { - .bLength = USB_DEV_DESC_LEN, - .bDescriptorType = USB_DESCTYPE_DEV, - }, + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, .bcdUSB = 0x0200U, .bDeviceClass = 0x00U, .bDeviceSubClass = 0x00U, @@ -63,15 +65,15 @@ __ALIGN_BEGIN const usb_desc_dev custom_hid_dev_desc __ALIGN_END = }; /* USB device configuration descriptor */ -__ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = +__ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = { .config = { .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG - }, + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, .wTotalLength = DESC_LEN_CONFIG, .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, @@ -83,10 +85,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = .hid_itf = { .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x02U, @@ -99,10 +101,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = .hid_vendor = { .header = - { - .bLength = sizeof(usb_desc_hid), - .bDescriptorType = USB_DESCTYPE_HID - }, + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, .bcdHID = 0x0111U, .bCountryCode = 0x00U, .bNumDescriptors = 0x01U, @@ -113,10 +115,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = .hid_epin = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = CUSTOMHID_IN_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = CUSTOMHID_IN_PACKET, @@ -126,10 +128,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = .hid_epout = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = CUSTOMHID_OUT_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = CUSTOMHID_OUT_PACKET, @@ -138,50 +140,50 @@ __ALIGN_BEGIN const usb_hid_desc_config_set custom_hid_config_desc __ALIGN_END = }; /* USB language ID descriptor */ -static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR - }, + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ -static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ -static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(14U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(14U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'C', 'u', 's', 't', 'o', 'm', 'H', 'I', 'D'} }; /* USBD serial string */ -static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - } + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; /* USB string descriptor set */ -void *const usbd_hid_strings[] = +void *const usbd_hid_strings[] = { [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, @@ -270,7 +272,7 @@ static uint8_t custom_hid_req_handler (usb_dev *udev, usb_req *req); static uint8_t custom_hid_data_in (usb_dev *udev, uint8_t ep_num); static uint8_t custom_hid_data_out (usb_dev *udev, uint8_t ep_num); -usb_class_core usbd_custom_hid_cb = +usb_class_core usbd_custom_hid_cb = { .command = NO_CMD, .alter_set = 0U, @@ -330,10 +332,10 @@ static uint8_t custom_hid_init (usb_dev *udev, uint8_t config_index) memset((void *)&hid_handler, 0U, sizeof(custom_hid_handler)); - /* initialize the data TX endpoint */ + /* initialize the data Tx endpoint */ usbd_ep_setup (udev, &(custom_hid_config_desc.hid_epin)); - /* Initialize the data RX endpoint */ + /* initialize the data Rx endpoint */ usbd_ep_setup (udev, &(custom_hid_config_desc.hid_epout)); /* prepare receive data */ @@ -353,7 +355,7 @@ static uint8_t custom_hid_init (usb_dev *udev, uint8_t config_index) } /*! - \brief de-initialize the HID device + \brief deinitialize the HID device \param[in] udev: pointer to USB device instance \param[in] config_index: configuration index \param[out] none @@ -444,43 +446,40 @@ static uint8_t custom_hid_data_out (usb_dev *udev, uint8_t ep_num) { custom_hid_handler *hid = (custom_hid_handler *)udev->dev.class_data[CUSTOM_HID_INTERFACE]; - if ((CUSTOMHID_OUT_EP & 0x7FU) == ep_num) { - switch (hid->data[0]){ - case 0x11U: - if (RESET != hid->data[1]) { - gd_eval_led_on(LED1); - } else { - gd_eval_led_off(LED1); - } - break; - - case 0x12U: - if (RESET != hid->data[1]) { - gd_eval_led_on(LED2); - } else { - gd_eval_led_off(LED2); - } - break; - - case 0x13U: - if (RESET != hid->data[1]) { - gd_eval_led_on(LED3); - } else { - gd_eval_led_off(LED3); - } - break; - - case 0x14U: - break; - - default: - break; + /* light the LED */ + switch (hid->data[0]){ + case 0x11U: + if (RESET != hid->data[1]) { + gd_eval_led_on(LED1); + } else { + gd_eval_led_off(LED1); } + break; - usbd_ep_recev (udev, CUSTOMHID_IN_EP, hid->data, 2U); + case 0x12U: + if (RESET != hid->data[1]) { + gd_eval_led_on(LED2); + } else { + gd_eval_led_off(LED2); + } + break; - return USBD_OK; - } + case 0x13U: + if (RESET != hid->data[1]) { + gd_eval_led_on(LED3); + } else { + gd_eval_led_off(LED3); + } + break; - return USBD_FAIL; + case 0x14U: + break; + + default: + break; + } + + usbd_ep_recev (udev, CUSTOMHID_OUT_EP, hid->data, 2U); + + return USBD_OK; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Source/standard_hid_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Source/standard_hid_core.c index 8252e33e97..e3b498143a 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Source/standard_hid_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/hid/Source/standard_hid_core.c @@ -3,32 +3,34 @@ \brief HID class driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -43,10 +45,10 @@ OF SUCH DAMAGE. __ALIGN_BEGIN const usb_desc_dev hid_dev_desc __ALIGN_END = { .header = - { - .bLength = USB_DEV_DESC_LEN, - .bDescriptorType = USB_DESCTYPE_DEV - }, + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, .bcdUSB = 0x0200U, .bDeviceClass = 0x00U, .bDeviceSubClass = 0x00U, @@ -61,15 +63,15 @@ __ALIGN_BEGIN const usb_desc_dev hid_dev_desc __ALIGN_END = .bNumberConfigurations = USBD_CFG_MAX_NUM }; -__ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = +__ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = { .config = { .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG - }, + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, .wTotalLength = USB_HID_CONFIG_DESC_LEN, .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, @@ -81,10 +83,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = .hid_itf = { .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x01U, @@ -97,10 +99,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = .hid_vendor = { .header = - { - .bLength = sizeof(usb_desc_hid), - .bDescriptorType = USB_DESCTYPE_HID - }, + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, .bcdHID = 0x0111U, .bCountryCode = 0x00U, .bNumDescriptors = 0x01U, @@ -111,10 +113,71 @@ __ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = .hid_epin = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = HID_IN_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = HID_IN_PACKET, + .bInterval = 0x10U + } +}; + +__ALIGN_BEGIN const usb_hid_desc_config_set other_speed_hid_config_desc __ALIGN_END = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_OTHER_SPD_CONFIG + }, + .wTotalLength = USB_HID_CONFIG_DESC_LEN, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xA0U, + .bMaxPower = 0x32U + }, + + .hid_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_HID_CLASS, + .bInterfaceSubClass = USB_HID_SUBCLASS_BOOT_ITF, + .bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD, + .iInterface = 0x00U + }, + + .hid_vendor = + { + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, + .bcdHID = 0x0111U, + .bCountryCode = 0x00U, + .bNumDescriptors = 0x01U, + .bDescriptorType = USB_DESCTYPE_REPORT, + .wDescriptorLength = USB_HID_REPORT_DESC_LEN, + }, + + .hid_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = HID_IN_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = HID_IN_PACKET, @@ -122,50 +185,64 @@ __ALIGN_BEGIN const usb_hid_desc_config_set hid_config_desc __ALIGN_END = } }; +__ALIGN_BEGIN const uint8_t usbd_qualifier_desc[10] __ALIGN_END = +{ + 0x0A, + 0x06, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00 +}; + /* USB language ID Descriptor */ -static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR - }, + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ -static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ -static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(17U), - .bDescriptorType = USB_DESCTYPE_STR, - }, - .unicode_string = {'G', 'D', '3', '2', '-','U', 'S', 'B', '_', 'K', 'e', 'y', 'b', 'o', 'a', 'r', 'd'} + { + .bLength = USB_STRING_LEN(17U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'K', 'e', 'y', 'b', 'o', 'a', 'r', 'd'} }; /* USBD serial string */ -static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - } + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; -void *const usbd_hid_strings[] = +void *const usbd_hid_strings[] = { [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, @@ -176,6 +253,10 @@ void *const usbd_hid_strings[] = usb_desc hid_desc = { .dev_desc = (uint8_t *)&hid_dev_desc, .config_desc = (uint8_t *)&hid_config_desc, +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + .other_speed_config_desc = (uint8_t *)&other_speed_hid_config_desc, + .qualifier_desc = (uint8_t *)&usbd_qualifier_desc, +#endif .strings = usbd_hid_strings }; @@ -200,7 +281,9 @@ __ALIGN_BEGIN const uint8_t hid_report_desc[USB_HID_REPORT_DESC_LEN] __ALIGN_END 0x95, 0x06, /* REPORT_COUNT (6) */ 0x75, 0x08, /* REPORT_SIZE (8) */ - 0x25, 0xFF, /* LOGICAL_MAXIMUM (255) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x26, 0xFF, 0x00, /* LOGICAL_MAXIMUM (255) */ + 0x05, 0x07, /* USAGE_PAGE (Keyboard/Keypad) */ 0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */ 0x29, 0x65, /* USAGE_MAXIMUM (Keyboard Application) */ 0x81, 0x00, /* INPUT (Data,Ary,Abs) */ @@ -289,7 +372,7 @@ static uint8_t hid_init (usb_dev *udev, uint8_t config_index) } /*! - \brief de-initialize the HID device + \brief deinitialize the HID device \param[in] udev: pointer to USB device instance \param[in] config_index: configuration index \param[out] none @@ -351,6 +434,9 @@ static uint8_t hid_req (usb_dev *udev, usb_req *req) transc->xfer_buf = (uint8_t *)hid_report_desc; return REQ_SUPP; + } else if (USB_DESCTYPE_HID == (req->wValue >> 8U)) { + transc->remain_len = USB_MIN(9U, req->wLength); + transc->xfer_buf = (uint8_t *)(&(hid_config_desc.hid_vendor)); } break; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/iap/Include/usb_iap_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/iap/Include/usb_iap_core.h index a84dc4a255..21696a93ca 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/iap/Include/usb_iap_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/iap/Include/usb_iap_core.h @@ -3,32 +3,34 @@ \brief the header file of IAP driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -43,7 +45,11 @@ OF SUCH DAMAGE. #ifdef USE_USB_FS #define USB_DESC_LEN_IAP_REPORT 35U #elif defined(USE_USB_HS) - #define USB_DESC_LEN_IAP_REPORT 36U + #ifdef USE_ULPI_PHY + #define USB_DESC_LEN_IAP_REPORT 36U + #else + #define USB_DESC_LEN_IAP_REPORT 35U + #endif #else #error "please select 'USE_USB_FS' or 'USE_USB_HS'" #endif diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/iap/Source/usb_iap_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/iap/Source/usb_iap_core.c index 6dced66ab8..3761a89c6c 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/iap/Source/usb_iap_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/iap/Source/usb_iap_core.c @@ -3,32 +3,34 @@ \brief IAP driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -44,10 +46,10 @@ OF SUCH DAMAGE. __ALIGN_BEGIN const usb_desc_dev iap_dev_desc __ALIGN_END = { .header = - { - .bLength = USB_DEV_DESC_LEN, - .bDescriptorType = USB_DESCTYPE_DEV - }, + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, .bcdUSB = 0x0200U, .bDeviceClass = 0x00U, .bDeviceSubClass = 0x00U, @@ -62,15 +64,15 @@ __ALIGN_BEGIN const usb_desc_dev iap_dev_desc __ALIGN_END = .bNumberConfigurations = USBD_CFG_MAX_NUM }; -__ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = +__ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = { .config = { .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG - }, + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, .wTotalLength = USB_DESC_LEN_IAP_CONFIG_SET, .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, @@ -82,10 +84,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = .hid_itf = { .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x02U, @@ -98,10 +100,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = .hid_vendor = { .header = - { - .bLength = sizeof(usb_desc_hid), - .bDescriptorType = USB_DESCTYPE_HID - }, + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, .bcdHID = 0x0111U, .bCountryCode = 0x00U, .bNumDescriptors = 0x01U, @@ -112,10 +114,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = .hid_epin = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = IAP_IN_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = IAP_IN_PACKET, @@ -125,10 +127,10 @@ __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = .hid_epout = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = IAP_OUT_EP, .bmAttributes = USB_EP_ATTR_INT, .wMaxPacketSize = IAP_OUT_PACKET, @@ -137,49 +139,49 @@ __ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = }; /* USB language ID Descriptor */ -static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR - }, + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ -static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ -static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'I', 'A', 'P'} }; /* USBD serial string */ -static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(2U), - .bDescriptorType = USB_DESCTYPE_STR, - } + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; -void *const usbd_iap_strings[] = +void *const usbd_iap_strings[] = { [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, @@ -194,17 +196,17 @@ usb_desc iap_desc = { }; /* local function prototypes ('static') */ -static uint8_t iap_init (usb_dev *udev, uint8_t config_index); -static uint8_t iap_deinit (usb_dev *udev, uint8_t config_index); -static uint8_t iap_req_handler (usb_dev *udev, usb_req *req); -static uint8_t iap_data_out (usb_dev *udev, uint8_t ep_num); +static uint8_t iap_init (usb_dev *udev, uint8_t config_index); +static uint8_t iap_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t iap_req_handler (usb_dev *udev, usb_req *req); +static uint8_t iap_data_out (usb_dev *udev, uint8_t ep_num); /* IAP requests management functions */ -static void iap_req_erase (usb_dev *udev); -static void iap_req_dnload (usb_dev *udev); -static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num); -static void iap_req_leave (usb_dev *udev); -static void iap_address_send (usb_dev *udev); +static void iap_req_erase (usb_dev *udev); +static void iap_req_dnload (usb_dev *udev); +static void iap_req_optionbyte (usb_dev *udev, uint8_t option_num); +static void iap_req_leave (usb_dev *udev); +static void iap_address_send (usb_dev *udev); usb_class_core iap_class = { .init = iap_init, @@ -275,10 +277,10 @@ static uint8_t iap_init (usb_dev *udev, uint8_t config_index) { static __ALIGN_BEGIN usbd_iap_handler iap_handler __ALIGN_END; - /* initialize TX endpoint */ + /* initialize Tx endpoint */ usbd_ep_setup(udev, &(iap_config_desc.hid_epin)); - /* initialize RX endpoint */ + /* initialize Rx endpoint */ usbd_ep_setup(udev, &(iap_config_desc.hid_epout)); /* unlock the internal flash */ @@ -380,47 +382,45 @@ static uint8_t iap_data_out (usb_dev *udev ,uint8_t ep_num) { usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; - if ((IAP_OUT_EP & 0x7FU) == ep_num) { - if (0x01U == iap->report_buf[0]) { - switch (iap->report_buf[1]) { - case IAP_DNLOAD: - iap_req_dnload(udev); - break; + if (0x01U == iap->report_buf[0]) { + switch (iap->report_buf[1]) { + case IAP_DNLOAD: + iap_req_dnload(udev); + break; - case IAP_ERASE: - iap_req_erase(udev); - break; + case IAP_ERASE: + iap_req_erase(udev); + break; - case IAP_OPTION_BYTE1: - iap_req_optionbyte(udev, 0x01U); - break; + case IAP_OPTION_BYTE1: + iap_req_optionbyte(udev, 0x01U); + break; - case IAP_LEAVE: - iap_req_leave(udev); - break; + case IAP_LEAVE: + iap_req_leave(udev); + break; - case IAP_GETBIN_ADDRESS: - iap_address_send(udev); - break; + case IAP_GETBIN_ADDRESS: + iap_address_send(udev); + break; - case IAP_OPTION_BYTE2: - iap_req_optionbyte(udev, 0x02U); - break; + case IAP_OPTION_BYTE2: + iap_req_optionbyte(udev, 0x02U); + break; - default: - break; - } + default: + break; } - - usbd_ep_recev(udev, IAP_OUT_EP, iap->report_buf, IAP_OUT_PACKET); } + usbd_ep_recev(udev, IAP_OUT_EP, iap->report_buf, IAP_OUT_PACKET); + return USBD_OK; } /*! \brief handle the IAP_DNLOAD request - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[out] none \retval none */ @@ -452,7 +452,7 @@ static void iap_req_dnload(usb_dev *udev) /*! \brief handle the IAP_ERASE request - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[out] none \retval none */ @@ -515,7 +515,7 @@ static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num) usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; - iap->option_byte[0]= 0x02U; + iap->option_byte[0] = 0x02U; if (0x01U == option_num) { address = OPT_BYTE_ADDR1; @@ -537,7 +537,7 @@ static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num) /*! \brief handle the IAP_LEAVE request - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[out] none \retval none */ @@ -552,7 +552,7 @@ static void iap_req_leave(usb_dev *udev) /*! \brief handle the IAP_SEND_ADDRESS request - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[out] none \retval none */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_bbb.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_bbb.h index 266b932d7a..d855d878f2 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_bbb.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_bbb.h @@ -1,34 +1,36 @@ /*! \file usbd_msc_bbb.h - \brief the header file of the usbd_msc_bot.c file + \brief the header file of the usbd_msc_bbb.c file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -83,7 +85,7 @@ typedef struct } usbd_msc_handler; /* function declarations */ -/* initialize the bbb process */ +/* initialize the BBB process */ void msc_bbb_init (usb_core_driver *udev); /* reset the BBB machine */ void msc_bbb_reset (usb_core_driver *udev); diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_core.h index a67b539746..8782c5d3f8 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_core.h @@ -3,32 +3,34 @@ \brief the header file of USB MSC device class core functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_mem.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_mem.h index c39778fcf6..aa8c9ccf99 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_mem.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_mem.h @@ -3,32 +3,34 @@ \brief header file for storage memory \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -52,7 +54,7 @@ typedef struct uint8_t *mem_inquiry_data[MEM_LUN_NUM]; uint32_t mem_block_size[MEM_LUN_NUM]; uint32_t mem_block_len[MEM_LUN_NUM]; -}usbd_mem_cb; +} usbd_mem_cb; extern usbd_mem_cb *usbd_mem_fops; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_scsi.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_scsi.h index 188e592ced..828eab1364 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_scsi.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Include/usbd_msc_scsi.h @@ -3,44 +3,54 @@ \brief the header file of the usbd_msc_scsi.c file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBD_MSC_SCSI_H #define __USBD_MSC_SCSI_H -#include "usbd_msc_data.h" #include "usbd_msc_bbb.h" #include "msc_scsi.h" #define SENSE_LIST_DEEPTH 4U +#define MODE_SENSE6_LENGTH 8U +#define MODE_SENSE10_LENGTH 8U +#define INQUIRY_PAGE00_LENGTH 96U +#define FORMAT_CAPACITIES_LENGTH 20U + +extern const uint8_t msc_page00_inquiry_data[]; +extern const uint8_t msc_mode_sense6_data[]; +extern const uint8_t msc_mode_sense10_data[]; + /* function declarations */ /* process SCSI commands */ int8_t scsi_process_cmd (usb_core_driver *udev, uint8_t lun, uint8_t *cmd); diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_bbb.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_bbb.c index d9a74d5d5d..cbd5e62c84 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_bbb.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_bbb.c @@ -4,32 +4,34 @@ \note BBB means Bulk-only transport protocol for USB MSC \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -38,11 +40,11 @@ OF SUCH DAMAGE. /* local function prototypes ('static') */ static void msc_bbb_cbw_decode (usb_core_driver *udev); -static void msc_bbb_data_send (usb_core_driver *udev, uint8_t *pbuf, uint32_t Len); -static void msc_bbb_abort (usb_core_driver *udev); +static void msc_bbb_data_send (usb_core_driver *udev, uint8_t *pbuf, uint32_t Len); +static void msc_bbb_abort (usb_core_driver *udev); /*! - \brief initialize the bbb process + \brief initialize the BBB process \param[in] udev: pointer to USB device instance \param[out] none \retval none @@ -61,10 +63,10 @@ void msc_bbb_init (usb_core_driver *udev) usbd_mem_fops->mem_init(lun_num); } - /* flush the RX FIFO */ + /* flush the Rx FIFO */ usbd_fifo_flush (udev, MSC_OUT_EP); - /* flush the TX FIFO */ + /* flush the Tx FIFO */ usbd_fifo_flush (udev, MSC_IN_EP); /* prepare endpoint to receive the first BBB CBW */ @@ -89,7 +91,7 @@ void msc_bbb_reset (usb_core_driver *udev) } /*! - \brief de-initialize the BBB machine + \brief deinitialize the BBB machine \param[in] udev: pointer to USB device instance \param[out] none \retval none @@ -188,7 +190,7 @@ void msc_bbb_clrfeature (usb_core_driver *udev, uint8_t ep_num) { usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; - if (msc->bbb_status == BBB_STATUS_ERROR)/* bad CBW signature */ { + if (msc->bbb_status == BBB_STATUS_ERROR) { /* bad CBW signature */ usbd_ep_stall(udev, MSC_IN_EP); msc->bbb_status = BBB_STATUS_NORMAL; @@ -212,11 +214,11 @@ static void msc_bbb_cbw_decode (usb_core_driver *udev) msc->bbb_csw.dCSWTag = msc->bbb_cbw.dCBWTag; msc->bbb_csw.dCSWDataResidue = msc->bbb_cbw.dCBWDataTransferLength; - if ((BBB_CBW_LENGTH != usbd_rxcount_get (udev, MSC_OUT_EP)) || - (BBB_CBW_SIGNATURE != msc->bbb_cbw.dCBWSignature)|| - (msc->bbb_cbw.bCBWLUN > 1U) || - (msc->bbb_cbw.bCBWCBLength < 1U) || - (msc->bbb_cbw.bCBWCBLength > 16U)) { + if((BBB_CBW_LENGTH != usbd_rxcount_get(udev, MSC_OUT_EP)) || + (BBB_CBW_SIGNATURE != msc->bbb_cbw.dCBWSignature) || + (msc->bbb_cbw.bCBWLUN > 1U) || + (msc->bbb_cbw.bCBWCBLength < 1U) || + (msc->bbb_cbw.bCBWCBLength > 16U)) { /* illegal command handler */ scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); @@ -226,7 +228,7 @@ static void msc_bbb_cbw_decode (usb_core_driver *udev) } else { if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) { msc_bbb_abort (udev); - } else if ((BBB_DATA_IN != msc->bbb_state) && + } else if ((BBB_DATA_IN != msc->bbb_state) && (BBB_DATA_OUT != msc->bbb_state) && (BBB_LAST_DATA_IN != msc->bbb_state)) { /* burst xfer handled internally */ if (msc->bbb_datalen > 0U) { @@ -273,9 +275,9 @@ static void msc_bbb_abort (usb_core_driver *udev) { usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; - if ((0U == msc->bbb_cbw.bmCBWFlags) && - (0U != msc->bbb_cbw.dCBWDataTransferLength) && - (BBB_STATUS_NORMAL == msc->bbb_status)) { + if ((0U == msc->bbb_cbw.bmCBWFlags) && + (0U != msc->bbb_cbw.dCBWDataTransferLength) && + (BBB_STATUS_NORMAL == msc->bbb_status)) { usbd_ep_stall(udev, MSC_OUT_EP); } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_core.c index 9c6e9f0857..1c9d4fc7dc 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_core.c @@ -3,32 +3,34 @@ \brief USB MSC device class core functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -47,7 +49,7 @@ static uint8_t msc_core_req (usb_dev *udev, usb_req *req); static uint8_t msc_core_in (usb_dev *udev, uint8_t ep_num); static uint8_t msc_core_out (usb_dev *udev, uint8_t ep_num); -usb_class_core msc_class = +usb_class_core msc_class = { .init = msc_core_init, .deinit = msc_core_deinit, @@ -62,8 +64,9 @@ usb_class_core msc_class = /* USB standard device descriptor */ __ALIGN_BEGIN const usb_desc_dev msc_dev_desc __ALIGN_END = { - .header = { - .bLength = USB_DEV_DESC_LEN, + .header = + { + .bLength = USB_DEV_DESC_LEN, .bDescriptorType = USB_DESCTYPE_DEV }, .bcdUSB = 0x0200U, @@ -81,12 +84,13 @@ __ALIGN_BEGIN const usb_desc_dev msc_dev_desc __ALIGN_END = }; /* USB device configuration descriptor */ -__ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = +__ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = { - .config = + .config = { - .header = { - .bLength = sizeof(usb_desc_config), + .header = + { + .bLength = sizeof(usb_desc_config), .bDescriptorType = USB_DESCTYPE_CONFIG }, .wTotalLength = USB_MSC_CONFIG_DESC_SIZE, @@ -97,10 +101,11 @@ __ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = .bMaxPower = 0x32U }, - .msc_itf = + .msc_itf = { - .header = { - .bLength = sizeof(usb_desc_itf), + .header = + { + .bLength = sizeof(usb_desc_itf), .bDescriptorType = USB_DESCTYPE_ITF }, .bInterfaceNumber = 0x00U, @@ -112,10 +117,11 @@ __ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = .iInterface = 0x00U }, - .msc_epin = + .msc_epin = { - .header = { - .bLength = sizeof(usb_desc_ep), + .header = + { + .bLength = sizeof(usb_desc_ep), .bDescriptorType = USB_DESCTYPE_EP }, .bEndpointAddress = MSC_IN_EP, @@ -124,10 +130,11 @@ __ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = .bInterval = 0x00U }, - .msc_epout = + .msc_epout = { - .header = { - .bLength = sizeof(usb_desc_ep), + .header = + { + .bLength = sizeof(usb_desc_ep), .bDescriptorType = USB_DESCTYPE_EP }, .bEndpointAddress = MSC_OUT_EP, @@ -137,51 +144,126 @@ __ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = } }; -/* USB language ID descriptor */ -static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +/* USB device configuration descriptor */ +__ALIGN_BEGIN const usb_desc_config_set other_speed_msc_config_desc __ALIGN_END = { - .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR - }, + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_OTHER_SPD_CONFIG + }, + .wTotalLength = USB_MSC_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xC0U, + .bMaxPower = 0x32U + }, + + .msc_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_MSC, + .bInterfaceSubClass = USB_MSC_SUBCLASS_SCSI, + .bInterfaceProtocol = USB_MSC_PROTOCOL_BBB, + .iInterface = 0x00U + }, + + .msc_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = MSC_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = 64U, + .bInterval = 0x00U + }, + + .msc_epout = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = MSC_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = 64U, + .bInterval = 0x00U + } +}; + +__ALIGN_BEGIN const uint8_t usbd_qualifier_desc[10] __ALIGN_END = +{ + 0x0A, + 0x06, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00 +}; + +/* USB language ID descriptor */ +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ -static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ -static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'M', 'S', 'C'} }; /* USBD serial string */ -static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - } + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; /* USB string descriptor */ -static void *const usbd_msc_strings[] = +static void *const usbd_msc_strings[] = { [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, @@ -192,6 +274,12 @@ static void *const usbd_msc_strings[] = usb_desc msc_desc = { .dev_desc = (uint8_t *)&msc_dev_desc, .config_desc = (uint8_t *)&msc_config_desc, + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + .other_speed_config_desc = (uint8_t *)&other_speed_msc_config_desc, + .qualifier_desc = (uint8_t *)&usbd_qualifier_desc, +#endif /* USE_USB_HS && USE_ULPI_PHY */ + .strings = usbd_msc_strings }; @@ -212,10 +300,10 @@ static uint8_t msc_core_init (usb_dev *udev, uint8_t config_index) udev->dev.class_data[USBD_MSC_INTERFACE] = (void *)&msc_handler; - /* configure MSC TX endpoint */ + /* configure MSC Tx endpoint */ usbd_ep_setup (udev, &(msc_config_desc.msc_epin)); - /* configure MSC RX endpoint */ + /* configure MSC Rx endpoint */ usbd_ep_setup (udev, &(msc_config_desc.msc_epout)); /* initialize the BBB layer */ @@ -225,7 +313,7 @@ static uint8_t msc_core_init (usb_dev *udev, uint8_t config_index) } /*! - \brief de-initialize the MSC device + \brief deinitialize the MSC device \param[in] udev: pointer to USB device instance \param[in] config_index: configuration index \param[out] none @@ -256,7 +344,7 @@ static uint8_t msc_core_req (usb_dev *udev, usb_req *req) switch (req->bRequest) { case BBB_GET_MAX_LUN : - if((0U == req->wValue) && + if((0U == req->wValue) && (1U == req->wLength) && (0x80U == (req->bmRequestType & 0x80U))) { usbd_msc_maxlun = (uint8_t)usbd_mem_fops->mem_maxlun(); @@ -269,7 +357,7 @@ static uint8_t msc_core_req (usb_dev *udev, usb_req *req) break; case BBB_RESET : - if((0U == req->wValue) && + if((0U == req->wValue) && (0U == req->wLength) && (0x80U != (req->bmRequestType & 0x80U))) { msc_bbb_reset(udev); @@ -298,9 +386,7 @@ static uint8_t msc_core_req (usb_dev *udev, usb_req *req) */ static uint8_t msc_core_in (usb_dev *udev, uint8_t ep_num) { - if ((MSC_IN_EP & 0x7FU) == ep_num) { - msc_bbb_data_in(udev, ep_num); - } + msc_bbb_data_in (udev, ep_num); return USBD_OK; } @@ -314,9 +400,7 @@ static uint8_t msc_core_in (usb_dev *udev, uint8_t ep_num) */ static uint8_t msc_core_out (usb_dev *udev, uint8_t ep_num) { - if (MSC_OUT_EP == ep_num) { - msc_bbb_data_out (udev, ep_num); - } + msc_bbb_data_out (udev, ep_num); return USBD_OK; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_scsi.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_scsi.c index 7afae6fa30..870c3a6399 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_scsi.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/msc/Source/usbd_msc_scsi.c @@ -3,41 +3,83 @@ \brief USB SCSI layer functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ + #include "usbd_enum.h" #include "usbd_msc_bbb.h" #include "usbd_msc_scsi.h" -#include "usbd_msc_data.h" + +/* USB mass storage page 0 inquiry data */ +const uint8_t msc_page00_inquiry_data[] = +{ + 0x00U, + 0x00U, + 0x00U, + 0x00U, + (INQUIRY_PAGE00_LENGTH - 4U), + 0x80U, + 0x83U, +}; + +/* USB mass storage sense 6 data */ +const uint8_t msc_mode_sense6_data[] = +{ + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U +}; + +/* USB mass storage sense 10 data */ +const uint8_t msc_mode_sense10_data[] = +{ + 0x00U, + 0x06U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U +}; /* local function prototypes ('static') */ static int8_t scsi_test_unit_ready (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_select6 (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_select10 (usb_core_driver *udev, uint8_t lun, uint8_t *params); static int8_t scsi_inquiry (usb_core_driver *udev, uint8_t lun, uint8_t *params); static int8_t scsi_read_format_capacity (usb_core_driver *udev, uint8_t lun, uint8_t *params); static int8_t scsi_read_capacity10 (usb_core_driver *udev, uint8_t lun, uint8_t *params); @@ -96,7 +138,7 @@ int8_t scsi_process_cmd(usb_core_driver *udev, uint8_t lun, uint8_t *params) return scsi_read_capacity10 (udev, lun, params); case SCSI_READ10: - return scsi_read10 (udev, lun, params); + return scsi_read10 (udev, lun, params); case SCSI_WRITE10: return scsi_write10 (udev, lun, params); @@ -110,6 +152,12 @@ int8_t scsi_process_cmd(usb_core_driver *udev, uint8_t lun, uint8_t *params) case SCSI_READ_TOC_DATA: return scsi_toc_cmd_read (udev, lun, params); + case SCSI_MODE_SELECT6: + return scsi_mode_select6 (udev, lun, params); + + case SCSI_MODE_SELECT10: + return scsi_mode_select10 (udev, lun, params); + default: scsi_sense_code (udev, lun, ILLEGAL_REQUEST, INVALID_CDB); return -1; @@ -130,7 +178,7 @@ void scsi_sense_code (usb_core_driver *udev, uint8_t lun, uint8_t skey, uint8_t usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; msc->scsi_sense[msc->scsi_sense_tail].SenseKey = skey; - msc->scsi_sense[msc->scsi_sense_tail].ASC = asc << 8U; + msc->scsi_sense[msc->scsi_sense_tail].ASC = asc; msc->scsi_sense_tail++; if (SENSE_LIST_DEEPTH == msc->scsi_sense_tail) { @@ -163,9 +211,39 @@ static int8_t scsi_test_unit_ready (usb_core_driver *udev, uint8_t lun, uint8_t return -1; } - if (1U == msc->scsi_disk_pop) { - usbd_disconnect (udev); - } + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Inquiry command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_select6 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Inquiry command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_select10 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; msc->bbb_datalen = 0U; @@ -347,8 +425,8 @@ static int8_t scsi_request_sense (usb_core_driver *udev, uint8_t lun, uint8_t *p if ((msc->scsi_sense_head != msc->scsi_sense_tail)) { msc->bbb_data[2] = msc->scsi_sense[msc->scsi_sense_head].SenseKey; - msc->bbb_data[12] = msc->scsi_sense[msc->scsi_sense_head].ASCQ; - msc->bbb_data[13] = msc->scsi_sense[msc->scsi_sense_head].ASC; + msc->bbb_data[12] = msc->scsi_sense[msc->scsi_sense_head].ASC; + msc->bbb_data[13] = msc->scsi_sense[msc->scsi_sense_head].ASCQ; msc->scsi_sense_head++; if (msc->scsi_sense_head == SENSE_LIST_DEEPTH) { @@ -506,9 +584,9 @@ static int8_t scsi_write10 (usb_core_driver *udev, uint8_t lun, uint8_t *params) /* prepare endpoint to receive first data packet */ msc->bbb_state = BBB_DATA_OUT; - usbd_ep_recev (udev, - MSC_OUT_EP, - msc->bbb_data, + usbd_ep_recev (udev, + MSC_OUT_EP, + msc->bbb_data, USB_MIN (msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE)); } else { /* write process ongoing */ return scsi_process_write (udev, lun); @@ -580,12 +658,12 @@ static int8_t scsi_process_read (usb_core_driver *udev, uint8_t lun) uint32_t len = USB_MIN(msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE); if (usbd_mem_fops->mem_read(lun, - msc->bbb_data, - msc->scsi_blk_addr, + msc->bbb_data, + msc->scsi_blk_addr, (uint16_t)(len / msc->scsi_blk_size[lun])) < 0) { scsi_sense_code(udev, lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); - return -1; + return -1; } usbd_ep_send (udev, MSC_IN_EP, msc->bbb_data, len); @@ -617,8 +695,8 @@ static int8_t scsi_process_write (usb_core_driver *udev, uint8_t lun) uint32_t len = USB_MIN(msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE); if (usbd_mem_fops->mem_write (lun, - msc->bbb_data, - msc->scsi_blk_addr, + msc->bbb_data, + msc->scsi_blk_addr, (uint16_t)(len / msc->scsi_blk_size[lun])) < 0) { scsi_sense_code(udev, lun, HARDWARE_ERROR, WRITE_FAULT); @@ -635,9 +713,9 @@ static int8_t scsi_process_write (usb_core_driver *udev, uint8_t lun) msc_bbb_csw_send (udev, CSW_CMD_PASSED); } else { /* prepare endpoint to receive next packet */ - usbd_ep_recev (udev, - MSC_OUT_EP, - msc->bbb_data, + usbd_ep_recev (udev, + MSC_OUT_EP, + msc->bbb_data, USB_MIN (msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE)); } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/printer/Include/printer_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/printer/Include/printer_core.h index 88c933ac94..da83a69f0b 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/printer/Include/printer_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/printer/Include/printer_core.h @@ -3,32 +3,34 @@ \brief the header file of USB printer device class core functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/printer/Source/printer_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/printer/Source/printer_core.c index 71818f03b9..67e49f18ff 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/printer/Source/printer_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/class/printer/Source/printer_core.c @@ -3,32 +3,34 @@ \brief USB printer device class core functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -61,10 +63,10 @@ __ALIGN_BEGIN uint8_t PRINTER_DEVICE_ID[DEVICE_ID_LEN] __ALIGN_END = __ALIGN_BEGIN const usb_desc_dev printer_dev_desc __ALIGN_END = { .header = - { - .bLength = USB_DEV_DESC_LEN, - .bDescriptorType = USB_DESCTYPE_DEV, - }, + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, .bcdUSB = 0x0200U, .bDeviceClass = 0x00U, .bDeviceSubClass = 0x00U, @@ -80,15 +82,15 @@ __ALIGN_BEGIN const usb_desc_dev printer_dev_desc __ALIGN_END = }; /* USB device configuration descriptor */ -__ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END = +__ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END = { - .config = + .config = { .header = - { - .bLength = sizeof(usb_desc_config), - .bDescriptorType = USB_DESCTYPE_CONFIG - }, + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, .wTotalLength = USB_PRINTER_CONFIG_DESC_LEN, .bNumInterfaces = 0x01U, .bConfigurationValue = 0x01U, @@ -100,10 +102,10 @@ __ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END .printer_itf = { .header = - { - .bLength = sizeof(usb_desc_itf), - .bDescriptorType = USB_DESCTYPE_ITF - }, + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, .bInterfaceNumber = 0x00U, .bAlternateSetting = 0x00U, .bNumEndpoints = 0x02U, @@ -116,10 +118,10 @@ __ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END .printer_epin = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = PRINTER_IN_EP, .bmAttributes = USB_EP_ATTR_BULK, .wMaxPacketSize = PRINTER_IN_PACKET, @@ -129,10 +131,10 @@ __ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END .printer_epout = { .header = - { - .bLength = sizeof(usb_desc_ep), - .bDescriptorType = USB_DESCTYPE_EP - }, + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, .bEndpointAddress = PRINTER_OUT_EP, .bmAttributes = USB_EP_ATTR_BULK, .wMaxPacketSize = PRINTER_OUT_PACKET, @@ -141,50 +143,50 @@ __ALIGN_BEGIN const usb_printer_desc_config_set printer_config_desc __ALIGN_END }; /* USB language ID Descriptor */ -static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { - .header = - { - .bLength = sizeof(usb_desc_LANGID), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR, + }, .wLANGID = ENG_LANGID }; /* USB manufacture string */ -static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(10U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} }; /* USB product string */ -static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(16U), - .bDescriptorType = USB_DESCTYPE_STR, - }, + .header = + { + .bLength = USB_STRING_LEN(16U), + .bDescriptorType = USB_DESCTYPE_STR, + }, .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'P', 'r', 'i', 'n', 't', 'e', 'r'} }; /* USBD serial string */ -static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { - .header = - { - .bLength = USB_STRING_LEN(12U), - .bDescriptorType = USB_DESCTYPE_STR, - } + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } }; /* USB string descriptor */ -static void *const usbd_msc_strings[] = +static void *const usbd_msc_strings[] = { [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, @@ -217,17 +219,17 @@ usb_class_core usbd_printer_cb = { /*! \brief initialize the printer device - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[in] config_index: configuration index \param[out] none - \retval USB device operation status + \retval usb device operation status */ static uint8_t printer_init (usb_dev *udev, uint8_t config_index) { - /* initialize the data TX endpoint */ + /* initialize the data Tx endpoint */ usbd_ep_setup (udev, &(printer_config_desc.printer_epin)); - /* initialize the data RX endpoint */ + /* initialize the data Rx endpoint */ usbd_ep_setup (udev, &(printer_config_desc.printer_epout)); /* prepare to receive data */ @@ -238,14 +240,14 @@ static uint8_t printer_init (usb_dev *udev, uint8_t config_index) /*! \brief deinitialize the printer device - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[in] config_index: configuration index \param[out] none - \retval USB device operation status + \retval usb device operation status */ static uint8_t printer_deinit (usb_dev *udev, uint8_t config_index) { - /* deinitialize the data TX/RX endpoint */ + /* deinitialize the data Tx/Rx endpoint */ usbd_ep_clear (udev, PRINTER_IN_EP); usbd_ep_clear (udev, PRINTER_OUT_EP); @@ -254,10 +256,10 @@ static uint8_t printer_deinit (usb_dev *udev, uint8_t config_index) /*! \brief handle the printer class-specific requests - \param[in] udev: pointer to USB device instance + \param[in] udev: pointer to usb device instance \param[in] req: device class-specific request \param[out] none - \retval USB device operation status + \retval usb device operation status */ static uint8_t printer_req(usb_dev *udev, usb_req *req) { @@ -292,9 +294,9 @@ static uint8_t printer_req(usb_dev *udev, usb_req *req) \param[out] none \retval USB device operation status */ -static uint8_t printer_in (usb_dev *udev, uint8_t ep_num) +static uint8_t printer_in (usb_dev *udev, uint8_t ep_num) { - return USBD_OK; + return USBD_OK; } /*! @@ -304,7 +306,7 @@ static uint8_t printer_in (usb_dev *udev, uint8_t ep_num) \param[out] none \retval USB device operation status */ -static uint8_t printer_out (usb_dev *udev, uint8_t ep_num) +static uint8_t printer_out (usb_dev *udev, uint8_t ep_num) { - return USBD_OK; + return USBD_OK; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_core.h index 8446487b1d..d037bdc310 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_core.h @@ -1,34 +1,36 @@ /*! \file usbd_core.h - \brief USB device mode core functions protype + \brief USB device mode core functions prototype \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,7 +44,7 @@ typedef enum { USBD_OK = 0U, /*!< status OK */ USBD_BUSY, /*!< status busy */ - USBD_FAIL, /*!< status fail */ + USBD_FAIL /*!< status fail */ } usbd_status; enum _usbd_status { diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_enum.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_enum.h index ffa7f0ca93..d3bf1fa712 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_enum.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_enum.h @@ -3,32 +3,34 @@ \brief USB enumeration definitions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -57,11 +59,7 @@ enum _str_index STR_IDX_SERIAL = 0x3U, /* serial string index */ STR_IDX_CONFIG = 0x4U, /* configuration string index */ STR_IDX_ITF = 0x5U, /* interface string index */ -#ifndef WINUSB_EXEMPT_DRIVER - STR_IDX_MAX = 0x6U, /* string maximum index */ -#else STR_IDX_MAX = 0xEFU, /* string maximum index */ -#endif /* WINUSB_EXEMPT_DRIVER */ }; typedef enum _usb_pwrsta { diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_transc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_transc.h index 014ea34aee..9c620ff77f 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_transc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Include/usbd_transc.h @@ -3,32 +3,34 @@ \brief USB transaction core functions prototype \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_core.c index 065dd3ad15..823f8a7990 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_core.c @@ -3,32 +3,34 @@ \brief USB device mode core functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -76,7 +78,7 @@ void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_c #ifndef USE_OTG_MODE usb_curmode_set(&udev->regs, DEVICE_MODE); -#endif +#endif /* USE_OTG_MODE */ /* initializes device mode */ (void)usb_devcore_init (udev); diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_enum.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_enum.c index 21094d5df4..3358149a69 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_enum.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_enum.c @@ -3,32 +3,34 @@ \brief USB enumeration function \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,22 +44,26 @@ extern usbd_status usbd_OEM_req(usb_dev *udev, usb_req *req); #endif /* WINUSB_EXEMPT_DRIVER */ /* local function prototypes ('static') */ -static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req); -static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); -static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); -static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); -static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); -static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req); -static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req); +static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) +static uint8_t* _usb_other_speed_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_qualifier_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +#endif +static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req); static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = { @@ -78,9 +84,13 @@ static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = /* get standard descriptor handler */ static uint8_t* (*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len) = { - [(uint8_t)USB_DESCTYPE_DEV - 1U] = _usb_dev_desc_get, - [(uint8_t)USB_DESCTYPE_CONFIG - 1U] = _usb_config_desc_get, - [(uint8_t)USB_DESCTYPE_STR - 1U] = _usb_str_desc_get + [(uint8_t)USB_DESCTYPE_DEV - 1U] = _usb_dev_desc_get, + [(uint8_t)USB_DESCTYPE_CONFIG - 1U] = _usb_config_desc_get, + [(uint8_t)USB_DESCTYPE_STR - 1U] = _usb_str_desc_get, +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + [(uint8_t)USB_DESCTYPE_DEV_QUALIFIER - 3U] = _usb_qualifier_desc_get, + [(uint8_t)USB_DESCTYPE_OTHER_SPD_CONFIG - 3U] = _usb_other_speed_config_desc_get, +#endif }; /*! @@ -167,7 +177,7 @@ void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len) if ((value >> 28U) < 0x0AU) { pbuf[2U * index] = (uint8_t)((value >> 28U) + '0'); } else { - pbuf[2U * index] = (uint8_t)((value >> 28U) + 'A' - 10U); + pbuf[2U * index] = (uint8_t)((value >> 28U) + 'A' - 10U); } value = value << 4U; @@ -252,11 +262,47 @@ static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint { (void)index; - *len = udev->dev.desc->config_desc[2]; + *len = udev->dev.desc->config_desc[2] | (udev->dev.desc->config_desc[3]<< 8U); return udev->dev.desc->config_desc; } +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + +/*! + \brief get the other speed configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_other_speed_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->other_speed_config_desc[2]; + + return udev->dev.desc->other_speed_config_desc; +} + +/*! + \brief get the other speed configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_qualifier_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->qualifier_desc[0]; + + return udev->dev.desc->qualifier_desc; +} + +#endif /* USE_USB_HS && USE_ULPI_PHY */ + /*! \brief get the BOS descriptor \brief[in] udev: pointer to USB device instance @@ -525,8 +571,18 @@ static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req) case USB_DESCTYPE_ITF: case USB_DESCTYPE_EP: + break; + +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) case USB_DESCTYPE_DEV_QUALIFIER: + transc->xfer_buf = std_desc_get[desc_type - 3U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + case USB_DESCTYPE_OTHER_SPD_CONFIG: + transc->xfer_buf = std_desc_get[desc_type - 3U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; +#endif + case USB_DESCTYPE_ITF_POWER: break; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_transc.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_transc.c index a4349ee3a1..a076977308 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_transc.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/device/core/Source/usbd_transc.c @@ -3,32 +3,34 @@ \brief USB transaction core functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -186,8 +188,8 @@ uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num) case USB_CTL_LAST_DATA_OUT: if (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { - if (udev->dev.class_core->data_out != NULL) { - (void)udev->dev.class_core->data_out (udev, 0U); + if (udev->dev.class_core->ctlx_out != NULL) { + (void)udev->dev.class_core->ctlx_out (udev); } } @@ -240,8 +242,8 @@ uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num) udev->dev.control.ctl_zlp = 0U; } else { if (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { - if (udev->dev.class_core->data_in != NULL) { - (void)udev->dev.class_core->data_in (udev, 0U); + if (udev->dev.class_core->ctlx_in != NULL) { + (void)udev->dev.class_core->ctlx_in (udev); } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h index daefca3de5..65c3dbf81e 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h @@ -3,32 +3,34 @@ \brief USB core low level driver header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -105,6 +107,11 @@ typedef struct _usb_desc { uint8_t *config_desc; /*!< configure descriptor */ uint8_t *bos_desc; /*!< BOS descriptor */ +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) + uint8_t *other_speed_config_desc; /*!< other speed configuration descriptor */ + uint8_t *qualifier_desc; /*!< qualifier descriptor */ +#endif + void* const *strings; /*!< string descriptor */ } usb_desc; @@ -162,6 +169,9 @@ typedef struct _usb_class_core uint8_t (*set_intf) (usb_dev *udev, usb_req *req); /*!< device set interface callback */ + uint8_t (*ctlx_in) (usb_dev *udev); /*!< device contrl in callback */ + uint8_t (*ctlx_out) (usb_dev *udev); + uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ @@ -232,8 +242,9 @@ typedef struct _usb_pipe uint16_t mps; } ep; - uint8_t ping; - uint32_t DPID; + __IO uint8_t supp_ping; + __IO uint8_t do_ping; + __IO uint32_t DPID; uint8_t *xfer_buf; uint32_t xfer_len; @@ -251,7 +262,7 @@ typedef struct _usb_host_drv { __IO uint32_t connect_status; __IO uint32_t port_enabled; - __IO uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; + uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; usb_pipe pipe[USBFS_MAX_TX_FIFOS]; void *data; @@ -283,7 +294,11 @@ typedef struct _usb_core_driver */ __STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs) { - return usb_regs->gr->GINTEN & usb_regs->gr->GINTF; + uint32_t reg_data = usb_regs->gr->GINTEN; + + reg_data &= usb_regs->gr->GINTF; + + return reg_data; } /*! @@ -327,13 +342,13 @@ __STATIC_INLINE void usb_globalint_disable(usb_core_regs *usb_regs) usb_status usb_basic_init (usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core); /* initializes the USB controller registers and prepares the core device mode or host mode operation */ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs); -/* write a packet into the TX FIFO associated with the endpoint */ +/* write a packet into the Tx FIFO associated with the endpoint */ usb_status usb_txfifo_write (usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count); -/* read a packet from the RX FIFO associated with the endpoint */ +/* read a packet from the Rx FIFO associated with the endpoint */ void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count); -/* flush a TX FIFO or all TX FIFOs */ +/* flush a Tx FIFO or all Tx FIFOs */ usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num); -/* flush the entire RX FIFO */ +/* flush the entire Rx FIFO */ usb_status usb_rxfifo_flush (usb_core_regs *usb_regs); /* set endpoint or channel TX FIFO size */ void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size); diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h index 8c0431bc1f..c187e8693f 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h @@ -3,32 +3,34 @@ \brief USB device low level driver header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -130,7 +132,7 @@ __STATIC_INLINE uint32_t usb_iepintnum_read (usb_core_driver *udev) uint32_t value = udev->regs.dr->DAEPINT; value &= udev->regs.dr->DAEPINTEN; - + return value & DAEPINT_IEPITB; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h index 55ac908d52..53c5183eef 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h @@ -3,32 +3,34 @@ \brief USB host mode low level driver header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -120,4 +122,4 @@ usb_status usb_pipe_ping (usb_core_driver *udev, uint8_t pipe_num); /* stop the USB host and clean up FIFO */ void usb_host_stop (usb_core_driver *udev); -#endif /* __DRV_USB_HOST_H */ +#endif /* __DRV_USB_HOST_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h index 725a8d48b0..ff65e2bd9c 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h @@ -3,32 +3,34 @@ \brief usb hardware configuration header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -52,20 +54,11 @@ void usb_udelay (const uint32_t usec); void usb_mdelay (const uint32_t msec); /* configures system clock after wakeup from STOP mode */ void system_clk_config_stop(void); - -/* configure the CTC peripheral */ -#ifdef USE_IRC48M - void ctc_config(void); -#endif /* USE_IRC48M */ - #ifdef USE_HOST_MODE - void systick_config(void); - - /* configure USB VBus */ - void usb_vbus_config (void); - - /* drive USB VBus */ - void usb_vbus_drive (uint8_t State); +/* configure USB VBus */ +void usb_vbus_config (void); +/* drive USB VBus */ +void usb_vbus_drive (uint8_t State); #endif /* USE_HOST_MODE */ #endif /* __DRV_USB_HW_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h index 9620357a5a..ae93df8185 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h @@ -3,32 +3,34 @@ \brief USB cell registers definition and handle macros \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -302,9 +304,7 @@ typedef struct _usb_regs #define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ #define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ -/** - * @brief USB IN endpoint 0 transmit FIFO length register bits definitions - */ +/* USB IN endpoint 0 transmit FIFO length register bits definitions */ #define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ #define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ @@ -356,7 +356,6 @@ typedef struct _usb_regs #define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - #define TFQSTAT_TXFS BITS(0, 15) #define TFQSTAT_CNUM BITS(27, 30) @@ -432,12 +431,11 @@ typedef struct _usb_regs /* host channel-x DMA address register bits definitions */ #define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ +#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ -#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ - -#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ -#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ -#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ +#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ +#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ +#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ #define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ #define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ @@ -621,13 +619,13 @@ extern const uint32_t PIPE_DPID[2]; #define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ #define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ -#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ #define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ #define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ #define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ -#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ #define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ #define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ @@ -658,5 +656,9 @@ extern const uint32_t PIPE_DPID[2]; #define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */ #define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */ #define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */ +#define EP4_OUT ((uint8_t)0x04) /*!< endpoint out 4 */ +#define EP4_IN ((uint8_t)0x84) /*!< endpoint in 4 */ +#define EP5_OUT ((uint8_t)0x05) /*!< endpoint out 5 */ +#define EP5_IN ((uint8_t)0x85) /*!< endpoint in 5 */ #endif /* __DRV_USB_REGS_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h index dc4a70cc8d..eb79e15d27 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h @@ -3,32 +3,34 @@ \brief USB device mode interrupt header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h index d42146e46d..99a606dad7 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h @@ -3,32 +3,34 @@ \brief USB host mode interrupt management header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -38,16 +40,14 @@ OF SUCH DAMAGE. #include "drv_usb_host.h" #include "usbh_core.h" -typedef struct _usbh_int_cb +typedef struct _usbh_ev_cb { uint8_t (*connect) (usbh_host *uhost); uint8_t (*disconnect) (usbh_host *uhost); - uint8_t (*port_enabled) (usbh_host *uhost); - uint8_t (*port_disabled) (usbh_host *uhost); uint8_t (*SOF) (usbh_host *uhost); -} usbh_int_cb; +} usbh_ev_cb; -extern usbh_int_cb *usbh_int_fop; +extern usbh_ev_cb *usbh_int_fop; /* function declarations */ /* handle global host interrupt */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c index 50c1544214..ba9ee199b2 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c @@ -3,32 +3,34 @@ \brief USB core driver which can operate in host and device mode \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -39,15 +41,15 @@ OF SUCH DAMAGE. static void usb_core_reset (usb_core_regs *usb_regs); /*! - \brief configure USB core basic + \brief configure USB core basic \param[in] usb_basic: pointer to USB capabilities \param[in] usb_regs: USB core registers \param[in] usb_core: USB core \param[out] none \retval operation status */ -usb_status usb_basic_init (usb_core_basic *usb_basic, - usb_core_regs *usb_regs, +usb_status usb_basic_init (usb_core_basic *usb_basic, + usb_core_regs *usb_regs, usb_core_enum usb_core) { /* configure USB default transfer mode as FIFO mode */ @@ -77,6 +79,12 @@ usb_status usb_basic_init (usb_core_basic *usb_basic, #ifdef USB_HS_INTERNAL_DMA_ENABLED usb_basic->transfer_mode = USB_USE_DMA; #endif /* USB_HS_INTERNAL_DMA_ENABLED */ + +#ifdef USB_HS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBHS_SOF_OUTPUT; + usb_basic->low_power = USBHS_LOW_POWER; +#endif /* USB_HS_CORE */ break; case USB_CORE_ENUM_FS: @@ -90,15 +98,18 @@ usb_status usb_basic_init (usb_core_basic *usb_basic, /* USBFS core use embedded physical layer */ usb_basic->phy_itf = USB_EMBEDDED_PHY; + +#ifdef USB_FS_CORE + /* configure the SOF output and the low power support */ + usb_basic->sof_enable = USBFS_SOF_OUTPUT; + usb_basic->low_power = USBFS_LOW_POWER; +#endif /* USB_FS_CORE */ break; default: return USB_FAIL; } - usb_basic->sof_enable = USB_SOF_OUTPUT; - usb_basic->low_power = USB_LOW_POWER; - /* assign main registers address */ *usb_regs = (usb_core_regs) { .gr = (usb_gr*) (usb_basic->base_reg + USB_REG_OFFSET_CORE), @@ -131,7 +142,7 @@ usb_status usb_basic_init (usb_core_basic *usb_basic, } /*! - \brief initializes the USB controller registers and + \brief initializes the USB controller registers and prepares the core device mode or host mode operation \param[in] usb_basic: pointer to USB capabilities \param[in] usb_regs: pointer to USB core registers @@ -195,7 +206,7 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) usb_regs->gr->GINTF = 0xBFFFFFFFU; usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \ - GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; #endif /* USE_OTG_MODE */ @@ -203,17 +214,17 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) } /*! - \brief write a packet into the TX FIFO associated with the endpoint + \brief write a packet into the Tx FIFO associated with the endpoint \param[in] usb_regs: pointer to USB core registers \param[in] src_buf: pointer to source buffer - \param[in] fifo_num: FIFO number which is in (0..3) + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) \param[in] byte_count: packet byte count \param[out] none \retval operation status */ -usb_status usb_txfifo_write (usb_core_regs *usb_regs, - uint8_t *src_buf, - uint8_t fifo_num, +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, uint16_t byte_count) { uint32_t word_count = (byte_count + 3U) / 4U; @@ -253,9 +264,9 @@ void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte } /*! - \brief flush a TX FIFO or all TX FIFOs + \brief flush a Tx FIFO or all Tx FIFOs \param[in] usb_regs: pointer to USB core registers - \param[in] fifo_num: FIFO number which is in (0..3) + \param[in] fifo_num: FIFO number which is in (0..3 or 0..5) \param[out] none \retval operation status */ @@ -263,7 +274,7 @@ usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num) { usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; - /* wait for TX FIFO flush bit is set */ + /* wait for Tx FIFO flush bit is set */ while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) { /* no operation */ } @@ -284,7 +295,7 @@ usb_status usb_rxfifo_flush (usb_core_regs *usb_regs) { usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; - /* wait for RX FIFO flush bit is set */ + /* wait for Rx FIFO flush bit is set */ while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) { /* no operation */ } @@ -309,7 +320,7 @@ void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size) tx_offset = usb_regs->gr->GRFLEN; - if (fifo == 0U) { + if(0U == fifo) { usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16) | tx_offset; } else { tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c index 3f6a52a3c4..11bfab7e58 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c @@ -3,32 +3,34 @@ \brief USB device mode low level driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -47,7 +49,7 @@ static const uint8_t EP0_MAXLEN[4] = { #ifdef USB_FS_CORE /* USB endpoint Tx FIFO size */ -static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = { (uint16_t)TX0_FIFO_FS_SIZE, (uint16_t)TX1_FIFO_FS_SIZE, @@ -59,7 +61,7 @@ static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = #ifdef USB_HS_CORE -uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = +uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = { (uint16_t)TX0_FIFO_HS_SIZE, (uint16_t)TX1_FIFO_HS_SIZE, @@ -98,7 +100,7 @@ usb_status usb_devcore_init (usb_core_driver *udev) /* set Rx FIFO size */ usb_set_rxfifo(&udev->regs, RX_FIFO_FS_SIZE); - /* set endpoint 0 to 3's TX FIFO length and RAM address */ + /* set endpoint 0 to 3's Tx FIFO length and RAM address */ for (i = 0U; i < USBFS_MAX_EP_COUNT; i++) { usb_set_txfifo(&udev->regs, i, USBFS_TX_FIFO_SIZE[i]); } @@ -125,10 +127,10 @@ usb_status usb_devcore_init (usb_core_driver *udev) /* make sure all FIFOs are flushed */ - /* flush all TX FIFOs */ + /* flush all Tx FIFOs */ (void)usb_txfifo_flush (&udev->regs, 0x10U); - /* flush entire RX FIFO */ + /* flush entire Rx FIFO */ (void)usb_rxfifo_flush (&udev->regs); /* clear all pending device interrupts */ @@ -213,6 +215,8 @@ usb_status usb_devint_enable (usb_core_driver *udev) usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) { __IO uint32_t *reg_addr = NULL; + + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; /* get the endpoint number */ uint8_t ep_num = transc->ep_addr.num; @@ -229,11 +233,10 @@ usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) } /* endpoint 0 is activated after USB clock is enabled */ - *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); /* set endpoint 0 maximum packet length */ - *reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES]; + *reg_addr |= EP0_MAXLEN[enum_speed]; /* activate endpoint */ *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; @@ -251,7 +254,8 @@ usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) { __IO uint32_t *reg_addr = NULL; - __IO uint32_t epinten = 0U; + uint32_t epinten = 0U; + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; /* get the endpoint number */ uint8_t ep_num = transc->ep_addr.num; @@ -273,7 +277,7 @@ usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) /* set endpoint maximum packet length */ if (0U == ep_num) { - *reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES]; + *reg_addr |= EP0_MAXLEN[enum_speed]; } else { *reg_addr |= transc->max_len; } @@ -394,10 +398,8 @@ usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc) udev->regs.er_in[ep_num]->DIEPCTL = epctl; if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { - udev->regs.er_in[ep_num]->DIEPCTL = epctl; - if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) { - /* enable the TX FIFO empty interrupt for this endpoint */ + /* enable the Tx FIFO empty interrupt for this endpoint */ if (transc->xfer_len > 0U) { udev->regs.dr->DIEPFEINTEN |= 1U << ep_num; } @@ -631,7 +633,7 @@ void usb_dev_suspend (usb_core_driver *udev) *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER,PMU_LOWDRIVER_DISABLE,WFI_CMD); } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c index c47abac6c7..ab82a5ff03 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c @@ -3,32 +3,34 @@ \brief USB host mode low level driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -59,7 +61,7 @@ usb_status usb_host_init (usb_core_driver *udev) /* initialize host configuration register */ if (USB_ULPI_PHY == udev->bp.phy_itf) { - usb_phyclock_config (udev, HCTL_30_60MHZ); + usb_phyclock_config (udev, HCTL_30_60MHZ); } else { usb_phyclock_config (udev, HCTL_48MHZ); } @@ -73,12 +75,12 @@ usb_status usb_host_init (usb_core_driver *udev) /* set Rx FIFO size */ udev->regs.gr->GRFLEN = USB_RX_FIFO_FS_SIZE; - /* set non-periodic TX FIFO size and address */ + /* set non-periodic Tx FIFO size and address */ nptxfifolen |= USB_RX_FIFO_FS_SIZE; nptxfifolen |= USB_HTX_NPFIFO_FS_SIZE << 16U; udev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; - /* set periodic TX FIFO size and address */ + /* set periodic Tx FIFO size and address */ ptxfifolen |= USB_RX_FIFO_FS_SIZE + USB_HTX_NPFIFO_FS_SIZE; ptxfifolen |= USB_HTX_PFIFO_FS_SIZE << 16U; udev->regs.gr->HPTFLEN = ptxfifolen; @@ -111,7 +113,7 @@ usb_status usb_host_init (usb_core_driver *udev) /* make sure the FIFOs are flushed */ - /* flush all TX FIFOs in device or host mode */ + /* flush all Tx FIFOs in device or host mode */ usb_txfifo_flush (&udev->regs, 0x10U); /* flush the entire Rx FIFO */ @@ -240,9 +242,8 @@ usb_status usb_pipe_init (usb_core_driver *udev, uint8_t pipe_num) | HCHINTEN_DTERIE | HCHINTEN_NAKIE; if (!pp->ep.dir) { - pp_inten |= HCHINTEN_NYETIE; - - if (pp->ping) { + if (PORT_SPEED_HIGH == pp->dev_speed) { + pp_inten |= HCHINTEN_NYETIE; pp_inten |= HCHINTEN_ACKIE; } } @@ -376,7 +377,7 @@ usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num) break; } - /* write packet into the TX fifo. */ + /* write packet into the Tx fifo. */ usb_txfifo_write (&udev->regs, pp->xfer_buf, pipe_num, (uint16_t)pp->xfer_len); } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c index 04844af1aa..f22e79507e 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c @@ -3,32 +3,34 @@ \brief USB device mode interrupt routines \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -36,13 +38,13 @@ OF SUCH DAMAGE. #include "drv_usbd_int.h" #include "usbd_transc.h" +/* local function prototypes ('static') */ static uint32_t usbd_int_epout (usb_core_driver *udev); static uint32_t usbd_int_epin (usb_core_driver *udev); static uint32_t usbd_int_rxfifo (usb_core_driver *udev); static uint32_t usbd_int_reset (usb_core_driver *udev); static uint32_t usbd_int_enumfinish (usb_core_driver *udev); static uint32_t usbd_int_suspend (usb_core_driver *udev); - static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num); static const uint8_t USB_SPEED[4] = { @@ -61,7 +63,8 @@ static const uint8_t USB_SPEED[4] = { void usbd_isr (usb_core_driver *udev) { if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) { - uint32_t intr = udev->regs.gr->GINTF & udev->regs.gr->GINTEN; + uint32_t intr = udev->regs.gr->GINTF; + intr &= udev->regs.gr->GINTEN; /* there are no interrupts, avoid spurious interrupt */ if (!intr) { @@ -228,7 +231,7 @@ uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev) return 1; } -#endif +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ /*! \brief indicates that an OUT endpoint has a pending interrupt @@ -347,20 +350,20 @@ static uint32_t usbd_int_rxfifo (usb_core_driver *udev) bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4U; data_PID = (uint8_t)((devrxstat & GRSTATRP_DPID) >> 15U); -#ifdef USE_USB_HS +#if defined(USE_USB_HS) && defined(USE_ULPI_PHY) #ifndef USE_450Z_EVAL - /* ensure no-DMA mode can work */ - if ((1U == ep_num) && (0U == (udev->regs.er_out[ep_num]->DOEPLEN & DEPLEN_PCNT))) { - uint32_t devepctl = udev->regs.er_out[ep_num]->DOEPCTL; + /* ensure no-DMA mode can work */ + if (0U == (udev->regs.er_out[ep_num]->DOEPLEN & DEPLEN_PCNT)) { + uint32_t devepctl = udev->regs.er_out[ep_num]->DOEPCTL; - devepctl |= DEPCTL_SNAK; - devepctl &= ~DEPCTL_EPEN; - devepctl &= ~DEPCTL_EPD; + devepctl |= DEPCTL_SNAK; + devepctl &= ~DEPCTL_EPEN; + devepctl &= ~DEPCTL_EPD; - udev->regs.er_out[ep_num]->DOEPCTL = devepctl; - } + udev->regs.er_out[ep_num]->DOEPCTL = devepctl; + } #endif /* USE_450Z_EVAL */ -#endif /* USE_USB_HS */ +#endif /* USE_USB_HS && USE_ULPI_PHY */ switch ((devrxstat & GRSTATRP_RPCKST) >> 17U) { case RSTAT_GOUT_NAK: @@ -415,7 +418,7 @@ static uint32_t usbd_int_reset (usb_core_driver *udev) /* clear the remote wakeup signaling */ udev->regs.dr->DCTL &= ~DCTL_RWKUP; - /* flush the TX FIFO */ + /* flush the Tx FIFO */ (void)usb_txfifo_flush (&udev->regs, 0U); for (i = 0U; i < udev->bp.num_ep; i++) { @@ -434,14 +437,14 @@ static uint32_t usbd_int_reset (usb_core_driver *udev) #ifdef USB_HS_DEDICATED_EP1_ENABLED udev->regs.dr->DOEP1INTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; -#endif +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ /* enable IN endpoint interrupts */ udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN; #ifdef USB_HS_DEDICATED_EP1_ENABLED udev->regs.dr->DIEP1INTEN = DIEPINTEN_TFEN; -#endif +#endif /* USB_HS_DEDICATED_EP1_ENABLED */ /* reset device address */ udev->regs.dr->DCFG &= ~DCFG_DAR; @@ -518,7 +521,7 @@ static uint32_t usbd_int_suspend (usb_core_driver *udev) { __IO uint8_t low_power = udev->bp.low_power; __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST); - __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)? 1U : 0U; + __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) ? 1U : 0U; udev->dev.backup_status = udev->dev.cur_status; udev->dev.cur_status = (uint8_t)USBD_SUSPENDED; @@ -528,7 +531,7 @@ static uint32_t usbd_int_suspend (usb_core_driver *udev) *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); } /* clear interrupt */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c index 2bde1469a0..b4358ea9bc 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c @@ -3,45 +3,44 @@ \brief USB host mode interrupt handler file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "drv_usb_core.h" -#include "drv_usb_host.h" #include "drv_usbh_int.h" -#include "usbh_core.h" #if defined (__CC_ARM) /*!< ARM compiler */ #pragma O0 #elif defined (__GNUC__) /*!< GNU compiler */ #pragma GCC optimize ("O0") -#elif defined (__TASKING__) /*!< TASKING compiler */ +#elif defined (__TASKING__) /*!< TASKING compiler */ #pragma optimize=0 #endif /* __CC_ARM */ @@ -138,8 +137,8 @@ uint32_t usbh_isr (usb_core_driver *udev) \param[out] none \retval none */ -static inline void usb_pp_halt (usb_core_driver *udev, - uint8_t pp_num, +static inline void usb_pp_halt (usb_core_driver *udev, + uint8_t pp_num, uint32_t pp_int, usb_pipe_staus pp_status) { @@ -206,20 +205,22 @@ static uint32_t usbh_int_port (usb_core_driver *udev) udev->regs.hr->HFT = 48000U; if (HCTL_48MHZ != clock_type) { - usb_phyclock_config (udev, HCTL_48MHZ); - } + if (USB_EMBEDDED_PHY == udev->bp.phy_itf) { + usb_phyclock_config (udev, HCTL_48MHZ); + } - port_reset = 1U; + port_reset = 1U; + } } else { /* for high speed device and others */ port_reset = 1U; } - usbh_int_fop->port_enabled(udev->host.data); + udev->host.port_enabled = 1; udev->regs.gr->GINTEN |= GINTEN_DISCIE | GINTEN_SOFIE; } else { - usbh_int_fop->port_disabled(udev->host.data); + udev->host.port_enabled = 0; } } @@ -273,7 +274,8 @@ static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num) usb_pipe *pp = &udev->host.pipe[pp_num]; - __IO uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; + uint32_t intr_pp = pp_reg->HCHINTF; + intr_pp &= pp_reg->HCHINTEN; uint8_t ep_type = (uint8_t)((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U); @@ -400,16 +402,17 @@ static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num) #endif /* __ICCARM */ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) { + usbh_host *uhost = udev->host.data; usb_pr *pp_reg = udev->regs.pr[pp_num]; - usb_pipe *pp = &udev->host.pipe[pp_num]; - - uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; + uint32_t intr_pp = pp_reg->HCHINTF; + intr_pp &= pp_reg->HCHINTEN; if (intr_pp & HCHINTF_ACK) { - if (URB_PING == pp->urb_state) { + if (1U == udev->host.pipe[pp_num].do_ping) { + udev->host.pipe[pp_num].do_ping = 0; pp->err_count = 0U; - usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_TF, PIPE_XF); + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_ACK, pp->pp_status); } pp_reg->HCHINTF = HCHINTF_ACK; @@ -424,14 +427,31 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) pp->err_count = 0U; usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_TF, PIPE_XF); } else if (intr_pp & HCHINTF_NAK) { + if (0U == udev->host.pipe[pp_num].do_ping) { + if (1U == udev->host.pipe[pp_num].supp_ping) { + udev->host.pipe[pp_num].do_ping = 1; + } + } + pp->err_count = 0U; usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK); } else if (intr_pp & HCHINTF_USBER) { pp->err_count++; usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR); } else if (intr_pp & HCHINTF_NYET) { + if (CTL_STATUS_OUT != uhost->control.ctl_state) { + if (0U == udev->host.pipe[pp_num].do_ping) { + if (1U == udev->host.pipe[pp_num].supp_ping) { + udev->host.pipe[pp_num].do_ping = 1; + } + } + + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_NYET); + } else { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_XF); + } + pp->err_count = 0U; - usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_NYET); } else if (intr_pp & HCHINTF_CH) { udev->regs.pr[pp_num]->HCHINTEN &= ~HCHINTEN_CHIE; @@ -440,27 +460,13 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) pp->urb_state = URB_DONE; if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) { - pp->data_toggle_out ^= 1U; + pp->data_toggle_out ^= 1U; } break; case PIPE_NAK: - - if (URB_PING == pp->urb_state) { - (void)usb_pipe_ping (udev, (uint8_t)pp_num); - } else { - pp->urb_state = URB_NOTREADY; - } - break; - case PIPE_NYET: - if (1U == udev->host.pipe[pp_num].ping) { - (void)usb_pipe_ping (udev, (uint8_t)pp_num); - pp->urb_state = URB_PING; - } - else { - pp->urb_state = URB_NOTREADY; - } + pp->urb_state = URB_NOTREADY; break; case PIPE_STALL: @@ -502,7 +508,7 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) #endif /* __ICCARM */ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev) { - uint32_t count = 0U; + uint32_t count = 0U, xfer_count = 0U; __IO uint8_t pp_num = 0U; __IO uint32_t rx_stat = 0U; @@ -524,12 +530,14 @@ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev) /* manage multiple transfer packet */ udev->host.pipe[pp_num].xfer_buf += count; udev->host.pipe[pp_num].xfer_count += count; + + xfer_count = udev->host.pipe[pp_num].xfer_count; - udev->host.backup_xfercount[pp_num] = udev->host.pipe[pp_num].xfer_count; + udev->host.backup_xfercount[pp_num] = xfer_count; if (udev->regs.pr[pp_num]->HCHLEN & HCHLEN_PCNT) { /* re-activate the channel when more packets are expected */ - __IO uint32_t pp_ctl = udev->regs.pr[pp_num]->HCHCTL; + uint32_t pp_ctl = udev->regs.pr[pp_num]->HCHCTL; pp_ctl |= HCHCTL_CEN; pp_ctl &= ~HCHCTL_CDIS; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Include/usbh_hid_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Include/usbh_hid_core.h index 610af2e0c5..c386f7c8f9 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Include/usbh_hid_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Include/usbh_hid_core.h @@ -3,32 +3,34 @@ \brief header file for the usbh_hid_core.c \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,47 +43,8 @@ OF SUCH DAMAGE. #define HID_MIN_POLL 10U #define HID_REPORT_SIZE 16U -#define HID_MAX_USAGE 10U -#define HID_MAX_NBR_REPORT_FMT 10U #define HID_QUEUE_SIZE 10U -#define HID_ITEM_LONG 0xFEU - -#define HID_ITEM_TYPE_MAIN 0x00U -#define HID_ITEM_TYPE_GLOBAL 0x01U -#define HID_ITEM_TYPE_LOCAL 0x02U -#define HID_ITEM_TYPE_RESERVED 0x03U - -#define HID_MAIN_ITEM_TAG_INPUT 0x08U -#define HID_MAIN_ITEM_TAG_OUTPUT 0x09U -#define HID_MAIN_ITEM_TAG_COLLECTION 0x0AU -#define HID_MAIN_ITEM_TAG_FEATURE 0x0BU -#define HID_MAIN_ITEM_TAG_ENDCOLLECTION 0x0CU - -#define HID_GLOBAL_ITEM_TAG_USAGE_PAGE 0x00U -#define HID_GLOBAL_ITEM_TAG_LOG_MIN 0x01U -#define HID_GLOBAL_ITEM_TAG_LOG_MAX 0x02U -#define HID_GLOBAL_ITEM_TAG_PHY_MIN 0x03U -#define HID_GLOBAL_ITEM_TAG_PHY_MAX 0x04U -#define HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT 0x05U -#define HID_GLOBAL_ITEM_TAG_UNIT 0x06U -#define HID_GLOBAL_ITEM_TAG_REPORT_SIZE 0x07U -#define HID_GLOBAL_ITEM_TAG_REPORT_ID 0x08U -#define HID_GLOBAL_ITEM_TAG_REPORT_COUNT 0x09U -#define HID_GLOBAL_ITEM_TAG_PUSH 0x0AU -#define HID_GLOBAL_ITEM_TAG_POP 0x0BU - -#define HID_LOCAL_ITEM_TAG_USAGE 0x00U -#define HID_LOCAL_ITEM_TAG_USAGE_MIN 0x01U -#define HID_LOCAL_ITEM_TAG_USAGE_MAX 0x02U -#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 0x03U -#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MIN 0x04U -#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAX 0x05U -#define HID_LOCAL_ITEM_TAG_STRING_INDEX 0x07U -#define HID_LOCAL_ITEM_TAG_STRING_MIN 0x08U -#define HID_LOCAL_ITEM_TAG_STRING_MAX 0x09U -#define HID_LOCAL_ITEM_TAG_DELIMITER 0x0AU - #define USB_HID_DESC_SIZE 9U /* states for HID state machine */ @@ -113,51 +76,6 @@ typedef enum HID_UNKNOWN = 0xFFU, } hid_type; -typedef struct _hid_report_data -{ - uint8_t ReportID; - uint8_t ReportType; - uint16_t UsagePage; - uint32_t Usage[HID_MAX_USAGE]; - uint32_t NbrUsage; - uint32_t UsageMin; - uint32_t UsageMax; - int32_t LogMin; - int32_t LogMax; - int32_t PhyMin; - int32_t PhyMax; - int32_t UnitExp; - uint32_t Unit; - uint32_t ReportSize; - uint32_t ReportCnt; - uint32_t Flag; - uint32_t PhyUsage; - uint32_t AppUsage; - uint32_t LogUsage; -} hid_report_data; - -typedef struct _hid_report_ID -{ - uint8_t size; /*!< report size return by the device ID */ - uint8_t reportID; /*!< report ID */ - uint8_t type; /*!< report type (INPUT/OUTPUT/FEATURE) */ -} hid_report_ID; - -typedef struct _hid_collection -{ - uint32_t usage; - uint8_t type; - struct _hid_collection *next_ptr; -} hid_collection; - -typedef struct _hid_appcollection -{ - uint32_t usage; - uint8_t type; - uint8_t nbr_report_fmt; - hid_report_data report_data[HID_MAX_NBR_REPORT_FMT]; -} hid_appcollection; - typedef struct { uint8_t *buf; @@ -175,21 +93,19 @@ typedef struct _hid_process uint8_t ep_addr; uint8_t ep_in; uint8_t ep_out; - __IO uint8_t data_ready; uint8_t *pdata; + __IO uint8_t data_ready; uint16_t len; uint16_t poll; __IO uint32_t timer; - - data_fifo fifo; usb_desc_hid hid_desc; - hid_report_data hid_report; hid_state state; hid_ctlstate ctl_state; + usbh_status (*init)(usb_core_driver *udev, usbh_host *uhost); - void (*machine)(usb_core_driver *udev, usbh_host *uhost); + usbh_status (*decode)(uint8_t *data); } usbh_hid_handler; extern usbh_class usbh_hid; @@ -202,11 +118,5 @@ usbh_status usbh_set_report (usb_core_driver *udev, uint8_t report_ID, uint8_t report_len, uint8_t *report_buf); -/* read data from FIFO */ -uint16_t usbh_hid_fifo_read (data_fifo *fifo, void *buf, uint16_t nbytes); -/* write data to FIFO */ -uint16_t usbh_hid_fifo_write (data_fifo *fifo, void *buf, uint16_t nbytes); -/* initialize FIFO */ -void usbh_hid_fifo_init (data_fifo *fifo, uint8_t *buf, uint16_t size); #endif /* __USBH_HID_CORE_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Include/usbh_standard_hid.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Include/usbh_standard_hid.h new file mode 100644 index 0000000000..a676c7f8a8 --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Include/usbh_standard_hid.h @@ -0,0 +1,101 @@ +/*! + \file usbh_standard_hid.h + \brief header file for usbh_standard_hid.c + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_STANDARD_HID_H +#define __USBH_STANDARD_HID_H + +#include "usb_conf.h" +#include "usbh_hid_core.h" + +//#define AZERTY_KEYBOARD +#define QWERTY_KEYBOARD + +#define MOUSE_BUTTON_1 0x01U +#define MOUSE_BUTTON_2 0x02U +#define MOUSE_BUTTON_3 0x04U + +#define KBD_LEFT_CTRL 0x01U +#define KBD_LEFT_SHIFT 0x02U +#define KBD_LEFT_ALT 0x04U +#define KBD_LEFT_GUI 0x08U +#define KBD_RIGHT_CTRL 0x10U +#define KBD_RIGHT_SHIFT 0x20U +#define KBD_RIGHT_ALT 0x40U +#define KBD_RIGHT_GUI 0x80U + +#define KBD_PRESSED_MAX_NUM 6U + +typedef struct _hid_mouse_info +{ + uint8_t x; + uint8_t y; + uint8_t buttons[3]; +} hid_mouse_info; + +typedef struct +{ + uint8_t state; + uint8_t lctrl; + uint8_t lshift; + uint8_t lalt; + uint8_t lgui; + uint8_t rctrl; + uint8_t rshift; + uint8_t ralt; + uint8_t rgui; + uint8_t keys[6]; +} hid_keybd_info; + +/* function declarations */ +/* initialize mouse */ +void usr_mouse_init (void); +/* process mouse data */ +void usr_mouse_process_data (hid_mouse_info *data); +/* initialize mouse function */ +usbh_status usbh_hid_mouse_init (usb_core_driver *udev, usbh_host *uhost); +/* decode mouse information */ +usbh_status usbh_hid_mouse_decode(uint8_t *data); + +/* initialize keyboard */ +void usr_keybrd_init (void); +/* process keyboard data */ +void usr_keybrd_process_data (uint8_t pbuf); +/* initialize the keyboard function */ +usbh_status usbh_hid_keybrd_init (usb_core_driver *udev, usbh_host *uhost); +/* decode keyboard information */ +usbh_status usbh_hid_keybrd_decode (uint8_t *data); + +#endif /* __USBH_STANDARD_HID_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Source/usbh_hid_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Source/usbh_hid_core.c index 75e89959fe..473a58d855 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Source/usbh_hid_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Source/usbh_hid_core.c @@ -3,43 +3,44 @@ \brief USB host HID class driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "usbh_pipe.h" -#include "usbh_hid_core.h" -#include "usbh_hid_mouse.h" -#include "usbh_hid_keybd.h" - #include #include +#include "usbh_pipe.h" +#include "usbh_hid_core.h" +#include "usbh_standard_hid.h" +/* local function prototypes ('static') */ static void usbh_hiddesc_parse (usb_desc_hid *hid_desc, uint8_t *buf); static void usbh_hid_itf_deinit (usbh_host *uhost); static usbh_status usbh_hid_itf_init (usbh_host *uhost); @@ -51,7 +52,7 @@ static usbh_status usbh_hid_desc_get (usbh_host *uhost, uint16_t len); static usbh_status usbh_set_idle (usbh_host *uhost, uint8_t duration, uint8_t report_ID); static usbh_status usbh_set_protocol (usbh_host *uhost, uint8_t protocol); -usbh_class usbh_hid = +usbh_class usbh_hid = { USB_HID_CLASS, usbh_hid_itf_init, @@ -107,7 +108,7 @@ usbh_status usbh_get_report (usbh_host *uhost, \param[out] none \retval operation status */ -usbh_status usbh_set_report (usb_core_driver *udev, +usbh_status usbh_set_report (usb_core_driver *udev, usbh_host *uhost, uint8_t report_type, uint8_t report_ID, @@ -200,7 +201,7 @@ uint8_t usbh_hid_poll_interval_get (usb_core_driver *udev, usbh_host *uhost) if ((HOST_CLASS_ENUM == uhost->cur_state) || (HOST_USER_INPUT == uhost->cur_state) || - (HOST_CHECK_CLASS == uhost->cur_state) || + (HOST_CLASS_CHECK == uhost->cur_state) || (HOST_CLASS_HANDLER == uhost->cur_state)) { return (uint8_t)(hid->poll); } else { @@ -208,98 +209,6 @@ uint8_t usbh_hid_poll_interval_get (usb_core_driver *udev, usbh_host *uhost) } } -/*! - \brief read from FIFO - \param[in] fifo: fifo address - \param[in] buf: read buffer - \param[in] nbytes: number of item to read - \param[out] none - \retval number of read items -*/ -uint16_t usbh_hid_fifo_read (data_fifo *fifo, void *buf, uint16_t nbytes) -{ - uint16_t i = 0U; - uint8_t *p = (uint8_t*) buf; - - if (0U == fifo->lock) { - fifo->lock = 1U; - - for (i = 0U; i < nbytes; i++) { - if (fifo->tail != fifo->head) { - *p++ = fifo->buf[fifo->tail]; - fifo->tail++; - - if (fifo->tail == fifo->size) { - fifo->tail = 0U; - } - } else { - fifo->lock = 0U; - - return i; - } - } - } - - fifo->lock = 0U; - - return nbytes; -} - -/*! - \brief write to FIFO - \param[in] fifo: fifo address - \param[in] buf: read buffer - \param[in] nbytes: number of item to read - \param[out] none - \retval number of write items -*/ -uint16_t usbh_hid_fifo_write (data_fifo *fifo, void *buf, uint16_t nbytes) -{ - uint16_t i = 0U; - uint8_t *p = (uint8_t*) buf; - - if (0U == fifo->lock) { - fifo->lock = 1U; - - for (i = 0U; i < nbytes; i++) { - if ((fifo->head + 1U == fifo->tail) || - ((fifo->head + 1U == fifo->size) && (0U == fifo->tail))) { - fifo->lock = 0U; - - return i; - } else { - fifo->buf[fifo->head] = *p++; - fifo->head++; - - if (fifo->head == fifo->size) { - fifo->head = 0U; - } - } - } - } - - fifo->lock = 0U; - - return nbytes; -} - -/*! - \brief initialize FIFO - \param[in] fifo: fifo address - \param[in] buf: read buffer - \param[in] size: size of FIFO - \param[out] none - \retval none -*/ -void usbh_hid_fifo_init (data_fifo *fifo, uint8_t *buf, uint16_t size) -{ - fifo->head = 0U; - fifo->tail = 0U; - fifo->lock = 0U; - fifo->size = size; - fifo->buf = buf; -} - /*! \brief initialize the hid class \param[in] uhost: pointer to USB host @@ -328,11 +237,11 @@ static usbh_status usbh_hid_itf_init (usbh_host *uhost) uint8_t itf_protocol = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].itf_desc.bInterfaceProtocol; if (USB_HID_PROTOCOL_KEYBOARD == itf_protocol) { - hid_handler.init = usbh_hid_keybd_init; - hid_handler.machine = usbh_hid_keybrd_machine; + hid_handler.init = usbh_hid_keybrd_init; + hid_handler.decode = usbh_hid_keybrd_decode; } else if (USB_HID_PROTOCOL_MOUSE == itf_protocol) { hid_handler.init = usbh_hid_mouse_init; - hid_handler.machine = usbh_hid_mouse_machine; + hid_handler.decode = usbh_hid_mouse_decode; } else { status = USBH_FAIL; } @@ -347,7 +256,7 @@ static usbh_status usbh_hid_itf_init (usbh_host *uhost) hid_handler.poll = HID_MIN_POLL; } - /* check fifo available number of endpoints */ + /* check for available number of endpoints */ /* find the number of endpoints in the interface descriptor */ /* choose the lower number in order not to overrun the buffer allocated */ ep_num = USB_MIN(uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].itf_desc.bNumEndpoints, USBH_MAX_EP_NUM); @@ -364,7 +273,7 @@ static usbh_status usbh_hid_itf_init (usbh_host *uhost) /* open channel for IN endpoint */ usbh_pipe_create (uhost->data, - &uhost->dev_prop, + &uhost->dev_prop, hid_handler.pipe_in, USB_EPTYPE_INTR, hid_handler.len); @@ -410,7 +319,7 @@ static usbh_status usbh_hid_class_req (usbh_host *uhost) switch (hid->ctl_state) { case HID_REQ_INIT: case HID_REQ_GET_HID_DESC: - /* get HID descriptor */ + /* get HID descriptor */ if (USBH_OK == usbh_hid_desc_get (uhost, USB_HID_DESC_SIZE)) { usbh_hiddesc_parse(&hid->hid_desc, uhost->dev_prop.data); @@ -419,7 +328,7 @@ static usbh_status usbh_hid_class_req (usbh_host *uhost) break; case HID_REQ_GET_REPORT_DESC: - /* get report descriptor */ + /* get report descriptor */ if (USBH_OK == usbh_hid_reportdesc_get(uhost, hid->hid_desc.wDescriptorLength)) { hid->ctl_state = HID_REQ_SET_IDLE; } @@ -436,7 +345,7 @@ static usbh_status usbh_hid_class_req (usbh_host *uhost) hid->ctl_state = HID_REQ_SET_PROTOCOL; } } - break; + break; case HID_REQ_SET_PROTOCOL: /* set protocol */ @@ -495,15 +404,15 @@ static usbh_status usbh_hid_handle (usbh_host *uhost) case HID_POLL: if (URB_DONE == usbh_urbstate_get (uhost->data, hid->pipe_in)) { - if (0U == hid->data_ready) { /* handle data once */ - usbh_hid_fifo_write(&hid->fifo, hid->pdata, hid->len); + if (0U == hid->data_ready) { hid->data_ready = 1U; - hid->machine(uhost->data, uhost); + hid->decode(hid->pdata); } } else { - if (URB_STALL == usbh_urbstate_get (uhost->data, hid->pipe_in)) { /* IN endpoint stalled */ - /* issue clear feature on interrupt in endpoint */ + /* check IN endpoint stall status */ + if (URB_STALL == usbh_urbstate_get (uhost->data, hid->pipe_in)) { + /* issue clear feature on interrupt in endpoint */ if (USBH_OK == (usbh_clrfeature (uhost, hid->ep_addr, hid->pipe_in))) { /* change state to issue next in token */ hid->state = HID_GET_DATA; @@ -663,7 +572,7 @@ static usbh_status usbh_set_protocol (usbh_host *uhost, uint8_t protocol) \param[out] none \retval none */ -static void usbh_hiddesc_parse (usb_desc_hid *hid_desc, uint8_t *buf) +static void usbh_hiddesc_parse (usb_desc_hid *hid_desc, uint8_t *buf) { hid_desc->header.bLength = *(uint8_t *)(buf + 0U); hid_desc->header.bDescriptorType = *(uint8_t *)(buf + 1U); diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Source/usbh_standard_hid.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Source/usbh_standard_hid.c new file mode 100644 index 0000000000..5c9172b97b --- /dev/null +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/hid/Source/usbh_standard_hid.c @@ -0,0 +1,276 @@ +/*! + \file usbh_standard_hid.c + \brief USB host HID keyboard and mouse driver + + \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_standard_hid.h" +#include + +hid_mouse_info mouse_info; +hid_keybd_info keybd_info; + +__ALIGN_BEGIN uint8_t mouse_report_data[4] __ALIGN_END = {0U}; +__ALIGN_BEGIN uint32_t keybd_report_data[2] __ALIGN_END; + +/* local constants */ +static const uint8_t kbd_codes[] = +{ + 0, 0, 0, 0, 31, 50, 48, 33, + 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ + 52, 51, 25, 26, 17, 20, 32, 21, + 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ + 4, 5, 6, 7, 8, 9, 10, 11, + 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ + 28, 29, 42, 40, 41, 1, 53, 54, + 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ + 118, 119, 120, 121, 122, 123, 124, 125, + 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ + 79, 84, 83, 90, 95, 100, 105, 106, + 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ + 96, 101, 99, 104, 45, 129, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ + 0, 0, 0, 0, 0, 107, 0, 56, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ + 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ +}; + +#ifdef QWERTY_KEYBOARD + +static const int8_t kbd_key[] = +{ + '\0', '`', '1', '2', '3', '4', '5', '6', + '7', '8', '9', '0', '-', '=', '\0', '\r', + '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', + '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', + 'k', 'l', ';', '\'', '\0', '\n', + '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n', + 'm', ',', '.', '/', '\0', '\0', + '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '7', '4', '1', + '\0', '/', '8', '5', '2', + '0', '*', '9', '6', '3', + '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0' +}; + +static const int8_t kbd_key_shift[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', + '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', + 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', + 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', + 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#else + +static const int8_t kbd_key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', + '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', + 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', + 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', + '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/', + '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', + '\n', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +static const int8_t kbd_key_shift[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', + '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', + 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K', + 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N', + '?', '.', '/', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#endif /* QWERTY_KEYBOARD */ + +/*! + \brief initialize the mouse function + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval none +*/ +usbh_status usbh_hid_mouse_init (usb_core_driver *udev, usbh_host *uhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data; + + mouse_info.x = 0U; + mouse_info.y = 0U; + mouse_info.buttons[0] = 0U; + mouse_info.buttons[1] = 0U; + mouse_info.buttons[2] = 0U; + + if(hid->len > sizeof(mouse_report_data)) { + hid->len = sizeof(mouse_report_data); + } + + hid->pdata = (uint8_t *)(void *)mouse_report_data; + + usr_mouse_init(); + + return USBH_OK; +} + +/*! + \brief decode mouse information + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_hid_mouse_decode(uint8_t *data) +{ + mouse_info.buttons[0] = data[0] & MOUSE_BUTTON_1; + mouse_info.buttons[1] = data[0] & MOUSE_BUTTON_2; + mouse_info.buttons[2] = data[0] & MOUSE_BUTTON_3; + + mouse_info.x = data[1]; + mouse_info.y = data[2]; + + /* handle mouse data position */ + usr_mouse_process_data(&mouse_info); + + return USBH_FAIL; +} + +/*! + \brief initialize the keyboard function + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_hid_keybrd_init (usb_core_driver *udev, usbh_host *uhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data; + + keybd_info.lctrl = keybd_info.lshift = 0U; + keybd_info.lalt = keybd_info.lgui = 0U; + keybd_info.rctrl = keybd_info.rshift = 0U; + keybd_info.ralt = keybd_info.rgui = 0U; + + for (uint32_t x = 0U; x < (sizeof(keybd_report_data) / sizeof(uint32_t)); x++) { + keybd_report_data[x] = 0U; + } + + if (hid->len > (sizeof(keybd_report_data) / sizeof(uint32_t))) { + hid->len = (sizeof(keybd_report_data) / sizeof(uint32_t)); + } + + hid->pdata = (uint8_t*)(void *)keybd_report_data; + + /* call user initialization*/ + usr_keybrd_init(); + + return USBH_OK; +} + +/*! + \brief get ascii code + \param[in] info: keyboard information + \param[out] none + \retval output +*/ +uint8_t usbh_hid_ascii_code_get (hid_keybd_info *info) +{ + uint8_t output; + if ((1U == info->lshift) || (info->rshift)) { + output = kbd_key_shift[kbd_codes[info->keys[0]]]; + } else { + output = kbd_key[kbd_codes[info->keys[0]]]; + } + + return output; +} + +/*! + \brief decode keyboard information + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_hid_keybrd_decode (uint8_t *data) +{ + uint8_t output; + + keybd_info.lshift = data[0] & KBD_LEFT_SHIFT; + keybd_info.rshift = data[0] & KBD_RIGHT_SHIFT; + + keybd_info.keys[0] = data[2]; + + if (keybd_info.lshift || keybd_info.rshift) { + output = kbd_key_shift[kbd_codes[keybd_info.keys[0]]]; + } else { + output = kbd_key[kbd_codes[keybd_info.keys[0]]]; + } + + if (0U != output) { + usr_keybrd_process_data(output); + } + + return USBH_OK; +} diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_bbb.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_bbb.h index da71b743ae..5a786dd1f7 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_bbb.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_bbb.h @@ -3,32 +3,34 @@ \brief header file for usbh_msc_bbb.c \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,23 +44,23 @@ typedef union { msc_bbb_cbw field; uint8_t CBWArray[31]; -}usbh_cbw_pkt; +} usbh_cbw_pkt; typedef union { msc_bbb_csw field; uint8_t CSWArray[13]; -}usbh_csw_pkt; +} usbh_csw_pkt; enum usbh_msc_state { - USBH_MSC_BOT_INIT_STATE = 0U, - USBH_MSC_BOT_RESET, + USBH_MSC_BBB_INIT_STATE = 0U, + USBH_MSC_BBB_RESET, USBH_MSC_GET_MAX_LUN, USBH_MSC_TEST_UNIT_READY, USBH_MSC_READ_CAPACITY10, USBH_MSC_MODE_SENSE6, USBH_MSC_REQUEST_SENSE, - USBH_MSC_BOT_USB_TRANSFERS, + USBH_MSC_BBB_USB_TRANSFERS, USBH_MSC_DEFAULT_APPLI_STATE, USBH_MSC_CTRL_ERROR_STATE, USBH_MSC_UNRECOVERED_STATE @@ -66,54 +68,54 @@ enum usbh_msc_state { typedef enum { - BOT_OK = 0U, - BOT_FAIL, - BOT_PHASE_ERROR, - BOT_BUSY -} bot_status; + BBB_OK = 0U, + BBB_FAIL, + BBB_PHASE_ERROR, + BBB_BUSY +} bbb_status; typedef enum { - BOT_CMD_IDLE = 0U, - BOT_CMD_SEND, - BOT_CMD_WAIT, -} bot_cmd_state; + BBB_CMD_IDLE = 0U, + BBB_CMD_SEND, + BBB_CMD_WAIT +} bbb_cmd_state; /* csw status definitions */ typedef enum { - BOT_CSW_CMD_PASSED = 0U, - BOT_CSW_CMD_FAILED, - BOT_CSW_PHASE_ERROR, -} bot_csw_status; + BBB_CSW_CMD_PASSED = 0U, + BBB_CSW_CMD_FAILED, + BBB_CSW_PHASE_ERROR +} bbb_csw_status; typedef enum { - BOT_SEND_CBW = 1U, - BOT_SEND_CBW_WAIT, - BOT_DATA_IN, - BOT_DATA_IN_WAIT, - BOT_DATA_OUT, - BOT_DATA_OUT_WAIT, - BOT_RECEIVE_CSW, - BOT_RECEIVE_CSW_WAIT, - BOT_ERROR_IN, - BOT_ERROR_OUT, - BOT_UNRECOVERED_ERROR -} bot_state; + BBB_SEND_CBW = 1U, + BBB_SEND_CBW_WAIT, + BBB_DATA_IN, + BBB_DATA_IN_WAIT, + BBB_DATA_OUT, + BBB_DATA_OUT_WAIT, + BBB_RECEIVE_CSW, + BBB_RECEIVE_CSW_WAIT, + BBB_ERROR_IN, + BBB_ERROR_OUT, + BBB_UNRECOVERED_ERROR +} bbb_state; typedef struct { uint8_t *pbuf; uint32_t data[16]; - bot_state state; - bot_state prev_state; - bot_cmd_state cmd_state; + bbb_state state; + bbb_state prev_state; + bbb_cmd_state cmd_state; usbh_cbw_pkt cbw; usbh_csw_pkt csw; -} bot_handle; +} bbb_handle; -#define USBH_MSC_BOT_CBW_TAG 0x20304050U +#define USBH_MSC_BBB_CBW_TAG 0x20304050U #define USBH_MSC_CSW_MAX_LENGTH 63U @@ -130,21 +132,21 @@ typedef struct #define CBW_LENGTH 10U #define CBW_LENGTH_TEST_UNIT_READY 0U -#define MAX_BULK_STALL_COUNT_LIMIT 0x04U /*!< If STALL is seen on Bulk - Endpoint continously, this means +#define MAX_BULK_STALL_COUNT_LIMIT 0x04U /*!< If STALL is seen on Bulk + Endpoint continously, this means that device and Host has phase error Hence a Reset is needed */ /* function declarations */ /* initialize the mass storage parameters */ -void usbh_msc_bot_init (usbh_host *uhost); -/* manage the different states of BOT transfer and updates the status to upper layer */ -usbh_status usbh_msc_bot_process (usbh_host *uhost, uint8_t lun); +void usbh_msc_bbb_init (usbh_host *uhost); +/* manage the different states of BBB transfer and updates the status to upper layer */ +usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun); /* manages the different error handling for stall */ -usbh_status usbh_msc_bot_abort (usbh_host *uhost, uint8_t direction); -/* reset MSC bot request structure */ -usbh_status usbh_msc_bot_reset (usbh_host *uhost); +usbh_status usbh_msc_bbb_abort (usbh_host *uhost, uint8_t direction); +/* reset MSC BBB request structure */ +usbh_status usbh_msc_bbb_reset (usbh_host *uhost); /* decode the CSW received by the device and updates the same to upper layer */ -bot_csw_status usbh_msc_csw_decode (usbh_host *uhost); +bbb_csw_status usbh_msc_csw_decode (usbh_host *uhost); #endif /* __USBH_MSC_BBB_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_core.h index 6f32ddcf86..3f6380db26 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_core.h @@ -3,32 +3,34 @@ \brief header file for the usbh_core.c \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -70,7 +72,7 @@ typedef enum MSC_REQ_ERROR, } msc_req_state; -/* Structure for LUN */ +/* structure for LUN */ typedef struct { msc_state state; @@ -82,7 +84,7 @@ typedef struct uint8_t state_changed; } msc_lun; -/* structure for MSC process */ +/* structure for msc process */ typedef struct _msc_process { uint8_t pipe_in; @@ -98,7 +100,7 @@ typedef struct _msc_process msc_error error; msc_req_state req_state; msc_req_state prev_req_state; - bot_handle bot; + bbb_handle bbb; msc_lun unit[MSC_MAX_SUPPORTED_LUN]; uint32_t timer; } usbh_msc_handler; @@ -121,4 +123,4 @@ usbh_status usbh_msc_write (usbh_host *uhost, uint8_t *pbuf, uint32_t length); -#endif /* __USBH_MSC_CORE_H */ +#endif /* __USBH_MSC_CORE_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_scsi.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_scsi.h index 85cd3c65a1..013265cc2c 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_scsi.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Include/usbh_msc_scsi.h @@ -3,32 +3,34 @@ \brief header file for usbh_msc_scsi.c \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -62,7 +64,7 @@ typedef struct uint32_t msc_sense_key; uint16_t msc_page_len; uint8_t msc_write_protect; -}usbh_msc_parameter; +} usbh_msc_parameter; #define DESC_REQUEST_SENSE 0x00U #define ALLOCATION_LENGTH_REQUEST_SENSE 63U diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_bbb.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_bbb.c index b5129d8e74..6224d56c53 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_bbb.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_bbb.c @@ -3,32 +3,34 @@ \brief USB MSC BBB protocol related functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -45,202 +47,202 @@ OF SUCH DAMAGE. \param[out] none \retval none */ -void usbh_msc_bot_init (usbh_host *uhost) +void usbh_msc_bbb_init (usbh_host *uhost) { usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - msc->bot.cbw.field.dCBWSignature = BBB_CBW_SIGNATURE; - msc->bot.cbw.field.dCBWTag = USBH_MSC_BOT_CBW_TAG; - msc->bot.state = BOT_SEND_CBW; - msc->bot.cmd_state = BOT_CMD_SEND; + msc->bbb.cbw.field.dCBWSignature = BBB_CBW_SIGNATURE; + msc->bbb.cbw.field.dCBWTag = USBH_MSC_BBB_CBW_TAG; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_SEND; } /*! - \brief manage the different states of BOT transfer and updates the status to upper layer - \param[in] uhost: pointer to usb host handler + \brief manage the different states of BBB transfer and updates the status to upper layer + \param[in] uhost: pointer to USB host handler \param[in] lun: logic unit number \param[out] none \retval operation status */ -usbh_status usbh_msc_bot_process (usbh_host *uhost, uint8_t lun) +usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun) { - bot_csw_status csw_status = BOT_CSW_CMD_FAILED; + bbb_csw_status csw_status = BBB_CSW_CMD_FAILED; usbh_status status = USBH_BUSY; usbh_status error = USBH_BUSY; usb_urb_state urb_status = URB_IDLE; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.state) { - case BOT_SEND_CBW: - msc->bot.cbw.field.bCBWLUN = lun; - msc->bot.state = BOT_SEND_CBW_WAIT; + switch (msc->bbb.state) { + case BBB_SEND_CBW: + msc->bbb.cbw.field.bCBWLUN = lun; + msc->bbb.state = BBB_SEND_CBW_WAIT; /* send CBW */ usbh_data_send (uhost->data, - msc->bot.cbw.CBWArray, - msc->pipe_out, + msc->bbb.cbw.CBWArray, + msc->pipe_out, BBB_CBW_LENGTH); break; - case BOT_SEND_CBW_WAIT: + case BBB_SEND_CBW_WAIT: urb_status = usbh_urbstate_get(uhost->data, msc->pipe_out); if (URB_DONE == urb_status) { - if (0U != msc->bot.cbw.field.dCBWDataTransferLength) { - if (USB_TRX_IN == (msc->bot.cbw.field.bmCBWFlags & USB_TRX_MASK)) { - msc->bot.state = BOT_DATA_IN; + if (0U != msc->bbb.cbw.field.dCBWDataTransferLength) { + if (USB_TRX_IN == (msc->bbb.cbw.field.bmCBWFlags & USB_TRX_MASK)) { + msc->bbb.state = BBB_DATA_IN; } else { - msc->bot.state = BOT_DATA_OUT; + msc->bbb.state = BBB_DATA_OUT; } } else { - msc->bot.state = BOT_RECEIVE_CSW; + msc->bbb.state = BBB_RECEIVE_CSW; } } else if (URB_NOTREADY == urb_status) { - msc->bot.state = BOT_SEND_CBW; + msc->bbb.state = BBB_SEND_CBW; } else { if (URB_STALL == urb_status) { - msc->bot.state = BOT_ERROR_OUT; + msc->bbb.state = BBB_ERROR_OUT; } } break; - case BOT_DATA_IN: - usbh_data_recev (uhost->data, - msc->bot.pbuf, - msc->pipe_in, + case BBB_DATA_IN: + usbh_data_recev (uhost->data, + msc->bbb.pbuf, + msc->pipe_in, msc->ep_size_in); - msc->bot.state = BOT_DATA_IN_WAIT; + msc->bbb.state = BBB_DATA_IN_WAIT; break; - case BOT_DATA_IN_WAIT: + case BBB_DATA_IN_WAIT: urb_status = usbh_urbstate_get(uhost->data, msc->pipe_in); - /* BOT DATA IN stage */ + /* BBB DATA IN stage */ if (URB_DONE == urb_status) { - if (msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_in) { - msc->bot.pbuf += msc->ep_size_in; - msc->bot.cbw.field.dCBWDataTransferLength -= msc->ep_size_in; + if (msc->bbb.cbw.field.dCBWDataTransferLength > msc->ep_size_in) { + msc->bbb.pbuf += msc->ep_size_in; + msc->bbb.cbw.field.dCBWDataTransferLength -= msc->ep_size_in; } else { - msc->bot.cbw.field.dCBWDataTransferLength = 0U; + msc->bbb.cbw.field.dCBWDataTransferLength = 0U; } - if (msc->bot.cbw.field.dCBWDataTransferLength > 0U) { - usbh_data_recev (uhost->data, - msc->bot.pbuf, - msc->pipe_in, + if (msc->bbb.cbw.field.dCBWDataTransferLength > 0U) { + usbh_data_recev (uhost->data, + msc->bbb.pbuf, + msc->pipe_in, msc->ep_size_in); } else { - msc->bot.state = BOT_RECEIVE_CSW; + msc->bbb.state = BBB_RECEIVE_CSW; } } else if(URB_STALL == urb_status) { /* this is data stage stall condition */ - msc->bot.state = BOT_ERROR_IN; + msc->bbb.state = BBB_ERROR_IN; } else { /* no operation */ } break; - case BOT_DATA_OUT: + case BBB_DATA_OUT: usbh_data_send (uhost->data, - msc->bot.pbuf, - msc->pipe_out, + msc->bbb.pbuf, + msc->pipe_out, msc->ep_size_out); - msc->bot.state = BOT_DATA_OUT_WAIT; + msc->bbb.state = BBB_DATA_OUT_WAIT; break; - case BOT_DATA_OUT_WAIT: - /* BOT DATA OUT stage */ + case BBB_DATA_OUT_WAIT: + /* BBB DATA OUT stage */ urb_status = usbh_urbstate_get(uhost->data, msc->pipe_out); if (URB_DONE == urb_status) { - if (msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_out) { - msc->bot.pbuf += msc->ep_size_out; - msc->bot.cbw.field.dCBWDataTransferLength -= msc->ep_size_out; + if (msc->bbb.cbw.field.dCBWDataTransferLength > msc->ep_size_out) { + msc->bbb.pbuf += msc->ep_size_out; + msc->bbb.cbw.field.dCBWDataTransferLength -= msc->ep_size_out; } else { - msc->bot.cbw.field.dCBWDataTransferLength = 0; /* reset this value and keep in same state */ + msc->bbb.cbw.field.dCBWDataTransferLength = 0; /* reset this value and keep in same state */ } - if (msc->bot.cbw.field.dCBWDataTransferLength > 0) { + if (msc->bbb.cbw.field.dCBWDataTransferLength > 0) { usbh_data_send (uhost->data, - msc->bot.pbuf, - msc->pipe_out, + msc->bbb.pbuf, + msc->pipe_out, msc->ep_size_out); } else { - msc->bot.state = BOT_RECEIVE_CSW; + msc->bbb.state = BBB_RECEIVE_CSW; } } else if (URB_NOTREADY == urb_status) { - msc->bot.state = BOT_DATA_OUT; + msc->bbb.state = BBB_DATA_OUT; } else if (URB_STALL == urb_status) { - msc->bot.state = BOT_ERROR_OUT; + msc->bbb.state = BBB_ERROR_OUT; } else { /* no operation */ } break; - case BOT_RECEIVE_CSW: - /* BOT CSW stage */ + case BBB_RECEIVE_CSW: + /* BBB CSW stage */ usbh_data_recev (uhost->data, - msc->bot.csw.CSWArray, - msc->pipe_in, + msc->bbb.csw.CSWArray, + msc->pipe_in, BBB_CSW_LENGTH); - msc->bot.state = BOT_RECEIVE_CSW_WAIT; + msc->bbb.state = BBB_RECEIVE_CSW_WAIT; break; - case BOT_RECEIVE_CSW_WAIT: + case BBB_RECEIVE_CSW_WAIT: urb_status = usbh_urbstate_get(uhost->data, msc->pipe_in); /* decode CSW */ if (URB_DONE == urb_status) { - msc->bot.state = BOT_SEND_CBW; - msc->bot.cmd_state = BOT_CMD_SEND; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_SEND; csw_status = usbh_msc_csw_decode(uhost); - if (BOT_CSW_CMD_PASSED == csw_status) { + if (BBB_CSW_CMD_PASSED == csw_status) { status = USBH_OK; } else { status = USBH_FAIL; } } else if (URB_STALL == urb_status) { - msc->bot.state = BOT_ERROR_IN; + msc->bbb.state = BBB_ERROR_IN; } else { /* no operation */ } break; - case BOT_ERROR_IN: - error = usbh_msc_bot_abort(uhost, USBH_MSC_DIR_IN); + case BBB_ERROR_IN: + error = usbh_msc_bbb_abort(uhost, USBH_MSC_DIR_IN); if (USBH_OK == error) { - msc->bot.state = BOT_RECEIVE_CSW; + msc->bbb.state = BBB_RECEIVE_CSW; } else if (USBH_UNRECOVERED_ERROR == status) { /* this means that there is a stall error limit, do reset recovery */ - msc->bot.state = BOT_UNRECOVERED_ERROR; + msc->bbb.state = BBB_UNRECOVERED_ERROR; } else { /* no operation */ } break; - case BOT_ERROR_OUT: - status = usbh_msc_bot_abort (uhost, USBH_MSC_DIR_OUT); + case BBB_ERROR_OUT: + status = usbh_msc_bbb_abort (uhost, USBH_MSC_DIR_OUT); if (USBH_OK == status) { uint8_t toggle = usbh_pipe_toggle_get(uhost->data, msc->pipe_out); usbh_pipe_toggle_set(uhost->data, msc->pipe_out, 1U - toggle); usbh_pipe_toggle_set(uhost->data, msc->pipe_in, 0U); - msc->bot.state = BOT_ERROR_IN; + msc->bbb.state = BBB_ERROR_IN; } else { if (USBH_UNRECOVERED_ERROR == status) { - msc->bot.state = BOT_UNRECOVERED_ERROR; + msc->bbb.state = BBB_UNRECOVERED_ERROR; } } break; - case BOT_UNRECOVERED_ERROR: - status = usbh_msc_bot_reset(uhost); + case BBB_UNRECOVERED_ERROR: + status = usbh_msc_bbb_reset(uhost); if (USBH_OK == status) { - msc->bot.state = BOT_SEND_CBW; + msc->bbb.state = BBB_SEND_CBW; } break; @@ -258,21 +260,21 @@ usbh_status usbh_msc_bot_process (usbh_host *uhost, uint8_t lun) \param[out] none \retval operation status */ -usbh_status usbh_msc_bot_abort (usbh_host *uhost, uint8_t direction) +usbh_status usbh_msc_bbb_abort (usbh_host *uhost, uint8_t direction) { usbh_status status = USBH_BUSY; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; switch (direction) { case USBH_MSC_DIR_IN : - /* send clear feature command on bulk IN endpoint */ + /* send clrfeature command on bulk IN endpoint */ status = usbh_clrfeature(uhost, msc->ep_in, msc->pipe_in); break; case USBH_MSC_DIR_OUT : - /*send clear feature command on bulk OUT endpoint */ + /*send clrfeature command on bulk OUT endpoint */ status = usbh_clrfeature(uhost, msc->ep_out, msc->pipe_out); @@ -286,12 +288,12 @@ usbh_status usbh_msc_bot_abort (usbh_host *uhost, uint8_t direction) } /*! - \brief reset MSC bot transfer + \brief reset msc bbb transfer \param[in] uhost: pointer to USB host handler \param[out] none \retval operation status */ -usbh_status usbh_msc_bot_reset (usbh_host *uhost) +usbh_status usbh_msc_bbb_reset (usbh_host *uhost) { usbh_status status = USBH_BUSY; @@ -305,7 +307,7 @@ usbh_status usbh_msc_bot_reset (usbh_host *uhost) }; usbh_ctlstate_config (uhost, NULL, 0U); - } + } status = usbh_ctl_handler (uhost); @@ -318,43 +320,43 @@ usbh_status usbh_msc_bot_reset (usbh_host *uhost) \param[out] none \retval on success USBH_MSC_OK, on failure USBH_MSC_FAIL \notes - Refer to USB Mass-Storage Class: BOT (www.usb.org) + Refer to USB Mass-Storage Class: BBB (www.usb.org) 6.3.1 Valid CSW Conditions : The host shall consider the CSW valid when: 1. dCSWSignature is equal to 53425355h 2. the CSW is 13 (Dh) bytes in length, 3. dCSWTag matches the dCBWTag from the corresponding CBW. */ -bot_csw_status usbh_msc_csw_decode (usbh_host *uhost) +bbb_csw_status usbh_msc_csw_decode (usbh_host *uhost) { - bot_csw_status status = BOT_CSW_CMD_FAILED; + bbb_csw_status status = BBB_CSW_CMD_FAILED; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; /* checking if the transfer length is different than 13 */ if (BBB_CSW_LENGTH != usbh_xfercount_get (uhost->data, msc->pipe_in)) { - status = BOT_CSW_PHASE_ERROR; + status = BBB_CSW_PHASE_ERROR; } else { /* CSW length is correct */ /* check validity of the CSW Signature and CSWStatus */ - if (BBB_CSW_SIGNATURE == msc->bot.csw.field.dCSWSignature) { + if (BBB_CSW_SIGNATURE == msc->bbb.csw.field.dCSWSignature) { /* check condition 1. dCSWSignature is equal to 53425355h */ - if (msc->bot.csw.field.dCSWTag == msc->bot.cbw.field.dCBWTag) { + if (msc->bbb.csw.field.dCSWTag == msc->bbb.cbw.field.dCBWTag) { /* check condition 3. dCSWTag matches the dCBWTag from the corresponding CBW */ - if (0U == msc->bot.csw.field.bCSWStatus) { - status = BOT_CSW_CMD_PASSED; - } else if (1U == msc->bot.csw.field.bCSWStatus) { - status = BOT_CSW_CMD_FAILED; - } else if (2U == msc->bot.csw.field.bCSWStatus) { - status = BOT_CSW_PHASE_ERROR; + if (0U == msc->bbb.csw.field.bCSWStatus) { + status = BBB_CSW_CMD_PASSED; + } else if (1U == msc->bbb.csw.field.bCSWStatus) { + status = BBB_CSW_CMD_FAILED; + } else if (2U == msc->bbb.csw.field.bCSWStatus) { + status = BBB_CSW_PHASE_ERROR; } else { /* no operation */ } } } else { - /* If the CSW signature is not valid, we shall return the phase error to + /* if the CSW signature is not valid, we shall return the phase error to upper layers for reset recovery */ - status = BOT_CSW_PHASE_ERROR; + status = BBB_CSW_PHASE_ERROR; } } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_core.c index afb992b017..81da24411b 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_core.c @@ -3,32 +3,34 @@ \brief USB MSC(mass storage device) class driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -48,7 +50,7 @@ static usbh_status usbh_msc_handle (usbh_host *uhost); static usbh_status usbh_msc_maxlun_get (usbh_host *uhost, uint8_t *maxlun); static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun); -usbh_class usbh_msc = +usbh_class usbh_msc = { USB_CLASS_MSC, usbh_msc_itf_init, @@ -59,7 +61,7 @@ usbh_class usbh_msc = /*! \brief interface initialization for MSC class - \param[in] uhost: pointer to usb host + \param[in] uhost: pointer to USB host \param[out] none \retval operation status */ @@ -74,65 +76,65 @@ static usbh_status usbh_msc_itf_init (usbh_host *uhost) status = USBH_FAIL; } else { - uhost->active_class->class_data = (usbh_msc_handler *)malloc(sizeof(usbh_msc_handler)); + static usbh_msc_handler msc_handler; - usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - - memset(msc, 0U, sizeof(usbh_msc_handler)); + memset((void*)&msc_handler, 0U, sizeof(usbh_msc_handler)); + + uhost->active_class->class_data = (void *)&msc_handler; usbh_interface_select(&uhost->dev_prop, interface); usb_desc_ep *ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[0]; - if (ep_desc->bEndpointAddress & 0x80) { - msc->ep_in = ep_desc->bEndpointAddress; - msc->ep_size_in = ep_desc->wMaxPacketSize; + if (ep_desc->bEndpointAddress & 0x80U) { + msc_handler.ep_in = ep_desc->bEndpointAddress; + msc_handler.ep_size_in = ep_desc->wMaxPacketSize; } else { - msc->ep_out = ep_desc->bEndpointAddress; - msc->ep_size_out = ep_desc->wMaxPacketSize; + msc_handler.ep_out = ep_desc->bEndpointAddress; + msc_handler.ep_size_out = ep_desc->wMaxPacketSize; } ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[1]; - if (ep_desc->bEndpointAddress & 0x80) { - msc->ep_in = ep_desc->bEndpointAddress; - msc->ep_size_in = ep_desc->wMaxPacketSize; + if (ep_desc->bEndpointAddress & 0x80U) { + msc_handler.ep_in = ep_desc->bEndpointAddress; + msc_handler.ep_size_in = ep_desc->wMaxPacketSize; } else { - msc->ep_out = ep_desc->bEndpointAddress; - msc->ep_size_out = ep_desc->wMaxPacketSize; + msc_handler.ep_out = ep_desc->bEndpointAddress; + msc_handler.ep_size_out = ep_desc->wMaxPacketSize; } - msc->state = MSC_INIT; - msc->error = MSC_OK; - msc->req_state = MSC_REQ_IDLE; - msc->pipe_out = usbh_pipe_allocate(uhost->data, msc->ep_out); - msc->pipe_in = usbh_pipe_allocate(uhost->data, msc->ep_in); + msc_handler.state = MSC_INIT; + msc_handler.error = MSC_OK; + msc_handler.req_state = MSC_REQ_IDLE; + msc_handler.pipe_out = usbh_pipe_allocate(uhost->data, msc_handler.ep_out); + msc_handler.pipe_in = usbh_pipe_allocate(uhost->data, msc_handler.ep_in); - usbh_msc_bot_init(uhost); + usbh_msc_bbb_init(uhost); /* open the new channels */ usbh_pipe_create (uhost->data, &uhost->dev_prop, - msc->pipe_out, + msc_handler.pipe_out, USB_EPTYPE_BULK, - msc->ep_size_out); + msc_handler.ep_size_out); usbh_pipe_create (uhost->data, &uhost->dev_prop, - msc->pipe_in, + msc_handler.pipe_in, USB_EPTYPE_BULK, - msc->ep_size_in); + msc_handler.ep_size_in); - usbh_pipe_toggle_set (uhost->data, msc->pipe_out, 0U); - usbh_pipe_toggle_set (uhost->data, msc->pipe_in, 0U); + usbh_pipe_toggle_set (uhost->data, msc_handler.pipe_out, 0U); + usbh_pipe_toggle_set (uhost->data, msc_handler.pipe_in, 0U); } return status; } /*! - \brief de-initialize interface by freeing host channels allocated to interface - \param[in] uhost: pointer to usb host + \brief deinitialize interface by freeing host channels allocated to interface + \param[in] uhost: pointer to USB host \param[out] none \retval operation status */ @@ -157,7 +159,7 @@ void usbh_msc_itf_deinit (usbh_host *uhost) /*! \brief initialize the MSC state machine - \param[in] uhost: pointer to usb host + \param[in] uhost: pointer to USB host \param[out] none \retval operation status */ @@ -188,7 +190,7 @@ static usbh_status usbh_msc_req (usbh_host *uhost) break; case MSC_REQ_ERROR: - /* issue clear feature request */ + /* issue clearfeature request */ if (USBH_OK == usbh_clrfeature(uhost, 0x00U, uhost->control.pipe_out_num)) { msc->req_state = msc->prev_req_state; } @@ -203,7 +205,7 @@ static usbh_status usbh_msc_req (usbh_host *uhost) /*! \brief MSC state machine handler - \param[in] uhost: pointer to usb host + \param[in] uhost: pointer to USB host \param[out] none \retval operation status */ @@ -221,107 +223,108 @@ static usbh_status usbh_msc_handle (usbh_host *uhost) msc->unit[msc->cur_lun].error = MSC_NOT_READY; switch (msc->unit[msc->cur_lun].state) { - case MSC_INIT: - msc->unit[msc->cur_lun].state = MSC_READ_INQUIRY; - msc->timer = uhost->control.timer; - break; + case MSC_INIT: + msc->unit[msc->cur_lun].state = MSC_READ_INQUIRY; + msc->timer = uhost->control.timer; + break; - case MSC_READ_INQUIRY: - scsi_status = usbh_msc_scsi_inquiry(uhost, msc->cur_lun, &msc->unit[msc->cur_lun].inquiry); + case MSC_READ_INQUIRY: + scsi_status = usbh_msc_scsi_inquiry (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].inquiry); - if (USBH_OK == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; - } else if (scsi_status == USBH_FAIL) { - msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; - } else { - if (scsi_status == USBH_UNRECOVERED_ERROR) { - msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_ERROR; - } - } - break; - - case MSC_TEST_UNIT_READY: - /* issue SCSI command TestUnitReady */ - ready_status = usbh_msc_test_unitready(uhost, msc->cur_lun); - - if (USBH_OK == ready_status) { - if (USBH_OK != msc->unit[msc->cur_lun].prev_ready_state) { - msc->unit[msc->cur_lun].state_changed = 1U; - } else { - msc->unit[msc->cur_lun].state_changed = 0U; - } - - msc->unit[msc->cur_lun].state = MSC_READ_CAPACITY10; - msc->unit[msc->cur_lun].error = MSC_OK; - msc->unit[msc->cur_lun].prev_ready_state = USBH_OK; - } else if (USBH_FAIL == ready_status) { - if (USBH_FAIL != msc->unit[msc->cur_lun].prev_ready_state) { - msc->unit[msc->cur_lun].state_changed = 1U; - } else { - msc->unit[msc->cur_lun].state_changed = 0U; - } - - msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; - msc->unit[msc->cur_lun].error = MSC_NOT_READY; - msc->unit[msc->cur_lun].prev_ready_state = USBH_FAIL; - } else { - if (USBH_UNRECOVERED_ERROR == ready_status) { - msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_ERROR; - } - } - break; - - case MSC_READ_CAPACITY10: - /* issue READ_CAPACITY10 SCSI command */ - scsi_status = usbh_msc_read_capacity10(uhost, msc->cur_lun, &msc->unit[msc->cur_lun].capacity); - - if (USBH_OK == scsi_status) { - if (1U == msc->unit[msc->cur_lun].state_changed) { - } + if (USBH_OK == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; + } else if (scsi_status == USBH_FAIL) { + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + } else { + if (scsi_status == USBH_UNRECOVERED_ERROR) { msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_OK; - msc->cur_lun ++; - } else if (USBH_FAIL == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; - } else { - if (USBH_UNRECOVERED_ERROR == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_ERROR; - } + msc->unit[msc->cur_lun].error = MSC_ERROR; } - break; + } + break; - case MSC_REQUEST_SENSE: - /* issue RequestSense SCSI command for receiving error code */ - scsi_status = usbh_msc_request_sense (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].sense); - if (USBH_OK == scsi_status) { - if ((msc->unit[msc->cur_lun].sense.SenseKey == UNIT_ATTENTION) || (msc->unit[msc->cur_lun].sense.SenseKey == NOT_READY)) { - if ((uhost->control.timer - msc->timer) < 10000U) { - msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; - break; - } - } + case MSC_TEST_UNIT_READY: + /* issue SCSI command TestUnitReady */ + ready_status = usbh_msc_test_unitready (uhost, msc->cur_lun); + if (USBH_OK == ready_status) { + if (USBH_OK != msc->unit[msc->cur_lun].prev_ready_state) { + msc->unit[msc->cur_lun].state_changed = 1U; + } else { + msc->unit[msc->cur_lun].state_changed = 0U; + } + + msc->unit[msc->cur_lun].state = MSC_READ_CAPACITY10; + msc->unit[msc->cur_lun].error = MSC_OK; + msc->unit[msc->cur_lun].prev_ready_state = USBH_OK; + } else if (USBH_FAIL == ready_status) { + if (USBH_FAIL != msc->unit[msc->cur_lun].prev_ready_state) { + msc->unit[msc->cur_lun].state_changed = 1U; + } else { + msc->unit[msc->cur_lun].state_changed = 0U; + } + + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + msc->unit[msc->cur_lun].error = MSC_NOT_READY; + msc->unit[msc->cur_lun].prev_ready_state = USBH_FAIL; + } else { + if (USBH_UNRECOVERED_ERROR == ready_status) { msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->cur_lun++; - } else if (USBH_FAIL == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_UNRECOVERED_ERROR; - } else { - if (MSC_UNRECOVERED_ERROR == scsi_status) { - msc->unit[msc->cur_lun].state = MSC_IDLE; - msc->unit[msc->cur_lun].error = MSC_ERROR; - } + msc->unit[msc->cur_lun].error = MSC_ERROR; } - break; + } + break; - case MSC_UNRECOVERED_ERROR: + case MSC_READ_CAPACITY10: + /* issue READ_CAPACITY10 SCSI command */ + scsi_status = usbh_msc_read_capacity10 (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].capacity); + + if (USBH_OK == scsi_status) { + if (1U == msc->unit[msc->cur_lun].state_changed) { + } + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_OK; msc->cur_lun ++; - break; + } else if (USBH_FAIL == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + } else { + if (USBH_UNRECOVERED_ERROR == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; - default: - break; + case MSC_REQUEST_SENSE: + /* issue RequestSense SCSI command for retrieving error code */ + scsi_status = usbh_msc_request_sense (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].sense); + if (USBH_OK == scsi_status) { + if ((msc->unit[msc->cur_lun].sense.SenseKey == UNIT_ATTENTION) || (msc->unit[msc->cur_lun].sense.SenseKey == NOT_READY)) { + if (((uhost->control.timer > msc->timer) && ((uhost->control.timer - msc->timer) < 10000U)) \ + || ((uhost->control.timer < msc->timer) && ((uhost->control.timer + 0x3FFFU - msc->timer) < 10000U))) { + msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; + break; + } + } + + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->cur_lun++; + } else if (USBH_FAIL == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_UNRECOVERED_ERROR; + } else { + if (MSC_UNRECOVERED_ERROR == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; + + case MSC_UNRECOVERED_ERROR: + msc->cur_lun++; + break; + + default: + break; } } else { msc->cur_lun = 0U; @@ -362,7 +365,7 @@ static usbh_status usbh_msc_maxlun_get (usbh_host *uhost, uint8_t *maxlun) }; usbh_ctlstate_config (uhost, maxlun, 1U); - } + } status = usbh_ctl_handler (uhost); @@ -406,7 +409,7 @@ static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun) if (USBH_OK == scsi_status) { msc->unit[lun].state = MSC_IDLE; error = USBH_OK; - } else if(USBH_FAIL == scsi_status) { + } else if (USBH_FAIL == scsi_status) { msc->unit[lun].state = MSC_REQUEST_SENSE; } else { if (USBH_UNRECOVERED_ERROR == scsi_status) { @@ -425,7 +428,7 @@ static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun) error = USBH_FAIL; } - + if (USBH_FAIL == scsi_status) { } else { if (USBH_UNRECOVERED_ERROR == scsi_status) { @@ -483,8 +486,8 @@ usbh_status usbh_msc_read (usbh_host *uhost, usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; usb_core_driver *udev = (usb_core_driver *)uhost->data; - if ((0U == udev->host.connect_status) || - (HOST_CLASS_HANDLER != uhost->cur_state) || + if ((0U == udev->host.connect_status) || + (HOST_CLASS_HANDLER != uhost->cur_state) || (MSC_IDLE != msc->unit[lun].state)) { return USBH_FAIL; } @@ -498,7 +501,9 @@ usbh_status usbh_msc_read (usbh_host *uhost, timeout = uhost->control.timer; while (USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) { - if (((uhost->control.timer - timeout) > (1000U * length)) || (0U == udev->host.connect_status)) { + if (((uhost->control.timer > timeout) && ((uhost->control.timer - timeout) > (10000U * length))) \ + || ((uhost->control.timer < timeout) && ((uhost->control.timer + 0x3FFFU - timeout) > (10000U * length))) \ + || (0U == udev->host.connect_status)){ msc->state = MSC_IDLE; return USBH_FAIL; } @@ -529,8 +534,8 @@ usbh_status usbh_msc_write (usbh_host *uhost, usb_core_driver *udev = (usb_core_driver *)uhost->data; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - if ((0U == udev->host.connect_status) || - (HOST_CLASS_HANDLER != uhost->cur_state) || + if ((0U == udev->host.connect_status) || + (HOST_CLASS_HANDLER != uhost->cur_state) || (MSC_IDLE != msc->unit[lun].state)) { return USBH_FAIL; } @@ -544,7 +549,9 @@ usbh_status usbh_msc_write (usbh_host *uhost, timeout = uhost->control.timer; while (USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) { - if (((uhost->control.timer - timeout) > (1000U * length)) || (0U == udev->host.connect_status)) { + if (((uhost->control.timer > timeout) && ((uhost->control.timer - timeout) > (10000U * length))) \ + || ((uhost->control.timer < timeout) && ((uhost->control.timer + 0x3FFFU - timeout) > (10000U * length))) \ + || (0U == udev->host.connect_status)){ msc->state = MSC_IDLE; return USBH_FAIL; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_fatfs.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_fatfs.c index f89d7d740a..4a8f723935 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_fatfs.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_fatfs.c @@ -3,32 +3,34 @@ \brief USB MSC host FATFS related functions \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -205,7 +207,7 @@ DRESULT disk_ioctl (BYTE drv, BYTE ctrl, void *buff) /* get erase block size in unit of sector (dword) */ case GET_BLOCK_SIZE: - *(DWORD*)buff = 512; + *(DWORD *)buff = 512U; break; default: @@ -222,12 +224,12 @@ DRESULT disk_ioctl (BYTE drv, BYTE ctrl, void *buff) \param[out] none \retval time value */ -DWORD get_fattime(void) { - - return ((DWORD)(2019U - 1980U) << 25U) /* year 2019 */ - | ((DWORD)1U << 21U) /* month 1 */ - | ((DWORD)1U << 16U) /* day 1 */ - | ((DWORD)0U << 11U) /* hour 0 */ - | ((DWORD)0U << 5U) /* min 0 */ - | ((DWORD)0U >> 1U); /* sec 0 */ +DWORD get_fattime (void) +{ + return ((DWORD)(2019U - 1980U) << 25U) /* year 2019 */ + | ((DWORD)1U << 21U) /* month 1 */ + | ((DWORD)1U << 16U) /* day 1 */ + | ((DWORD)0U << 11U) /* hour 0 */ + | ((DWORD)0U << 5U) /* min 0 */ + | ((DWORD)0U >> 1U); /* sec 0 */ } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_scsi.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_scsi.c index e9566af405..b7a9b593a7 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_scsi.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/class/msc/Source/usbh_msc_scsi.c @@ -1,34 +1,36 @@ /*! \file usbh_msc_scsi.c - \brief USB MSC SCSI commands implementing + \brief USB MSC SCSI commands implemention \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -51,44 +53,44 @@ usbh_status usbh_msc_scsi_inquiry (usbh_host *uhost, uint8_t lun, scsi_std_inqui usbh_status error = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { - case BOT_CMD_SEND: - /* prepare the CBW and relevant field*/ - msc->bot.cbw.field.dCBWDataTransferLength = STANDARD_INQUIRY_DATA_LEN; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + /* prepare the cbw and relevant field*/ + msc->bbb.cbw.field.dCBWDataTransferLength = STANDARD_INQUIRY_DATA_LEN; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_INQUIRY; - msc->bot.cbw.field.CBWCB[1] = (lun << 5U); - msc->bot.cbw.field.CBWCB[4] = 0x24U; + msc->bbb.cbw.field.CBWCB[0] = SCSI_INQUIRY; + msc->bbb.cbw.field.CBWCB[1] = (lun << 5U); + msc->bbb.cbw.field.CBWCB[4] = 0x24U; - msc->bot.state = BOT_SEND_CBW; - msc->bot.cmd_state = BOT_CMD_WAIT; - msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; error = USBH_BUSY; break; - case BOT_CMD_WAIT: - error = usbh_msc_bot_process(uhost, lun); + case BBB_CMD_WAIT: + error = usbh_msc_bbb_process(uhost, lun); if (USBH_OK == error) { memset(inquiry, 0U, sizeof(scsi_std_inquiry_data)); /* assign inquiry data */ - inquiry->device_type = msc->bot.pbuf[0] & 0x1FU; - inquiry->peripheral_qualifier = msc->bot.pbuf[0] >> 5U; + inquiry->device_type = msc->bbb.pbuf[0] & 0x1FU; + inquiry->peripheral_qualifier = msc->bbb.pbuf[0] >> 5U; - if (0x80U == ((uint32_t)msc->bot.pbuf[1] & 0x80U)) { + if (0x80U == ((uint32_t)msc->bbb.pbuf[1] & 0x80U)) { inquiry->removable_media = 1U; } else { inquiry->removable_media = 0U; } - memcpy (inquiry->vendor_id, &msc->bot.pbuf[8], 8U); - memcpy (inquiry->product_id, &msc->bot.pbuf[16], 16U); - memcpy (inquiry->revision_id, &msc->bot.pbuf[32], 4U); + memcpy (inquiry->vendor_id, &msc->bbb.pbuf[8], 8U); + memcpy (inquiry->product_id, &msc->bbb.pbuf[16], 16U); + memcpy (inquiry->revision_id, &msc->bbb.pbuf[32], 4U); } break; @@ -112,24 +114,24 @@ usbh_status usbh_msc_test_unitready (usbh_host *uhost, uint8_t lun) usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { - case BOT_CMD_SEND: + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: /* prepare the CBW and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = CBW_LENGTH_TEST_UNIT_READY; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_OUT; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = CBW_LENGTH_TEST_UNIT_READY; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_OUT; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_TEST_UNIT_READY; - msc->bot.state = BOT_SEND_CBW; - msc->bot.cmd_state = BOT_CMD_WAIT; + msc->bbb.cbw.field.CBWCB[0] = SCSI_TEST_UNIT_READY; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; status = USBH_BUSY; break; - case BOT_CMD_WAIT: - status = usbh_msc_bot_process(uhost, lun); + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); break; default: @@ -152,33 +154,33 @@ usbh_status usbh_msc_read_capacity10 (usbh_host *uhost, uint8_t lun, scsi_capaci usbh_status status = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { - case BOT_CMD_SEND: + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: /* prepare the CBW and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = READ_CAPACITY10_DATA_LEN; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = READ_CAPACITY10_DATA_LEN; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_READ_CAPACITY10; - msc->bot.state = BOT_SEND_CBW; - msc->bot.cmd_state = BOT_CMD_WAIT; - msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + msc->bbb.cbw.field.CBWCB[0] = SCSI_READ_CAPACITY10; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; status = USBH_BUSY; break; - case BOT_CMD_WAIT: - status = usbh_msc_bot_process(uhost, lun); + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); if (USBH_OK == status) { - capacity->block_nbr = msc->bot.pbuf[3] | \ - ((uint32_t)msc->bot.pbuf[2] << 8U) | \ - ((uint32_t)msc->bot.pbuf[1] << 16U) | \ - ((uint32_t)msc->bot.pbuf[0] << 24U); + capacity->block_nbr = msc->bbb.pbuf[3] | \ + ((uint32_t)msc->bbb.pbuf[2] << 8U) | \ + ((uint32_t)msc->bbb.pbuf[1] << 16U) | \ + ((uint32_t)msc->bbb.pbuf[0] << 24U); - capacity->block_size = (uint16_t)(msc->bot.pbuf[7] | ((uint32_t)msc->bot.pbuf[6] << 8U)); + capacity->block_size = (uint16_t)(msc->bbb.pbuf[7] | ((uint32_t)msc->bbb.pbuf[6] << 8U)); } break; @@ -202,30 +204,30 @@ usbh_status usbh_msc_mode_sense6 (usbh_host *uhost, uint8_t lun) usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { - case BOT_CMD_SEND: + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: /* prepare the CBW and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = XFER_LEN_MODE_SENSE6; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = XFER_LEN_MODE_SENSE6; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_MODE_SENSE6; - msc->bot.cbw.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | MODE_SENSE_PAGE_CODE; - msc->bot.cbw.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; - msc->bot.state = BOT_SEND_CBW; - msc->bot.cmd_state = BOT_CMD_WAIT; - msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + msc->bbb.cbw.field.CBWCB[0] = SCSI_MODE_SENSE6; + msc->bbb.cbw.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | MODE_SENSE_PAGE_CODE; + msc->bbb.cbw.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; status = USBH_BUSY; break; - case BOT_CMD_WAIT: - status = usbh_msc_bot_process(uhost, lun); + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); if (USBH_OK == status) { - if (msc->bot.data[2] & MASK_MODE_SENSE_WRITE_PROTECT) { + if (msc->bbb.data[2] & MASK_MODE_SENSE_WRITE_PROTECT) { } else { @@ -254,34 +256,34 @@ usbh_status usbh_msc_request_sense (usbh_host *uhost, uint8_t lun, msc_scsi_sens usbh_status status = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { - case BOT_CMD_SEND: - /* prepare the CBW and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = ALLOCATION_LENGTH_REQUEST_SENSE; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + /* prepare the cbw and relevant field */ + msc->bbb.cbw.field.dCBWDataTransferLength = ALLOCATION_LENGTH_REQUEST_SENSE; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_REQUEST_SENSE; - msc->bot.cbw.field.CBWCB[1] = (lun << 5U); - msc->bot.cbw.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; + msc->bbb.cbw.field.CBWCB[0] = SCSI_REQUEST_SENSE; + msc->bbb.cbw.field.CBWCB[1] = (lun << 5U); + msc->bbb.cbw.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; - msc->bot.state = BOT_SEND_CBW; - msc->bot.cmd_state = BOT_CMD_WAIT; - msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; status = USBH_BUSY; break; - case BOT_CMD_WAIT: - status = usbh_msc_bot_process(uhost, lun); + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); if (status == USBH_OK) { /* get sense data */ - sense_data->SenseKey = msc->bot.pbuf[2] & 0x0FU; - sense_data->ASC = msc->bot.pbuf[12]; - sense_data->ASCQ = msc->bot.pbuf[13]; + sense_data->SenseKey = msc->bbb.pbuf[2] & 0x0FU; + sense_data->ASC = msc->bbb.pbuf[12]; + sense_data->ASCQ = msc->bbb.pbuf[13]; } break; @@ -307,35 +309,35 @@ usbh_status usbh_msc_write10 (usbh_host *uhost, uint8_t lun, uint8_t *data_buf, usbh_status status = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { - case BOT_CMD_SEND: - msc->bot.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_OUT; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + msc->bbb.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_OUT; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_WRITE10; + msc->bbb.cbw.field.CBWCB[0] = SCSI_WRITE10; /* logical block address */ - msc->bot.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); - msc->bot.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); - msc->bot.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); - msc->bot.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); + msc->bbb.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); + msc->bbb.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); + msc->bbb.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); + msc->bbb.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); /* transfer length */ - msc->bot.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); - msc->bot.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); + msc->bbb.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); + msc->bbb.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); - msc->bot.state = BOT_SEND_CBW; - msc->bot.cmd_state = BOT_CMD_WAIT; - msc->bot.pbuf = data_buf; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = data_buf; status = USBH_BUSY; break; - case BOT_CMD_WAIT: - status = usbh_msc_bot_process(uhost, lun); + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); break; default: @@ -360,36 +362,36 @@ usbh_status usbh_msc_read10 (usbh_host *uhost, uint8_t lun, uint8_t *data_buf, u usbh_status status = USBH_FAIL; usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; - switch (msc->bot.cmd_state) { - case BOT_CMD_SEND: + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: /* prepare the CBW and relevant field */ - msc->bot.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; - msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; - msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + msc->bbb.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; - memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); - msc->bot.cbw.field.CBWCB[0] = SCSI_READ10; + msc->bbb.cbw.field.CBWCB[0] = SCSI_READ10; /* logical block address */ - msc->bot.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); - msc->bot.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); - msc->bot.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); - msc->bot.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); + msc->bbb.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); + msc->bbb.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); + msc->bbb.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); + msc->bbb.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); /* transfer length */ - msc->bot.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); - msc->bot.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); + msc->bbb.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); + msc->bbb.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); - msc->bot.state = BOT_SEND_CBW; - msc->bot.cmd_state = BOT_CMD_WAIT; - msc->bot.pbuf = data_buf; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = data_buf; status = USBH_BUSY; break; - case BOT_CMD_WAIT: - status = usbh_msc_bot_process(uhost, lun); + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); break; default: diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_core.h index c8e7ca1e7c..3eca1de8d5 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_core.h @@ -3,32 +3,34 @@ \brief USB host core state machine header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -64,15 +66,15 @@ typedef enum { HOST_DEFAULT = 0U, HOST_DETECT_DEV_SPEED, - HOST_DEV_ATTACHED, + HOST_DEV_CONNECT, HOST_DEV_DETACHED, - HOST_ENUM, - HOST_SET_WAKEUP_FEATURE, - HOST_CHECK_CLASS, + HOST_DEV_ENUM, + HOST_PWR_FEATURE_SET, + HOST_CLASS_CHECK, HOST_CLASS_ENUM, HOST_CLASS_HANDLER, HOST_USER_INPUT, - HOST_SUSPENDED, + HOST_SUSPEND, HOST_WAKEUP, HOST_ERROR } usb_host_state; @@ -94,7 +96,7 @@ typedef enum } usbh_enum_state; /* USB host control transfer state */ -typedef enum +typedef enum { CTL_IDLE = 0U, CTL_SETUP, @@ -114,18 +116,17 @@ typedef enum /* user action state */ typedef enum { - USBH_USER_NO_RESP = 0U, - USBH_USER_RESP_OK = 1U, + USR_IN_NO_RESP = 0U, + USR_IN_RESP_OK = 1U, } usbh_user_status; +/* USB host wakeup mode */ typedef enum { - USBH_PORT_EVENT = 1U, - USBH_URB_EVENT, - USBH_CONTROL_EVENT, - USBH_CLASS_EVENT, - USBH_STATE_CHANGED_EVENT, -}usbh_os_event; + NORMAL_WORK = 0U, + GENERAL_WAKEUP = 1U, + REMOTE_WAKEUP = 2, +} usbh_wakeup_mode; /* control transfer information */ typedef struct _usbh_control @@ -169,9 +170,9 @@ typedef struct usb_desc_dev dev_desc; usb_desc_cfg_set cfg_desc_set; -#if (USBH_KEEP_CFG_DESCRIPTOR == 1U) +#if (USBH_CFG_DESC_KEEP == 1U) uint8_t cfgdesc_rawdata[USBH_CFGSET_MAX_LEN]; -#endif /* (USBH_KEEP_CFG_DESCRIPTOR == 1U) */ +#endif /* (USBH_CFG_DESC_KEEP == 1U) */ } usb_dev_prop; struct _usbh_host; @@ -179,7 +180,7 @@ struct _usbh_host; /* device class callbacks */ typedef struct { - uint8_t class_code; /*!< USB class type */ + uint8_t class_code; /*!< USB class type */ usbh_status (*class_init) (struct _usbh_host *phost); void (*class_deinit) (struct _usbh_host *phost); @@ -203,7 +204,7 @@ typedef struct void (*dev_devdesc_assigned) (void *dev_desc); void (*dev_address_set) (void); - void (*dev_cfgdesc_assigned) (usb_desc_config *cfg_desc, + void (*dev_cfgdesc_assigned) (usb_desc_config *cfg_desc, usb_desc_itf *itf_desc, usb_desc_ep *ep_desc); @@ -234,9 +235,9 @@ typedef struct _usbh_host void *data; /*!< used for... */ -#ifdef USB_LOW_PWR_ENABLE - uint8_t suspend_flag; -#endif /* USB_LOW_PWR_ENABLE*/ + uint8_t suspend_flag; /*!< host suspend flag */ + uint8_t dev_supp_remote_wkup; /*!< record device remote wakeup function */ + usbh_wakeup_mode wakeup_mode; /*!< record wakeup mode */ } usbh_host; /*! @@ -274,9 +275,5 @@ usbh_status usbh_deinit (usbh_host *uhost); void usbh_core_task (usbh_host *uhost); /* handle the error on USB host side */ void usbh_error_handler (usbh_host *uhost, usbh_status err_type); -#ifdef USB_LOW_PWR_ENABLE -/* handles the USB resume from suspend mode */ -void usb_hwp_resume(usb_core_driver *udev); -#endif /* USB_LOW_PWR_ENABLE */ #endif /* __USBH_CORE_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_enum.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_enum.h index 3112d1a998..43127e6f0f 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_enum.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_enum.h @@ -3,39 +3,40 @@ \brief USB host mode USB enumeration header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBH_ENUM_H #define __USBH_ENUM_H -#include "usb_conf.h" #include "usbh_core.h" /* function declarations */ @@ -58,7 +59,7 @@ usbh_status usbh_setdevfeature (usbh_host *uhost, uint8_t feature_selector, uint /* clear or disable a specific device feature */ usbh_status usbh_clrdevfeature (usbh_host *uhost, uint8_t feature_selector, uint16_t windex); /* clear or disable a specific feature */ -usbh_status usbh_clrfeature (usbh_host *uhost, uint8_t ep_addr, uint8_t pp_num); +usbh_status usbh_clrfeature (usbh_host *uhost, uint8_t ep_addr, uint8_t pp_num); /* get the next descriptor header */ usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr); /* select an interface */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_pipe.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_pipe.h index e89c5fe22f..58e51ea593 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_pipe.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_pipe.h @@ -3,32 +3,34 @@ \brief USB host mode pipe header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -37,12 +39,14 @@ OF SUCH DAMAGE. #include "usbh_core.h" -#define HC_MAX 8U +/* host pipe maximum */ +#define HP_MAX 8U -#define HC_OK 0x0000U -#define HC_USED 0x8000U -#define HC_ERROR 0xFFFFU -#define HC_USED_MASK 0x7FFFU +/* host pipe status */ +#define HP_OK 0x0000U +#define HP_USED 0x8000U +#define HP_ERROR 0xFFFFU +#define HP_USED_MASK 0x7FFFU /*! \brief set toggle for a pipe diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_transc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_transc.h index 65f4328c55..ea2f8d239f 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_transc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Include/usbh_transc.h @@ -3,39 +3,40 @@ \brief USB host mode transactions header file \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBH_TRANSC_H #define __USBH_TRANSC_H -#include "usb_conf.h" #include "usbh_core.h" /* function declarations */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_core.c index 8cb32af254..480b3aa19f 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_core.c @@ -3,32 +3,34 @@ \brief USB host core state machine driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,37 +42,39 @@ OF SUCH DAMAGE. #include /* local function prototypes ('static') */ -static uint8_t usbh_sof (usbh_host *uhost); -static uint8_t usbh_connect (usbh_host *uhost); -static uint8_t usbh_disconnect (usbh_host *uhost); -static uint8_t usbh_port_enabled (usbh_host *uhost); -static uint8_t usbh_port_disabled (usbh_host *uhost); -static usbh_status usbh_enum_task (usbh_host *uhost); +static uint8_t usb_ev_sof (usbh_host *uhost); +static uint8_t usb_ev_connect (usbh_host *uhost); +static uint8_t usb_ev_disconnect (usbh_host *uhost); +static usbh_status usbh_enum_task (usbh_host *uhost); +#if USBFS_LOW_POWER || USBHS_LOW_POWER +static void usb_hwp_suspend (usb_core_driver *udev); +static void usb_hwp_resume (usb_core_driver *udev); +#endif /* USBFS_LOW_POWER || USBHS_LOW_POWER */ -#ifdef USB_LOW_PWR_ENABLE -static void usb_hwp_suspend(usb_core_driver *udev); -#endif - -usbh_int_cb usbh_int_op = +usbh_ev_cb usbh_int_op = { - usbh_connect, - usbh_disconnect, - usbh_port_enabled, - usbh_port_disabled, - usbh_sof + usb_ev_connect, + usb_ev_disconnect, + usb_ev_sof, }; -usbh_int_cb *usbh_int_fop = &usbh_int_op; +usbh_ev_cb *usbh_int_fop = &usbh_int_op; /*! \brief USB host stack initializations \param[in] uhost: pointer to USB host + \param[in] udev: pointer to USB device instance + \param[in] usb_core: USB core type \param[in] user_cb: pointer to user callback \param[out] none \retval none */ void usbh_init (usbh_host *uhost, usb_core_driver *udev, usb_core_enum usb_core, usbh_user_cb *user_cb) { + /* link driver to the stack */ + udev->host.data = (void *)uhost; + uhost->data = (void *)udev; + /* host deinitialization */ usbh_deinit(uhost); @@ -102,10 +106,6 @@ void usbh_init (usbh_host *uhost, usb_core_driver *udev, usb_core_enum usb_core, usb_globalint_enable(&udev->regs); #endif /* DUAL_ROLE_MODE_ENABLED */ - /* link driver to the stack */ - udev->host.data = (void *)uhost; - uhost->data = (void *)udev; - /* upon initialize call usr call back */ uhost->usr_cb->dev_init(); } @@ -135,7 +135,7 @@ usbh_status usbh_class_register (usbh_host *uhost, usbh_class *puclass) } /*! - \brief de-initialize USB host + \brief deinitialize USB host \param[in] uhost: pointer to USB host \param[out] none \retval operation status @@ -195,7 +195,7 @@ void usbh_core_task (usbh_host *uhost) case HOST_DETECT_DEV_SPEED: if (udev->host.port_enabled) { - uhost->cur_state = HOST_DEV_ATTACHED; + uhost->cur_state = HOST_DEV_CONNECT; uhost->dev_prop.speed = usb_curspeed_get (udev); @@ -205,7 +205,7 @@ void usbh_core_task (usbh_host *uhost) } break; - case HOST_DEV_ATTACHED: + case HOST_DEV_CONNECT: uhost->usr_cb->dev_attach(); uhost->control.pipe_out_num = usbh_pipe_allocate(udev, 0x00U); uhost->control.pipe_in_num = usbh_pipe_allocate(udev, 0x80U); @@ -224,10 +224,10 @@ void usbh_core_task (usbh_host *uhost) USB_EPTYPE_CTRL, (uint16_t)uhost->control.max_len); - uhost->cur_state = HOST_ENUM; + uhost->cur_state = HOST_DEV_ENUM; break; - case HOST_ENUM: + case HOST_DEV_ENUM: /* check for enumeration status */ if (USBH_OK == usbh_enum_task (uhost)) { /* the function shall return USBH_OK when full enumeration is complete */ @@ -235,25 +235,32 @@ void usbh_core_task (usbh_host *uhost) /* user callback for end of device basic enumeration */ uhost->usr_cb->dev_enumerated(); -#ifdef USB_LOW_PWR_ENABLE - uhost->cur_state = HOST_SUSPENDED; +#if USBFS_LOW_POWER || USBHS_LOW_POWER + uhost->cur_state = HOST_SUSPEND; + + /* judge device remote wakeup function */ + if ((uhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5)) { + uhost->dev_supp_remote_wkup = 1; + }else{ + uhost->dev_supp_remote_wkup = 0; + } #else - uhost->cur_state = HOST_SET_WAKEUP_FEATURE; -#endif + uhost->cur_state = HOST_PWR_FEATURE_SET; +#endif /* USBFS_LOW_POWER || USBHS_LOW_POWER */ } break; - case HOST_SET_WAKEUP_FEATURE: + case HOST_PWR_FEATURE_SET: if ((uhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5)) { if (usbh_setdevfeature(uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U) == USBH_OK) { - uhost->cur_state = HOST_CHECK_CLASS; + uhost->cur_state = HOST_CLASS_CHECK; } } else { - uhost->cur_state = HOST_CHECK_CLASS; + uhost->cur_state = HOST_CLASS_CHECK; } break; - case HOST_CHECK_CLASS: + case HOST_CLASS_CHECK: if (0U == uhost->class_num) { uhost->cur_state = HOST_ERROR; } else { @@ -277,33 +284,61 @@ void usbh_core_task (usbh_host *uhost) case HOST_USER_INPUT: /* the function should return user response true to move to class state */ - if (USBH_USER_RESP_OK == uhost->usr_cb->dev_user_input()) { + if (USR_IN_RESP_OK == uhost->usr_cb->dev_user_input()) { if ((USBH_OK == uhost->active_class->class_init(uhost))) { uhost->cur_state = HOST_CLASS_ENUM; } } break; -#ifdef USB_LOW_PWR_ENABLE - case HOST_SUSPENDED: - if (USBH_OK == usbh_setdevfeature(uhost, FEATURE_SELECTOR_DEV, 0U)) { - uhost->suspend_flag = 1; - usb_hwp_suspend(uhost->data); - uhost->usr_cb->dev_user_input(); - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); - uhost->cur_state = HOST_WAKEUP; +#if USBFS_LOW_POWER || USBHS_LOW_POWER + case HOST_SUSPEND: + if(uhost->dev_supp_remote_wkup){ + /* send set feature command*/ + if (USBH_OK == usbh_setdevfeature (uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U)) { + + usb_hwp_suspend (udev); + + usb_mdelay (20U); + uhost->suspend_flag = 1; + uhost->usr_cb->dev_user_input(); + + /* MCU enter deep-sleep*/ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + uhost->cur_state = HOST_WAKEUP; + } + } else { + /* host suspend */ + usb_hwp_suspend (udev); + + usb_mdelay(20U); + uhost->suspend_flag = 1U; + uhost->usr_cb->dev_user_input(); + + /* MCU enter deep-sleep */ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + uhost->cur_state = HOST_WAKEUP; } break; case HOST_WAKEUP: - if (USBH_OK == usbh_clrdevfeature(uhost, FEATURE_SELECTOR_DEV, 0U)) { - /* user callback for initialization */ - uhost->usr_cb->dev_init(); - - uhost->cur_state = HOST_CHECK_CLASS; + /* judge suspend status */ + if (0U == uhost->suspend_flag) { + usb_hwp_resume(udev); + usb_mdelay(500U); + + if (uhost->dev_supp_remote_wkup) { + if (USBH_OK == usbh_clrdevfeature (uhost, FEATURE_SELECTOR_DEV, 0U)) { + /* user callback for initialization */ + uhost->usr_cb->dev_init(); + uhost->cur_state = HOST_CLASS_CHECK; + } + } else { + uhost->cur_state = HOST_CLASS_CHECK; + } } break; -#endif +#endif /* USBFS_LOW_POWER || USBHS_LOW_POWER */ case HOST_CLASS_ENUM: /* process class standard control requests state machine */ @@ -324,7 +359,7 @@ void usbh_core_task (usbh_host *uhost) break; case HOST_ERROR: - /* initialize host for new enumeration */ + /* deinitialize host for new enumeration */ usbh_deinit (uhost); uhost->usr_cb->dev_deinit(); uhost->active_class->class_deinit(uhost); @@ -335,7 +370,7 @@ void usbh_core_task (usbh_host *uhost) uhost->usr_cb->dev_detach(); /* re-initialize host for new enumeration */ - usbh_deinit(uhost); + usbh_deinit (uhost); uhost->usr_cb->dev_deinit(); uhost->active_class->class_deinit(uhost); usbh_pipe_delete(udev); @@ -372,12 +407,12 @@ void usbh_error_handler (usbh_host *uhost, usbh_status err_type) } /*! - \brief USB SOF callback function from the interrupt + \brief USB SOF event function from the interrupt \param[in] uhost: pointer to USB host \param[out] none \retval operation status */ -static uint8_t usbh_sof (usbh_host *uhost) +static uint8_t usb_ev_sof (usbh_host *uhost) { usb_core_driver *udev = (usb_core_driver *)uhost->data; @@ -394,12 +429,12 @@ static uint8_t usbh_sof (usbh_host *uhost) } /*! - \brief USB connect callback function from the interrupt + \brief USB connect event function from the interrupt \param[in] uhost: pointer to USB host \param[out] none \retval operation status */ -static uint8_t usbh_connect (usbh_host *uhost) +static uint8_t usb_ev_connect (usbh_host *uhost) { usb_core_driver *udev = (usb_core_driver *)uhost->data; udev->host.connect_status = 1U; @@ -408,12 +443,12 @@ static uint8_t usbh_connect (usbh_host *uhost) } /*! - \brief USB disconnect callback function from the interrupt + \brief USB disconnect event function from the interrupt \param[in] uhost: pointer to USB host \param[out] none \retval operation status */ -static uint8_t usbh_disconnect (usbh_host *uhost) +static uint8_t usb_ev_disconnect (usbh_host *uhost) { usb_core_driver *udev = (usb_core_driver *)uhost->data; udev->host.connect_status = 0U; @@ -421,34 +456,6 @@ static uint8_t usbh_disconnect (usbh_host *uhost) return 0U; } -/*! - \brief USB port enable callback function from the interrupt - \param[in] uhost: pointer to USB host - \param[out] none - \retval operation status -*/ -static uint8_t usbh_port_enabled (usbh_host *uhost) -{ - usb_core_driver *udev = (usb_core_driver *)uhost->data; - udev->host.port_enabled = 1U; - - return 0U; -} - -/*! - \brief USB port disabled callback function from the interrupt - \param[in] uhost: pointer to USB host - \param[out] none - \retval operation status -*/ -static uint8_t usbh_port_disabled (usbh_host *uhost) -{ - usb_core_driver *udev = (usb_core_driver *)uhost->data; - udev->host.port_enabled = 0U; - - return 0U; -} - /*! \brief handle the USB enumeration task \param[in] uhost: pointer to host @@ -457,7 +464,7 @@ static uint8_t usbh_port_disabled (usbh_host *uhost) */ static usbh_status usbh_enum_task (usbh_host *uhost) { - uint8_t str_buf[64]; + uint8_t str_buf[512]; usbh_status status = USBH_BUSY; usb_core_driver *udev = (usb_core_driver *)uhost->data; @@ -497,7 +504,7 @@ static usbh_status usbh_enum_task (usbh_host *uhost) } break; - case ENUM_SET_ADDR: + case ENUM_SET_ADDR: /* set address */ if (USBH_OK == usbh_setaddress (uhost, USBH_DEV_ADDR)) { usb_mdelay (2U); @@ -543,8 +550,8 @@ static usbh_status usbh_enum_task (usbh_host *uhost) case ENUM_GET_STR_DESC: if (index_mfc_str) { - if (USBH_OK == usbh_strdesc_get (uhost, - uhost->dev_prop.dev_desc.iManufacturer, + if (USBH_OK == usbh_strdesc_get (uhost, + uhost->dev_prop.dev_desc.iManufacturer, str_buf, 0xFFU)) { /* user callback for manufacturing string */ @@ -555,9 +562,9 @@ static usbh_status usbh_enum_task (usbh_host *uhost) } else { if (index_prod_str) { /* check that product string is available */ - if (USBH_OK == usbh_strdesc_get (uhost, - uhost->dev_prop.dev_desc.iProduct, - str_buf, + if (USBH_OK == usbh_strdesc_get (uhost, + uhost->dev_prop.dev_desc.iProduct, + str_buf, 0xFFU)) { uhost->usr_cb->dev_prod_str(str_buf); @@ -565,9 +572,9 @@ static usbh_status usbh_enum_task (usbh_host *uhost) } } else { if (index_serial_str) { - if (USBH_OK == usbh_strdesc_get (uhost, + if (USBH_OK == usbh_strdesc_get (uhost, uhost->dev_prop.dev_desc.iSerialNumber, - str_buf, + str_buf, 0xFFU)) { uhost->usr_cb->dev_seral_str(str_buf); uhost->enum_state = ENUM_SET_CONFIGURATION; @@ -597,7 +604,7 @@ static usbh_status usbh_enum_task (usbh_host *uhost) return status; } -#ifdef USB_LOW_PWR_ENABLE +#if USBFS_LOW_POWER || USBHS_LOW_POWER /*! \brief handles the USB resume from suspend mode @@ -605,7 +612,7 @@ static usbh_status usbh_enum_task (usbh_host *uhost) \param[out] none \retval none */ -void usb_hwp_resume(usb_core_driver *udev) +static void usb_hwp_resume(usb_core_driver *udev) { __IO uint32_t hprt = 0U; @@ -650,4 +657,4 @@ static void usb_hwp_suspend(usb_core_driver *udev) *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; } -#endif /* USB_LOW_PWR_ENABLE */ +#endif /* USBFS_LOW_POWER || USBHS_LOW_POWER */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_enum.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_enum.c index 7966d8a9ac..361acdb3c9 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_enum.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_enum.c @@ -3,32 +3,34 @@ \brief USB host mode enumeration driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -111,11 +113,11 @@ usbh_status usbh_cfgdesc_get (usbh_host *uhost, uint16_t len) usbh_control *usb_ctl = &uhost->control; -#if (USBH_KEEP_CFG_DESCRIPTOR == 1U) +#if (USBH_CFG_DESC_KEEP == 1U) pdata = uhost->dev_prop.cfgdesc_rawdata; #else pdata = uhost->dev_prop.data; -#endif +#endif /* (USBH_CFG_DESC_KEEP == 1U) */ if (CTL_IDLE == usb_ctl->ctl_state) { usb_ctl->setup.req = (usb_req) { @@ -152,8 +154,8 @@ usbh_status usbh_cfgdesc_get (usbh_host *uhost, uint16_t len) \retval operation status */ usbh_status usbh_strdesc_get (usbh_host *uhost, - uint8_t str_index, - uint8_t *buf, + uint8_t str_index, + uint8_t *buf, uint16_t len) { usbh_status status = USBH_BUSY; @@ -297,7 +299,7 @@ usbh_status usbh_setdevfeature (usbh_host *uhost, uint8_t feature_selector, uint }; usbh_ctlstate_config (uhost, NULL, 0U); - } + } status = usbh_ctl_handler (uhost); @@ -328,7 +330,7 @@ usbh_status usbh_clrdevfeature (usbh_host *uhost, uint8_t feature_selector, uint }; usbh_ctlstate_config (uhost, NULL, 0U); - } + } status = usbh_ctl_handler (uhost); @@ -343,7 +345,7 @@ usbh_status usbh_clrdevfeature (usbh_host *uhost, uint8_t feature_selector, uint \param[out] none \retval operation status */ -usbh_status usbh_clrfeature (usbh_host *uhost, uint8_t ep_addr, uint8_t pp_num) +usbh_status usbh_clrfeature (usbh_host *uhost, uint8_t ep_addr, uint8_t pp_num) { usbh_status status = USBH_BUSY; usbh_control *usb_ctl = &uhost->control; @@ -365,7 +367,7 @@ usbh_status usbh_clrfeature (usbh_host *uhost, uint8_t ep_addr, uint8_t pp_num) } usbh_ctlstate_config (uhost, NULL, 0U); - } + } status = usbh_ctl_handler (uhost); @@ -676,13 +678,13 @@ static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len) if (USB_DESCTYPE_STR == psrc[1]) { /* make sure the descriptor is string type */ - /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ + /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ str_len = USB_MIN((uint16_t)psrc[0] - 2U, len); - psrc += 2U; /* adjust the offset ignoring the string len and descriptor type */ + psrc += 2U; /* adjust the offset ignoring the string length and descriptor type */ - for (index = 0U; index < str_len; index += 2U) { - /* copy only the string and ignore the unicode id, hence add the src */ + for(index = 0U; index < str_len; index += 2U) { + /* copy only the string and ignore the unicode id, hence add the source */ *pdest = psrc[index]; pdest++; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_pipe.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_pipe.c index 7d00be8d2a..a3d6253dc2 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_pipe.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_pipe.c @@ -3,32 +3,34 @@ \brief USB host mode pipe operation driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -59,11 +61,14 @@ uint8_t usbh_pipe_create (usb_core_driver *udev, pp->dev_speed = dev->speed; pp->ep.type = ep_type; pp->ep.mps = ep_mpl; - pp->ping = (uint8_t)(dev->speed == PORT_SPEED_HIGH); + + if ((USB_USE_DMA != udev->bp.transfer_mode) && ((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type))) { + pp->supp_ping = (uint8_t)(pp->dev_speed == PORT_SPEED_HIGH); + } usb_pipe_init (udev, pp_num); - return HC_OK; + return HP_OK; } /*! @@ -90,15 +95,19 @@ uint8_t usbh_pipe_update (usb_core_driver *udev, if ((pp->dev_speed != dev_speed) && (dev_speed)) { pp->dev_speed = dev_speed; + + if ((USB_USE_DMA != udev->bp.transfer_mode) && ((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type))) { + pp->supp_ping = (uint8_t)(pp->dev_speed == PORT_SPEED_HIGH); + } } if ((pp->ep.mps != ep_mpl) && (ep_mpl)) { - pp->ep.mps = ep_mpl; + pp->ep.mps = ep_mpl; } usb_pipe_init (udev, pp_num); - return HC_OK; + return HP_OK; } /*! @@ -112,7 +121,7 @@ uint8_t usbh_pipe_allocate (usb_core_driver *udev, uint8_t ep_addr) { uint16_t pp_num = usbh_freepipe_get (udev); - if (HC_ERROR != pp_num) { + if (HP_ERROR != pp_num) { udev->host.pipe[pp_num].in_used = 1U; udev->host.pipe[pp_num].ep.dir = EP_DIR(ep_addr); udev->host.pipe[pp_num].ep.num = EP_ID(ep_addr); @@ -130,7 +139,7 @@ uint8_t usbh_pipe_allocate (usb_core_driver *udev, uint8_t ep_addr) */ uint8_t usbh_pipe_free (usb_core_driver *udev, uint8_t pp_num) { - if (pp_num < HC_MAX) { + if (pp_num < HP_MAX) { udev->host.pipe[pp_num].in_used = 0U; } @@ -147,7 +156,7 @@ uint8_t usbh_pipe_delete (usb_core_driver *udev) { uint8_t pp_num = 0U; - for (pp_num = 2U; pp_num < HC_MAX; pp_num++) { + for (pp_num = 2U; pp_num < HP_MAX; pp_num++) { udev->host.pipe[pp_num] = (usb_pipe) {0}; } @@ -164,11 +173,11 @@ static uint16_t usbh_freepipe_get (usb_core_driver *udev) { uint8_t pp_num = 0U; - for (pp_num = 0U; pp_num < HC_MAX; pp_num++) { + for (pp_num = 0U; pp_num < HP_MAX; pp_num++) { if (0U == udev->host.pipe[pp_num].in_used) { return (uint16_t)pp_num; } } - return HC_ERROR; + return HP_ERROR; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_transc.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_transc.c index 63d6121350..7ceeac6e25 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_transc.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/host/core/Source/usbh_transc.c @@ -3,32 +3,34 @@ \brief USB host mode transactions driver \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -37,12 +39,12 @@ OF SUCH DAMAGE. #include "usbh_transc.h" /* local function prototypes ('static') */ -static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t wait_time); -static void usbh_setup_transc (usbh_host *uhost); -static void usbh_data_in_transc (usbh_host *uhost); -static void usbh_data_out_transc (usbh_host *uhost); -static void usbh_status_in_transc (usbh_host *uhost); -static void usbh_status_out_transc (usbh_host *uhost); +static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t wait_time); +static void usbh_setup_transc (usbh_host *uhost); +static void usbh_data_in_transc (usbh_host *uhost); +static void usbh_data_out_transc (usbh_host *uhost); +static void usbh_status_in_transc (usbh_host *uhost); +static void usbh_status_out_transc (usbh_host *uhost); static uint32_t usbh_request_submit (usb_core_driver *udev, uint8_t pp_num); /*! @@ -136,7 +138,7 @@ usbh_status usbh_data_recev (usb_core_driver *udev, uint8_t *buf, uint8_t pp_num case USB_EPTYPE_INTR: pp->DPID = PIPE_DPID[pp->data_toggle_in]; - /* Toggle DATA PID */ + /* toggle DATA PID */ pp->data_toggle_in ^= 1U; break; @@ -220,7 +222,9 @@ usbh_status usbh_ctl_handler (usbh_host *uhost) */ static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t wait_time) { + uint32_t timeout = 0U; usb_urb_state urb_status = URB_IDLE; + timeout = uhost->control.timer; while (URB_DONE != (urb_status = usbh_urbstate_get(uhost->data, pp_num))) { if (URB_NOTREADY == urb_status) { @@ -231,7 +235,8 @@ static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t w } else if (URB_ERROR == urb_status) { uhost->control.ctl_state = CTL_ERROR; break; - } else if ((wait_time > 0U) && ((usb_curframe_get(uhost->data)- uhost->control.timer) > wait_time)) { + } else if ((wait_time > 0U) && (((usb_curframe_get(uhost->data) > timeout) && ((usb_curframe_get(uhost->data) - timeout) > wait_time)) \ + || ((usb_curframe_get(uhost->data) < timeout) && ((usb_curframe_get(uhost->data) + 0x3FFFU - timeout) > wait_time)))){ /* timeout for in transfer */ uhost->control.ctl_state = CTL_ERROR; break; @@ -252,8 +257,8 @@ static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t w static void usbh_setup_transc (usbh_host *uhost) { /* send a SETUP packet */ - usbh_ctlsetup_send (uhost->data, - uhost->control.setup.data, + usbh_ctlsetup_send (uhost->data, + uhost->control.setup.data, uhost->control.pipe_out_num); if (URB_DONE == usbh_urb_wait (uhost, uhost->control.pipe_out_num, 0U)) { @@ -294,7 +299,6 @@ static void usbh_data_in_transc (usbh_host *uhost) if (URB_DONE == usbh_urb_wait (uhost, uhost->control.pipe_in_num, DATA_STAGE_TIMEOUT)) { uhost->control.ctl_state = CTL_STATUS_OUT; - uhost->control.timer = (uint16_t)usb_curframe_get(uhost->data); } } @@ -315,8 +319,6 @@ static void usbh_data_out_transc (usbh_host *uhost) if (URB_DONE == usbh_urb_wait (uhost, uhost->control.pipe_out_num, DATA_STAGE_TIMEOUT)) { uhost->control.ctl_state = CTL_STATUS_IN; - - uhost->control.timer = (uint16_t)usb_curframe_get(uhost->data); } } @@ -361,10 +363,15 @@ static void usbh_status_out_transc (usbh_host *uhost) \param[out] none \retval operation status */ -static uint32_t usbh_request_submit (usb_core_driver *udev, uint8_t pp_num) +static uint32_t usbh_request_submit (usb_core_driver *udev, uint8_t pp_num) { udev->host.pipe[pp_num].urb_state = URB_IDLE; udev->host.pipe[pp_num].xfer_count = 0U; + if (1U == udev->host.pipe[pp_num].do_ping) { + (void)usb_pipe_ping (udev, (uint8_t)pp_num); + return USB_OK; + } + return (uint32_t)usb_pipe_xfer (udev, pp_num); } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/cdc/usb_cdc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/cdc/usb_cdc.h index df3e56538d..0a2595cd02 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/cdc/usb_cdc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/cdc/usb_cdc.h @@ -3,32 +3,34 @@ \brief the header file of communication device class standard \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/hid/usb_hid.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/hid/usb_hid.h index 220468f42b..dacec6e8e6 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/hid/usb_hid.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/hid/usb_hid.h @@ -3,32 +3,34 @@ \brief definitions for the USB HID class \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -78,6 +80,6 @@ typedef struct usb_desc_hid hid_vendor; usb_desc_ep hid_epin; usb_desc_ep hid_epout; -}usb_hid_desc_config_set; +} usb_hid_desc_config_set; #endif /* __USB_HID_H */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/msc_bbb.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/msc_bbb.h index dddab34227..b3c5130313 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/msc_bbb.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/msc_bbb.h @@ -3,32 +3,34 @@ \brief definitions for the USB MSC BBB(bulk/bulk/bulk) protocol \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -50,14 +52,14 @@ typedef struct { uint8_t bCBWLUN; uint8_t bCBWCBLength; uint8_t CBWCB[16]; -}msc_bbb_cbw; +} msc_bbb_cbw; typedef struct { uint32_t dCSWSignature; uint32_t dCSWTag; uint32_t dCSWDataResidue; uint8_t bCSWStatus; -}msc_bbb_csw; +} msc_bbb_csw; /* CSW command status */ enum msc_csw_status { diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/msc_scsi.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/msc_scsi.h index 5e836d36da..d8cacdd49d 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/msc_scsi.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/msc_scsi.h @@ -3,32 +3,34 @@ \brief definitions for the USB MSC SCSI commands \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/usb_msc.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/usb_msc.h index 541bfb037b..e032a7621d 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/usb_msc.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/class/msc/usb_msc.h @@ -3,32 +3,34 @@ \brief definitions for the USB MSC class \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/common/usb_ch9_std.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/common/usb_ch9_std.h index c52931c91e..bf0fe0aa39 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/common/usb_ch9_std.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/ustd/common/usb_ch9_std.h @@ -3,32 +3,34 @@ \brief USB 2.0 standard defines \version 2020-08-01, V3.0.0, firmware for GD32F4xx + \version 2022-03-09, V3.1.0, firmware for GD32F4xx + \version 2022-06-30, V3.2.0, firmware for GD32F4xx */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -237,7 +239,7 @@ typedef struct _usb_desc_LANGID { typedef struct _usb_desc_str { usb_desc_header header; /*!< descriptor header, including type and size. */ - uint16_t unicode_string[64]; /*!< unicode string data */ + uint16_t unicode_string[128]; /*!< unicode string data */ } usb_desc_str; #pragma pack() diff --git a/components/net/netdev/src/netdev.c b/components/net/netdev/src/netdev.c index 44eecea6b8..b41351dd39 100644 --- a/components/net/netdev/src/netdev.c +++ b/components/net/netdev/src/netdev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 *