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Merge remote-tracking branch 'rtt_gitee/gitee_master'

This commit is contained in:
rtthread-bot 2021-09-23 16:24:09 +00:00
parent cf82025470 5e643ff619
commit 240f67d145
323 changed files with 159082 additions and 90 deletions
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1
.gitignore vendored
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@ -10,6 +10,7 @@
*.idb
*.ilk
*.old
*.crf
build
Debug
documentation/html

596
bsp/Vango_V85xx/.config Normal file
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@ -0,0 +1,596 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_RT_LINK is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
#
# system packages
#
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_WCWIDTH is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_TERMBOX is not set
CONFIG_SOC_SERIES_V85XX=y
CONFIG_SOC_V85XX=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
# CONFIG_BSP_USING_UART0 is not set
# CONFIG_BSP_USING_UART1 is not set
CONFIG_BSP_USING_UART2=y
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_HWTIMER is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_RTC is not set

6
bsp/Vango_V85xx/.ignore_format.yml Normal file
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# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- Libraries/VangoV85xx_standard_peripheral

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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default: "rt-thread"
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_SERIES_V85XX
bool
default y
config SOC_V85XX
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select SOC_SERIES_V85XX
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "using uart0"
default n
config BSP_USING_UART1
bool "using uart1"
default n
config BSP_USING_UART2
bool "using uart2"
default y
config BSP_USING_UART3
bool "using uart3"
default n
config BSP_USING_UART4
bool "using uart4"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "using adc0"
default n
config BSP_USING_ADC1
bool "using adc1"
default n
endif
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
select RT_USING_HWTIMER
if BSP_USING_HWTIMER
config BSP_USING_HWTIMER0
bool "using hwtimer0"
default n
config BSP_USING_HWTIMER1
bool "using hwtimer1"
default n
config BSP_USING_HWTIMER2
bool "using hwtimer2"
default n
config BSP_USING_HWTIMER3
bool "using hwtimer3"
default n
config BSP_USING_HWTIMER4
bool "using hwtimer4"
default n
config BSP_USING_HWTIMER5
bool "using hwtimer5"
default n
config BSP_USING_HWTIMER6
bool "using hwtimer6"
default n
config BSP_USING_HWTIMER7
bool "using hwtimer7"
default n
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_RTC
bool "using internal rtc"
default n
select RT_USING_RTC
endmenu

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/**
******************************************************************************
* @file lib_CodeRAM.h
* @author Application Team
* @version V4.4.0
* @date 2019-01-18
* @brief Codes executed in SRAM.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CODERAM_H
#define __LIB_CODERAM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
#ifndef __GNUC__
#ifdef __ICCARM__ /* EWARM */
#define __RAM_FUNC __ramfunc
#endif
#ifdef __CC_ARM /* MDK-ARM */
#define __RAM_FUNC __attribute__((used))
#endif
/* Exported Functions ------------------------------------------------------- */
__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void);
#endif /* __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CODERAM_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_LoadNVR.h
* @author Application Team
* @version V4.7.0
* @date 2019-12-12
* @brief Load information from NVR.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_LOADNVR_H
#define __LIB_LOADNVR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
/* BAT measure result */
typedef struct
{
float BATRESResult; // BAT Resistor division Measure Result
float BATCAPResult; // BATRTC Cap division Measure Result
} NVR_BATMEARES;
/* Power Measure Result */
typedef struct
{
uint32_t AVCCMEAResult; // LDO33 Measure Result
uint32_t DVCCMEAResult; // LDO15 Measure Result
uint32_t BGPMEAResult; // BGP Measure Result
uint32_t RCLMEAResult; // RCL Measure Result
uint32_t RCHMEAResult; // RCH Measure Result
} NVR_MISCGain;
/* Chip ID */
typedef struct
{
uint32_t ChipID0; // ID word 0
uint32_t ChipID1; // ID word 1
} NVR_CHIPID;
/* Temperature information */
typedef struct
{
float TempOffset;
} NVR_TEMPINFO;
/* LCD information */
typedef struct
{
uint32_t MEALCDLDO; // Measure LCD LDO pre trim value
uint32_t MEALCDVol; // VLCD setting
} NVR_LCDINFO;
/* RTC(temp) information */
typedef struct
{
int16_t RTCTempP0; //P0
int16_t RTCTempP1; //P1
int32_t RTCTempP2; //P2
int16_t RTCTempP4; //P4
int16_t RTCTempP5; //P5
int16_t RTCTempP6; //P6
int16_t RTCTempP7; //P7
int16_t RTCTempK1; //K1
int16_t RTCTempK2; //K2
int16_t RTCTempK3; //K3
int16_t RTCTempK4; //K4
int16_t RTCTempK5; //K5
int16_t RTCACTI; //Center temperature
uint32_t RTCACKTemp; //section X temperature
int16_t RTCTempDelta; //Temperature delta
uint32_t RTCACF200; //RTC_ACF200
uint32_t APBClock; //APB clock
} NVR_RTCINFO;
/* ADC Voltage Parameters */
typedef struct
{
float aParameter;
float bParameter;
} NVR_ADCVOLPARA;
//Mode
#define NVR_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None
#define NVR_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive
#define NVR_3V_EXTERNAL_CAPDIV (0x002UL) // Power supply: 3.3V; Channel: External; Divider modeL: Capacitive
#define NVR_3V_VDD_RESDIV (0x003UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive
#define NVR_3V_VDD_CAPDIV (0x004UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Capacitive
#define NVR_3V_BATRTC_RESDIV (0x005UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive
#define NVR_3V_BATRTC_CAPDIV (0x006UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Capacitive
#define NVR_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None
#define NVR_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive
#define NVR_5V_EXTERNAL_CAPDIV (0x102UL) // Power supply: 5V; Channel: External; Divider modeL: Capacitive
#define NVR_5V_VDD_RESDIV (0x103UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive
#define NVR_5V_VDD_CAPDIV (0x104UL) // Power supply: 5V; Channel: VDD; Divider modeL: Capacitive
#define NVR_5V_BATRTC_RESDIV (0x105UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive
#define NVR_5V_BATRTC_CAPDIV (0x106UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Capacitive
#define IS_NVR_ADCVOL_MODE(__MODE__) (((__MODE__) == NVR_3V_EXTERNAL_NODIV) ||\
((__MODE__) == NVR_3V_EXTERNAL_RESDIV) ||\
((__MODE__) == NVR_3V_EXTERNAL_CAPDIV) ||\
((__MODE__) == NVR_3V_VDD_RESDIV) ||\
((__MODE__) == NVR_3V_VDD_CAPDIV) ||\
((__MODE__) == NVR_3V_BATRTC_RESDIV) ||\
((__MODE__) == NVR_3V_BATRTC_CAPDIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_NODIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_RESDIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_CAPDIV) ||\
((__MODE__) == NVR_5V_VDD_RESDIV) ||\
((__MODE__) == NVR_5V_VDD_CAPDIV) ||\
((__MODE__) == NVR_5V_BATRTC_RESDIV) ||\
((__MODE__) == NVR_5V_BATRTC_CAPDIV))
/********** NVR Address **********/
//ADC Voltage Parameters
#define NVR_3VPARA_BASEADDR1 (__IO uint32_t *)(0x40400)
#define NVR_3VPARA_BASEADDR2 (__IO uint32_t *)(0x40440)
#define NVR_5VPARA_BASEADDR1 (__IO uint32_t *)(0x40480)
#define NVR_5VPARA_BASEADDR2 (__IO uint32_t *)(0x404C0)
//RTC DATA
//P4
#define NVR_RTC1_P4 (__IO uint32_t *)(0x40800)
#define NVR_RTC1_P4_CHKSUM (__IO uint32_t *)(0x40804)
#define NVR_RTC2_P4 (__IO uint32_t *)(0x40808)
#define NVR_RTC2_P4_CHKSUM (__IO uint32_t *)(0x4080C)
//ACK1~ACK5
#define NVR_RTC1_ACK1 (__IO uint32_t *)(0x40810)
#define NVR_RTC1_ACK2 (__IO uint32_t *)(0x40814)
#define NVR_RTC1_ACK3 (__IO uint32_t *)(0x40818)
#define NVR_RTC1_ACK4 (__IO uint32_t *)(0x4081C)
#define NVR_RTC1_ACK5 (__IO uint32_t *)(0x40820)
#define NVR_RTC1_ACK_CHKSUM (__IO uint32_t *)(0x40824)
#define NVR_RTC2_ACK1 (__IO uint32_t *)(0x40828)
#define NVR_RTC2_ACK2 (__IO uint32_t *)(0x4082C)
#define NVR_RTC2_ACK3 (__IO uint32_t *)(0x40830)
#define NVR_RTC2_ACK4 (__IO uint32_t *)(0x40834)
#define NVR_RTC2_ACK5 (__IO uint32_t *)(0x40838)
#define NVR_RTC2_ACK_CHKSUM (__IO uint32_t *)(0x4083C)
//ACTI
#define NVR_RTC1_ACTI (__IO uint32_t *)(0x40840)
#define NVR_RTC1_ACTI_CHKSUM (__IO uint32_t *)(0x40844)
#define NVR_RTC2_ACTI (__IO uint32_t *)(0x40848)
#define NVR_RTC2_ACTI_CHKSUM (__IO uint32_t *)(0x4084C)
//ACKTEMP
#define NVR_RTC1_ACKTEMP (__IO uint32_t *)(0x40850)
#define NVR_RTC1_ACKTEMP_CHKSUM (__IO uint32_t *)(0x40854)
#define NVR_RTC2_ACKTEMP (__IO uint32_t *)(0x40858)
#define NVR_RTC2_ACKTEMP_CHKSUM (__IO uint32_t *)(0x4085C)
//Analog trim data
#define NVR_ANA_TRIMDATA1 (__IO uint32_t *)(0x40DC0)
#define NVR_ANA_OPREG1 (__IO uint32_t *)(0x40DC4)
#define NVR_ANA_KEYREG1 (__IO uint32_t *)(0x40DC8)
#define NVR_ANA_CHECKSUM1 (__IO uint32_t *)(0x40DCC)
#define NVR_ANA_TRIMDATA2 (__IO uint32_t *)(0x40DD0)
#define NVR_ANA_OPREG2 (__IO uint32_t *)(0x40DD4)
#define NVR_ANA_KEYREG2 (__IO uint32_t *)(0x40DD8)
#define NVR_ANA_CHECKSUM2 (__IO uint32_t *)(0x40DDC)
//BAT Measure Result
#define NVR_BAT_R1 (__IO uint32_t *)(0x40CE0)
#define NVR_BAT_C1 (__IO uint32_t *)(0x40CE4)
#define NVR_BATMEA_CHECHSUM1 (__IO uint32_t *)(0x40CE8)
#define NVR_BAT_R2 (__IO uint32_t *)(0x40CF0)
#define NVR_BAT_C2 (__IO uint32_t *)(0x40CF4)
#define NVR_BATMEA_CHECHSUM2 (__IO uint32_t *)(0x40CF8)
//RTC AutoCal Px pramameters
#define NVR_RTC1_P1_P0 (__IO uint32_t *)(0x40D00)
#define NVR_RTC1_P2 (__IO uint32_t *)(0x40D04)
#define NVR_RTC1_P5_P4 (__IO uint32_t *)(0x40D08)
#define NVR_RTC1_P7_P6 (__IO uint32_t *)(0x40D0C)
#define NVR_RTC1_PCHECHSUM (__IO uint32_t *)(0x40D10)
#define NVR_RTC2_P1_P0 (__IO uint32_t *)(0x40D14)
#define NVR_RTC2_P2 (__IO uint32_t *)(0x40D18)
#define NVR_RTC2_P5_P4 (__IO uint32_t *)(0x40D1C)
#define NVR_RTC2_P7_P6 (__IO uint32_t *)(0x40D20)
#define NVR_RTC2_PCHECHSUM (__IO uint32_t *)(0x40D24)
//Power Measure Result
#define NVR_DVCC_MEA1 (__IO uint32_t *)(0x40D28)
#define NVR_AVCC_MEA1 (__IO uint32_t *)(0x40D2C)
#define NVR_BGP_MEA1 (__IO uint32_t *)(0x40D30)
#define NVR_RCL_MEA1 (__IO uint32_t *)(0x40D34)
#define NVR_RCH_MEA1 (__IO uint32_t *)(0x40D38)
#define NVR_PWR_CHECKSUM1 (__IO uint32_t *)(0x40D3C)
#define NVR_DVCC_MEA2 (__IO uint32_t *)(0x40D40)
#define NVR_AVCC_MEA2 (__IO uint32_t *)(0x40D44)
#define NVR_BGP_MEA2 (__IO uint32_t *)(0x40D48)
#define NVR_RCL_MEA2 (__IO uint32_t *)(0x40D4C)
#define NVR_RCH_MEA2 (__IO uint32_t *)(0x40D50)
#define NVR_PWR_CHECKSUM2 (__IO uint32_t *)(0x40D54)
//Chip ID
#define NVR_CHIP1_ID0 (__IO uint32_t *)(0x40D58)
#define NVR_CHIP1_ID1 (__IO uint32_t *)(0x40D5C)
#define NVR_CHIP1_CHECKSUM (__IO uint32_t *)(0x40D60)
#define NVR_CHIP2_ID0 (__IO uint32_t *)(0x40D64)
#define NVR_CHIP2_ID1 (__IO uint32_t *)(0x40D68)
#define NVR_CHIP2_CHECKSUM (__IO uint32_t *)(0x40D6C)
//Temperature information
#define NVR_REALTEMP1 (__IO uint32_t *)(0x40D70)
#define NVR_MEATEMP1 (__IO uint32_t *)(0x40D74)
#define NVR_TEMP_CHECKSUM1 (__IO uint32_t *)(0x40D78)
#define NVR_REALTEMP2 (__IO uint32_t *)(0x40D7C)
#define NVR_MEATEMP2 (__IO uint32_t *)(0x40D80)
#define NVR_TEMP_CHECKSUM2 (__IO uint32_t *)(0x40D84)
//LCD Information
#define NVR_LCD_LDO1 (__IO uint32_t *)(0x40D90)
#define NVR_LCD_VOL1 (__IO uint32_t *)(0x40D94)
#define NVR_LCD_CHECKSUM1 (__IO uint32_t *)(0x40D98)
#define NVR_LCD_LDO2 (__IO uint32_t *)(0x40D9C)
#define NVR_LCD_VOL2 (__IO uint32_t *)(0x40DA0)
#define NVR_LCD_CHECKSUM2 (__IO uint32_t *)(0x40DA4)
uint32_t NVR_LoadANADataManual(void);
uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter);
uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult);
uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData);
uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult);
uint32_t NVR_GetChipID(NVR_CHIPID *ChipID);
uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_LOADNVR_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_conf.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Dirver configuration.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CONF_H
#define __LIB_CONF_H
/* ########################## Assert Selection ############################## */
//#define ASSERT_NDEBUG 1
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#include "lib_ana.h"
#include "lib_adc.h"
#include "lib_adc_tiny.h"
#include "lib_clk.h"
#include "lib_comp.h"
#include "lib_crypt.h"
#include "lib_dma.h"
#include "lib_flash.h"
#include "lib_gpio.h"
#include "lib_i2c.h"
#include "lib_iso7816.h"
#include "lib_lcd.h"
#include "lib_misc.h"
#include "lib_pmu.h"
#include "lib_pwm.h"
#include "lib_rtc.h"
#include "lib_spi.h"
#include "lib_tmr.h"
#include "lib_u32k.h"
#include "lib_uart.h"
#include "lib_version.h"
#include "lib_wdt.h"
#include "lib_LoadNVR.h"
#include "lib_CodeRAM.h"
#include "lib_cortex.h"
/* Exported macro ------------------------------------------------------------*/
#ifndef ASSERT_NDEBUG
#define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_errhandler(uint8_t* file, uint32_t line);
#else
#define assert_parameters(expr) ((void)0U)
#endif /* ASSERT_NDEBUG */
#endif
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_Cortex.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Cortex module driver.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CORTEX_H
#define __LIB_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
/* Exported Functions ------------------------------------------------------- */
void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority);
void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn);
uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn);
void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority);
void CORTEX_NVIC_SystemReset(void);
uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CORTEX_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file system_target.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief system source file.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __SYSTEM_TARGET_H
#define __SYSTEM_TARGET_H
#ifdef __cplusplus
extern "C" {
#endif
#include "type_def.h"
#define NVR_REGINFOCOUNT1 (0x80400)
#define NVR_REGINFOBAKOFFSET (0x100)
/* ########################### System Configuration ######################### */
extern void SystemInit(void);
extern void SystemUpdate(void);
#ifdef USE_TARGET_DRIVER
#include "lib_conf.h"
#endif /* USE_TARGET_DRIVER */
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_TARGET_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file type_def.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Typedef file
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __TYPE_DEF_H
#define __TYPE_DEF_H
#define ENABLE 1
#define DISABLE 0
#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE))
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#endif /* __TYPE_DEF_H */
/*********************************** END OF FILE ******************************/

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;/**
;* @file startup_target.s
;* @author Application Team
;* @version V1.1.0
;* @date 2019-10-28
;* @brief Target Devices vector table.
;******************************************************************************/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.equ __CHIPINITIAL, 1
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/*************************************************************************
* Chip init.
* 1. Load flash configuration
* 2. Load ANA_REG(B/C/D/E) information
* 3. Load ANA_REG10 information
**************************************************************************/
.if (__CHIPINITIAL != 0)
.section .chipinit_section.__CHIP_INIT
__CHIP_INIT:
CONFIG1_START:
/*-------------------------------*/
/* 1. Load flash configuration */
/* Unlock flash */
LDR R0, =0x000FFFE0
LDR R1, =0x55AAAA55
STR R1, [R0]
/* Load configure word 0 to 7
Compare bit[7:0] */
LDR R0, =0x00080E00
LDR R1, =0x20
LDR R2, =0x000FFFE8
LDR R3, =0x000FFFF0
LDR R4, =0x0
LDR R7, =0x0FF
FLASH_CONF_START_1:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_AGAIN_1:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_1:
BNE FLASH_CONF_WHILELOOP_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_END_1:
/* Load configure word 8 to 11
Compare bit 31,24,23:16,8,7:0 */
LDR R1, =0x30
LDR R7, =0x81FF81FF
FLASH_CONF_START_2:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_AGAIN_2:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_2:
BNE FLASH_CONF_WHILELOOP_2
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_END_2:
/* Lock flash */
LDR R0, =0x000FFFE0
LDR R1, =0x0
STR R1, [R0]
/*-------------------------------*/
/* 2. Load ANA_REG(B/C/D/E) information */
CONFIG2_START:
LDR R4, =0x4001422C
LDR R5, =0x40014230
LDR R6, =0x40014234
LDR R7, =0x40014238
LDR R0, =0x80DC0
LDR R0, [R0]
LDR R1, =0x80DC4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DCC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM1_OK
B ANADAT_CHECKSUM1_ERR
ANADAT_CHECKSUM1_OK:
/* ANA_REGB */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
/* ANA_REGC */
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
/* ANA_REGD */
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
/* ANA_REGE */
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM1_ERR:
LDR R0, =0x80DD0
LDR R0, [R0]
LDR R1, =0x80DD4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DDC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM2_OK
B ANADAT_CHECKSUM2_ERR
ANADAT_CHECKSUM2_OK:
/* ANA_REGB */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
/* ANA_REGC */
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
/* ANA_REGD */
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
/* ANA_REGE */
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM2_ERR:
B ANADAT_CHECKSUM2_ERR
/*-------------------------------*/
/* 3. Load ANA_REG10 information */
CONFIG3_START:
LDR R7, =0x40014240
LDR R0, =0x80DE0
LDR R0, [R0]
LDR R1, =0x80DE4
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM1_OK
B ANADAT10_CHECKSUM1_ERR
ANADAT10_CHECKSUM1_OK:
/* ANA_REG10 */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM1_ERR:
LDR R0, =0x80DE8
LDR R0, [R0]
LDR R1, =0x80DEC
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM2_OK
B ANADAT10_CHECKSUM2_ERR
ANADAT10_CHECKSUM2_OK:
/* ANA_REG10 */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM2_ERR:
B ANADAT10_CHECKSUM2_ERR
.size __CHIP_INIT, .-__CHIP_INIT
.endif
.if (__CHIPINITIAL != 0)
.global __CHIP_INIT
.section .chipinit_section.Reset_Handler
.else
.section .text.Reset_Handler
.endif
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.if (__CHIPINITIAL != 0)
/* Chip Initiliazation */
bl __CHIP_INIT
/* System Initiliazation */
bl SystemInit
.endif
/* set stack pointer */
ldr r0, =_estack
mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word PMU_IRQHandler /* 0: PMU */
.word RTC_IRQHandler /* 1: RTC */
.word U32K0_IRQHandler /* 2: U32K0 */
.word U32K1_IRQHandler /* 3: U32K1 */
.word I2C_IRQHandler /* 4: I2C */
.word SPI1_IRQHandler /* 5: SPI1 */
.word UART0_IRQHandler /* 6: UART0 */
.word UART1_IRQHandler /* 7: UART1 */
.word UART2_IRQHandler /* 8: UART2 */
.word UART3_IRQHandler /* 9: UART3 */
.word UART4_IRQHandler /* 10: UART4 */
.word UART5_IRQHandler /* 11: UART5 */
.word ISO78160_IRQHandler /* 12: ISO78160 */
.word ISO78161_IRQHandler /* 13: ISO78161 */
.word TMR0_IRQHandler /* 14: TMR0 */
.word TMR1_IRQHandler /* 15: TMR1 */
.word TMR2_IRQHandler /* 16: TMR2 */
.word TMR3_IRQHandler /* 17: TMR3 */
.word PWM0_IRQHandler /* 18: PWM0 */
.word PWM1_IRQHandler /* 19: PWM1 */
.word PWM2_IRQHandler /* 20: PWM2 */
.word PWM3_IRQHandler /* 21: PWM3 */
.word DMA_IRQHandler /* 22: DMA */
.word FLASH_IRQHandler /* 23: FLASH */
.word ANA_IRQHandler /* 24: ANA */
.word 0 /* 25: Reserved */
.word 0 /* 26: Reserved */
.word SPI2_IRQHandler /* 27: SPI2 */
.word SPI3_IRQHandler /* 28: SPI3 */
.word 0 /* 29: Reserved */
.word 0 /* 30: Reserved */
.word 0 /* 31: Reserved */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak PMU_IRQHandler
.thumb_set PMU_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak U32K0_IRQHandler
.thumb_set U32K0_IRQHandler,Default_Handler
.weak U32K1_IRQHandler
.thumb_set U32K1_IRQHandler,Default_Handler
.weak I2C_IRQHandler
.thumb_set I2C_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak UART0_IRQHandler
.thumb_set UART0_IRQHandler,Default_Handler
.weak UART1_IRQHandler
.thumb_set UART1_IRQHandler,Default_Handler
.weak UART2_IRQHandler
.thumb_set UART2_IRQHandler,Default_Handler
.weak UART3_IRQHandler
.thumb_set UART3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak ISO78160_IRQHandler
.thumb_set ISO78160_IRQHandler,Default_Handler
.weak ISO78161_IRQHandler
.thumb_set ISO78161_IRQHandler,Default_Handler
.weak TMR0_IRQHandler
.thumb_set TMR0_IRQHandler,Default_Handler
.weak TMR1_IRQHandler
.thumb_set TMR1_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak PWM0_IRQHandler
.thumb_set PWM0_IRQHandler,Default_Handler
.weak PWM1_IRQHandler
.thumb_set PWM1_IRQHandler,Default_Handler
.weak PWM2_IRQHandler
.thumb_set PWM2_IRQHandler,Default_Handler
.weak PWM3_IRQHandler
.thumb_set PWM3_IRQHandler,Default_Handler
.weak DMA_IRQHandler
.thumb_set DMA_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak ANA_IRQHandler
.thumb_set ANA_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler

450
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;/**
;* @file startup_target.s
;* @author Application Team
;* @version V1.1.0
;* @date 2019-10-28
;* @brief Target Devices vector table.
;******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
__CHIPINITIAL EQU 1
Stack_Size EQU 0x000001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PMU_IRQHandler ; 0: PMU
DCD RTC_IRQHandler ; 1: RTC
DCD U32K0_IRQHandler ; 2: U32K0
DCD U32K1_IRQHandler ; 3: U32K1
DCD I2C_IRQHandler ; 4: I2C
DCD SPI1_IRQHandler ; 5: SPI1
DCD UART0_IRQHandler ; 6: UART0
DCD UART1_IRQHandler ; 7: UART1
DCD UART2_IRQHandler ; 8: UART2
DCD UART3_IRQHandler ; 9: UART3
DCD UART4_IRQHandler ; 10: UART4
DCD UART5_IRQHandler ; 11: UART5
DCD ISO78160_IRQHandler ; 12: ISO78160
DCD ISO78161_IRQHandler ; 13: ISO78161
DCD TMR0_IRQHandler ; 14: TMR0
DCD TMR1_IRQHandler ; 15: TMR1
DCD TMR2_IRQHandler ; 16: TMR2
DCD TMR3_IRQHandler ; 17: TMR3
DCD PWM0_IRQHandler ; 18: PWM0
DCD PWM1_IRQHandler ; 19: PWM1
DCD PWM2_IRQHandler ; 20: PWM2
DCD PWM3_IRQHandler ; 21: PWM3
DCD DMA_IRQHandler ; 22: DMA
DCD FLASH_IRQHandler ; 23: FLASH
DCD ANA_IRQHandler ; 24: ANA
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD SPI2_IRQHandler ; 27: SPI2
DCD SPI3_IRQHandler ; 28: SPI3
DCD 0 ; 29: Reserved
DCD 0 ; 30: Reserved
DCD 0 ; 31: Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
IF (__CHIPINITIAL != 0)
AREA |.ARM.__AT_0xC0|, CODE, READONLY
ELSE
AREA |.text|, CODE, READONLY
ENDIF
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
IF (__CHIPINITIAL != 0)
LDR R0, =__CHIP_INIT
BLX R0
ENDIF
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
AREA |.text|, CODE, READONLY
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PMU_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT U32K0_IRQHandler [WEAK]
EXPORT U32K1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT ISO78160_IRQHandler [WEAK]
EXPORT ISO78161_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
EXPORT PWM3_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT ANA_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
PMU_IRQHandler
RTC_IRQHandler
U32K0_IRQHandler
U32K1_IRQHandler
I2C_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
ISO78160_IRQHandler
ISO78161_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
PWM0_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
PWM3_IRQHandler
DMA_IRQHandler
FLASH_IRQHandler
ANA_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Chip init.
;; 1. Load flash configuration
;; 2. Load ANA_REG(B/C/D/E) information
;; 3. Load ANA_REG10 information
IF (__CHIPINITIAL != 0)
AREA |.ARM.__AT_0xC0|, CODE, READONLY
__CHIP_INIT PROC
CONFIG1_START
;-------------------------------;
;; 1. Load flash configuration
; Unlock flash
LDR R0, =0x000FFFE0
LDR R1, =0x55AAAA55
STR R1, [R0]
; Load configure word 0 to 7
; Compare bit[7:0]
LDR R0, =0x00080E00
LDR R1, =0x20
LDR R2, =0x000FFFE8
LDR R3, =0x000FFFF0
LDR R4, =0x0
LDR R7, =0x0FF
FLASH_CONF_START_1
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_AGAIN_1
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_1
BNE FLASH_CONF_WHILELOOP_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_END_1
; Load configure word 8 to 11
; Compare bit 31,24,23:16,8,7:0
LDR R1, =0x30
LDR R7, =0x81FF81FF
FLASH_CONF_START_2
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_AGAIN_2
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_2
BNE FLASH_CONF_WHILELOOP_2
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_END_2
; Lock flash
LDR R0, =0x000FFFE0
LDR R1, =0x0
STR R1, [R0]
;-------------------------------;
;; 2. Load ANA_REG(B/C/D/E) information
CONFIG2_START
LDR R4, =0x4001422C
LDR R5, =0x40014230
LDR R6, =0x40014234
LDR R7, =0x40014238
LDR R0, =0x80DC0
LDR R0, [R0]
LDR R1, =0x80DC4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DCC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM1_OK
B ANADAT_CHECKSUM1_ERR
ANADAT_CHECKSUM1_OK
; ANA_REGB
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
; ANA_REGC
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
; ANA_REGD
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
; ANA_REGE
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM1_ERR
LDR R0, =0x80DD0
LDR R0, [R0]
LDR R1, =0x80DD4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DDC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM2_OK
B ANADAT_CHECKSUM2_ERR
ANADAT_CHECKSUM2_OK
; ANA_REGB
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
; ANA_REGC
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
; ANA_REGD
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
; ANA_REGE
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM2_ERR
B ANADAT_CHECKSUM2_ERR
;-------------------------------;
;; 2. Load ANA_REG10 information
CONFIG3_START
LDR R7, =0x40014240
LDR R0, =0x80DE0
LDR R0, [R0]
LDR R1, =0x80DE4
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM1_OK
B ANADAT10_CHECKSUM1_ERR
ANADAT10_CHECKSUM1_OK
; ANA_REG10
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM1_ERR
LDR R0, =0x80DE8
LDR R0, [R0]
LDR R1, =0x80DEC
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM2_OK
B ANADAT10_CHECKSUM2_ERR
ANADAT10_CHECKSUM2_OK
; ANA_REG10
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM2_ERR
B ANADAT10_CHECKSUM2_ERR
NOP
ENDP
ENDIF
END
/*********************************** END OF FILE ******************************/

35
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c Normal file
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/**
******************************************************************************
* @file lib_CodeRAM.c
* @author Application Team
* @version V4.4.0
* @date 2019-01-18
* @brief Codes executed in SRAM.
******************************************************************************
* @attention
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_CodeRAM.h"
#ifndef __GNUC__
/**
* @brief Flash deep standby, enter idle mode.
* @note This function is executed in RAM.
* @param None
* @retval None
*/
__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void)
{
/* Flash deep standby */
FLASH->PASS = 0x55AAAA55;
FLASH->DSTB = 0xAA5555AA;
/* Enter Idle mode */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
__WFI();
}
#endif
/*********************************** END OF FILE ******************************/

648
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/**
******************************************************************************
* @file lib_LoadNVR.c
* @author Application Team
* @version V4.7.0
* @date 2019-12-12
* @brief Load information from NVR.
******************************************************************************
* @attention
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_LoadNVR.h"
/**
* @breif Load Analog trim data from NVR manually.
* @note Successful Operation:
* - Load [0x40DC0] or [0x40DD0] to ANA registers(B C D E), return 0.
* Operation failed:
* - return 1.
* @param None
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_LoadANADataManual(void)
{
uint32_t checksum;
uint32_t op_reg;
uint32_t ana_data;
uint32_t key_reg = 0xFFFFFFFF;
/* Get Analog data1 */
ana_data = *NVR_ANA_TRIMDATA1;
op_reg = *NVR_ANA_OPREG1;
/* Calculate checksum1 */
checksum = ~(ana_data + op_reg + key_reg);
/* Compare checksum1 */
if (checksum == (*NVR_ANA_CHECKSUM1))
{
ANA->REGB = (uint8_t)(ana_data);
ANA->REGC = (uint8_t)(ana_data >> 8);
ANA->REGD = (uint8_t)(ana_data >> 16);
ANA->REGE = (uint8_t)(ana_data >> 24);
return 0;
}
/* Get Analog data2 */
ana_data = *NVR_ANA_TRIMDATA2;
op_reg = *NVR_ANA_OPREG2;
/* Calculate checksum2 */
checksum = ~(ana_data + op_reg + key_reg);
/* Compare checksum2 */
if (checksum == (*NVR_ANA_CHECKSUM2))
{
ANA->REGB = (uint8_t)(ana_data);
ANA->REGC = (uint8_t)(ana_data >> 8);
ANA->REGD = (uint8_t)(ana_data >> 16);
ANA->REGE = (uint8_t)(ana_data >> 24);
return 0;
}
else
{
return 1;
}
}
/**
* @breif Get the parameters of ADC voltage measuring.
* @note Voltage(unit:V) = aParameter*ADC_DATA + bParameter
* ADC_DATA: ADC channel original data
* aParameter/bParameter: Get from this function
* @param [in]Mode:
* NVR_3V_EXTERNAL_NODIV
* NVR_3V_EXTERNAL_RESDIV
* NVR_3V_EXTERNAL_CAPDIV
* NVR_3V_VDD_RESDIV
* NVR_3V_VDD_CAPDIV
* NVR_3V_BATRTC_RESDIV
* NVR_3V_BATRTC_CAPDIV
* NVR_5V_EXTERNAL_NODIV
* NVR_5V_EXTERNAL_RESDIV
* NVR_5V_EXTERNAL_CAPDIV
* NVR_5V_VDD_RESDIV
* NVR_5V_VDD_CAPDIV
* NVR_5V_BATRTC_RESDIV
* NVR_5V_BATRTC_CAPDIV
* @param [out]Parameter: The parameters get from NVR
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter)
{
uint32_t checksum;
uint32_t i;
int32_t tmp_int;
/* Check the parameters */
assert_parameters(IS_NVR_ADCVOL_MODE(Mode));
/*----- Power supply: 5V -----*/
if (0x100UL & Mode)
{
checksum = 0UL;
for (i=0; i<14; i++)
checksum += *(NVR_5VPARA_BASEADDR1+i);
checksum = ~(checksum);
if (checksum != *(NVR_5VPARA_BASEADDR1+i)) /* Checksum1 error */
{
checksum = 0UL;
for (i=0; i<14; i++)
checksum += *(NVR_5VPARA_BASEADDR2+i);
checksum = ~(checksum);
if (checksum != *(NVR_5VPARA_BASEADDR2+i)) /* Checksum2 error */
{
return 1;
}
else
{
tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL));
Parameter->aParameter = (float)(tmp_int / 100000000.0);
tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL)+1);
Parameter->bParameter = (float)(tmp_int / 100000000.0);
return 0;
}
}
else
{
tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL));
Parameter->aParameter = (float)(tmp_int / 100000000.0);
tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL)+1);
Parameter->bParameter = (float)(tmp_int / 100000000.0);
return 0;
}
}
/*----- Power supply: 3.3V -----*/
else
{
checksum = 0UL;
for (i=0; i<14; i++)
checksum += *(NVR_3VPARA_BASEADDR1+i);
checksum = ~(checksum);
if (checksum != *(NVR_3VPARA_BASEADDR1+i)) /* Checksum1 error */
{
checksum = 0UL;
for (i=0; i<14; i++)
checksum += *(NVR_3VPARA_BASEADDR2+i);
checksum = ~(checksum);
if (checksum != *(NVR_3VPARA_BASEADDR2+i)) /* Checksum2 error */
{
return 1;
}
else
{
tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode));
Parameter->aParameter = (float)(tmp_int / 100000000.0);
tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode)+1);
Parameter->bParameter = (float)(tmp_int / 100000000.0);
return 0;
}
}
else
{
tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode));
Parameter->aParameter = (float)(tmp_int / 100000000.0);
tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode)+1);
Parameter->bParameter = (float)(tmp_int / 100000000.0);
return 0;
}
}
}
/**
* @breif Get BAT Measure result.
* @param [out]MEAResult The pointer to struct NVR_BATMEARES.
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult)
{
uint32_t bat_r;
uint32_t bat_c;
uint32_t checksum;
bat_r = *NVR_BAT_R1;
bat_c = *NVR_BAT_C1;
/* Calculate checksum1 */
checksum = ~(bat_r + bat_c);
if (checksum == (*NVR_BATMEA_CHECHSUM1))
{
MEAResult->BATRESResult = (float)((int32_t)bat_r / 1000.0);
MEAResult->BATCAPResult = (float)((int32_t)bat_c / 1000.0);
return 0;
}
bat_r = *NVR_BAT_R2;
bat_c = *NVR_BAT_C2;
/* Calculate checksum2 */
checksum = ~(bat_r + bat_c);
if (checksum == (*NVR_BATMEA_CHECHSUM2))
{
MEAResult->BATRESResult = (float)((int32_t)bat_r / 1000.0);
MEAResult->BATCAPResult = (float)((int32_t)bat_c / 1000.0);
return 0;
}
else
{
return 1;
}
}
/**
* @breif Load RTC ACPx pramameters from NVR to RTC registers.
Get RTC pramameters.
* @param [out]RTCTempData The pointer to struct NVR_RTCINFO.
* @retval 0: Function succeeded.
!0: Function not succeeded, load default value to registers.
bit[0]=1: Temperature Measure delta information checksum error, default value is 0.
bit[1]=1: P paramters checksum error, default value as follows
[P0]-214, [P1]1060, [P2]-19746971, [P5]6444, [P6]1342, [P7]0
bit[2]=1: P4 checksum error, default value is 0
bit[3]=1: ACKx checksum error, default value as follows
[K1]20827, [K2]21496, [K3]22020, [K4]24517, [K5]25257
bit[4]=1: ACTI checksum error, default value is 0x1800(24.0)
bit[5]=1: ACKTEMP checksum error, defalut value is 0x3C2800EC
*/
uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData)
{
uint32_t real_temp, mea_temp;
uint32_t rtc_data1, rtc_data2, rtc_data3, rtc_data4;
uint32_t rtc_p4;
uint32_t rtc_ack[5];
uint32_t rtc_acti;
uint32_t rtc_acktemp;
uint32_t checksum;
float pclk_mul;
int16_t TempDelta;
uint32_t retval = 0;
/*------------------------ Temperature Measure delta -------------------------*/
real_temp = *NVR_REALTEMP1;
mea_temp = *NVR_MEATEMP1;
/* Calculate checksum1 */
checksum = ~(real_temp + mea_temp);
if (checksum == (*NVR_TEMP_CHECKSUM1)) //checksum1 true
{
TempDelta = (int16_t)real_temp - (int16_t)mea_temp;
}
else
{
real_temp = *NVR_REALTEMP2;
mea_temp = *NVR_MEATEMP2;
/* Calculate checksum2 */
checksum = ~(real_temp + mea_temp);
if (checksum == (*NVR_TEMP_CHECKSUM2)) //checksum2 true
{
TempDelta = (int16_t)real_temp - (int16_t)mea_temp;
}
else
{
TempDelta = 0;
retval |= BIT0;
}
}
/* Get Measure delta information */
RTCTempData->RTCTempDelta = TempDelta;
/*------------------------------ P parameters --------------------------------*/
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
/* Get PCLK */
RTCTempData->APBClock = CLK_GetPCLKFreq();
pclk_mul = RTCTempData->APBClock / 6553600.0;
rtc_data1 = *NVR_RTC1_P1_P0;
rtc_data2 = *NVR_RTC1_P2;
rtc_data3 = *NVR_RTC1_P5_P4;
rtc_data4 = *NVR_RTC1_P7_P6;
/* Calculate checksum1 */
checksum = ~(rtc_data1 + rtc_data2 + rtc_data3 + rtc_data4);
if (checksum == (*NVR_RTC1_PCHECHSUM)) //checksum1 true
{
/* Get information */
RTCTempData->RTCTempP0 = (int16_t)(rtc_data1);
RTCTempData->RTCTempP1 = (int16_t)(rtc_data1 >> 16);
RTCTempData->RTCTempP2 = (int32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256));
RTCTempData->RTCTempP5 = (int16_t)(rtc_data3 >> 16);
RTCTempData->RTCTempP6 = (int16_t)(rtc_data4 * pclk_mul);
RTCTempData->RTCTempP7 = (int16_t)(rtc_data4 >> 16);
/* Load data to ACPx register */
RTC->ACP0 = (uint16_t)(rtc_data1 & 0xFFFF);
RTC->ACP1 = (uint16_t)((rtc_data1 >> 16) & 0xFFFF);
RTC->ACP2 = (uint32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256));
RTC->ACP5 = (uint16_t)((rtc_data3 >> 16) & 0xFFFF);
RTC->ACP6 = (uint16_t)((int16_t)(rtc_data4 * pclk_mul));
RTC->ACP7 = (uint16_t)((rtc_data4 >> 16) & 0xFFFF);
}
else
{
rtc_data1 = *NVR_RTC2_P1_P0;
rtc_data2 = *NVR_RTC2_P2;
rtc_data3 = *NVR_RTC2_P5_P4;
rtc_data4 = *NVR_RTC2_P7_P6;
/* Calculate checksum2 */
checksum = ~(rtc_data1 + rtc_data2 + rtc_data3 + rtc_data4);
if (checksum == (*NVR_RTC2_PCHECHSUM)) //checksum2 true
{
/* Get information */
RTCTempData->RTCTempP0 = (int16_t)(rtc_data1);
RTCTempData->RTCTempP1 = (int16_t)(rtc_data1 >> 16);
RTCTempData->RTCTempP2 = (int32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256));
RTCTempData->RTCTempP5 = (int16_t)(rtc_data3 >> 16);
RTCTempData->RTCTempP6 = (int16_t)(rtc_data4 * pclk_mul);
RTCTempData->RTCTempP7 = (int16_t)(rtc_data4 >> 16);
/* Load data to ACPx register */
RTC->ACP0 = (uint16_t)(rtc_data1 & 0xFFFF);
RTC->ACP1 = (uint16_t)((rtc_data1 >> 16) & 0xFFFF);
RTC->ACP2 = (uint32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256));
RTC->ACP5 = (uint16_t)((rtc_data3 >> 16) & 0xFFFF);
RTC->ACP6 = (uint16_t)((int16_t)(rtc_data4 * pclk_mul));
RTC->ACP7 = (uint16_t)((rtc_data4 >> 16) & 0xFFFF);
}
else
{
/* Get information */
RTCTempData->RTCTempP0 = -214;
RTCTempData->RTCTempP1 = 1060;
RTCTempData->RTCTempP2 = -19746971 + (TempDelta*256);
RTCTempData->RTCTempP5 = 6444;
RTCTempData->RTCTempP6 = (uint32_t)((int32_t)(1342*pclk_mul));
RTCTempData->RTCTempP7 = 0;
/* Load data to ACPx register */
RTC->ACP0 = (uint16_t)(-214);
RTC->ACP1 = (uint16_t)(1060);
RTC->ACP2 = (uint32_t)(-19746971 + (TempDelta*256));
RTC->ACP5 = (uint16_t)(6444);
RTC->ACP6 = (uint16_t)((int32_t)(1342*pclk_mul));
RTC->ACP7 = (uint16_t)(0);
retval |= BIT1;
}
}
/*----------------------------------- P4 -------------------------------------*/
/* Calculate checksum1 */
rtc_p4 = *NVR_RTC1_P4;
checksum = ~rtc_p4;
if (checksum == (*NVR_RTC1_P4_CHKSUM))//checksum1 true
{
/* Get information */
RTCTempData->RTCTempP4 = (int16_t)(*NVR_RTC1_P4);
RTC->ACP4 = *NVR_RTC1_P4;
}
else
{
rtc_p4 = *NVR_RTC2_P4;
checksum = ~rtc_p4;
if (checksum == (*NVR_RTC2_P4_CHKSUM))//checksum2 true
{
/* Get information */
RTCTempData->RTCTempP4 = (int16_t)(*NVR_RTC1_P4);
RTC->ACP4 = *NVR_RTC1_P4;
}
else
{
RTCTempData->RTCTempP4 = 0;
RTC->ACP4 = 0;
retval |= BIT2;
}
}
/*-------------------------- RTC ACKx parameters -----------------------------*/
rtc_ack[0] = *NVR_RTC1_ACK1;
rtc_ack[1] = *NVR_RTC1_ACK2;
rtc_ack[2] = *NVR_RTC1_ACK3;
rtc_ack[3] = *NVR_RTC1_ACK4;
rtc_ack[4] = *NVR_RTC1_ACK5;
checksum = ~(rtc_ack[0] + rtc_ack[1] + rtc_ack[2] + rtc_ack[3] + rtc_ack[4]);
if (checksum == (*NVR_RTC1_ACK_CHKSUM))//checksum1 true
{
/* Get information */
RTCTempData->RTCTempK1 = rtc_ack[0];
RTCTempData->RTCTempK2 = rtc_ack[1];
RTCTempData->RTCTempK3 = rtc_ack[2];
RTCTempData->RTCTempK4 = rtc_ack[3];
RTCTempData->RTCTempK5 = rtc_ack[4];
/* Load data to ACKx register */
RTC->ACK1 = rtc_ack[0];
RTC->ACK2 = rtc_ack[1];
RTC->ACK3 = rtc_ack[2];
RTC->ACK4 = rtc_ack[3];
RTC->ACK5 = rtc_ack[4];
}
else
{
rtc_ack[0] = *NVR_RTC2_ACK1;
rtc_ack[1] = *NVR_RTC2_ACK2;
rtc_ack[2] = *NVR_RTC2_ACK3;
rtc_ack[3] = *NVR_RTC2_ACK4;
rtc_ack[4] = *NVR_RTC2_ACK5;
checksum = ~(rtc_ack[0] + rtc_ack[1] + rtc_ack[2] + rtc_ack[3] + rtc_ack[4]);
if (checksum == (*NVR_RTC2_ACK_CHKSUM))//checksum2 true
{
/* Get information */
RTCTempData->RTCTempK1 = rtc_ack[0];
RTCTempData->RTCTempK2 = rtc_ack[1];
RTCTempData->RTCTempK3 = rtc_ack[2];
RTCTempData->RTCTempK4 = rtc_ack[3];
RTCTempData->RTCTempK5 = rtc_ack[4];
/* Load data to ACKx register */
RTC->ACK1 = rtc_ack[0];
RTC->ACK2 = rtc_ack[1];
RTC->ACK3 = rtc_ack[2];
RTC->ACK4 = rtc_ack[3];
RTC->ACK5 = rtc_ack[4];
}
else
{
/* Get information */
RTCTempData->RTCTempK1 = 20827;
RTCTempData->RTCTempK2 = 21496;
RTCTempData->RTCTempK3 = 22020;
RTCTempData->RTCTempK4 = 24517;
RTCTempData->RTCTempK5 = 25257;
/* Load data to ACKx register */
RTC->ACK1 = 20827;
RTC->ACK2 = 21496;
RTC->ACK3 = 22020;
RTC->ACK4 = 24517;
RTC->ACK5 = 25257;
retval |= BIT3;
}
}
/*-------------------------- RTC ACTI parameters -----------------------------*/
rtc_acti = *NVR_RTC1_ACTI;
checksum = ~rtc_acti;
if (checksum == (*NVR_RTC1_ACTI_CHKSUM))
{
/* Get information */
RTCTempData->RTCACTI = rtc_acti;
/* Load data to ACKx register */
RTC->ACTI = rtc_acti;
}
else
{
rtc_acti = *NVR_RTC2_ACTI;
checksum = ~rtc_acti;
if (checksum == (*NVR_RTC2_ACTI_CHKSUM))
{
/* Get information */
RTCTempData->RTCACTI = rtc_acti;
/* Load data to ACKx register */
RTC->ACTI = rtc_acti;
}
else
{
/* Get information */
RTCTempData->RTCACTI = 0x1800;
RTC->ACTI = 0x1800;
retval |= BIT4;
}
}
/*------------------------- RTC ACKTemp parameters ---------------------------*/
rtc_acktemp = *NVR_RTC1_ACKTEMP;
checksum = ~rtc_acktemp;
if (checksum == (*NVR_RTC1_ACKTEMP_CHKSUM))
{
/* Get information */
RTCTempData->RTCACKTemp = rtc_acktemp;
/* Load data to ACKx register */
RTC->ACKTEMP = rtc_acktemp;
}
else
{
rtc_acktemp = *NVR_RTC2_ACKTEMP;
checksum = ~rtc_acktemp;
if (checksum == (*NVR_RTC2_ACKTEMP_CHKSUM))
{
/* Get information */
RTCTempData->RTCACKTemp = rtc_acktemp;
/* Load data to ACKx register */
RTC->ACKTEMP = rtc_acktemp;
}
else
{
/* Get information */
RTCTempData->RTCACKTemp = 0x3C2800EC;
RTC->ACKTEMP = 0x3C2800EC;
retval |= BIT5;
}
}
/*--------------------------------- ACF200 -----------------------------------*/
RTCTempData->RTCACF200 = (uint32_t)((int32_t)(pclk_mul*0x320000));
RTC->ACF200 = (uint32_t)((int32_t)(pclk_mul*0x320000));
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
return retval;
}
/**
* @breif Get Power/Clock Measure result.
* @param [out]MEAResult The pointer to struct NVR_PWRMEARES.
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult)
{
uint32_t avcc_data, dvcc_data, bgp_data, rcl_data, rch_data;
uint32_t checksum;
avcc_data = *NVR_AVCC_MEA1;
dvcc_data = *NVR_DVCC_MEA1;
bgp_data = *NVR_BGP_MEA1;
rcl_data = *NVR_RCL_MEA1;
rch_data = *NVR_RCH_MEA1;
/* Calculate checksum1 */
checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data);
if (checksum == (*NVR_PWR_CHECKSUM1))
{
MEAResult->AVCCMEAResult = avcc_data;
MEAResult->DVCCMEAResult = dvcc_data;
MEAResult->BGPMEAResult = bgp_data;
MEAResult->RCLMEAResult = rcl_data;
MEAResult->RCHMEAResult = rch_data;
return 0;
}
avcc_data = *NVR_AVCC_MEA2;
dvcc_data = *NVR_DVCC_MEA2;
bgp_data = *NVR_BGP_MEA2;
rcl_data = *NVR_RCL_MEA2;
rch_data = *NVR_RCH_MEA2;
/* Calculate checksum2 */
checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data);
if (checksum == (*NVR_PWR_CHECKSUM2))
{
MEAResult->AVCCMEAResult = avcc_data;
MEAResult->DVCCMEAResult = dvcc_data;
MEAResult->BGPMEAResult = bgp_data;
MEAResult->RCLMEAResult = rcl_data;
MEAResult->RCHMEAResult = rch_data;
return 0;
}
else
{
return 1;
}
}
/**
* @breif Get Chip ID.
* @param [out]ChipID The pointer to struct NVR_CHIPID.
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetChipID(NVR_CHIPID *ChipID)
{
uint32_t id0, id1;
uint32_t checksum;
id0 = *NVR_CHIP1_ID0;
id1 = *NVR_CHIP1_ID1;
/* Calculate checksum1 */
checksum = ~(id0 + id1);
if (checksum == (*NVR_CHIP1_CHECKSUM))
{
ChipID->ChipID0 = id0;
ChipID->ChipID1 = id1;
return 0;
}
id0 = *NVR_CHIP2_ID0;
id1 = *NVR_CHIP2_ID1;
/* Calculate checksum2 */
checksum = ~(id0 + id1);
if (checksum == (*NVR_CHIP2_CHECKSUM))
{
ChipID->ChipID0 = id0;
ChipID->ChipID1 = id1;
return 0;
}
else
{
return 1;
}
}
/**
* @breif Get LCD information.
* @param [out]LCDInfo The pointer to struct NVR_LCDINFO.
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo)
{
uint32_t lcd_ldo, lcd_vol;
uint32_t checksum;
lcd_ldo = *NVR_LCD_LDO1;
lcd_vol = *NVR_LCD_VOL1;
/* Calculate checksum1 */
checksum = ~(lcd_ldo + lcd_vol);
if (checksum == (*NVR_LCD_CHECKSUM1))
{
LCDInfo->MEALCDLDO = lcd_ldo;
LCDInfo->MEALCDVol = lcd_vol;
return 0;
}
lcd_ldo = *NVR_LCD_LDO2;
lcd_vol = *NVR_LCD_VOL2;
/* Calculate checksum2 */
checksum = ~(lcd_ldo + lcd_vol);
if (checksum == (*NVR_LCD_CHECKSUM2))
{
LCDInfo->MEALCDLDO = lcd_ldo;
LCDInfo->MEALCDVol = lcd_vol;
return 0;
}
else
{
return 1;
}
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_cortex.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Cortex module driver.
******************************************************************************
* @attention
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_cortex.h"
#include "core_cm0.h"
/**
* @brief 1. Clears Pending of a device specific External Interrupt.
* 2. Sets Priority of a device specific External Interrupt.
* 3. Enables a device specific External Interrupt.
* @param IRQn: External interrupt number .
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to target.h file)
* @param Priority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 3.
* A lower priority value indicates a higher priority
* @retval None
*/
void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
/* Clear Pending Interrupt */
NVIC_ClearPendingIRQ(IRQn);
/* Set Interrupt Priority */
NVIC_SetPriority(IRQn, Priority);
/* Enable Interrupt in NVIC */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly before calling it.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt in NVIC */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt in NVIC */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
* @retval None
*/
void CORTEX_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Gets the Pending bit of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval 0 Interrupt status is not pending.
1 Interrupt status is pending.
*/
uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Get priority for Cortex-M0 system or device specific interrupts */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Clear interrupt pending */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Gets the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval Interrupt Priority. Value is aligned automatically to the implemented
* priority bits of the microcontroller.
*/
uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn)
{
/* Get priority for Cortex-M0 system or device specific interrupts */
return NVIC_GetPriority(IRQn);
}
/**
* @brief Sets the priority of an interrupt.
* @param IRQn: External interrupt number .
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to target.h file)
* @param Priority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 3.
* A lower priority value indicates a higher priority
* @retval None
*/
void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
/* Get priority for Cortex-M0 system or device specific interrupts */
NVIC_SetPriority(IRQn, Priority);
}
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum)
{
return SysTick_Config(TicksNum);
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file system_target.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief system source file.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "target.h"
#define NVR_REGINFOCOUNT1 (0x80400)
#define NVR_REGINFOBAKOFFSET (0x100)
/**
* @brief Setup the microcontroller system
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
uint32_t i,nCount,nValue,nAddress,nChecksum;
nCount = *(__IO uint32_t *)NVR_REGINFOCOUNT1;
nChecksum = nCount;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+4))
{
nCount = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET);
nChecksum = nCount;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+4))
{
while(1);
}
}
for(i=0; i<nCount; i++)
{
nAddress = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+8+i*12);
nValue = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+12+i*12);
nChecksum = nAddress + nValue;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+16+i*12))
{
nAddress = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+8+i*12);
nValue = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+12+i*12);
nChecksum = nAddress + nValue;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+16+i*12))
{
while(1);
}
}
if((nAddress>=0x40014800) && (nAddress<=0x40015000))
{
RTC_WriteRegisters(nAddress, &nValue, 1);
}
else
{
*(__IO uint32_t *)(nAddress) = nValue;
}
}
}
/**
* @brief Initializes registers.
* @param None
* @retval None
*/
void SystemUpdate(void)
{
}
/*********************************** END OF FILE ******************************/

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.5
* @date 28. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return (__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr);
#else
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile("MRS %0, control" : "=r"(result));
return (result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile("MSR control, %0" : : "r"(control));
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, ipsr" : "=r"(result));
return (result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, apsr" : "=r"(result));
return (result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, xpsr" : "=r"(result));
return (result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile("MRS %0, psp\n" : "=r"(result));
return (result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack));
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile("MRS %0, msp\n" : "=r"(result));
return (result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack));
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile("MRS %0, primask" : "=r"(result));
return (result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile("MSR primask, %0" : : "r"(priMask));
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile("MRS %0, basepri_max" : "=r"(result));
return (result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile("MSR basepri, %0" : : "r"(value));
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile("MRS %0, faultmask" : "=r"(result));
return (result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile("MSR faultmask, %0" : : "r"(faultMask));
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpscr" : "=r"(result));
return (result);
#else
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile("VMSR fpscr, %0" : : "r"(fpscr));
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
__ASM volatile("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
{
__ASM volatile("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
__ASM volatile("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
__ASM volatile("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
__ASM volatile("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile("rev %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile("ror %0, %0, %1" : "+r"(op1) : "r"(op2));
return (op1);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr));
return (result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr));
return (result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr));
return (result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile("strexb %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
return (result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile("strexh %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
return (result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile("strex %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
return (result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile("clz %0, %1" : "=r"(result) : "r"(value));
return (result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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bsp/Vango_V85xx/Libraries/SConscript Normal file
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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('VangoV85xx_standard_peripheral/Source/*.c')
src += [cwd + '/CMSIS/Vango/V85xx/Source/system_target.c']
src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c']
src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_cortex.c']
src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/CMSIS/Vango/V85xx/Source/GCC/startup_target.S']
if rtconfig.CROSS_TOOL == 'keil':
src += [cwd + '/CMSIS/Vango/V85xx/Source/Keil5/startup_target.S']
path = [
cwd + '/CMSIS/Vango/V85xx/Include',
cwd + '/CMSIS',
cwd + '/VangoV85xx_standard_peripheral/Include',]
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'V85xx','USE_TARGET_DRIVER']
group = DefineGroup('Vango_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/**
******************************************************************************
* @file lib_adc.h
* @author Application Team
* @version V4.6.0
* @date 2019-06-18
* @brief ADC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_ADC_H
#define __LIB_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t TrigMode;
uint32_t ConvMode;
uint32_t ClockSource;
uint32_t ClockDivider;
uint32_t Channel;
} ADCInitType;
//TrigMode
#define ADC_TRIGMODE_AUTO 0
#define ADC_TRIGMODE_MANUAL ANA_ADCCTRL_MTRIG
#define IS_ADC_TRIGMODE(__TRIGMODE__) (((__TRIGMODE__) == ADC_TRIGMODE_AUTO) ||\
((__TRIGMODE__) == ADC_TRIGMODE_MANUAL))
//ConvMode
#define ADC_CONVMODE_SINGLECHANNEL 0
#define ADC_CONVMODE_MULTICHANNEL 1
#define IS_ADC_CONVMODE(__CONVMODE__) (((__CONVMODE__) == ADC_CONVMODE_SINGLECHANNEL) ||\
((__CONVMODE__) == ADC_CONVMODE_MULTICHANNEL))
//ClockSource
#define ADC_CLKSRC_RCH 0
#define ADC_CLKSRC_PLLL ANA_ADCCTRL_CLKSEL
#define IS_ADC_CLKSRC(__CLKSRC__) (((__CLKSRC__) == ADC_CLKSRC_RCH) ||\
((__CLKSRC__) == ADC_CLKSRC_PLLL))
//TrigSource
#define ADC_TRIGSOURCE_OFF ANA_ADCCTRL_AEN_OFF
#define ADC_TRIGSOURCE_TIM0 ANA_ADCCTRL_AEN_TMR0
#define ADC_TRIGSOURCE_TIM1 ANA_ADCCTRL_AEN_TMR1
#define ADC_TRIGSOURCE_TIM2 ANA_ADCCTRL_AEN_TMR2
#define ADC_TRIGSOURCE_TIM3 ANA_ADCCTRL_AEN_TMR3
#define IS_ADC_TRIGSOURCE(__TRIGSOURCE__) (((__TRIGSOURCE__) == ADC_TRIGSOURCE_OFF) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM0) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM1) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM2) ||\
((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM3))
//ClockDivider
#define ADC_CLKDIV_1 ANA_ADCCTRL_CLKDIV_1
#define ADC_CLKDIV_2 ANA_ADCCTRL_CLKDIV_2
#define ADC_CLKDIV_3 ANA_ADCCTRL_CLKDIV_3
#define ADC_CLKDIV_4 ANA_ADCCTRL_CLKDIV_4
#define ADC_CLKDIV_5 ANA_ADCCTRL_CLKDIV_5
#define ADC_CLKDIV_6 ANA_ADCCTRL_CLKDIV_6
#define ADC_CLKDIV_7 ANA_ADCCTRL_CLKDIV_7
#define ADC_CLKDIV_8 ANA_ADCCTRL_CLKDIV_8
#define ADC_CLKDIV_9 ANA_ADCCTRL_CLKDIV_9
#define ADC_CLKDIV_10 ANA_ADCCTRL_CLKDIV_10
#define ADC_CLKDIV_11 ANA_ADCCTRL_CLKDIV_11
#define ADC_CLKDIV_12 ANA_ADCCTRL_CLKDIV_12
#define ADC_CLKDIV_13 ANA_ADCCTRL_CLKDIV_13
#define ADC_CLKDIV_14 ANA_ADCCTRL_CLKDIV_14
#define ADC_CLKDIV_15 ANA_ADCCTRL_CLKDIV_15
#define ADC_CLKDIV_16 ANA_ADCCTRL_CLKDIV_16
#define IS_ADC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == ADC_CLKDIV_1) ||\
((__CLKDIV__) == ADC_CLKDIV_2) ||\
((__CLKDIV__) == ADC_CLKDIV_3) ||\
((__CLKDIV__) == ADC_CLKDIV_4) ||\
((__CLKDIV__) == ADC_CLKDIV_5) ||\
((__CLKDIV__) == ADC_CLKDIV_6) ||\
((__CLKDIV__) == ADC_CLKDIV_7) ||\
((__CLKDIV__) == ADC_CLKDIV_8) ||\
((__CLKDIV__) == ADC_CLKDIV_9) ||\
((__CLKDIV__) == ADC_CLKDIV_10) ||\
((__CLKDIV__) == ADC_CLKDIV_11) ||\
((__CLKDIV__) == ADC_CLKDIV_12) ||\
((__CLKDIV__) == ADC_CLKDIV_13) ||\
((__CLKDIV__) == ADC_CLKDIV_14) ||\
((__CLKDIV__) == ADC_CLKDIV_15) ||\
((__CLKDIV__) == ADC_CLKDIV_16))
//Channel
#define ADC_CHANNEL0 0
#define ADC_CHANNEL1 1
#define ADC_CHANNEL2 2
#define ADC_CHANNEL3 3
#define ADC_CHANNEL4 4
#define ADC_CHANNEL5 5
#define ADC_CHANNEL6 6
#define ADC_CHANNEL7 7
#define ADC_CHANNEL8 8
#define ADC_CHANNEL9 9
#define ADC_CHANNEL10 10
#define ADC_CHANNEL11 11
#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL0) ||\
((__CHANNEL__) == ADC_CHANNEL1) ||\
((__CHANNEL__) == ADC_CHANNEL2) ||\
((__CHANNEL__) == ADC_CHANNEL3) ||\
((__CHANNEL__) == ADC_CHANNEL4) ||\
((__CHANNEL__) == ADC_CHANNEL5) ||\
((__CHANNEL__) == ADC_CHANNEL6) ||\
((__CHANNEL__) == ADC_CHANNEL7) ||\
((__CHANNEL__) == ADC_CHANNEL8) ||\
((__CHANNEL__) == ADC_CHANNEL9) ||\
((__CHANNEL__) == ADC_CHANNEL10) ||\
((__CHANNEL__) == ADC_CHANNEL11))
//INTMask
#define ADC_INT_AUTODONE ANA_INTEN_INTEN1
#define ADC_INT_MANUALDONE ANA_INTEN_INTEN0
#define ADC_INT_Msk (ADC_INT_AUTODONE | ADC_INT_MANUALDONE)
#define IS_ADC_INT(__INT__) ((((__INT__) & ADC_INT_Msk) != 0U) &&\
(((__INT__) & ~ADC_INT_Msk) == 0U))
//ScaleDown
#define ADC_SCA_NONE 0
#define ADC_SCA_DIV2 ANA_ADCCTRL_CICSCA
#define IS_ADC_SCA(__SCA__) (((__SCA__) == ADC_SCA_NONE) || ((__SCA__) == ADC_SCA_DIV2))
//Skip
#define ADC_SKIP_4 ANA_ADCCTRL_CICSKIP_4
#define ADC_SKIP_5 ANA_ADCCTRL_CICSKIP_5
#define ADC_SKIP_6 ANA_ADCCTRL_CICSKIP_6
#define ADC_SKIP_7 ANA_ADCCTRL_CICSKIP_7
#define ADC_SKIP_0 ANA_ADCCTRL_CICSKIP_0
#define ADC_SKIP_1 ANA_ADCCTRL_CICSKIP_1
#define ADC_SKIP_2 ANA_ADCCTRL_CICSKIP_2
#define ADC_SKIP_3 ANA_ADCCTRL_CICSKIP_3
#define IS_ADC_SKIP(__SKIP__) (((__SKIP__) == ADC_SKIP_4) ||\
((__SKIP__) == ADC_SKIP_5) ||\
((__SKIP__) == ADC_SKIP_6) ||\
((__SKIP__) == ADC_SKIP_7) ||\
((__SKIP__) == ADC_SKIP_0) ||\
((__SKIP__) == ADC_SKIP_1) ||\
((__SKIP__) == ADC_SKIP_2) ||\
((__SKIP__) == ADC_SKIP_3))
//DSRSelection
#define ADC_SDRSEL_DIV512 ANA_ADCCTRL_DSRSEL_512
#define ADC_SDRSEL_DIV256 ANA_ADCCTRL_DSRSEL_256
#define ADC_SDRSEL_DIV128 ANA_ADCCTRL_DSRSEL_128
#define ADC_SDRSEL_DIV64 ANA_ADCCTRL_DSRSEL_64
#define IS_ADC_SDR(__SDR__) (((__SDR__) == ADC_SDRSEL_DIV512) ||\
((__SDR__) == ADC_SDRSEL_DIV256) ||\
((__SDR__) == ADC_SDRSEL_DIV128) ||\
((__SDR__) == ADC_SDRSEL_DIV64))
typedef struct
{
float VDDVoltage;
float BATRTCVoltage;
float Temperature;
} ADC_CalResType;
//Division
#define ADC_BAT_CAPDIV (ANA_REG1_GDE4)
#define ADC_BAT_RESDIV (ANA_REG1_RESDIV)
#define IS_ADC_BATDIV(__BATDIV__) (((__BATDIV__) == ADC_BAT_CAPDIV) ||\
((__BATDIV__) == ADC_BAT_RESDIV))
/* ADC_GetVoltage */
//Mode
#define ADC_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None
#define ADC_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive
#define ADC_3V_EXTERNAL_CAPDIV (0x002UL) // Power supply: 3.3V; Channel: External; Divider modeL: Capacitive
#define ADC_3V_VDD_RESDIV (0x003UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive
#define ADC_3V_VDD_CAPDIV (0x004UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Capacitive
#define ADC_3V_BATRTC_RESDIV (0x005UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive
#define ADC_3V_BATRTC_CAPDIV (0x006UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Capacitive
#define ADC_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None
#define ADC_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive
#define ADC_5V_EXTERNAL_CAPDIV (0x102UL) // Power supply: 5V; Channel: External; Divider modeL: Capacitive
#define ADC_5V_VDD_RESDIV (0x103UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive
#define ADC_5V_VDD_CAPDIV (0x104UL) // Power supply: 5V; Channel: VDD; Divider modeL: Capacitive
#define ADC_5V_BATRTC_RESDIV (0x105UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive
#define ADC_5V_BATRTC_CAPDIV (0x106UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Capacitive
#define IS_ADCVOL_MODE(__MODE__) (((__MODE__) == ADC_3V_EXTERNAL_NODIV) ||\
((__MODE__) == ADC_3V_EXTERNAL_RESDIV) ||\
((__MODE__) == ADC_3V_EXTERNAL_CAPDIV) ||\
((__MODE__) == ADC_3V_VDD_RESDIV) ||\
((__MODE__) == ADC_3V_VDD_CAPDIV) ||\
((__MODE__) == ADC_3V_BATRTC_RESDIV) ||\
((__MODE__) == ADC_3V_BATRTC_CAPDIV) ||\
((__MODE__) == ADC_5V_EXTERNAL_NODIV) ||\
((__MODE__) == ADC_5V_EXTERNAL_RESDIV) ||\
((__MODE__) == ADC_5V_EXTERNAL_CAPDIV) ||\
((__MODE__) == ADC_5V_VDD_RESDIV) ||\
((__MODE__) == ADC_5V_VDD_CAPDIV) ||\
((__MODE__) == ADC_5V_BATRTC_RESDIV) ||\
((__MODE__) == ADC_5V_BATRTC_CAPDIV))
/* Exported Functions ------------------------------------------------------- */
/* ADC Exported Functions Group1:
(De)Initialization -------------------------*/
void ADC_DeInit(void);
void ADC_StructInit(ADCInitType* ADC_InitStruct);
void ADC_Init(ADCInitType* ADC_InitStruct);
/* ADC Exported Functions Group2:
Get NVR Info, Calculate datas --------------*/
uint32_t ADC_CalculateVoltage(uint32_t Mode, int16_t adc_data, float *Voltage);
uint32_t ADC_GetVDDVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults);
uint32_t ADC_GetVDDVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults);
uint32_t ADC_GetBATRTCVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults);
uint32_t ADC_GetBATRTCVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults);
uint32_t ADC_GetTemperature(ADC_CalResType *CalResults);
/* ADC Exported Functions Group3:
Interrupt (flag) ---------------------------*/
int16_t ADC_GetADCConversionValue(uint32_t Channel);
void ADC_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t ADC_GetAutoDoneFlag(void);
uint8_t ADC_GetManualDoneFlag(void);
void ADC_ClearAutoDoneFlag(void);
void ADC_ClearManualDoneFlag(void);
/* ADC Exported Functions Group4:
MISC Configuration -------------------------*/
uint32_t ADC_Cmd(uint32_t NewState);
void ADC_StartManual(void);
void ADC_WaitForManual(void);
void ADC_TrigSourceConfig(uint32_t TrigSource);
void ADC_RESDivisionCmd(uint32_t NewState);
void ADC_CAPDivisionCmd(uint32_t NewState);
//CIC Control
void ADC_CICAlwaysOnCmd(uint32_t NewState);
void ADC_CICINVCmd(uint32_t NewState);
void ADC_CICScaleDownConfig(uint32_t ScaleDown);
void ADC_CICSkipConfig(uint32_t Skip);
void ADC_CICDownSamRateConfig(uint32_t DSRSelection);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ADC_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_adc_tiny.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief ADC_TINY library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_ADC_TINY_H
#define __LIB_ADC_TINY_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t SignalSel;
uint32_t ADTREF1;
uint32_t ADTREF2;
uint32_t ADTREF3;
} TADCInitType;
//SelADT
#define ADCTINY_SIGNALSEL_IOE6 0
#define ADCTINY_SIGNALSEL_IOE7 ANA_REGF_SELADT
#define IS_ADCTINY_SELADT(__SELADT__) (((__SELADT__) == ADCTINY_SIGNALSEL_IOE6) ||\
((__SELADT__) == ADCTINY_SIGNALSEL_IOE7))
//ADTREF1
#define ADCTINY_REF1_0_9 0
#define ADCTINY_REF1_0_7 ANA_REGF_ADTREF1SEL
#define IS_ADCTINY_ADTREF1(__ADTREF1__) (((__ADTREF1__) == ADCTINY_REF1_0_9) ||\
((__ADTREF1__) == ADCTINY_REF1_0_7))
//ADTREF2
#define ADCTINY_REF2_1_8 0
#define ADCTINY_REF2_1_6 ANA_REGF_ADTREF2SEL
#define IS_ADCTINY_ADTREF2(__ADTREF2__) (((__ADTREF2__) == ADCTINY_REF2_1_8) ||\
((__ADTREF2__) == ADCTINY_REF2_1_6))
//ADTREF3
#define ADCTINY_REF3_2_7 0
#define ADCTINY_REF3_2_5 ANA_REGF_ADTREF3SEL
#define IS_ADCTINY_ADTREF3(__ADTREF3__) (((__ADTREF3__) == ADCTINY_REF3_2_7) ||\
((__ADTREF3__) == ADCTINY_REF3_2_5))
//THSel
#define ADCTINY_THSEL_0 ANA_MISC_TADCTH_0
#define ADCTINY_THSEL_1 ANA_MISC_TADCTH_1
#define ADCTINY_THSEL_2 ANA_MISC_TADCTH_2
#define ADCTINY_THSEL_3 ANA_MISC_TADCTH_3
#define IS_ADCTINY_THSEL(__THSEL__) (((__THSEL__) == ADCTINY_THSEL_0) ||\
((__THSEL__) == ADCTINY_THSEL_1) ||\
((__THSEL__) == ADCTINY_THSEL_2) ||\
((__THSEL__) == ADCTINY_THSEL_3))
/* Exported Functions ------------------------------------------------------- */
void TADC_DeInit(void);
void TADC_StructInit(TADCInitType* TADC_InitStruct);
void TADC_Init(TADCInitType* TADC_InitStruct);
void TADC_Cmd(uint32_t NewState);
uint8_t TADC_GetOutput(void);
void TADC_IntTHConfig(uint32_t THSel);
void TADC_INTConfig(uint32_t NewState);
uint8_t TADC_GetINTStatus(void);
void TADC_ClearINTStatus(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ADC_TINY_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_ana.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Analog library.
******************************************************************************
* @attention
*
*
******************************************************************************
*/
#ifndef __LIB_ANA_H
#define __LIB_ANA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/***** StatusMask (ANA_GetStatus) *****/
#define ANA_STATUS_AVCCLV ANA_COMPOUT_AVCCLV
#define ANA_STATUS_VDCINDROP ANA_COMPOUT_VDCINDROP
#define ANA_STATUS_VDDALARM ANA_COMPOUT_VDDALARM
#define ANA_STATUS_COMP2 ANA_COMPOUT_COMP2
#define ANA_STATUS_COMP1 ANA_COMPOUT_COMP1
#define ANA_STATUS_LOCKL ANA_COMPOUT_LOCKL
#define ANA_STATUS_LOCKH ANA_COMPOUT_LOCKH
/***** IntMask (ANA_GetINTStatus / ANA_ClearINTStatus / ANA_INTConfig) *****/
#define ANA_INT_TADC_OVER ANA_INTSTS_INTSTS13
#define ANA_INT_REGERR ANA_INTSTS_INTSTS12
#define ANA_INT_SME ANA_INTSTS_INTSTS11
#define ANA_INT_AVCCLV ANA_INTSTS_INTSTS10
#define ANA_INT_VDCINDROP ANA_INTSTS_INTSTS8
#define ANA_INT_VDDALARM ANA_INTSTS_INTSTS7
#define ANA_INT_COMP2 ANA_INTSTS_INTSTS3
#define ANA_INT_COMP1 ANA_INTSTS_INTSTS2
#define ANA_INT_ADCA ANA_INTSTS_INTSTS1
#define ANA_INT_ADCM ANA_INTSTS_INTSTS0
#define ANA_INT_Msk (0x3DEFUL)
/* Private macros ------------------------------------------------------------*/
#define IS_ANA_STATUS(__STATUS__) (((__STATUS__) == ANA_STATUS_AVCCLV) ||\
((__STATUS__) == ANA_STATUS_VDCINDROP) ||\
((__STATUS__) == ANA_STATUS_VDDALARM) ||\
((__STATUS__) == ANA_STATUS_COMP2) ||\
((__STATUS__) == ANA_STATUS_COMP1) ||\
((__STATUS__) == ANA_STATUS_LOCKL) ||\
((__STATUS__) == ANA_STATUS_LOCKH))
#define IS_ANA_INTSTSR(__INTSTSR__) (((__INTSTSR__) == ANA_INT_TADC_OVER) ||\
((__INTSTSR__) == ANA_INT_REGERR) ||\
((__INTSTSR__) == ANA_INT_SME) ||\
((__INTSTSR__) == ANA_INT_AVCCLV) ||\
((__INTSTSR__) == ANA_INT_VDCINDROP) ||\
((__INTSTSR__) == ANA_INT_VDDALARM) ||\
((__INTSTSR__) == ANA_INT_COMP2) ||\
((__INTSTSR__) == ANA_INT_COMP1) ||\
((__INTSTSR__) == ANA_INT_ADCA) ||\
((__INTSTSR__) == ANA_INT_ADCM))
#define IS_ANA_INTSTSC(__INTSTSC__) ((((__INTSTSC__) & ANA_INT_Msk) != 0U) &&\
(((__INTSTSC__) & ~ANA_INT_Msk) == 0U))
#define IS_ANA_INT(__INT__) IS_ANA_INTSTSC(__INT__)
/* Exported Functions ------------------------------------------------------- */
uint8_t ANA_GetStatus(uint32_t StatusMask);
uint8_t ANA_GetINTStatus(uint32_t IntMask);
void ANA_ClearINTStatus(uint32_t IntMask);
void ANA_INTConfig(uint32_t IntMask, uint32_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ANA_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_clk.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Clock library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CLK_H
#define __LIB_CLK_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* PLLL Configure */
typedef struct
{
uint32_t Source;
uint32_t State;
uint32_t Frequency;
} PLLL_ConfTypeDef;
/* PLLH Configure */
typedef struct
{
uint32_t Source;
uint32_t State;
uint32_t Frequency;
} PLLH_ConfTypeDef;
/* RCH Configure */
typedef struct
{
uint32_t State;
} RCH_ConfTypeDef;
/* XTALH Configure */
typedef struct
{
uint32_t State;
} XTALH_ConfTypeDef;
/* RTCCLK Configure */
typedef struct
{
uint32_t Source;
uint32_t Divider;
} RTCCLK_ConfTypeDef;
/* HCLK Configure */
typedef struct
{
uint32_t Divider; /* 1 ~ 256 */
} HCLK_ConfTypeDef;
/* PCLK Configure */
typedef struct
{
uint32_t Divider; /* 1 ~ 256 */
} PCLK_ConfTypeDef;
/* Clock Configure */
typedef struct
{
uint32_t ClockType; /* The clock to be configured */
uint32_t AHBSource;
PLLL_ConfTypeDef PLLL;
PLLH_ConfTypeDef PLLH;
XTALH_ConfTypeDef XTALH;
RTCCLK_ConfTypeDef RTCCLK;
HCLK_ConfTypeDef HCLK;
PCLK_ConfTypeDef PCLK;
} CLK_InitTypeDef;
/***** ClockType *****/
#define CLK_TYPE_Msk (0xFFUL)
#define CLK_TYPE_ALL CLK_TYPE_Msk
#define CLK_TYPE_AHBSRC (0x01UL) /* AHB Clock source to configure */
#define CLK_TYPE_PLLL (0x02UL) /* PLLL to configure */
#define CLK_TYPE_PLLH (0x04UL) /* PLLH to configure */
#define CLK_TYPE_XTALH (0x08UL) /* XTALH to configure */
#define CLK_TYPE_RTCCLK (0x20UL) /* RTCCLK to configure */
#define CLK_TYPE_HCLK (0x40UL) /* AHB Clock to configure */
#define CLK_TYPE_PCLK (0x80UL) /* APB Clock to configure */
/***** AHBSource *****/
#define CLK_AHBSEL_6_5MRC MISC2_CLKSEL_CLKSEL_RCOH
#define CLK_AHBSEL_6_5MXTAL MISC2_CLKSEL_CLKSEL_XOH
#define CLK_AHBSEL_HSPLL MISC2_CLKSEL_CLKSEL_PLLH
#define CLK_AHBSEL_RTCCLK MISC2_CLKSEL_CLKSEL_RTCCLK
#define CLK_AHBSEL_LSPLL MISC2_CLKSEL_CLKSEL_PLLL
/***** PLLL_ConfTypeDef PLLL *****/
/* PLLL.Source */
#define CLK_PLLLSRC_RCL PMU_CONTROL_PLLL_SEL
#define CLK_PLLLSRC_XTALL (0)
/* PLLL.State */
#define CLK_PLLL_ON ANA_REG3_PLLLPDN
#define CLK_PLLL_OFF (0)
/* PLLL.Frequency */
#define CLK_PLLL_26_2144MHz ANA_REG9_PLLLSEL_26M
#define CLK_PLLL_13_1072MHz ANA_REG9_PLLLSEL_13M
#define CLK_PLLL_6_5536MHz ANA_REG9_PLLLSEL_6_5M
#define CLK_PLLL_3_2768MHz ANA_REG9_PLLLSEL_3_2M
#define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M
#define CLK_PLLL_0_8192MHz ANA_REG9_PLLLSEL_800K
#define CLK_PLLL_0_4096MHz ANA_REG9_PLLLSEL_400K
#define CLK_PLLL_0_2048MHz ANA_REG9_PLLLSEL_200K
/***** PLLH_ConfTypeDef PLLH *****/
/* PLLH.Source */
#define CLK_PLLHSRC_RCH (0)
#define CLK_PLLHSRC_XTALH PMU_CONTROL_PLLH_SEL
/* PLLH.State */
#define CLK_PLLH_ON ANA_REG3_PLLHPDN
#define CLK_PLLH_OFF (0)
/* PLLH.Frequency */
#define CLK_PLLH_13_1072MHz ANA_REG9_PLLHSEL_X2
#define CLK_PLLH_16_384MHz ANA_REG9_PLLHSEL_X2_5
#define CLK_PLLH_19_6608MHz ANA_REG9_PLLHSEL_X3
#define CLK_PLLH_22_9376MHz ANA_REG9_PLLHSEL_X3_5
#define CLK_PLLH_26_2144MHz ANA_REG9_PLLHSEL_X4
#define CLK_PLLH_29_4912MHz ANA_REG9_PLLHSEL_X4_5
#define CLK_PLLH_32_768MHz ANA_REG9_PLLHSEL_X5
#define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5
#define CLK_PLLH_39_3216MHz ANA_REG9_PLLHSEL_X6
#define CLK_PLLH_42_5984MHz ANA_REG9_PLLHSEL_X6_5
#define CLK_PLLH_45_8752MHz ANA_REG9_PLLHSEL_X7
#define CLK_PLLH_49_152MHz ANA_REG9_PLLHSEL_X7_5
/* XTALH_ConfTypeDef XTALH */
/* XTALH.State */
#define CLK_XTALH_ON ANA_REG3_XOHPDN
#define CLK_XTALH_OFF (0)
/* RTCCLK Configure */
/* RTCCLK.Source */
#define CLK_RTCCLKSRC_XTALL (0)
#define CLK_RTCCLKSRC_RCL (PMU_CONTROL_RTCLK_SEL)
/* RTCCLK.Divider */
#define CLK_RTCCLKDIV_1 (RTC_PSCA_PSCA_0)
#define CLK_RTCCLKDIV_4 (RTC_PSCA_PSCA_1)
//AHB Periphral
#define CLK_AHBPERIPHRAL_DMA MISC2_HCLKEN_DMA
#define CLK_AHBPERIPHRAL_GPIO MISC2_HCLKEN_GPIO
#define CLK_AHBPERIPHRAL_LCD MISC2_HCLKEN_LCD
#define CLK_AHBPERIPHRAL_CRYPT MISC2_HCLKEN_CRYPT
#define CLK_AHBPERIPHRAL_ALL (MISC2_HCLKEN_DMA \
|MISC2_HCLKEN_GPIO \
|MISC2_HCLKEN_LCD \
|MISC2_HCLKEN_CRYPT)
//APB Periphral
#define CLK_APBPERIPHRAL_DMA MISC2_PCLKEN_DMA
#define CLK_APBPERIPHRAL_I2C MISC2_PCLKEN_I2C
#define CLK_APBPERIPHRAL_SPI1 MISC2_PCLKEN_SPI1
#define CLK_APBPERIPHRAL_UART0 MISC2_PCLKEN_UART0
#define CLK_APBPERIPHRAL_UART1 MISC2_PCLKEN_UART1
#define CLK_APBPERIPHRAL_UART2 MISC2_PCLKEN_UART2
#define CLK_APBPERIPHRAL_UART3 MISC2_PCLKEN_UART3
#define CLK_APBPERIPHRAL_UART4 MISC2_PCLKEN_UART4
#define CLK_APBPERIPHRAL_UART5 MISC2_PCLKEN_UART5
#define CLK_APBPERIPHRAL_ISO78160 MISC2_PCLKEN_ISO78160
#define CLK_APBPERIPHRAL_ISO78161 MISC2_PCLKEN_ISO78161
#define CLK_APBPERIPHRAL_TIMER MISC2_PCLKEN_TIMER
#define CLK_APBPERIPHRAL_MISC MISC2_PCLKEN_MISC
#define CLK_APBPERIPHRAL_MISC2 MISC2_PCLKEN_MISC2
#define CLK_APBPERIPHRAL_PMU MISC2_PCLKEN_PMU
#define CLK_APBPERIPHRAL_RTC MISC2_PCLKEN_RTC
#define CLK_APBPERIPHRAL_ANA MISC2_PCLKEN_ANA
#define CLK_APBPERIPHRAL_U32K0 MISC2_PCLKEN_U32K0
#define CLK_APBPERIPHRAL_U32K1 MISC2_PCLKEN_U32K1
#define CLK_APBPERIPHRAL_SPI2 MISC2_PCLKEN_SPI2
#define CLK_APBPERIPHRAL_ALL (MISC2_PCLKEN_DMA \
|MISC2_PCLKEN_I2C \
|MISC2_PCLKEN_SPI1 \
|MISC2_PCLKEN_UART0 \
|MISC2_PCLKEN_UART1 \
|MISC2_PCLKEN_UART2 \
|MISC2_PCLKEN_UART3 \
|MISC2_PCLKEN_UART4 \
|MISC2_PCLKEN_UART5 \
|MISC2_PCLKEN_ISO78160 \
|MISC2_PCLKEN_ISO78161 \
|MISC2_PCLKEN_TIMER \
|MISC2_PCLKEN_MISC \
|MISC2_PCLKEN_MISC2 \
|MISC2_PCLKEN_PMU \
|MISC2_PCLKEN_RTC \
|MISC2_PCLKEN_ANA \
|MISC2_PCLKEN_U32K0 \
|MISC2_PCLKEN_U32K1 \
|MISC2_PCLKEN_SPI2)
/***** PLLStatus (CLK_GetPLLLockStatus) *****/
#define CLK_STATUS_LOCKL ANA_COMPOUT_LOCKL
#define CLK_STATUS_LOCKH ANA_COMPOUT_LOCKH
/* Private macros ------------------------------------------------------------*/
#define IS_CLK_TYPE(__TYPE__) ((((__TYPE__) & CLK_TYPE_Msk) != 0UL) &&\
(((__TYPE__) & ~CLK_TYPE_Msk) == 0UL))
#define IS_CLK_AHBSRC(__AHBSRC__) (((__AHBSRC__) == CLK_AHBSEL_6_5MRC) ||\
((__AHBSRC__) == CLK_AHBSEL_6_5MXTAL) ||\
((__AHBSRC__) == CLK_AHBSEL_HSPLL) ||\
((__AHBSRC__) == CLK_AHBSEL_RTCCLK) ||\
((__AHBSRC__) == CLK_AHBSEL_LSPLL))
#define IS_CLK_PLLLSRC(__PLLLSRC__) (((__PLLLSRC__) == CLK_PLLLSRC_RCL) ||\
((__PLLLSRC__) == CLK_PLLLSRC_XTALL))
#define IS_CLK_PLLLSTA(__PLLLSTA__) (((__PLLLSTA__) == CLK_PLLL_ON) ||\
((__PLLLSTA__) == CLK_PLLL_OFF))
#define IS_CLK_PLLLFRQ(__PLLLFRQ__) (((__PLLLFRQ__) == CLK_PLLL_26_2144MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_13_1072MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_6_5536MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_3_2768MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_1_6384MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_0_8192MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_0_4096MHz) ||\
((__PLLLFRQ__) == CLK_PLLL_0_2048MHz))
#define IS_CLK_PLLHSRC(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLHSRC_RCH) ||\
((__PLLHSRC__) == CLK_PLLHSRC_XTALH))
#define IS_CLK_PLLHSTA(__PLLHSTA__) (((__PLLHSTA__) == CLK_PLLH_ON) ||\
((__PLLHSTA__) == CLK_PLLH_OFF))
#define IS_CLK_PLLHFRQ(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLH_13_1072MHz) ||\
((__PLLHSRC__) == CLK_PLLH_16_384MHz) ||\
((__PLLHSRC__) == CLK_PLLH_19_6608MHz) ||\
((__PLLHSRC__) == CLK_PLLH_22_9376MHz) ||\
((__PLLHSRC__) == CLK_PLLH_26_2144MHz) ||\
((__PLLHSRC__) == CLK_PLLH_29_4912MHz) ||\
((__PLLHSRC__) == CLK_PLLH_32_768MHz) ||\
((__PLLHSRC__) == CLK_PLLH_36_0448MHz) ||\
((__PLLHSRC__) == CLK_PLLH_39_3216MHz) ||\
((__PLLHSRC__) == CLK_PLLH_42_5984MHz) ||\
((__PLLHSRC__) == CLK_PLLH_45_8752MHz) ||\
((__PLLHSRC__) == CLK_PLLH_49_152MHz))
#define IS_CLK_XTALHSTA(__XTALHSTA__) (((__XTALHSTA__) == CLK_XTALH_ON) ||\
((__XTALHSTA__) == CLK_XTALH_OFF))
#define IS_CLK_RTCSRC(__RTCSRC__) (((__RTCSRC__) == CLK_RTCCLKSRC_XTALL) ||\
((__RTCSRC__) == CLK_RTCCLKSRC_RCL))
#define IS_CLK_RTCDIV(__RTCDIV__) (((__RTCDIV__) == CLK_RTCCLKDIV_1) ||\
((__RTCDIV__) == CLK_RTCCLKDIV_4))
#define IS_CLK_HCLKDIV(__HCLKDIV__) (((__HCLKDIV__) > 0UL) &&\
((__HCLKDIV__) < 257UL))
#define IS_CLK_PCLKDIV(__PCLKDIV__) (((__PCLKDIV__) > 0UL) &&\
((__PCLKDIV__) < 257UL))
#define IS_CLK_AHBPERIPHRAL(__AHBPERIPHRAL__) ((((__AHBPERIPHRAL__) & CLK_AHBPERIPHRAL_ALL) != 0UL) &&\
(((__AHBPERIPHRAL__) & ~CLK_AHBPERIPHRAL_ALL) == 0UL))
#define IS_CLK_APBPERIPHRAL(__APBPERIPHRAL__) ((((__APBPERIPHRAL__) & CLK_APBPERIPHRAL_ALL) != 0UL) &&\
(((__APBPERIPHRAL__) & ~CLK_APBPERIPHRAL_ALL) == 0UL))
#define IS_CLK_PLLLOCK(__PLLLOCK__) (((__PLLLOCK__) == ANA_COMPOUT_LOCKL) ||\
((__PLLLOCK__) == ANA_COMPOUT_LOCKH))
/* Exported Functions ------------------------------------------------------- */
/* CLK Exported Functions Group1:
Initialization and functions ---------------*/
void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct);
/* CLK Exported Functions Group2:
Peripheral Control -------------------------*/
void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState);
void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState);
/* CLK Exported Functions Group3:
Get clock/configuration information --------*/
uint32_t CLK_GetHCLKFreq(void);
uint32_t CLK_GetPCLKFreq(void);
void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct);
uint8_t CLK_GetXTALHStatus(void);
uint8_t CLK_GetXTALLStatus(void);
uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CLK_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_comp.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief COMP library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_COMP_H
#define __LIB_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* Macros --------------------------------------------------------------------*/
/***** COMP_DEBConfig *****/
//COMPx
#define COMP_1 (0x00U)
#define COMP_2 (0x02U)
#define IS_COMP(__COMP__) (((__COMP__) == COMP_1) || ((__COMP__) == COMP_2))
//Debounce
#define COMP_DEB_0 ANA_CTRL_CMP1DEB_0
#define COMP_DEB_1 ANA_CTRL_CMP1DEB_1
#define COMP_DEB_2 ANA_CTRL_CMP1DEB_2
#define COMP_DEB_3 ANA_CTRL_CMP1DEB_3
#define IS_COMP_DEB(__DEB__) (((__DEB__) == COMP_DEB_0) ||\
((__DEB__) == COMP_DEB_1) ||\
((__DEB__) == COMP_DEB_2) ||\
((__DEB__) == COMP_DEB_3))
/***** Mode (COMP_ModeConfig) *****/
#define COMP_MODE_OFF ANA_CTRL_COMP1_SEL_0
#define COMP_MODE_RISING ANA_CTRL_COMP1_SEL_1
#define COMP_MODE_FALLING ANA_CTRL_COMP1_SEL_2
#define COMP_MODE_BOTH ANA_CTRL_COMP1_SEL_3
#define IS_COMP_MODE(__MODE__) (((__MODE__) == COMP_MODE_OFF) ||\
((__MODE__) == COMP_MODE_RISING) ||\
((__MODE__) == COMP_MODE_FALLING) ||\
((__MODE__) == COMP_MODE_BOTH))
/***** SourceSelect (COMP_ConfigSignalSource) *****/
#define COMP_SIGNALSRC_P_TO_REF ANA_REG2_CMP1_SEL_0
#define COMP_SIGNALSRC_N_TO_REF ANA_REG2_CMP1_SEL_1
#define COMP_SIGNALSRC_P_TO_N ANA_REG2_CMP1_SEL_2
#define IS_COMP_SIGNALSRC(__SIGNALSRC__) (((__SIGNALSRC__) == COMP_SIGNALSRC_P_TO_REF) ||\
((__SIGNALSRC__) == COMP_SIGNALSRC_N_TO_REF) ||\
((__SIGNALSRC__) == COMP_SIGNALSRC_P_TO_N))
/***** REFSelect (COMP_ConfigREF) *****/
#define COMP_REF_VREF (0)
#define COMP_REF_BGPREF ANA_REG2_REFSEL_CMP1
#define IS_COMP_REF(__REF__) (((__REF__) == COMP_REF_VREF) ||\
((__REF__) == COMP_REF_BGPREF))
/***** BiasSel (COMP_BiasConfig) *****/
#define COMP_BIAS_20nA ANA_REG5_IT_CMP1_0
#define COMP_BIAS_100nA ANA_REG5_IT_CMP1_1
#define COMP_BIAS_500nA ANA_REG5_IT_CMP1_2
#define IS_COMP_BIAS(__BIAS__) (((__BIAS__) == COMP_BIAS_20nA) ||\
((__BIAS__) == COMP_BIAS_100nA)||\
((__BIAS__) == COMP_BIAS_500nA))
/* Exported Functions ------------------------------------------------------- */
void COMP_DEBConfig(uint32_t COMPx, uint32_t Debounce);
void COMP_ModeConfig(uint32_t COMPx, uint32_t Mode);
void COMP_SignalSourceConfig(uint32_t COMPx, uint32_t SourceSelect);
void COMP_REFConfig(uint32_t COMPx, uint32_t REFSelect);
void COMP_BiasConfig(uint32_t COMPx, uint32_t BiasSel);
void COMP_INTConfig(uint32_t COMPx, uint32_t NewState);
uint8_t COMP_GetINTStatus(uint32_t COMPx);
void COMP_ClearINTStatus(uint32_t COMPx);
void COMP_Output_Cmd(uint32_t COMPx, uint32_t NewState);
void COMP_Cmd(uint32_t COMPx, uint32_t NewState);
uint32_t COMP_GetCNTValue(uint32_t COMPx);
void COMP_ClearCNTValue(uint32_t COMPx);
uint8_t COMP1_GetOutputLevel(void);
uint8_t COMP2_GetOutputLevel(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_COMP_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_crypt.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief CRYPT library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CRYPT_H
#define __LIB_CRYPT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//Length
#define CRYPT_LENGTH_32 CRYPT_CTRL_LENGTH_32
#define CRYPT_LENGTH_64 CRYPT_CTRL_LENGTH_64
#define CRYPT_LENGTH_96 CRYPT_CTRL_LENGTH_96
#define CRYPT_LENGTH_128 CRYPT_CTRL_LENGTH_128
#define CRYPT_LENGTH_160 CRYPT_CTRL_LENGTH_160
#define CRYPT_LENGTH_192 CRYPT_CTRL_LENGTH_192
#define CRYPT_LENGTH_224 CRYPT_CTRL_LENGTH_224
#define CRYPT_LENGTH_256 CRYPT_CTRL_LENGTH_256
#define CRYPT_LENGTH_288 CRYPT_CTRL_LENGTH_288
#define CRYPT_LENGTH_320 CRYPT_CTRL_LENGTH_320
#define CRYPT_LENGTH_352 CRYPT_CTRL_LENGTH_352
#define CRYPT_LENGTH_384 CRYPT_CTRL_LENGTH_384
#define CRYPT_LENGTH_416 CRYPT_CTRL_LENGTH_416
#define CRYPT_LENGTH_448 CRYPT_CTRL_LENGTH_448
#define CRYPT_LENGTH_480 CRYPT_CTRL_LENGTH_480
#define CRYPT_LENGTH_512 CRYPT_CTRL_LENGTH_512
//Nostop
#define CRYPT_STOPCPU (0)
#define CRYPT_NOSTOPCPU CRYPT_CTRL_NOSTOP
/* Private macros ------------------------------------------------------------*/
#define IS_CRYPT_ADDR(__ADDR__) (((__ADDR__) < 0x8000) &&\
(((__ADDR__) & 0x3U) == 0U))
#define IS_CRYPT_LENGTH(__LENGTH__) (((__LENGTH__) == CRYPT_LENGTH_32) ||\
((__LENGTH__) == CRYPT_LENGTH_64) ||\
((__LENGTH__) == CRYPT_LENGTH_32) ||\
((__LENGTH__) == CRYPT_LENGTH_96) ||\
((__LENGTH__) == CRYPT_LENGTH_128) ||\
((__LENGTH__) == CRYPT_LENGTH_160) ||\
((__LENGTH__) == CRYPT_LENGTH_192) ||\
((__LENGTH__) == CRYPT_LENGTH_224) ||\
((__LENGTH__) == CRYPT_LENGTH_256) ||\
((__LENGTH__) == CRYPT_LENGTH_288) ||\
((__LENGTH__) == CRYPT_LENGTH_320) ||\
((__LENGTH__) == CRYPT_LENGTH_352) ||\
((__LENGTH__) == CRYPT_LENGTH_384) ||\
((__LENGTH__) == CRYPT_LENGTH_416) ||\
((__LENGTH__) == CRYPT_LENGTH_448) ||\
((__LENGTH__) == CRYPT_LENGTH_480) ||\
((__LENGTH__) == CRYPT_LENGTH_512))
#define IS_CRYPT_NOSTOP(__NOSTOP__) (((__NOSTOP__) == CRYPT_STOPCPU) || ((__NOSTOP__) == CRYPT_NOSTOPCPU))
/* Exported Functions ------------------------------------------------------- */
void CRYPT_AddressAConfig(uint16_t AddrA);
void CRYPT_AddressBConfig(uint16_t AddrB);
void CRYPT_AddressOConfig(uint16_t AddrO);
uint8_t CRYPT_GetCarryBorrowBit(void);
void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop);
void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop);
void CRYPT_StartSub(uint32_t Length, uint32_t Nostop);
void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop);
void CRYPT_WaitForLastOperation(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CRYPT_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_dma.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief DMA library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_DMA_H
#define __LIB_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//Channel
#define DMA_CHANNEL_0 0
#define DMA_CHANNEL_1 1
#define DMA_CHANNEL_2 2
#define DMA_CHANNEL_3 3
typedef struct
{
uint32_t DestAddr; /* destination address */
uint32_t SrcAddr; /* source address */
uint8_t FrameLen; /* Frame length */
uint8_t PackLen; /* Package length */
uint32_t ContMode; /* Continuous mode */
uint32_t TransMode; /* Transfer mode */
uint32_t ReqSrc; /* DMA request source */
uint32_t DestAddrMode; /* Destination address mode */
uint32_t SrcAddrMode; /* Source address mode */
uint32_t TransSize; /* Transfer size mode */
} DMA_InitType;
//ContMode
#define DMA_CONTMODE_ENABLE DMA_CTL_CONT
#define DMA_CONTMODE_DISABLE 0
//TransMode
#define DMA_TRANSMODE_SINGLE 0
#define DMA_TRANSMODE_PACK DMA_CTL_TMODE
//ReqSrc
#define DMA_REQSRC_SOFT DMA_CTL_DMASEL_SOFT
#define DMA_REQSRC_UART0TX DMA_CTL_DMASEL_UART0TX
#define DMA_REQSRC_UART0RX DMA_CTL_DMASEL_UART0RX
#define DMA_REQSRC_UART1TX DMA_CTL_DMASEL_UART1TX
#define DMA_REQSRC_UART1RX DMA_CTL_DMASEL_UART1RX
#define DMA_REQSRC_UART2TX DMA_CTL_DMASEL_UART2TX
#define DMA_REQSRC_UART2RX DMA_CTL_DMASEL_UART2RX
#define DMA_REQSRC_UART3TX DMA_CTL_DMASEL_UART3TX
#define DMA_REQSRC_UART3RX DMA_CTL_DMASEL_UART3RX
#define DMA_REQSRC_UART4TX DMA_CTL_DMASEL_UART4TX
#define DMA_REQSRC_UART4RX DMA_CTL_DMASEL_UART4RX
#define DMA_REQSRC_UART5TX DMA_CTL_DMASEL_UART5TX
#define DMA_REQSRC_UART5RX DMA_CTL_DMASEL_UART5RX
#define DMA_REQSRC_ISO78160TX DMA_CTL_DMASEL_ISO78160TX
#define DMA_REQSRC_ISO78160RX DMA_CTL_DMASEL_ISO78160RX
#define DMA_REQSRC_ISO78161TX DMA_CTL_DMASEL_ISO78161TX
#define DMA_REQSRC_ISO78161RX DMA_CTL_DMASEL_ISO78161RX
#define DMA_REQSRC_TIMER0 DMA_CTL_DMASEL_TIMER0
#define DMA_REQSRC_TIMER1 DMA_CTL_DMASEL_TIMER1
#define DMA_REQSRC_TIMER2 DMA_CTL_DMASEL_TIMER2
#define DMA_REQSRC_TIMER3 DMA_CTL_DMASEL_TIMER3
#define DMA_REQSRC_SPI1TX DMA_CTL_DMASEL_SPI1TX
#define DMA_REQSRC_SPI1RX DMA_CTL_DMASEL_SPI1RX
#define DMA_REQSRC_U32K0 DMA_CTL_DMASEL_U32K0
#define DMA_REQSRC_U32K1 DMA_CTL_DMASEL_U32K1
#define DMA_REQSRC_CMP1 DMA_CTL_DMASEL_CMP1
#define DMA_REQSRC_CMP2 DMA_CTL_DMASEL_CMP2
#define DMA_REQSRC_SPI2TX DMA_CTL_DMASEL_SPI2TX
#define DMA_REQSRC_SPI2RX DMA_CTL_DMASEL_SPI2RX
//DestAddrMode
#define DMA_DESTADDRMODE_FIX DMA_CxCTL_DMODE_FIX
#define DMA_DESTADDRMODE_PEND DMA_CxCTL_DMODE_PEND
#define DMA_DESTADDRMODE_FEND DMA_CxCTL_DMODE_FEND
//SrcAddrMode
#define DMA_SRCADDRMODE_FIX DMA_CxCTL_SMODE_FIX
#define DMA_SRCADDRMODE_PEND DMA_CxCTL_SMODE_PEND
#define DMA_SRCADDRMODE_FEND DMA_CxCTL_SMODE_FEND
//TransSize
#define DMA_TRANSSIZE_BYTE DMA_CxCTL_SIZE_BYTE
#define DMA_TRANSSIZE_HWORD DMA_CxCTL_SIZE_HWORD
#define DMA_TRANSSIZE_WORD DMA_CxCTL_SIZE_WORD
typedef struct
{
uint32_t Mode; /* AES mode */
uint32_t Direction; /* Direction */
uint32_t *KeyStr; /* AES key */
} DMA_AESInitType;
//AES MODE
#define DMA_AESMODE_128 DMA_AESCTL_MODE_AES128
#define DMA_AESMODE_192 DMA_AESCTL_MODE_AES192
#define DMA_AESMODE_256 DMA_AESCTL_MODE_AES256
//AES Direction
#define DMA_AESDIRECTION_ENCODE DMA_AESCTL_ENC
#define DMA_AESDIRECTION_DECODE 0
//INT
#define DMA_INT_C3DA DMA_IE_C3DAIE
#define DMA_INT_C2DA DMA_IE_C2DAIE
#define DMA_INT_C1DA DMA_IE_C1DAIE
#define DMA_INT_C0DA DMA_IE_C0DAIE
#define DMA_INT_C3FE DMA_IE_C3FEIE
#define DMA_INT_C2FE DMA_IE_C2FEIE
#define DMA_INT_C1FE DMA_IE_C1FEIE
#define DMA_INT_C0FE DMA_IE_C0FEIE
#define DMA_INT_C3PE DMA_IE_C3PEIE
#define DMA_INT_C2PE DMA_IE_C2PEIE
#define DMA_INT_C1PE DMA_IE_C1PEIE
#define DMA_INT_C0PE DMA_IE_C0PEIE
#define DMA_INT_Msk (0xFFFUL)
//INTSTS
#define DMA_INTSTS_C3DA DMA_STS_C3DA
#define DMA_INTSTS_C2DA DMA_STS_C2DA
#define DMA_INTSTS_C1DA DMA_STS_C1DA
#define DMA_INTSTS_C0DA DMA_STS_C0DA
#define DMA_INTSTS_C3FE DMA_STS_C3FE
#define DMA_INTSTS_C2FE DMA_STS_C2FE
#define DMA_INTSTS_C1FE DMA_STS_C1FE
#define DMA_INTSTS_C0FE DMA_STS_C0FE
#define DMA_INTSTS_C3PE DMA_STS_C3PE
#define DMA_INTSTS_C2PE DMA_STS_C2PE
#define DMA_INTSTS_C1PE DMA_STS_C1PE
#define DMA_INTSTS_C0PE DMA_STS_C0PE
#define DMA_INTSTS_C3BUSY DMA_STS_C3BUSY
#define DMA_INTSTS_C2BUSY DMA_STS_C2BUSY
#define DMA_INTSTS_C1BUSY DMA_STS_C1BUSY
#define DMA_INTSTS_C0BUSY DMA_STS_C0BUSY
#define DMA_INTSTS_Msk (0xFFF0UL)
/* Private macros ------------------------------------------------------------*/
#define IS_DMA_CHANNEL(__CH__) (((__CH__) == DMA_CHANNEL_0) ||\
((__CH__) == DMA_CHANNEL_1) ||\
((__CH__) == DMA_CHANNEL_2) ||\
((__CH__) == DMA_CHANNEL_3))
#define IS_DMA_ALIGNEDADDR_WORD(__ADDRW__) (((__ADDRW__) & 0x3U) == 0U)
#define IS_DMA_ALIGNEDADDR_HWORD(__ADDRHW__) (((__ADDRHW__) & 0x1U) == 0U)
#define IS_DMA_CONTMOD(__CONTMOD__) (((__CONTMOD__) == DMA_CONTMODE_ENABLE) ||\
((__CONTMOD__) == DMA_CONTMODE_DISABLE))
#define IS_DMA_TRANSMOD(__TRANSMOD__) (((__TRANSMOD__) == DMA_TRANSMODE_SINGLE) ||\
((__TRANSMOD__) == DMA_TRANSMODE_PACK))
#define IS_DMA_REQSRC(__REQSRC__) (((__REQSRC__) == DMA_REQSRC_SOFT) ||\
((__REQSRC__) == DMA_REQSRC_UART0TX) ||\
((__REQSRC__) == DMA_REQSRC_UART0RX) ||\
((__REQSRC__) == DMA_REQSRC_UART1TX) ||\
((__REQSRC__) == DMA_REQSRC_UART1RX) ||\
((__REQSRC__) == DMA_REQSRC_UART2TX) ||\
((__REQSRC__) == DMA_REQSRC_UART2RX) ||\
((__REQSRC__) == DMA_REQSRC_UART3TX) ||\
((__REQSRC__) == DMA_REQSRC_UART3RX) ||\
((__REQSRC__) == DMA_REQSRC_UART4TX) ||\
((__REQSRC__) == DMA_REQSRC_UART4RX) ||\
((__REQSRC__) == DMA_REQSRC_UART5TX) ||\
((__REQSRC__) == DMA_REQSRC_UART5RX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78160TX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78160RX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78161TX) ||\
((__REQSRC__) == DMA_REQSRC_ISO78161RX) ||\
((__REQSRC__) == DMA_REQSRC_TIMER0) ||\
((__REQSRC__) == DMA_REQSRC_TIMER1) ||\
((__REQSRC__) == DMA_REQSRC_TIMER2) ||\
((__REQSRC__) == DMA_REQSRC_TIMER3) ||\
((__REQSRC__) == DMA_REQSRC_SPI1TX) ||\
((__REQSRC__) == DMA_REQSRC_SPI1RX) ||\
((__REQSRC__) == DMA_REQSRC_U32K0) ||\
((__REQSRC__) == DMA_REQSRC_U32K1) ||\
((__REQSRC__) == DMA_REQSRC_CMP1) ||\
((__REQSRC__) == DMA_REQSRC_CMP2) ||\
((__REQSRC__) == DMA_REQSRC_SPI2TX) ||\
((__REQSRC__) == DMA_REQSRC_SPI2RX))
#define IS_DMA_DESTADDRMOD(__DAM__) (((__DAM__) == DMA_DESTADDRMODE_FIX) ||\
((__DAM__) == DMA_DESTADDRMODE_PEND) ||\
((__DAM__) == DMA_DESTADDRMODE_FEND))
#define IS_DMA_SRCADDRMOD(__SAM__) (((__SAM__) == DMA_SRCADDRMODE_FIX) ||\
((__SAM__) == DMA_SRCADDRMODE_PEND) ||\
((__SAM__) == DMA_SRCADDRMODE_FEND))
#define IS_DMA_TRANSSIZE(__TSIZE__) (((__TSIZE__) == DMA_TRANSSIZE_BYTE) ||\
((__TSIZE__) == DMA_TRANSSIZE_HWORD) ||\
((__TSIZE__) == DMA_TRANSSIZE_WORD))
#define IS_DMA_AESMOD(__AESMOD__) (((__AESMOD__) == DMA_AESMODE_128) ||\
((__AESMOD__) == DMA_AESMODE_192) ||\
((__AESMOD__) == DMA_AESMODE_256))
#define IS_DMA_AESDIR(__AESDIR__) (((__AESDIR__) == DMA_AESDIRECTION_ENCODE) ||\
((__AESDIR__) == DMA_AESDIRECTION_DECODE))
#define IS_DMA_INT(__INT__) ((((__INT__) & DMA_INT_Msk) != 0U) &&\
(((__INT__) & ~DMA_INT_Msk) == 0U))
#define IS_DMA_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == DMA_INTSTS_C3DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C2DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C1DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C0DA) ||\
((__INTFLAGR__) == DMA_INTSTS_C3FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C2FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C1FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C0FE) ||\
((__INTFLAGR__) == DMA_INTSTS_C3PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C2PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C1PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C0PE) ||\
((__INTFLAGR__) == DMA_INTSTS_C3BUSY) ||\
((__INTFLAGR__) == DMA_INTSTS_C2BUSY) ||\
((__INTFLAGR__) == DMA_INTSTS_C1BUSY) ||\
((__INTFLAGR__) == DMA_INTSTS_C0BUSY))
#define IS_DMA_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & DMA_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~DMA_INTSTS_Msk) == 0U))
/* Exported Functions ------------------------------------------------------- */
/* DMA Exported Functions Group1:
(De)Initialization ------------------------*/
void DMA_DeInit(uint32_t Channel);
void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel);
void DMA_AESDeInit(void);
void DMA_AESInit(DMA_AESInitType *InitStruct);
/* DMA Exported Functions Group2:
Interrupt (flag) --------------------------*/
void DMA_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t DMA_GetINTStatus(uint32_t INTMask);
void DMA_ClearINTStatus(uint32_t INTMask);
/* DMA Exported Functions Group3:
MISC Configuration ------------------------*/
void DMA_Cmd(uint32_t Channel, uint32_t NewState);
void DMA_AESCmd(uint32_t NewState);
void DMA_StopTransmit(uint32_t Channel, uint32_t NewState);
uint8_t DMA_GetFrameLenTransferred(uint32_t Channel);
uint8_t DMA_GetPackLenTransferred(uint32_t Channel);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_DMA_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_flash.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief FLASH library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_FLASH_H
#define __LIB_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//CSMode
#define FLASH_CSMODE_DISABLE FLASH_CTRL_CSMODE_DISABLE
#define FLASH_CSMODE_ALWAYSON FLASH_CTRL_CSMODE_ALWAYSON
#define FLASH_CSMODE_TIM2OF FLASH_CTRL_CSMODE_TIM2OV
#define FLASH_CSMODE_RTC FLASH_CTRL_CSMODE_RTC
#define IS_FLASH_CSMODE(__CSMODE__) (((__CSMODE__) == FLASH_CSMODE_DISABLE) ||\
((__CSMODE__) == FLASH_CSMODE_ALWAYSON) ||\
((__CSMODE__) == FLASH_CSMODE_TIM2OF) ||\
((__CSMODE__) == FLASH_CSMODE_RTC))
//INT
#define FLASH_INT_CS FLASH_CTRL_CSINTEN
#define IS_FLASH_INT(__INT__) ((__INT__) == FLASH_INT_CS)
//WriteStatus
#define FLASH_WSTA_BUSY 0
#define FLASH_WRITE_FINISH 1
#define FLASH_WSTA_FINISH FLASH_WRITE_FINISH
#define IS_FLASH_ADDRESS(__ADDRESS__) ((__ADDRESS__) < 0x40000UL)
#define IS_FLASH_ADRRW(__ADDRW__) (((__ADDRW__) < 0x40000UL) &&\
(((__ADDRW__) & 0x3U) == 0U))
#define IS_FLASH_ADRRHW(__ADDRHW__) (((__ADDRHW__) < 0x40000UL) &&\
(((__ADDRHW__) & 0x1U) == 0U))
#define IS_FLASH_CHECKSUMADDR(__ADDRESS1__,__ADDRESS2__) (((__ADDRESS1__) < 0x40000) && ((__ADDRESS2__) < 0x40000) && ((__ADDRESS1__) < (__ADDRESS2__)))
/* Exported Functions ------------------------------------------------------- */
void FLASH_Init(uint32_t CSMode);
void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState);
void FLASH_CycleInit(void);
void FLASH_SectorErase(uint32_t SectorAddr);
void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length);
void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length);
void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length);
uint32_t FLASH_GetWriteStatus(void);
void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd);
void FLASH_SetCheckSumCompValue(uint32_t Checksum);
uint32_t FLASH_GetCheckSum(void);
uint8_t FLASH_GetINTStatus(uint32_t IntMask);
void FLASH_ClearINTStatus(uint32_t IntMask);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_FLASH_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_gpio.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief GPIO library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_GPIO_H
#define __LIB_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t GPIO_Pin;
uint32_t GPIO_Mode;
} GPIO_InitType;
/**
* @brief Bit_State_enumeration
*/
typedef enum {
Bit_RESET = 0,
Bit_SET
} BitState;
//GPIO_Pin
#define GPIO_Pin_0 ((uint16_t)0x0001)
#define GPIO_Pin_1 ((uint16_t)0x0002)
#define GPIO_Pin_2 ((uint16_t)0x0004)
#define GPIO_Pin_3 ((uint16_t)0x0008)
#define GPIO_Pin_4 ((uint16_t)0x0010)
#define GPIO_Pin_5 ((uint16_t)0x0020)
#define GPIO_Pin_6 ((uint16_t)0x0040)
#define GPIO_Pin_7 ((uint16_t)0x0080)
#define GPIO_Pin_8 ((uint16_t)0x0100)
#define GPIO_Pin_9 ((uint16_t)0x0200)
#define GPIO_Pin_10 ((uint16_t)0x0400)
#define GPIO_Pin_11 ((uint16_t)0x0800)
#define GPIO_Pin_12 ((uint16_t)0x1000)
#define GPIO_Pin_13 ((uint16_t)0x2000)
#define GPIO_Pin_14 ((uint16_t)0x4000)
#define GPIO_Pin_15 ((uint16_t)0x8000)
#define GPIO_Pin_All ((uint16_t)0xFFFF)
//GPIO_Mode
#define GPIO_Mode_INPUT (0xCU)
#define GPIO_Mode_OUTPUT_CMOS (0x2U)
#define GPIO_Mode_OUTPUT_OD (0x3U)
#define GPIO_Mode_INOUT_OD (0xBU)
#define GPIO_Mode_INOUT_CMOS (0xAU)
#define GPIO_Mode_FORBIDDEN (0x4U)
//GPIO AF
#define GPIOB_AF_PLLHDIV IOB_SEL_SEL1
#define GPIOB_AF_OSC IOB_SEL_SEL6
#define GPIOB_AF_PLLLOUT IOB_SEL_SEL2
#define GPIOE_AF_CMP1O IOE_SEL_SEL7
//PMUIO AF
#define PMUIO7_AF_PLLDIV PMU_IOASEL_SEL7
#define PMUIO_AF_CMP2O PMU_IOASEL_SEL6
#define PMUIO3_AF_PLLDIV PMU_IOASEL_SEL3
#define PMUIO_AF_Msk (PMUIO7_AF_PLLDIV | PMUIO_AF_CMP2O | PMUIO3_AF_PLLDIV)
//GPIO pin remap
#define GPIO_REMAP_I2C IO_MISC_I2CIOC
//PLLDIV
#define GPIO_PLLDIV_1 IO_MISC_PLLHDIV_1
#define GPIO_PLLDIV_2 IO_MISC_PLLHDIV_2
#define GPIO_PLLDIV_4 IO_MISC_PLLHDIV_4
#define GPIO_PLLDIV_8 IO_MISC_PLLHDIV_8
#define GPIO_PLLDIV_16 IO_MISC_PLLHDIV_16
/* Private macros ------------------------------------------------------------*/
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_Pin_All) != 0UL) &&\
(((__PIN__) & ~GPIO_Pin_All) == 0UL))
#define IS_GPIO_PINR(__PINR__) (((__PINR__) == GPIO_Pin_0) ||\
((__PINR__) == GPIO_Pin_1) ||\
((__PINR__) == GPIO_Pin_2) ||\
((__PINR__) == GPIO_Pin_3) ||\
((__PINR__) == GPIO_Pin_4) ||\
((__PINR__) == GPIO_Pin_5) ||\
((__PINR__) == GPIO_Pin_6) ||\
((__PINR__) == GPIO_Pin_7) ||\
((__PINR__) == GPIO_Pin_8) ||\
((__PINR__) == GPIO_Pin_9) ||\
((__PINR__) == GPIO_Pin_10) ||\
((__PINR__) == GPIO_Pin_11) ||\
((__PINR__) == GPIO_Pin_12) ||\
((__PINR__) == GPIO_Pin_13) ||\
((__PINR__) == GPIO_Pin_14) ||\
((__PINR__) == GPIO_Pin_15))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_INPUT) ||\
((__MODE__) == GPIO_Mode_OUTPUT_CMOS) ||\
((__MODE__) == GPIO_Mode_OUTPUT_OD) ||\
((__MODE__) == GPIO_Mode_INOUT_OD) ||\
((__MODE__) == GPIO_Mode_INOUT_CMOS) ||\
((__MODE__) == GPIO_Mode_FORBIDDEN))
#define IS_GPIO_BITVAL(__BITVAL__) (((__BITVAL__) == 1U) || ((__BITVAL__) == 0U))
#define IS_GPIO_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\
((__GPIOAF__) == GPIOB_AF_OSC) ||\
((__GPIOAF__) == GPIOE_AF_CMP1O) ||\
((__GPIOAF__) == GPIOB_AF_PLLLOUT))
#define IS_GPIO_PMUIOAF(__PMUIOAF__) ((((__PMUIOAF__) & PMUIO_AF_Msk) != 0U) &&\
(((__PMUIOAF__) & ~PMUIO_AF_Msk) == 0U))
#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C)
#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\
((__PLLDIV__) == GPIO_PLLDIV_2) ||\
((__PLLDIV__) == GPIO_PLLDIV_4) ||\
((__PLLDIV__) == GPIO_PLLDIV_8) ||\
((__PLLDIV__) == GPIO_PLLDIV_16))
/* Exported Functions ------------------------------------------------------- */
/* GPIO Exported Functions Group1:
Initialization and functions --------------*/
void GPIOBToF_Init(GPIO_TypeDef *GPIOx, GPIO_InitType *InitStruct);
void GPIOA_Init(GPIOA_TypeDef *GPIOx, GPIO_InitType *InitStruct);
/* GPIO Exported Functions Group2:
Read input data ---------------------------*/
uint8_t GPIOBToF_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint8_t GPIOA_ReadInputDataBit(GPIOA_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIOBToF_ReadInputData(GPIO_TypeDef* GPIOx);
uint16_t GPIOA_ReadInputData(GPIOA_TypeDef* GPIOx);
/* GPIO Exported Functions Group3:
Read output data --------------------------*/
uint8_t GPIOBToF_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint8_t GPIOA_ReadOutputDataBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIOBToF_ReadOutputData(GPIO_TypeDef* GPIOx);
uint16_t GPIOA_ReadOutputData(GPIOA_TypeDef* GPIOx);
/* GPIO Exported Functions Group4:
Write output data -------------------------*/
void GPIOBToF_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIOA_SetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIOBToF_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIOA_ResetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIOBToF_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val);
void GPIOA_WriteBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val);
void GPIOBToF_Write(GPIO_TypeDef* GPIOx, uint16_t val);
void GPIOA_Write(GPIOA_TypeDef* GPIOx, uint16_t val);
/* GPIO Exported Functions Group5:
IO AF configure ---------------------------*/
void GPIOBToF_AFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_AFx, uint8_t NewState);
void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState);
/* GPIO Exported Functions Group6:
IO Remap configure ------------------------*/
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState);
/* GPIO Exported Functions Group7:
Others ------------------------------------*/
void GPIO_PLLDIV_Config(uint32_t Divider);
void GPIOA_NoDeg_Cmd( uint16_t GPIO_Pin, uint8_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_GPIO_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_i2c.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief IIC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_I2C_H
#define __LIB_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t SlaveAddr;
uint32_t GeneralCallAck;
uint32_t AssertAcknowledge;
uint32_t ClockSource;
} I2C_InitType;
//GeneralCallAck
#define I2C_GENERALCALLACK_ENABLE I2C_ADDR_GC
#define I2C_GENERALCALLACK_DISABLE 0
//AssertAcknowledge
#define I2C_ASSERTACKNOWLEDGE_ENABLE I2C_CTRL_AA
#define I2C_ASSERTACKNOWLEDGE_DISABLE 0
//ClockSource
#define I2C_CLOCKSOURCE_APBD256 I2C_CTRL_CR_0
#define I2C_CLOCKSOURCE_APBD224 I2C_CTRL_CR_1
#define I2C_CLOCKSOURCE_APBD192 I2C_CTRL_CR_2
#define I2C_CLOCKSOURCE_APBD160 I2C_CTRL_CR_3
#define I2C_CLOCKSOURCE_APBD960 I2C_CTRL_CR_4
#define I2C_CLOCKSOURCE_APBD120 I2C_CTRL_CR_5
#define I2C_CLOCKSOURCE_APBD60 I2C_CTRL_CR_6
#define I2C_CLOCKSOURCE_TIM3OFD8 I2C_CTRL_CR_7
typedef struct
{
uint16_t SlaveAddr;
uint8_t SubAddrType;
uint32_t PageRange;
uint32_t SubAddress;
uint8_t *pBuffer;
uint32_t Length;
} I2C_WRType;
//SubAddrType
#define I2C_SUBADDR_1BYTE 1
#define I2C_SUBADDR_2BYTE 2
#define I2C_SUBADDR_OTHER 3
//remap
#define I2C_REMAP_ENABLE 1
#define I2C_REMAP_DISABLE 0
/* Private macros ------------------------------------------------------------*/
#define IS_I2C_GC(__GC__) (((__GC__) == I2C_GENERALCALLACK_ENABLE) ||\
((__GC__) == I2C_GENERALCALLACK_DISABLE))
#define IS_I2C_AA(__AA__) (((__AA__) == I2C_ASSERTACKNOWLEDGE_ENABLE) ||\
((__AA__) == I2C_ASSERTACKNOWLEDGE_DISABLE))
#define IS_I2C_CLKSRC(__CLKSRC__) (((__CLKSRC__) == I2C_CLOCKSOURCE_APBD256) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD224) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD192) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD160) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD960) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD120) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_APBD60) ||\
((__CLKSRC__) == I2C_CLOCKSOURCE_TIM3OFD8))
#define I2C_SUBADDR_TYPE(__TYPE__) (((__TYPE__) == I2C_SUBADDR_1BYTE) ||\
((__TYPE__) == I2C_SUBADDR_2BYTE) ||\
((__TYPE__) == I2C_SUBADDR_OTHER))
/* Exported Functions ------------------------------------------------------- */
/* I2C Exported Functions Group1:
(De)Initialization ------------------------*/
void I2C_DeInit(uint32_t remap);
void I2C_StructInit(I2C_InitType *InitStruct);
void I2C_Init(I2C_InitType *InitStruct);
/* I2C Exported Functions Group2:
Interrupt ---------------------------------*/
void I2C_INTConfig(uint32_t NewState);
uint8_t I2C_GetINTStatus(void);
void I2C_ClearINTStatus(void);
/* I2C Exported Functions Group3:
Transfer datas ----------------------------*/
uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct);
uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct);
/* I2C Exported Functions Group4:
MISC Configuration ------------------------*/
void I2C_Cmd(uint32_t NewState);
/* I2C Exported Functions Group5:
Others ------------------------------------*/
void I2C_AssertAcknowledgeConfig(uint32_t NewState);
uint8_t I2C_ReceiveData(void);
void I2C_SendData(uint8_t Dat);
void I2C_GenerateSTART(uint32_t NewState);
void I2C_GenerateSTOP(uint32_t NewState);
uint8_t I2C_GetStatusCode(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_I2C_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_iso7816.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief ISO7816 library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_ISO7816_H
#define __LIB_ISO7816_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t FirstBit;
uint32_t ACKLen;
uint32_t Parity;
uint32_t Baudrate;
} ISO7816_InitType;
//FirstBit
#define ISO7816_FIRSTBIT_LSB ISO7816_INFO_LSB
#define ISO7816_FIRSTBIT_MSB 0
#define IS_ISO7816_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == ISO7816_FIRSTBIT_LSB) ||\
((__FIRSTBIT__) == ISO7816_FIRSTBIT_MSB))
//ACKLen
#define ISO7816_ACKLEN_1 0
#define ISO7816_ACKLEN_2 ISO7816_CFG_ACKLEN
#define IS_ISO7816_ACKLEN(__ACKLEN__) (((__ACKLEN__) == ISO7816_ACKLEN_1) ||\
((__ACKLEN__) == ISO7816_ACKLEN_2))
//Parity
#define ISO7816_PARITY_EVEN 0
#define ISO7816_PARITY_ODD ISO7816_CFG_CHKP
#define IS_ISO7816_PARITY(__PARITY__) (((__PARITY__) == ISO7816_PARITY_EVEN) || ((__PARITY__) == ISO7816_PARITY_ODD))
#define IS_ISO7816_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) > 299UL)
#define IS_ISO7816_PRESCALER(__PRESCALER__) (((__PRESCALER__) <= 0x80) && ((__PRESCALER__) > 0U))
//interrupt
#define ISO7816_INT_RXOV ISO7816_CFG_OVIE
#define ISO7816_INT_TX ISO7816_CFG_SDIE
#define ISO7816_INT_RX ISO7816_CFG_RCIE
#define ISO7816_INT_Msk (ISO7816_INT_RXOV \
|ISO7816_INT_TX \
|ISO7816_INT_RX)
#define IS_ISO7816_INT(__INT__) ((((__INT__) & ISO7816_INT_Msk) != 0U) &&\
(((__INT__) & ~ISO7816_INT_Msk) == 0U))
//INTStatus
#define ISO7816_INTSTS_RXOV ISO7816_INFO_OVIF
#define ISO7816_INTSTS_TX ISO7816_INFO_SDIF
#define ISO7816_INTSTS_RX ISO7816_INFO_RCIF
#define ISO7816_INTSTS_Msk (ISO7816_INTSTS_RXOV \
|ISO7816_INTSTS_TX \
|ISO7816_INTSTS_RX)
#define IS_ISO7816_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == ISO7816_INTSTS_RXOV) ||\
((__INTFLAG__) == ISO7816_INTSTS_TX) ||\
((__INTFLAG__) == ISO7816_INTSTS_RX))
#define IS_ISO7816_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&ISO7816_INTSTS_Msk) != 0U) &&\
(((__INTFLAG__)&(~ISO7816_INTSTS_Msk)) == 0U))
//status
#define ISO7816_FLAG_SDERR ISO7816_INFO_SDERR
#define ISO7816_FLAG_RCERR ISO7816_INFO_RCERR
#define ISO7816_FLAG_Msk (ISO7816_FLAG_SDERR|ISO7816_FLAG_RCERR)
#define IS_ISO7816_FLAGR(__FLAG__) (((__FLAG__) == ISO7816_FLAG_SDERR) || ((__FLAG__) == ISO7816_FLAG_RCERR))
#define IS_ISO7816_FLAGC(__FLAG__) ((((__FLAG__) & ISO7816_FLAG_Msk) != 0U) &&\
(((__FLAG__) & (~ISO7816_FLAG_Msk)) == 0U))
/* Exported Functions ------------------------------------------------------- */
void ISO7816_DeInit(ISO7816_TypeDef *ISO7816x);
void ISO7816_StructInit(ISO7816_InitType *InitStruct);
void ISO7816_Init(ISO7816_TypeDef *ISO7816x, ISO7816_InitType *Init_Struct);
void ISO7816_Cmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState);
void ISO7816_BaudrateConfig(ISO7816_TypeDef *ISO7816x, uint32_t BaudRate);
void ISO7816_CLKDIVConfig(ISO7816_TypeDef *ISO7816x, uint32_t Prescaler);
void ISO7816_CLKOutputCmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState);
void ISO7816_SendData(ISO7816_TypeDef *ISO7816x, uint8_t ch);
uint8_t ISO7816_ReceiveData(ISO7816_TypeDef *ISO7816x);
void ISO7816_INTConfig(ISO7816_TypeDef *ISO7816x, uint32_t INTMask, uint8_t NewState);
uint8_t ISO7816_GetINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask);
void ISO7816_ClearINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask);
uint8_t ISO7816_GetFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask);
void ISO7816_ClearFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask);
uint8_t ISO7816_GetLastTransmitACK(ISO7816_TypeDef *ISO7816x);
uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_TypeDef *ISO7816x);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_ISO7816_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_lcd.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief LCD library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_LCD_H
#define __LIB_LCD_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* LCD SEGx IO typedef */
typedef struct
{
__IO uint32_t *GPIO;
uint16_t Pin;
}LCD_SEGIO;
/* LCD COMx IO typedef */
typedef struct
{
__IO uint32_t *GPIO;
uint16_t Pin;
}LCD_COMIO;
typedef struct
{
uint32_t Type;
uint32_t Drv;
uint32_t FRQ;
uint32_t SWPR;
uint32_t FBMODE;
uint32_t BKFILL;
} LCD_InitType;
//Type
#define LCD_TYPE_4COM LCD_CTRL_TYPE_4COM
#define LCD_TYPE_6COM LCD_CTRL_TYPE_6COM
#define LCD_TYPE_8COM LCD_CTRL_TYPE_8COM
//DrivingRes
#define LCD_DRV_300 LCD_CTRL_DRV_300KOHM
#define LCD_DRV_600 LCD_CTRL_DRV_600KOHM
#define LCD_DRV_150 LCD_CTRL_DRV_150KOHM
#define LCD_DRV_200 LCD_CTRL_DRV_200KOHM
//ScanFRQ
#define LCD_FRQ_64H LCD_CTRL_FRQ_64HZ
#define LCD_FRQ_128H LCD_CTRL_FRQ_128HZ
#define LCD_FRQ_256H LCD_CTRL_FRQ_256HZ
#define LCD_FRQ_512H LCD_CTRL_FRQ_512HZ
//SwitchMode
#define LCD_FBMODE_BUFA LCD_CTRL2_FBMODE_BUFA
#define LCD_FBMODE_BUFAB LCD_CTRL2_FBMODE_BUFAANDBUFB
#define LCD_FBMODE_BUFABLANK LCD_CTRL2_FBMODE_BUFAANDBLANK
//BlankFill
#define LCD_BKFILL_1 LCD_CTRL2_BKFILL
#define LCD_BKFILL_0 0
//ComMode
#define LCD_COMMOD_4COM 1
#define LCD_COMMOD_6COM 3
#define LCD_COMMOD_8COM 7
//BiasSelection
#define LCD_BMODE_DIV3 0
#define LCD_BMODE_DIV4 ANA_REG6_LCD_BMODE
//VLCDSelection
#define LCD_VLCD_0 0
#define LCD_VLCD_INC60MV 1
#define LCD_VLCD_INC120MV 2
#define LCD_VLCD_INC180MV 3
#define LCD_VLCD_INC240MV 4
#define LCD_VLCD_INC300MV 5
#define LCD_VLCD_DEC60MV 6
#define LCD_VLCD_DEC120MV 7
#define LCD_VLCD_DEC180MV 8
#define LCD_VLCD_DEC240MV 9
#define LCD_VLCD_DEC300MV 10
#define LCD_VLCD_DEC360MV 11
#define LCD_VLCD_DEC420MV 12
#define LCD_VLCD_DEC480MV 13
#define LCD_VLCD_DEC540MV 14
#define LCD_VLCD_DEC600MV 15
/* Private macros ------------------------------------------------------------*/
#define IS_LCD_TYPE(__TYPE__) (((__TYPE__) == LCD_TYPE_4COM) ||\
((__TYPE__) == LCD_TYPE_6COM) ||\
((__TYPE__) == LCD_TYPE_8COM))
#define IS_LCD_DRV(__DRV__) (((__DRV__) == LCD_DRV_300) ||\
((__DRV__) == LCD_DRV_600) ||\
((__DRV__) == LCD_DRV_150) ||\
((__DRV__) == LCD_DRV_200))
#define IS_LCD_FRQ(__FRQ__) (((__FRQ__) == LCD_FRQ_64H) ||\
((__FRQ__) == LCD_FRQ_128H) ||\
((__FRQ__) == LCD_FRQ_256H) ||\
((__FRQ__) == LCD_FRQ_512H))
#define IS_LCD_SWPR(__SWPR__) ((__SWPR__) <= 0xFFUL)
#define IS_LCD_FBMODE(__FBMODE__) (((__FBMODE__) == LCD_FBMODE_BUFA) ||\
((__FBMODE__) == LCD_FBMODE_BUFAB) ||\
((__FBMODE__) == LCD_FBMODE_BUFABLANK))
#define IS_LCD_BKFILL(__BKFILL__) (((__BKFILL__) == LCD_BKFILL_1) || ((__BKFILL__) == LCD_BKFILL_0))
#define IS_LCD_BMODE(__BMODE__) (((__BMODE__) == LCD_BMODE_DIV3) ||\
((__BMODE__) == LCD_BMODE_DIV4))
#define IS_LCD_COMMOD(__COMMOD__) (((__COMMOD__) == LCD_COMMOD_4COM) ||\
((__COMMOD__) == LCD_COMMOD_6COM) ||\
((__COMMOD__) == LCD_COMMOD_8COM))
#define IS_LCD_VLCD(__VLCD__) (((__VLCD__) == LCD_VLCD_0) ||\
((__VLCD__) == LCD_VLCD_INC60MV) ||\
((__VLCD__) == LCD_VLCD_INC120MV) ||\
((__VLCD__) == LCD_VLCD_INC180MV) ||\
((__VLCD__) == LCD_VLCD_INC240MV) ||\
((__VLCD__) == LCD_VLCD_INC300MV) ||\
((__VLCD__) == LCD_VLCD_DEC60MV) ||\
((__VLCD__) == LCD_VLCD_DEC120MV) ||\
((__VLCD__) == LCD_VLCD_DEC180MV) ||\
((__VLCD__) == LCD_VLCD_DEC240MV) ||\
((__VLCD__) == LCD_VLCD_DEC300MV) ||\
((__VLCD__) == LCD_VLCD_DEC360MV) ||\
((__VLCD__) == LCD_VLCD_DEC420MV) ||\
((__VLCD__) == LCD_VLCD_DEC480MV) ||\
((__VLCD__) == LCD_VLCD_DEC540MV) ||\
((__VLCD__) == LCD_VLCD_DEC600MV))
/* Exported Functions ------------------------------------------------------- */
/* LCD Exported Functions Group1:
(De)Initialization -------------------------*/
void LCD_DeInit(void);
void LCD_StructInit(LCD_InitType *LCD_InitStruct);
void LCD_Init(LCD_InitType *InitStruct);
/* LCD Exported Functions Group1:
MISC Configuration -------------------------*/
void LCD_Cmd(uint32_t NewState);
void LCD_IOConfig(uint32_t ComMode, uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2, uint32_t NewState);
void LCD_SetSEG(uint32_t SegCtrl0, uint32_t SegCtrl1, uint16_t SegCtrl2);
void LCD_BiasModeConfig(uint32_t BiasSelection);
uint32_t LCD_VoltageConfig(uint32_t VLCDSelection);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_LCD_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_misc.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief MISC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_MISC_H
#define __LIB_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//FlagMask
#define MISC_FLAG_LOCKUP MISC_SRAMINT_LOCKUP
#define MISC_FLAG_PIAC MISC_SRAMINT_PIAC
#define MISC_FLAG_HIAC MISC_SRAMINT_HIAC
#define MISC_FLAG_PERR MISC_SRAMINT_PERR
#define MISC_FLAG_Msk (MISC_FLAG_LOCKUP | MISC_FLAG_PIAC | MISC_FLAG_HIAC | MISC_FLAG_PERR)
//MISC interrupt
#define MISC_INT_LOCK MISC_SRAMINIT_LOCKIE
#define MISC_INT_PIAC MISC_SRAMINIT_PIACIE
#define MISC_INT_HIAC MISC_SRAMINIT_HIACIE
#define MISC_INT_PERR MISC_SRAMINIT_PERRIE
#define MISC_INT_Msk (MISC_INT_LOCK | MISC_INT_PIAC | MISC_INT_HIAC | MISC_INT_PERR)
//IR
#define MISC_IREN_TX0 MISC_IREN_UART0
#define MISC_IREN_TX1 MISC_IREN_UART1
#define MISC_IREN_TX2 MISC_IREN_UART2
#define MISC_IREN_TX3 MISC_IREN_UART3
#define MISC_IREN_TX4 MISC_IREN_UART4
#define MISC_IREN_TX5 MISC_IREN_UART5
#define MISC_IREN_Msk (0x3FUL)
/* Private macros ------------------------------------------------------------*/
#define IS_MISC_FLAGR(__FLAGR__) (((__FLAGR__) == MISC_FLAG_LOCKUP) ||\
((__FLAGR__) == MISC_FLAG_PIAC) ||\
((__FLAGR__) == MISC_FLAG_HIAC) ||\
((__FLAGR__) == MISC_FLAG_PERR))
#define IS_MISC_FLAGC(__FLAGC__) ((((__FLAGC__) & MISC_FLAG_Msk) != 0U) &&\
(((__FLAGC__) & ~MISC_FLAG_Msk) == 0U))
#define IS_MISC_INT(__INT__) ((((__INT__) & MISC_INT_Msk) != 0U) &&\
(((__INT__) &~MISC_INT_Msk) == 0U))
#define IS_MISC_IREN(__IREN__) ((((__IREN__) & MISC_IREN_Msk) != 0U) &&\
(((__IREN__) & ~MISC_IREN_Msk) == 0U))
/* Exported Functions ------------------------------------------------------- */
uint8_t MISC_GetFlag(uint32_t FlagMask);
void MISC_ClearFlag(uint32_t FlagMask);
void MISC_INTConfig(uint32_t INTMask, uint32_t NewState);
void MISC_SRAMParityCmd(uint32_t NewState);
uint32_t MISC_GetSRAMPEAddr(void);
uint32_t MISC_GetAPBErrAddr(void);
uint32_t MISC_GetAHBErrAddr(void);
void MISC_IRCmd(uint32_t IRx, uint32_t NewState);
void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow);
void MISC_HardFaultCmd(uint32_t NewState);
void MISC_LockResetCmd(uint32_t NewState);
void MISC_IRQLATConfig(uint8_t Latency);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_MISC_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_pmu.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief PMU library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_PMU_H
#define __LIB_PMU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/**
* Deep-sleep low-power configuration
*/
typedef struct
{
uint32_t COMP1Power; /* Comparator 1 power control */
uint32_t COMP2Power; /* Comparator 2 power control */
uint32_t TADCPower; /* Tiny ADC power control */
uint32_t BGPPower; /* BGP power control */
uint32_t AVCCPower; /* AVCC power control */
uint32_t LCDPower; /* LCD controller power control */
uint32_t VDCINDetector; /* VDCIN detector control */
uint32_t VDDDetector; /* VDD detector control */
uint32_t AHBPeriphralDisable; /* AHB Periphral clock disable selection */
uint32_t APBPeriphralDisable; /* APB Periphral clock disable selection */
} PMU_LowPWRTypeDef;
/* COMP1Power */
#define PMU_COMP1PWR_ON (ANA_REG3_CMP1PDN)
#define PMU_COMP1PWR_OFF (0)
#define IS_PMU_COMP1PWR(__COMP1PWR__) (((__COMP1PWR__) == PMU_COMP1PWR_ON) ||\
((__COMP1PWR__) == PMU_COMP1PWR_OFF))
/* COMP2Power */
#define PMU_COMP2PWR_ON (ANA_REG3_CMP2PDN)
#define PMU_COMP2PWR_OFF (0)
#define IS_PMU_COMP2PWR(__COMP2PWR__) (((__COMP2PWR__) == PMU_COMP2PWR_ON) ||\
((__COMP2PWR__) == PMU_COMP2PWR_OFF))
/* TADCPower */
#define PMU_TADCPWR_ON (ANA_REGF_PDNADT)
#define PMU_TADCPWR_OFF (0)
#define IS_PMU_TADCPWR(__TADCPWR__) (((__TADCPWR__) == PMU_TADCPWR_ON) ||\
((__TADCPWR__) == PMU_TADCPWR_OFF))
/* BGPPower */
#define PMU_BGPPWR_ON (0)
#define PMU_BGPPWR_OFF (ANA_REG3_BGPPD)
#define IS_PMU_BGPPWR(__BGPPWR__) (((__BGPPWR__) == PMU_BGPPWR_ON) ||\
((__BGPPWR__) == PMU_BGPPWR_OFF))
/* AVCCPower */
#define PMU_AVCCPWR_ON (0)
#define PMU_AVCCPWR_OFF (ANA_REG8_PD_AVCCLDO)
#define IS_PMU_AVCCPWR(__AVCCPWR__) (((__AVCCPWR__) == PMU_AVCCPWR_ON) ||\
((__AVCCPWR__) == PMU_AVCCPWR_OFF))
/* LCDPower */
#define PMU_LCDPWER_ON (LCD_CTRL_EN)
#define PMU_LCDPWER_OFF (0)
#define IS_PMU_LCDPWER(__LCDPWER__) (((__LCDPWER__) == PMU_LCDPWER_ON) ||\
((__LCDPWER__) == PMU_LCDPWER_OFF))
/* VDCINDetector */
#define PMU_VDCINDET_ENABLE (0)
#define PMU_VDCINDET_DISABLE (ANA_REGA_PD_VDCINDET)
#define IS_PMU_VDCINDET(__VDCINDET__) (((__VDCINDET__) == PMU_VDCINDET_ENABLE) ||\
((__VDCINDET__) == PMU_VDCINDET_DISABLE))
/* VDDDetector */
#define PMU_VDDDET_ENABLE (0)
#define PMU_VDDDET_DISABLE (ANA_REG9_PDDET)
#define IS_PMU_VDDDET(__VDDDET__) (((__VDDDET__) == PMU_VDDDET_ENABLE) ||\
((__VDDDET__) == PMU_VDDDET_DISABLE))
/* APBPeriphralDisable */
#define PMU_APB_ALL (MISC2_PCLKEN_DMA \
|MISC2_PCLKEN_I2C \
|MISC2_PCLKEN_SPI1 \
|MISC2_PCLKEN_UART0 \
|MISC2_PCLKEN_UART1 \
|MISC2_PCLKEN_UART2 \
|MISC2_PCLKEN_UART3 \
|MISC2_PCLKEN_UART4 \
|MISC2_PCLKEN_UART5 \
|MISC2_PCLKEN_ISO78160\
|MISC2_PCLKEN_ISO78161\
|MISC2_PCLKEN_TIMER \
|MISC2_PCLKEN_MISC \
|MISC2_PCLKEN_U32K0 \
|MISC2_PCLKEN_U32K1 \
|MISC2_PCLKEN_SPI2)
#define PMU_APB_DMA MISC2_PCLKEN_DMA
#define PMU_APB_I2C MISC2_PCLKEN_I2C
#define PMU_APB_SPI1 MISC2_PCLKEN_SPI1
#define PMU_APB_UART0 MISC2_PCLKEN_UART0
#define PMU_APB_UART1 MISC2_PCLKEN_UART1
#define PMU_APB_UART2 MISC2_PCLKEN_UART2
#define PMU_APB_UART3 MISC2_PCLKEN_UART3
#define PMU_APB_UART4 MISC2_PCLKEN_UART4
#define PMU_APB_UART5 MISC2_PCLKEN_UART5
#define PMU_APB_ISO78160 MISC2_PCLKEN_ISO78160
#define PMU_APB_ISO78161 MISC2_PCLKEN_ISO78161
#define PMU_APB_TIMER MISC2_PCLKEN_TIMER
#define PMU_APB_MISC MISC2_PCLKEN_MISC
#define PMU_APB_U32K0 MISC2_PCLKEN_U32K0
#define PMU_APB_U32K1 MISC2_PCLKEN_U32K1
#define PMU_APB_SPI2 MISC2_PCLKEN_SPI2
/* AHBPeriphralDisable */
#define PMU_AHB_ALL (MISC2_HCLKEN_DMA \
|MISC2_HCLKEN_GPIO \
|MISC2_HCLKEN_LCD \
|MISC2_HCLKEN_CRYPT)
#define PMU_AHB_DMA MISC2_HCLKEN_DMA
#define PMU_AHB_GPIO MISC2_HCLKEN_GPIO
#define PMU_AHB_LCD MISC2_HCLKEN_LCD
#define PMU_AHB_CRYPT MISC2_HCLKEN_CRYPT
//PMU interrupt
#define PMU_INT_IOAEN PMU_CONTROL_INT_IOA_EN
#define PMU_INT_32K PMU_CONTROL_INT_32K_EN
#define PMU_INT_6M PMU_CONTROL_INT_6M_EN
#define PMU_INT_Msk (PMU_INT_IOAEN \
|PMU_INT_32K \
|PMU_INT_6M)
#define IS_PMU_INT(__INT__) ((((__INT__)&PMU_INT_Msk) != 0U) &&\
(((__INT__)&(~PMU_INT_Msk)) == 0U))
//INTStatus
#define PMU_INTSTS_32K PMU_STS_INT_32K
#define PMU_INTSTS_6M PMU_STS_INT_6M
#define PMU_INTSTS_EXTRST PMU_STS_EXTRST
#define PMU_INTSTS_PORST PMU_STS_PORST
#define PMU_INTSTS_DPORST PMU_STS_DPORST
#define PMU_INTSTS_Msk (PMU_INTSTS_32K \
|PMU_INTSTS_6M \
|PMU_INTSTS_EXTRST \
|PMU_INTSTS_PORST \
|PMU_INTSTS_DPORST)
#define IS_PMU_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == PMU_INTSTS_32K) ||\
((__INTFLAG__) == PMU_INTSTS_6M) ||\
((__INTFLAG__) == PMU_INTSTS_EXTRST) ||\
((__INTFLAG__) == PMU_INTSTS_PORST) ||\
((__INTFLAG__) == PMU_INTSTS_DPORST))
#define IS_PMU_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&PMU_INTSTS_Msk) != 0U) &&\
(((__INTFLAG__)&(~PMU_INTSTS_Msk)) == 0U))
//Status
#define PMU_STS_32K PMU_STS_EXIST_32K
#define PMU_STS_6M PMU_STS_EXIST_6M
#define IS_PMU_FLAG(__FLAG__) (((__FLAG__) == PMU_STS_32K) || ((__FLAG__) == PMU_STS_6M))
//Wakeup_Event
#define IOA_DISABLE (0)
#define IOA_RISING (1)
#define IOA_FALLING (2)
#define IOA_HIGH (3)
#define IOA_LOW (4)
#define IOA_EDGEBOTH (5)
#define IS_PMU_WAKEUP(__WAKEUP__) (((__WAKEUP__) == IOA_DISABLE) ||\
((__WAKEUP__) == IOA_RISING) ||\
((__WAKEUP__) == IOA_FALLING) ||\
((__WAKEUP__) == IOA_HIGH) ||\
((__WAKEUP__) == IOA_LOW) ||\
((__WAKEUP__) == IOA_EDGEBOTH))
/***** Wakeup_Event (PMU_SleepWKUSRC_Config_RTC) *****/
#define PMU_RTCEVT_ACDONE RTC_INTSTS_INTSTS7
#define PMU_RTCEVT_WKUCNT RTC_INTSTS_INTSTS6
#define PMU_RTCEVT_MIDNIGHT RTC_INTSTS_INTSTS5
#define PMU_RTCEVT_WKUHOUR RTC_INTSTS_INTSTS4
#define PMU_RTCEVT_WKUMIN RTC_INTSTS_INTSTS3
#define PMU_RTCEVT_WKUSEC RTC_INTSTS_INTSTS2
#define PMU_RTCEVT_TIMEILLE RTC_INTSTS_INTSTS1
#define PMU_RTCEVT_Msk (PMU_RTCEVT_ACDONE \
|PMU_RTCEVT_WKUCNT \
|PMU_RTCEVT_MIDNIGHT \
|PMU_RTCEVT_WKUHOUR \
|PMU_RTCEVT_WKUMIN \
|PMU_RTCEVT_WKUSEC \
|PMU_RTCEVT_TIMEILLE)
#define IS_PMU_RTCEVT(__RTCEVT__) ((((__RTCEVT__)&PMU_RTCEVT_Msk) != 0U) &&\
(((__RTCEVT__)&(~PMU_RTCEVT_Msk)) == 0U))
/***** BATDisc (PMU_BATDischargeConfig) *****/
#define PMU_BATRTC_DISC ANA_REG6_BATRTCDISC
#define IS_PMU_BATRTCDISC(__BATRTCDISC__) ((__BATRTCDISC__) == PMU_BATRTC_DISC)
/***** PowerThreshold (PMU_PowerAlarmTHConfig) *****/
#define PMU_PWTH_4_5 ANA_REG8_VDDPVDSEL_0
#define PMU_PWTH_4_2 ANA_REG8_VDDPVDSEL_1
#define PMU_PWTH_3_9 ANA_REG8_VDDPVDSEL_2
#define PMU_PWTH_3_6 ANA_REG8_VDDPVDSEL_3
#define PMU_PWTH_3_2 ANA_REG8_VDDPVDSEL_4
#define PMU_PWTH_2_9 ANA_REG8_VDDPVDSEL_5
#define PMU_PWTH_2_6 ANA_REG8_VDDPVDSEL_6
#define PMU_PWTH_2_3 ANA_REG8_VDDPVDSEL_7
#define IS_PMU_PWTH(__PWTH__) (((__PWTH__) == PMU_PWTH_4_5) ||\
((__PWTH__) == PMU_PWTH_4_2) ||\
((__PWTH__) == PMU_PWTH_3_9) ||\
((__PWTH__) == PMU_PWTH_3_6) ||\
((__PWTH__) == PMU_PWTH_3_2) ||\
((__PWTH__) == PMU_PWTH_2_9) ||\
((__PWTH__) == PMU_PWTH_2_6) ||\
((__PWTH__) == PMU_PWTH_2_3))
/***** RTCLDOSel (PMU_RTCLDOConfig) *****/
#define PMU_RTCLDO_1_5 (0)
#define PMU_RTCLDO_1_2 ANA_REGA_RTCVSEL
/***** StatusMask (PMU_GetPowerStatus) *****/
#define PMU_PWRSTS_AVCCLV ANA_COMPOUT_AVCCLV
#define PMU_PWRSTS_VDCINDROP ANA_COMPOUT_VDCINDROP
#define PMU_PWRSTS_VDDALARM ANA_COMPOUT_VDDALARM
/***** Debounce (PMU_PWRDropDEBConfig) *****/
#define PMU_PWRDROP_DEB_0 ANA_CTRL_PWRDROPDEB_0
#define PMU_PWRDROP_DEB_1 ANA_CTRL_PWRDROPDEB_1
#define PMU_PWRDROP_DEB_2 ANA_CTRL_PWRDROPDEB_2
#define PMU_PWRDROP_DEB_3 ANA_CTRL_PWRDROPDEB_3
#define IS_PMU_PWRDROP_DEB(__DEB__) (((__DEB__) == PMU_PWRDROP_DEB_0) ||\
((__DEB__) == PMU_PWRDROP_DEB_1) ||\
((__DEB__) == PMU_PWRDROP_DEB_2) ||\
((__DEB__) == PMU_PWRDROP_DEB_3))
/***** RSTSource (PMU_GetRSTSource) *****/
#define PMU_RSTSRC_EXTRST PMU_STS_EXTRST
#define PMU_RSTSRC_PORST PMU_STS_PORST
#define PMU_RSTSRC_DPORST PMU_STS_DPORST
//#define PMU_RSTSRC_WDTRST PMU_WDTSTS_WDTSTS
#define IS_PMU_RSTSRC(__RSTSRC__) (((__RSTSRC__) == PMU_RSTSRC_EXTRST) ||\
((__RSTSRC__) == PMU_RSTSRC_PORST) ||\
((__RSTSRC__) == PMU_RSTSRC_DPORST) )
/***** PMU_PDNDSleepConfig *****/
//VDCIN_PDNS
#define PMU_VDCINPDNS_0 (0)
#define PMU_VDCINPDNS_1 (ANA_CTRL_PDNS)
#define IS_PMU_VDCINPDNS(__VDCINPDNS__) (((__VDCINPDNS__) == PMU_VDCINPDNS_0) ||\
((__VDCINPDNS__) == PMU_VDCINPDNS_1))
//VDD_PDNS
#define PMU_VDDPDNS_0 (0)
#define PMU_VDDPDNS_1 (ANA_CTRL_PDNS2)
#define IS_PMU_VDDPDNS(__VDDPDNS__) (((__VDDPDNS__) == PMU_VDDPDNS_0) ||\
((__VDDPDNS__) == PMU_VDDPDNS_1))
/* Exported Functions ------------------------------------------------------- */
uint32_t PMU_EnterDSleepMode(void);
void PMU_EnterIdleMode(void);
uint32_t PMU_EnterSleepMode(void);
void PMU_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t PMU_GetINTStatus(uint32_t INTMask);
void PMU_ClearINTStatus(uint32_t INTMask);
uint8_t PMU_GetStatus(uint32_t Mask);
uint16_t PMU_GetIOAAllINTStatus(void);
uint16_t PMU_GetIOAINTStatus(uint16_t INTMask);
void PMU_ClearIOAINTStatus(uint16_t INTMask);
void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event);
uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct);
uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct);
#ifndef __GNUC__
void PMU_EnterIdle_LowPower(void);
#endif
void PMU_SleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority);
void PMU_SleepWKUSRC_Config_RTC(uint32_t Wakeup_Event, uint32_t Priority);
void PMU_DeepSleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event);
void PMU_DeepSleepWKUSRC_Config_RTC(uint32_t Wakeup_Event);
void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS);
/***** BGP functions *****/
void PMU_BGP_Cmd(uint32_t NewState);
/***** VDD functions *****/
void PMU_VDDAlarmTHConfig(uint32_t PowerThreshold);
uint8_t PMU_GetVDDALARMStatus(void);
void PMU_VDDDetectorCmd(uint32_t NewState);
/***** AVCC functions *****/
void PMU_AVCC_Cmd(uint32_t NewState);
void PMU_AVCCOutput_Cmd(uint32_t NewState);
void PMU_AVCCLVDetector_Cmd(uint32_t NewState);
uint8_t PMU_GetAVCCLVStatus(void);
/***** VDCIN functions *****/
void PMU_VDCINDetector_Cmd(uint32_t NewState);
uint8_t PMU_GetVDCINDropStatus(void);
/***** BAT functions *****/
void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState);
/***** Other functions *****/
uint8_t PMU_GetModeStatus(void);
uint8_t PMU_GetPowerStatus(uint32_t StatusMask);
void PMU_PWRDropDEBConfig(uint32_t Debounce);
uint8_t PMU_GetRSTSource(uint32_t RSTSource);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_PMU_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_pwm.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief PWM library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_PWM_H
#define __LIB_PWM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t ClockDivision;
uint32_t Mode;
uint32_t ClockSource;
} PWM_BaseInitType;
//ClockDivision
#define PWM_CLKDIV_2 PWM_CTL_ID_DIV2
#define PWM_CLKDIV_4 PWM_CTL_ID_DIV4
#define PWM_CLKDIV_8 PWM_CTL_ID_DIV8
#define PWM_CLKDIV_16 PWM_CTL_ID_DIV16
//Mode
#define PWM_MODE_STOP PWM_CTL_MC_STOP
#define PWM_MODE_UPCOUNT PWM_CTL_MC_UP
#define PWM_MODE_CONTINUOUS PWM_CTL_MC_CONTINUE
#define PWM_MODE_UPDOWN PWM_CTL_MC_UPDOWN
//ClockSource
#define PWM_CLKSRC_APB PWM_CTL_TESL_APBDIV1
#define PWM_CLKSRC_APBD128 PWM_CTL_TESL_APBDIV128
typedef struct
{
uint32_t Period;
uint32_t OutMode;
} PWM_OCInitType;
//OUTMOD
#define PWM_OUTMOD_CONST PWM_CCTL_OUTMOD_CONST
#define PWM_OUTMOD_SET PWM_CCTL_OUTMOD_SET
#define PWM_OUTMOD_TOGGLE_RESET PWM_CCTL_OUTMOD_TOGGLE_RESET
#define PWM_OUTMOD_SET_RESET PWM_CCTL_OUTMOD_SET_RESET
#define PWM_OUTMOD_TOGGLE PWM_CCTL_OUTMOD_TOGGLE
#define PWM_OUTMOD_RESET PWM_CCTL_OUTMOD_RESET
#define PWM_OUTMOD_TOGGLE_SET PWM_CCTL_OUTMOD_TOGGLE_SET
#define PWM_OUTMOD_RESET_SET PWM_CCTL_OUTMOD_RESET_SET
//PWM CHANNEL
#define PWM_CHANNEL_0 0
#define PWM_CHANNEL_1 1
#define PWM_CHANNEL_2 2
#define PWM_OSEL0_T0O0 (0<<0)
#define PWM_OSEL0_T0O1 (1<<0)
#define PWM_OSEL0_T0O2 (2<<0)
#define PWM_OSEL0_T1O0 (4<<0)
#define PWM_OSEL0_T1O1 (5<<0)
#define PWM_OSEL0_T1O2 (6<<0)
#define PWM_OSEL0_T2O0 (8<<0)
#define PWM_OSEL0_T2O1 (9<<0)
#define PWM_OSEL0_T2O2 (10<<0)
#define PWM_OSEL0_T3O0 (12<<0)
#define PWM_OSEL0_T3O1 (13<<0)
#define PWM_OSEL0_T3O2 (14<<0)
//outline
#define PWM_OLINE_0 1
#define PWM_OLINE_1 2
#define PWM_OLINE_2 4
#define PWM_OLINE_3 8
#define PWM_OLINE_Msk 0xF
//PWM output selection
#define PWM0_OUT0 PWM_OSEL0_T0O0
#define PWM0_OUT1 PWM_OSEL0_T0O1
#define PWM0_OUT2 PWM_OSEL0_T0O2
#define PWM1_OUT0 PWM_OSEL0_T1O0
#define PWM1_OUT1 PWM_OSEL0_T1O1
#define PWM1_OUT2 PWM_OSEL0_T1O2
#define PWM2_OUT0 PWM_OSEL0_T2O0
#define PWM2_OUT1 PWM_OSEL0_T2O1
#define PWM2_OUT2 PWM_OSEL0_T2O2
#define PWM3_OUT0 PWM_OSEL0_T3O0
#define PWM3_OUT1 PWM_OSEL0_T3O1
#define PWM3_OUT2 PWM_OSEL0_T3O2
//Level
#define PWM_LEVEL_HIGH PWM_CCTL_OUT
#define PWM_LEVEL_LOW 0
/* Private macros ------------------------------------------------------------*/
#define IS_PWM_CLKDIV(__CLKDIV__) (((__CLKDIV__) == PWM_CLKDIV_2) ||\
((__CLKDIV__) == PWM_CLKDIV_4) ||\
((__CLKDIV__) == PWM_CLKDIV_8) ||\
((__CLKDIV__) == PWM_CLKDIV_16))
#define IS_PWM_CNTMODE(__CNTMODE__) (((__CNTMODE__) == PWM_MODE_STOP) ||\
((__CNTMODE__) == PWM_MODE_UPCOUNT) ||\
((__CNTMODE__) == PWM_MODE_CONTINUOUS) ||\
((__CNTMODE__) == PWM_MODE_UPDOWN))
#define IS_PWM_CLKSRC(__CLKSRC__) (((__CLKSRC__) == PWM_CLKSRC_APB) ||\
((__CLKSRC__) == PWM_CLKSRC_APBD128))
#define IS_PWM_OUTMODE(__OUTMODE__) (((__OUTMODE__) == PWM_OUTMOD_CONST) ||\
((__OUTMODE__) == PWM_OUTMOD_SET) ||\
((__OUTMODE__) == PWM_OUTMOD_TOGGLE_RESET) ||\
((__OUTMODE__) == PWM_OUTMOD_SET_RESET) ||\
((__OUTMODE__) == PWM_OUTMOD_TOGGLE) ||\
((__OUTMODE__) == PWM_OUTMOD_RESET) ||\
((__OUTMODE__) == PWM_OUTMOD_TOGGLE_SET) ||\
((__OUTMODE__) == PWM_OUTMOD_RESET_SET))
#define IS_PWM_CCR(__CCR__) ((__CCR__) < 0x10000U)
#define IS_PWM_CHANNEL(__CHANNEL__) (((__CHANNEL__) == PWM_CHANNEL_0) ||\
((__CHANNEL__) == PWM_CHANNEL_1) ||\
((__CHANNEL__) == PWM_CHANNEL_2))
#define IS_PWM_OUTLINE(__OUTLINE__) ((((__OUTLINE__) & PWM_OLINE_Msk) != 0U) &&\
(((__OUTLINE__) & ~PWM_OLINE_Msk) == 0U))
#define IS_PWM_OUTSEL(__OUTSEL__) (((__OUTSEL__) == PWM0_OUT0) ||\
((__OUTSEL__) == PWM0_OUT1) ||\
((__OUTSEL__) == PWM0_OUT2) ||\
((__OUTSEL__) == PWM1_OUT0) ||\
((__OUTSEL__) == PWM1_OUT1) ||\
((__OUTSEL__) == PWM1_OUT2) ||\
((__OUTSEL__) == PWM2_OUT0) ||\
((__OUTSEL__) == PWM2_OUT1) ||\
((__OUTSEL__) == PWM2_OUT2) ||\
((__OUTSEL__) == PWM3_OUT0) ||\
((__OUTSEL__) == PWM3_OUT1) ||\
((__OUTSEL__) == PWM3_OUT2))
#define IS_PWM_OUTLVL(__OUTLVL__) (((__OUTLVL__) == PWM_LEVEL_HIGH) ||\
((__OUTLVL__) == PWM_LEVEL_LOW))
/* Exported Functions ------------------------------------------------------- */
/* PWM Exported Functions Group1:
Initialization ----------------------------*/
void PWM_BaseInit(PWM_TypeDef *PWMx, PWM_BaseInitType *InitStruct);
void PWM_BaseStructInit(PWM_BaseInitType *InitStruct);
void PWM_OC0Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType);
void PWM_OC1Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType);
void PWM_OC2Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType);
void PWM_OCStructInit(PWM_OCInitType *OCInitType);
/* PWM Exported Functions Group2:
Interrupt ---------------------------------*/
void PWM_BaseINTConfig(PWM_TypeDef *PWMx, uint32_t NewState);
uint8_t PWM_GetBaseINTStatus(PWM_TypeDef *PWMx);
void PWM_ClearBaseINTStatus(PWM_TypeDef *PWMx);
void PWM_ChannelINTConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState);
uint8_t PWM_GetChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel);
void PWM_ClearChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel);
/* PWM Exported Functions Group3:
MISC --------------------------------------*/
void PWM_ClearCounter(PWM_TypeDef *PWMx);
void PWM_CCRConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint16_t Period);
//Compare output
void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine);
void PWM_OutputCmd(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState);
void PWM_SetOutLevel(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t Level);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_PWM_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_rtc.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief RTC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_RTC_H
#define __LIB_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
/* RTC Time struct */
typedef struct
{
uint32_t Year;
uint32_t Month;
uint32_t Date;
uint32_t WeekDay;
uint32_t Hours;
uint32_t Minutes;
uint32_t Seconds;
} RTC_TimeTypeDef;
//INT
#define RTC_INT_CEILLE RTC_INTEN_INTEN8
#define RTC_INT_ACDONE RTC_INTEN_INTEN7
#define RTC_INT_WKUCNT RTC_INTEN_INTEN6
#define RTC_INT_MIDNIGHT RTC_INTEN_INTEN5
#define RTC_INT_WKUHOUR RTC_INTEN_INTEN4
#define RTC_INT_WKUMIN RTC_INTEN_INTEN3
#define RTC_INT_WKUSEC RTC_INTEN_INTEN2
#define RTC_INT_TIMEILLE RTC_INTEN_INTEN1
#define RTC_INT_Msk (0x1FEUL)
//INTSTS
#define RTC_INTSTS_CEILLE RTC_INTSTS_INTSTS8
#define RTC_INTSTS_ACDONE RTC_INTSTS_INTSTS7
#define RTC_INTSTS_WKUCNT RTC_INTSTS_INTSTS6
#define RTC_INTSTS_MIDNIGHT RTC_INTSTS_INTSTS5
#define RTC_INTSTS_WKUHOUR RTC_INTSTS_INTSTS4
#define RTC_INTSTS_WKUMIN RTC_INTSTS_INTSTS3
#define RTC_INTSTS_WKUSEC RTC_INTSTS_INTSTS2
#define RTC_INTSTS_TIMEILLE RTC_INTSTS_INTSTS1
#define RTC_INTSTS_Msk (0x1FEUL)
/* RTC AutoCal struct */
typedef struct
{
uint32_t Period;
uint32_t ATDelay;
uint32_t ATClockSource;
uint32_t ADCSource;
} RTC_AutCalType;
//ATDelay
#define RTC_ATDELAY_15MS RTC_ACCTRL_ACDEL_0
#define RTC_ATDELAY_31MS RTC_ACCTRL_ACDEL_1
#define RTC_ATDELAY_62MS RTC_ACCTRL_ACDEL_2
#define RTC_ATDELAY_125MS RTC_ACCTRL_ACDEL_3
//ATClockSource
#define RTC_ATCS_DISABLE RTC_ACCTRL_ACCLK_0
#define RTC_ATCS_SEC RTC_ACCTRL_ACCLK_1
#define RTC_ATCS_MIN RTC_ACCTRL_ACCLK_2
#define RTC_ATCS_HOUR RTC_ACCTRL_ACCLK_3
//ADCSource
#define RTC_ADCS_DATA (0)
#define RTC_ADCS_PORT RTC_ACCTRL_ADCSEL
//CNTCLK
#define RTC_WKUCNT_RTCCLK RTC_WKUCNT_CNTSEL_0
#define RTC_WKUCNT_2048 RTC_WKUCNT_CNTSEL_1
#define RTC_WKUCNT_512 RTC_WKUCNT_CNTSEL_2
#define RTC_WKUCNT_128 RTC_WKUCNT_CNTSEL_3
//Prescaler
#define RTC_CLKDIV_1 RTC_PSCA_PSCA_0
#define RTC_CLKDIV_4 RTC_PSCA_PSCA_1
/* Private macros ------------------------------------------------------------*/
#define IS_RTC_REGOP_STARTADDR(__STARTADDR__) (((__STARTADDR__) & 0x3U) == 0U)
/* Year 0 ~ 99 */
#define IS_RTC_TIME_YEAR(__YEAR__) ((__YEAR__) < 0x9AU)
/* Month 1 ~ 12 */
#define IS_RTC_TIME_MONTH(__MONTH__) (((__MONTH__) > 0x0U) && ((__MONTH__) < 0x13U))
/* Date 1 ~ 31 */
#define IS_RTC_TIME_DATE(__DATE__) (((__DATE__) > 0x0U) && ((__DATE__) < 0x32))
/* Weekday 0 ~ 6 */
#define IS_RTC_TIME_WEEKDAY(__WEEKDAY__) ((__WEEKDAY__) < 0x7U)
/* Hours 0 ~ 23 */
#define IS_RTC_TIME_HOURS(__HOURS__) ((__HOURS__) < 0x24)
/* Minutes 0 ~ 59 */
#define IS_RTC_TIME_MINS(__MINS__) ((__MINS__) < 0x5A)
/* Seconds 0 ~ 59 */
#define IS_RTC_TIME_SECS(__SECS__) ((__SECS__) < 0x5A)
#define IS_RTC_INT(__INT__) ((((__INT__) & RTC_INT_Msk) != 0U) &&\
(((__INT__) & ~RTC_INT_Msk) == 0U))
#define IS_RTC_INTFLAGR(__INTFLAGR_) (((__INTFLAGR_) == RTC_INTSTS_CEILLE) ||\
((__INTFLAGR_) == RTC_INTSTS_ACDONE) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUCNT) ||\
((__INTFLAGR_) == RTC_INTSTS_MIDNIGHT) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUHOUR) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUMIN) ||\
((__INTFLAGR_) == RTC_INTSTS_WKUSEC) ||\
((__INTFLAGR_) == RTC_INTSTS_TIMEILLE))
#define IS_RTC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & RTC_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~RTC_INTSTS_Msk) == 0U))
#define IS_RTC_AUTOCAL_RELOAD(__RELOAD__) (((__RELOAD__) == RTC_AUTORELOAD_DISABLE) ||\
((__RELOAD__) == RTC_AUTORELOAD_ENABLE))
#define IS_RTC_AUTOCAL_ATDLY(__ATDLY__) (((__ATDLY__) == RTC_ATDELAY_15MS) ||\
((__ATDLY__) == RTC_ATDELAY_31MS) ||\
((__ATDLY__) == RTC_ATDELAY_62MS) ||\
((__ATDLY__) == RTC_ATDELAY_125MS))
#define IS_RTC_AUTOCAL_ATCS(__ATCS__) (((__ATCS__) == RTC_ATCS_DISABLE) ||\
((__ATCS__) == RTC_ATCS_SEC) ||\
((__ATCS__) == RTC_ATCS_MIN) ||\
((__ATCS__) == RTC_ATCS_HOUR))
#define IS_RTC_AUTOCAL_ADCSRC(__ADCSRC__) (((__ADCSRC__) == RTC_ADCS_DATA) ||\
((__ADCSRC__) == RTC_ADCS_PORT))
#define IS_RTC_AUTOCAL_PERIOD(__PERIOD__) ((__PERIOD__) < 64U)
#define IS_RTC_WKUSEC_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U))
#define IS_RTC_WKUMIN_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U))
#define IS_RTC_WKUHOUR_PERIOD(__PERIOD__) (((__PERIOD__) < 0x21U) && ((__PERIOD__) > 0U))
#define IS_RTC_WKUCNT_PERIOD(__PERIOD__) (((__PERIOD__) < 0x1000001U) && ((__PERIOD__) > 0U))
#define IS_RTC_WKUCNT_CNTSEL(__CNTSEL__) (((__CNTSEL__) == RTC_WKUCNT_RTCCLK) ||\
((__CNTSEL__) == RTC_WKUCNT_2048) ||\
((__CNTSEL__) == RTC_WKUCNT_512) ||\
((__CNTSEL__) == RTC_WKUCNT_128))
#define IS_RTC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == RTC_CLKDIV_1) ||\
((__CLKDIV__) == RTC_CLKDIV_4))
/* Exported Functions ------------------------------------------------------- */
/* RTC Exported Functions Group1:
Time functions -----------------------------*/
void RTC_SetTime(RTC_TimeTypeDef *sTime);
void RTC_GetTime(RTC_TimeTypeDef *gTime);
/* RTC Exported Functions Group2:
Registers operation functions --------------*/
void RTC_WriteProtection(uint32_t NewState);
void RTC_WaitForSynchro(void);
void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len);
void RTC_ReadRegisters(uint32_t StartAddr, uint32_t *rBuffer, uint8_t Len);
/* RTC Exported Functions Group3:
Interrupt functions ------------------------*/
void RTC_INTConfig(uint32_t INTMask, uint32_t NewState);
uint8_t RTC_GetINTStatus(uint32_t FlagMask);
void RTC_ClearINTStatus(uint32_t FlagMask);
/* RTC Exported Functions Group4:
AutoCal functions --------------------------*/
void RTC_AutoCalStructInit(RTC_AutCalType *RTCAC_InitStruct);
void RTC_AutoCalInit(RTC_AutCalType *InitStruct);
void RTC_TrigSourceConfig(uint32_t TrigSource, uint32_t Period);
uint32_t RTC_AutoCalCmd(uint32_t NewState);
void RTC_StartAutoCalManual(void);
void RTC_WaitForAutoCalManual(void);
uint8_t RTC_GetACBusyFlag(void);
/* RTC Exported Functions Group5:
Wake-up functions --------------------------*/
void RTC_WKUSecondsConfig(uint8_t nPeriod);
void RTC_WKUMinutesConfig(uint8_t nPeriod);
void RTC_WKUHoursConfig(uint8_t nPeriod);
void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK);
uint32_t RTC_GetWKUCounterValue(void);
/* RTC Exported Functions Group6:
MISC functions -----------------------------*/
void RTC_PrescalerConfig(uint32_t Prescaler);
void RTC_PLLDIVConfig(uint32_t nfrequency);
void RTC_PLLDIVOutputCmd(uint8_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_RTC_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_spi.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief SPI library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_SPI_H
#define __LIB_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Mode;
uint32_t SPH;
uint32_t SPO;
uint32_t ClockDivision;
uint32_t CSNSoft;
uint32_t SWAP;
} SPI_InitType;
//Mode
#define SPI_MODE_MASTER 0
#define SPI_MODE_SLAVE SPI_CTRL_MOD
//SPH
#define SPI_SPH_0 0
#define SPI_SPH_1 SPI_CTRL_SCKPHA
//SPO
#define SPI_SPO_0 0
#define SPI_SPO_1 SPI_CTRL_SCKPOL
//ClockDivision
#define SPI_CLKDIV_2 (0)
#define SPI_CLKDIV_4 (SPI_CTRL_SCKSEL_0)
#define SPI_CLKDIV_8 (SPI_CTRL_SCKSEL_1)
#define SPI_CLKDIV_16 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_1)
#define SPI_CLKDIV_32 (SPI_CTRL_SCKSEL_2)
#define SPI_CLKDIV_64 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_2)
#define SPI_CLKDIV_128 (SPI_CTRL_SCKSEL_1 | SPI_CTRL_SCKSEL_2)
//CSNSoft
#define SPI_CSNSOFT_ENABLE SPI_CTRL_CSGPIO
#define SPI_CSNSOFT_DISABLE 0
//SWAP
#define SPI_SWAP_ENABLE SPI_CTRL_SWAP
#define SPI_SWAP_DISABLE 0
//INT
#define SPI_INT_TX (0x80000000|SPI_TXSTS_TXIEN)
#define SPI_INT_RX (0x40000000|SPI_RXSTS_RXIEN)
//status
#define SPI_STS_TXIF (0x80000000|SPI_TXSTS_TXIF)
#define SPI_STS_TXEMPTY (0x80000000|SPI_TXSTS_TXEMPTY)
#define SPI_STS_TXFUR (0x80000000|SPI_TXSTS_TXFUR)
#define SPI_STS_RXIF (0x40000000|SPI_RXSTS_RXIF)
#define SPI_STS_RXFULL (0x40000000|SPI_RXSTS_RXFULL)
#define SPI_STS_RXFOV (0x40000000|SPI_RXSTS_RXFOV)
#define SPI_STS_BSY (0x20000000|SPI_MISC_BSY)
#define SPI_STS_RFF (0x20000000|SPI_MISC_RFF)
#define SPI_STS_RNE (0x20000000|SPI_MISC_RNE)
#define SPI_STS_TNF (0x20000000|SPI_MISC_TNF)
#define SPI_STS_TFE (0x20000000|SPI_MISC_TFE)
//TXFLEV
#define SPI_TXFLEV_0 (0)
#define SPI_TXFLEV_1 (SPI_TXSTS_TXFLEV_0)
#define SPI_TXFLEV_2 (SPI_TXSTS_TXFLEV_1)
#define SPI_TXFLEV_3 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1)
#define SPI_TXFLEV_4 (SPI_TXSTS_TXFLEV_2)
#define SPI_TXFLEV_5 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_2)
#define SPI_TXFLEV_6 (SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2)
#define SPI_TXFLEV_7 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2)
//RXFLEV
#define SPI_RXFLEV_0 (0)
#define SPI_RXFLEV_1 (SPI_RXSTS_RXFLEV_0)
#define SPI_RXFLEV_2 (SPI_RXSTS_RXFLEV_1)
#define SPI_RXFLEV_3 (SPI_RXSTS_RXFLEV_0 | SPI_RXSTS_RXFLEV_1)
#define SPI_RXFLEV_4 (SPI_RXSTS_RXFLEV_2)
#define SPI_RXFLEV_5 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_0)
#define SPI_RXFLEV_6 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1)
#define SPI_RXFLEV_7 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1 | SPI_RXSTS_RXFLEV_0)
/* Private macros ------------------------------------------------------------*/
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_MASTER) || ((__MODE__) == SPI_MODE_SLAVE))
#define IS_SPI_SPH(__SPH__) (((__SPH__) == SPI_SPH_0) || ((__SPH__) == SPI_SPH_1))
#define IS_SPI_SPO(__SPO__) (((__SPO__) == SPI_SPO_0) || ((__SPO__) == SPI_SPO_1))
#define IS_SPI_CLKDIV(__CLKDIV__) (((__CLKDIV__) == SPI_CLKDIV_2) ||\
((__CLKDIV__) == SPI_CLKDIV_4) ||\
((__CLKDIV__) == SPI_CLKDIV_8) ||\
((__CLKDIV__) == SPI_CLKDIV_16) ||\
((__CLKDIV__) == SPI_CLKDIV_32) ||\
((__CLKDIV__) == SPI_CLKDIV_64) ||\
((__CLKDIV__) == SPI_CLKDIV_128))
#define IS_SPI_CSN(__CSN__) (((__CSN__) == SPI_CSNSOFT_ENABLE) || ((__CSN__) == SPI_CSNSOFT_DISABLE))
#define IS_SPI_SWAP(__SWAP__) (((__SWAP__) == SPI_SWAP_ENABLE) || ((__SWAP__) == SPI_SWAP_DISABLE))
#define IS_SPI_INT(__INT__) ((((__INT__) & (SPI_INT_TX | SPI_INT_RX)) != 0U) &&\
(((__INT__) & ~(SPI_INT_TX | SPI_INT_RX)) == 0U))
#define IS_SPI_STSR(__STSR__) (((__STSR__) == SPI_STS_TXIF) ||\
((__STSR__) == SPI_STS_TXEMPTY) ||\
((__STSR__) == SPI_STS_TXFUR) ||\
((__STSR__) == SPI_STS_RXFULL) ||\
((__STSR__) == SPI_STS_RXFOV) ||\
((__STSR__) == SPI_STS_BSY) ||\
((__STSR__) == SPI_STS_RFF) ||\
((__STSR__) == SPI_STS_RNE) ||\
((__STSR__) == SPI_STS_TNF) ||\
((__STSR__) == SPI_STS_TFE) ||\
((__STSR__) == SPI_STS_RXIF))
#define IS_SPI_STSC(__STSC__) ((((__STSC__) & (SPI_STS_TXIF | SPI_STS_RXIF)) != 0U) &&\
(((__STSC__) & ~(SPI_STS_TXIF | SPI_STS_RXIF)) == 0U))
#define IS_SPI_TXFLEV(__TXFLEV__) (((__TXFLEV__) == SPI_TXFLEV_0) ||\
((__TXFLEV__) == SPI_TXFLEV_1) ||\
((__TXFLEV__) == SPI_TXFLEV_2) ||\
((__TXFLEV__) == SPI_TXFLEV_3) ||\
((__TXFLEV__) == SPI_TXFLEV_4) ||\
((__TXFLEV__) == SPI_TXFLEV_5) ||\
((__TXFLEV__) == SPI_TXFLEV_6) ||\
((__TXFLEV__) == SPI_TXFLEV_7))
#define IS_SPI_RXFLEV(__RXFLEV__) (((__RXFLEV__) == SPI_RXFLEV_0) ||\
((__RXFLEV__) == SPI_RXFLEV_1) ||\
((__RXFLEV__) == SPI_RXFLEV_2) ||\
((__RXFLEV__) == SPI_RXFLEV_3) ||\
((__RXFLEV__) == SPI_RXFLEV_4) ||\
((__RXFLEV__) == SPI_RXFLEV_5) ||\
((__RXFLEV__) == SPI_RXFLEV_6) ||\
((__RXFLEV__) == SPI_RXFLEV_7))
/* Exported Functions ------------------------------------------------------- */
/* SPI Exported Functions Group1:
(De)Initialization -------------------------*/
void SPI_DeviceInit(SPI_TypeDef *SPIx);
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitType *InitStruct);
void SPI_StructInit(SPI_InitType *InitStruct);
/* SPI Exported Functions Group2:
Interrupt (flag) ---------------------------*/
void SPI_INTConfig(SPI_TypeDef *SPIx, uint32_t INTMask, uint32_t NewState);
uint8_t SPI_GetStatus(SPI_TypeDef *SPIx, uint32_t Status);
void SPI_ClearStatus(SPI_TypeDef *SPIx, uint32_t Status);
/* SPI Exported Functions Group3:
Transfer datas -----------------------------*/
void SPI_SendData(SPI_TypeDef *SPIx, uint8_t ch);
uint8_t SPI_ReceiveData(SPI_TypeDef *SPIx);
/* SPI Exported Functions Group4:
MISC Configuration -------------------------*/
void SPI_Cmd(SPI_TypeDef *SPIx, uint32_t NewState);
void SPI_TransmitFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel);
void SPI_ReceiveFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel);
uint8_t SPI_GetTransmitFIFOLevel(SPI_TypeDef *SPIx);
uint8_t SPI_GetReceiveFIFOLevel(SPI_TypeDef *SPIx);
void SPI_SmartModeCmd(SPI_TypeDef *SPIx, uint32_t NewState);
void SPI_OverWriteModeCmd(SPI_TypeDef *SPIx, uint32_t NewState);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_SPI_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_tmr.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Timer library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_TMR_H
#define __LIB_TMR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Period;
uint32_t ClockSource;
uint32_t EXTGT;
} TMR_InitType;
//ClockSource
#define TMR_CLKSRC_INTERNAL 0
#define TMR_CLKSRC_EXTERNAL TMR_CTRL_EXTCLK
//ClockGate
#define TMR_EXTGT_DISABLE 0
#define TMR_EXTGT_ENABLE TMR_CTRL_EXTEN
/* Private macros ------------------------------------------------------------*/
#define IS_TMR_CLKSRC(__CLKSRC__) (((__CLKSRC__) == TMR_CLKSRC_INTERNAL) || ((__CLKSRC__) == TMR_CLKSRC_EXTERNAL))
#define IS_TMR_EXTGT(__EXTGT__) (((__EXTGT__) == TMR_EXTGT_DISABLE) || ((__EXTGT__) == TMR_EXTGT_ENABLE))
/* Exported Functions ------------------------------------------------------- */
/* Timer Exported Functions Group1:
(De)Initialization ----------------------*/
void TMR_DeInit(TMR_TypeDef *TMRx);
void TMR_Init(TMR_TypeDef *TMRx, TMR_InitType *InitStruct);
void TMR_StructInit(TMR_InitType *InitStruct);
/* Timer Exported Functions Group2:
Interrupt (flag) -------------------------*/
void TMR_INTConfig(TMR_TypeDef *TMRx, uint32_t NewState);
uint8_t TMR_GetINTStatus(TMR_TypeDef *TMRx);
void TMR_ClearINTStatus(TMR_TypeDef *TMRx);
/* Timer Exported Functions Group3:
MISC Configuration -----------------------*/
void TMR_Cmd(TMR_TypeDef *TMRx, uint32_t NewState);
uint32_t TMR_GetCurrentValue(TMR_TypeDef *TMRx);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_TMR_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_u32k.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief UART 32K library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_U32K_H
#define __LIB_U32K_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
typedef struct
{
uint32_t Debsel;
uint32_t Parity;
uint32_t WordLen;
uint32_t FirstBit;
uint32_t AutoCal;
uint32_t Baudrate;
uint32_t LineSel;
} U32K_InitType;
//Debsel
#define U32K_DEBSEL_0 U32K_CTRL0_DEBSEL_0
#define U32K_DEBSEL_1 U32K_CTRL0_DEBSEL_1
#define U32K_DEBSEL_2 U32K_CTRL0_DEBSEL_2
#define U32K_DEBSEL_3 U32K_CTRL0_DEBSEL_3
//Parity
#define U32K_PARITY_EVEN U32K_CTRL0_PMODE_EVEN
#define U32K_PARITY_ODD U32K_CTRL0_PMODE_ODD
#define U32K_PARITY_0 U32K_CTRL0_PMODE_0
#define U32K_PARITY_1 U32K_CTRL0_PMODE_1
#define U32K_PARITY_NONE 0
//WordLen
#define U32K_WORDLEN_8B 0
#define U32K_WORDLEN_9B U32K_CTRL0_MODE
//FirstBit
#define U32K_FIRSTBIT_LSB 0
#define U32K_FIRSTBIT_MSB U32K_CTRL0_MSB
//AutoCal
#define U32K_AUTOCAL_ON 0
#define U32K_AUTOCAL_OFF U32K_CTRL0_ACOFF
//Line
#define U32K_LINE_RX0 U32K_CTRL1_RXSEL_RX0
#define U32K_LINE_RX1 U32K_CTRL1_RXSEL_RX1
#define U32K_LINE_RX2 U32K_CTRL1_RXSEL_RX2
#define U32K_LINE_RX3 U32K_CTRL1_RXSEL_RX3
//INT
#define U32K_INT_RXOV U32K_CTRL1_RXOVIE
#define U32K_INT_RXPE U32K_CTRL1_RXPEIE
#define U32K_INT_RX U32K_CTRL1_RXIE
#define U32K_INT_Msk (U32K_INT_RXOV \
|U32K_INT_RXPE \
|U32K_INT_RX)
//INT Status
#define U32K_INTSTS_RXOV U32K_STS_RXOV
#define U32K_INTSTS_RXPE U32K_STS_RXPE
#define U32K_INTSTS_RX U32K_STS_RXIF
#define U32K_INTSTS_Msk (U32K_INTSTS_RXOV \
|U32K_INTSTS_RXPE \
|U32K_INTSTS_RX)
//WKUMode
#define U32K_WKUMOD_RX 0 // Wake-up when receive data
#define U32K_WKUMOD_PC U32K_CTRL0_WKUMODE // Wake-up when receive data and parity/stop bit correct
/* Private macros ------------------------------------------------------------*/
#define IS_U32K_DEBSEL(__DEBSEL__) (((__DEBSEL__) == U32K_DEBSEL_0) ||\
((__DEBSEL__) == U32K_DEBSEL_1) ||\
((__DEBSEL__) == U32K_DEBSEL_2) ||\
((__DEBSEL__) == U32K_DEBSEL_3))
#define IS_U32K_PARITY(__PARITY__) (((__PARITY__) == U32K_PARITY_EVEN) ||\
((__PARITY__) == U32K_PARITY_ODD) ||\
((__PARITY__) == U32K_PARITY_0) ||\
((__PARITY__) == U32K_PARITY_1) ||\
((__PARITY__) == U32K_PARITY_NONE))
#define IS_U32K_WORDLEN(__WORDLEN__) (((__WORDLEN__) == U32K_WORDLEN_8B) || ((__WORDLEN__) == U32K_WORDLEN_9B))
#define IS_U32K_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == U32K_FIRSTBIT_LSB) || ((__FIRSTBIT__) == U32K_FIRSTBIT_MSB))
#define IS_U32K_AUTOCAL(__AUTOCAL__) (((__AUTOCAL__) == U32K_AUTOCAL_ON) || ((__AUTOCAL__) == U32K_AUTOCAL_OFF))
#define IS_U32K_LINE(__LINE__) (((__LINE__) == U32K_LINE_RX0) ||\
((__LINE__) == U32K_LINE_RX1) ||\
((__LINE__) == U32K_LINE_RX2) ||\
((__LINE__) == U32K_LINE_RX3))
#define IS_U32K_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9601UL)
#define IS_U32K_INT(__INT__) ((((__INT__) & U32K_INT_Msk) != 0U) &&\
(((__INT__) & ~U32K_INT_Msk) == 0U))
#define IS_U32K_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == U32K_INTSTS_RXOV) ||\
((__INTFLAGR__) == U32K_INTSTS_RXPE) ||\
((__INTFLAGR__) == U32K_INTSTS_RX))
#define IS_U32K_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & U32K_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~U32K_INTSTS_Msk) == 0U))
#define IS_U32K_WKUMODE(__WKUMODE__) (((__WKUMODE__) == U32K_WKUMOD_RX) || ((__WKUMODE__) == U32K_WKUMOD_PC))
/* Exported Functions ------------------------------------------------------- */
/* U32K Exported Functions Group1:
(De)Initialization -----------------------*/
void U32K_DeInit(U32K_TypeDef *U32Kx);
void U32K_Init(U32K_TypeDef *U32Kx, U32K_InitType *InitStruct);
void U32K_StructInit(U32K_InitType *InitStruct);
/* U32K Exported Functions Group2:
Interrupt (flag) configure ---------------*/
void U32K_INTConfig(U32K_TypeDef *U32Kx, uint32_t INTMask, uint8_t NewState);
uint8_t U32K_GetINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask);
void U32K_ClearINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask);
/* U32K Exported Functions Group3:
Receive datas -----------------------------*/
uint8_t U32K_ReceiveData(U32K_TypeDef *U32Kx);
/* U32K Exported Functions Group4:
MISC Configuration -------- ---------------*/
void U32K_BaudrateConfig(U32K_TypeDef *U32Kx, uint32_t BaudRate);
void U32K_Cmd(U32K_TypeDef *U32Kx, uint32_t NewState);
void U32K_LineConfig(U32K_TypeDef *U32Kx, uint32_t Line);
void U32K_WKUModeConfig(U32K_TypeDef *U32Kx, uint32_t WKUMode);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_U32K_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_uart.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief UART library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_UART_H
#define __LIB_UART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
//UART Init struct
typedef struct
{
uint32_t Mode;
uint32_t Parity;
uint32_t WordLen;
uint32_t FirstBit;
uint32_t Baudrate;
} UART_InitType;
//Mode
#define UART_MODE_RX UART_CTRL_RXEN
#define UART_MODE_TX UART_CTRL_TXEN
#define UART_MODE_OFF 0
#define UART_MODE_Msk (UART_CTRL_RXEN | UART_CTRL_TXEN)
//Parity
#define UART_PARITY_EVEN UART_CTRL2_PMODE_EVEN
#define UART_PARITY_ODD UART_CTRL2_PMODE_ODD
#define UART_PARITY_0 UART_CTRL2_PMODE_0
#define UART_PARITY_1 UART_CTRL2_PMODE_1
#define UART_PARITY_NONE 0
//WordLen
#define UART_WORDLEN_8B 0
#define UART_WORDLEN_9B UART_CTRL2_MODE
//FirstBit
#define UART_FIRSTBIT_LSB 0
#define UART_FIRSTBIT_MSB UART_CTRL2_MSB
//UART Configration Information struct
typedef struct
{
uint32_t Mode_Transmit :1; //1: TX Enable; 0: TX Disable
uint32_t Mode_Receive :1; //1: RX Enable; 0: RX Disable
uint32_t Baudrate; //The value of current budrate
uint8_t Parity; //0: parity bit=0; 1: parity bit=1; 2: Even parity; 3:Odd parity
uint8_t WordLen; //8: data bits=8; 9: data bits=9
uint8_t FirstBit; //0: LSB transmit first; 1: MSB transmit first
} UART_ConfigINFOType;
//status
#define UART_FLAG_RXPARITY UART_STATE_RXPSTS
#define UART_FLAG_TXDONE UART_STATE_TXDONE
#define UART_FLAG_RXPE UART_STATE_RXPE
#define UART_FLAG_RXOV UART_STATE_RXOV
#define UART_FLAG_TXOV UART_STATE_TXOV
#define UART_FLAG_RXFULL UART_STATE_RXFULL
#define UART_FLAG_RCMsk (UART_FLAG_TXDONE \
|UART_FLAG_RXPE \
|UART_FLAG_RXOV \
|UART_STATE_RXFULL\
|UART_FLAG_TXOV)
//interrupt
#define UART_INT_TXDONE UART_CTRL_TXDONEIE
#define UART_INT_RXPE UART_CTRL_RXPEIE
#define UART_INT_RXOV UART_CTRL_RXOVIE
#define UART_INT_TXOV UART_CTRL_TXOVIE
#define UART_INT_RX UART_CTRL_RXIE
#define UART_INT_Msk (UART_INT_TXDONE \
|UART_INT_RXPE \
|UART_INT_RXOV \
|UART_INT_TXOV \
|UART_INT_RX)
//INTStatus
#define UART_INTSTS_TXDONE UART_INTSTS_TXDONEIF
#define UART_INTSTS_RXPE UART_INTSTS_RXPEIF
#define UART_INTSTS_RXOV UART_INTSTS_RXOVIF
#define UART_INTSTS_TXOV UART_INTSTS_TXOVIF
#define UART_INTSTS_RX UART_INTSTS_RXIF
#define UART_INTSTS_Msk (UART_INTSTS_TXDONE \
|UART_INTSTS_RXPE \
|UART_INTSTS_RXOV \
|UART_INTSTS_TXOV \
|UART_INTSTS_RX)
/* Private macros ------------------------------------------------------------*/
#define IS_UART_MODE(__MODE__) (((((__MODE__) & UART_MODE_Msk) != 0U) && (((__MODE__) & ~UART_MODE_Msk) == 0U)) ||\
((__MODE__) == UART_MODE_OFF))
#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_EVEN) ||\
((__PARITY__) == UART_PARITY_ODD) ||\
((__PARITY__) == UART_PARITY_0) ||\
((__PARITY__) == UART_PARITY_1) ||\
((__PARITY__) == UART_PARITY_NONE))
#define IS_UART_WORDLEN(__WORDLEN__) (((__WORDLEN__) == UART_WORDLEN_8B) ||\
((__WORDLEN__) == UART_WORDLEN_9B))
#define IS_UART_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == UART_FIRSTBIT_LSB) ||\
((__FIRSTBIT__) == UART_FIRSTBIT_MSB))
#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 0x100000UL)
#define IS_UART_FLAGR(__FLAGR__) (((__FLAGR__) == UART_FLAG_RXPARITY) ||\
((__FLAGR__) == UART_FLAG_TXDONE) ||\
((__FLAGR__) == UART_FLAG_RXPE) ||\
((__FLAGR__) == UART_FLAG_RXOV) ||\
((__FLAGR__) == UART_FLAG_TXOV) ||\
((__FLAGR__) == UART_FLAG_RXFULL))
#define IS_UART_FLAGC(__FLAGC__) ((((__FLAGC__) & UART_FLAG_RCMsk) != 0U) &&\
(((__FLAGC__) & ~UART_FLAG_RCMsk) == 0U))
#define IS_UART_INT(__INT__) ((((__INT__) & UART_INT_Msk) != 0U) &&\
(((__INT__) & ~UART_INT_Msk) == 0U))
#define IS_UART_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == UART_INTSTS_TXDONE) ||\
((__INTFLAGR__) == UART_INTSTS_RXPE) ||\
((__INTFLAGR__) == UART_INTSTS_RXOV) ||\
((__INTFLAGR__) == UART_INTSTS_TXOV) ||\
((__INTFLAGR__) == UART_INTSTS_RX))
#define IS_UART_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & UART_INTSTS_Msk) != 0U) &&\
(((__INTFLAGC__) & ~UART_INTSTS_Msk) == 0U))
/* Exported Functions ------------------------------------------------------- */
/* UART Exported Functions Group1:
Initialization and functions --------------*/
void UART_DeInit(UART_TypeDef *UARTx);
void UART_Init(UART_TypeDef *UARTx, UART_InitType *InitStruct);
void UART_StructInit(UART_InitType *InitStruct);
/* UART Exported Functions Group2:
(Interrupt) Flag --------------------------*/
uint8_t UART_GetFlag(UART_TypeDef *UARTx, uint32_t FlagMask);
void UART_ClearFlag(UART_TypeDef *UARTx, uint32_t FlagMask);
void UART_INTConfig(UART_TypeDef *UARTx, uint32_t INTMask, uint8_t NewState);
uint8_t UART_GetINTStatus(UART_TypeDef *UARTx, uint32_t INTMask);
void UART_ClearINTStatus(UART_TypeDef *UARTx, uint32_t INTMask);
/* UART Exported Functions Group3:
Transfer datas ----------------------------*/
void UART_SendData(UART_TypeDef *UARTx, uint8_t ch);
uint8_t UART_ReceiveData(UART_TypeDef *UARTx);
/* UART Exported Functions Group4:
MISC Configuration ------------------------*/
void UART_BaudrateConfig(UART_TypeDef *UARTx, uint32_t BaudRate);
void UART_Cmd(UART_TypeDef *UARTx, uint32_t Mode, uint32_t NewState);
void UART_GetConfigINFO(UART_TypeDef *UARTx, UART_ConfigINFOType *ConfigInfo);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_UART_H */
/*********************************** END OF FILE ******************************/

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/**
*******************************************************************************
* @file lib_version.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief Version library.
*******************************************************************************/
#ifndef __LIB_VERSION_H
#define __LIB_VERSION_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
#define DRIVER_VERSION(major,minor) (((major) << 8) | (minor))
/* Exported Functions ------------------------------------------------------- */
/**
* @brief Read receive data register.
* @param None
* @retval Version value
*/
uint16_t Target_GetDriveVersion(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_VERSION_H */
/*********************************** END OF FILE ******************************/

46
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/**
******************************************************************************
* @file lib_wdt.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief WDT library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_WDT_H
#define __LIB_WDT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
#define WDT_2_SECS PMU_WDTEN_WDTSEL_0
#define WDT_1_SECS PMU_WDTEN_WDTSEL_1
#define WDT_0_5_SECS PMU_WDTEN_WDTSEL_2
#define WDT_0_25_SECS PMU_WDTEN_WDTSEL_3
/* Private macros ------------------------------------------------------------*/
#define IS_WDT_PERIOD(__PERIOD__) (((__PERIOD__) == WDT_2_SECS) ||\
((__PERIOD__) == WDT_1_SECS) ||\
((__PERIOD__) == WDT_0_5_SECS) ||\
((__PERIOD__) == WDT_0_25_SECS))
/* Exported Functions ------------------------------------------------------- */
void WDT_Enable(void);
void WDT_Disable(void);
void WDT_Clear(void);
void WDT_SetPeriod(uint32_t period);
uint16_t WDT_GetCounterValue(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_WDT_H */
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_adc.c
* @author Application Team
* @version V4.6.0
* @date 2019-06-18
* @brief ADC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_adc.h"
extern __IO uint32_t ana_reg3_tmp;
#define ANA_REG1_RSTValue (0U)
#define ANA_ADCCTRL_RSTValue (0U)
/**
* @brief Initializes ADC peripheral registers to their default reset values.
* @note 1. Disable ADC
2. Disable ADC overall bias current trim
3. Disable resistor/cap division.
4. Disable ADC auto/manual done interrupt
5. ANA_ADCCTRL(register) write default value.
* @param None
* @retval None
*/
void ADC_DeInit(void)
{
/* Power down ADC */
ana_reg3_tmp &= ~ANA_REG3_ADCPDN;
ANA->REG3 = ana_reg3_tmp;
/* Disable resistor/cap division. */
ANA->REG1 = ANA_REG1_RSTValue;
/* Disable interrupt, Clear interrupt flag */
ANA->INTEN &= ~(ANA_INTEN_INTEN0 | ANA_INTEN_INTEN1);
ANA->INTSTS = (ANA_INTSTS_INTSTS0 | ANA_INTSTS_INTSTS1);
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
ANA->ADCCTRL = ANA_ADCCTRL_RSTValue;
}
/**
* @brief Fills each ADC_InitStruct member with its default value.
* @param ADC_InitStruct: pointer to an ADCInitType structure which will be initialized.
* @retval None
*/
void ADC_StructInit(ADCInitType* ADC_InitStruct)
{
/*--------------- Reset ADC init structure parameters values ---------------*/
/* Initialize the ClockSource member */
ADC_InitStruct->ClockSource = ADC_CLKSRC_RCH;
/* Initialize the Channel member */
ADC_InitStruct->Channel = ADC_CHANNEL0;
/* Initialize the ClockDivider member */
ADC_InitStruct->ClockDivider = ADC_CLKDIV_1;
/* Initialize the ConvMode member */
ADC_InitStruct->ConvMode = ADC_CONVMODE_SINGLECHANNEL;
/* Initialize the TrigMode member */
ADC_InitStruct->TrigMode = ADC_TRIGMODE_MANUAL;
}
/**
* @brief ADC initialization.
* @param ADC_InitStruct:
TrigMode:
ADC_TRIGMODE_AUTO
ADC_TRIGMODE_MANUAL
ConvMode:
ADC_CONVMODE_SINGLECHANNEL
ADC_CONVMODE_MULTICHANNEL
ClockSource:
ADC_CLKSRC_RCH
ADC_CLKSRC_PLLL
ClockDivider:
ADC_CLKDIV_1
ADC_CLKDIV_2
ADC_CLKDIV_3
ADC_CLKDIV_4
ADC_CLKDIV_5
ADC_CLKDIV_6
ADC_CLKDIV_7
ADC_CLKDIV_8
ADC_CLKDIV_9
ADC_CLKDIV_10
ADC_CLKDIV_11
ADC_CLKDIV_12
ADC_CLKDIV_13
ADC_CLKDIV_14
ADC_CLKDIV_15
ADC_CLKDIV_16
Channel:(be valid when ConvMode is ADC_CONVMODE_SINGLECHANNEL)
ADC_CHANNEL0
ADC_CHANNEL1
ADC_CHANNEL2
ADC_CHANNEL3
ADC_CHANNEL4
ADC_CHANNEL5
ADC_CHANNEL6
ADC_CHANNEL7
ADC_CHANNEL8
ADC_CHANNEL9
ADC_CHANNEL10
ADC_CHANNEL11
* @retval None
*/
void ADC_Init(ADCInitType* ADC_InitStruct)
{
uint32_t tmp = 0;
/* Check parameters */
assert_parameters(IS_ADC_TRIGMODE(ADC_InitStruct->TrigMode));
assert_parameters(IS_ADC_CONVMODE(ADC_InitStruct->ConvMode));
assert_parameters(IS_ADC_CLKDIV(ADC_InitStruct->ClockDivider));
assert_parameters(IS_ADC_CLKSRC(ADC_InitStruct->ClockSource));
tmp = ANA->ADCCTRL;
tmp &= ~(ANA_ADCCTRL_AMODE \
|ANA_ADCCTRL_MMODE \
|ANA_ADCCTRL_CLKSEL \
|ANA_ADCCTRL_CLKDIV \
|ANA_ADCCTRL_AEN \
|ANA_ADCCTRL_MCH \
|ANA_ADCCTRL_ACH);
tmp |= (ADC_InitStruct->ClockDivider | ADC_InitStruct->ClockSource);
if(ADC_InitStruct->TrigMode == ADC_TRIGMODE_AUTO) //Auto mode
{
if(ADC_InitStruct->ConvMode == ADC_CONVMODE_SINGLECHANNEL) //signal channel
{
assert_parameters(IS_ADC_CHANNEL(ADC_InitStruct->Channel));
tmp &= (~ANA_ADCCTRL_ACH);
tmp |= (ADC_InitStruct->Channel << ANA_ADCCTRL_ACH_Pos);
}
else //multi channels
{
tmp |= ANA_ADCCTRL_AMODE;
}
}
else // Manual mode
{
if(ADC_InitStruct->ConvMode == ADC_CONVMODE_SINGLECHANNEL) //signal channel
{
assert_parameters(IS_ADC_CHANNEL(ADC_InitStruct->Channel));
tmp &= (~ANA_ADCCTRL_MCH);
tmp |= (ADC_InitStruct->Channel << ANA_ADCCTRL_MCH_Pos);
}
else //multi channels
{
tmp |= ANA_ADCCTRL_MMODE;
}
}
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
ANA->ADCCTRL = tmp;
}
/**
* @brief Calculate ADC voltage value(uint:V) via ADC original data.
* @param [in]Mode:
* ADC_3V_EXTERNAL_NODIV
* ADC_3V_EXTERNAL_RESDIV
* ADC_3V_EXTERNAL_CAPDIV
* ADC_3V_VDD_RESDIV
* ADC_3V_VDD_CAPDIV
* ADC_3V_BATRTC_RESDIV
* ADC_3V_BATRTC_CAPDIV
* ADC_5V_EXTERNAL_NODIV
* ADC_5V_EXTERNAL_RESDIV
* ADC_5V_EXTERNAL_CAPDIV
* ADC_5V_VDD_RESDIV
* ADC_5V_VDD_CAPDIV
* ADC_5V_BATRTC_RESDIV
* ADC_5V_BATRTC_CAPDIV
* @param [in]adc_data: The ADC original data
* @param [out]Voltage: The pointer of voltage value calculated by this function
* @retval 1 NVR checksum error.
0 Function successed.
*/
uint32_t ADC_CalculateVoltage(uint32_t Mode, int16_t adc_data, float *Voltage)
{
NVR_ADCVOLPARA parameter;
NVR_BATMEARES BAT_OffsetInfo;
/* Check parameters */
assert_parameters(IS_ADCVOL_MODE(Mode));
if (NVR_GetADCVoltageParameter(Mode, &parameter))
{
if ((Mode&0xFUL) > 2UL) /* VDD or BATRTC channel */
{
if (NVR_GetBATOffset(&BAT_OffsetInfo))
{
return 1;
}
else
{
if (((Mode&0xFUL) == 3UL) || ((Mode&0xFUL) == 5UL)) /* VDD/BATRTC, Resistive */
{
*Voltage = (float)(0.00015392*(float)adc_data + 0.06667986) + BAT_OffsetInfo.BATRESResult;
}
else /* VDD/BATRTC, Capacitive */
{
*Voltage = (float)(0.00014107*(float)adc_data - 0.00699515) + BAT_OffsetInfo.BATCAPResult;
}
}
}
else /* External channel */
{
if (Mode & 0x100UL) /* Power supply: 5V */
{
if ((Mode&0xFUL) == 0UL) /* No divider */
{
*Voltage = (float)(0.00003678*(float)adc_data + 0.00235783);
}
else if ((Mode&0xFUL) == 1UL) /* Resistive */
{
*Voltage = (float)(0.00016129*(float)adc_data + 0.00673599);
}
else /* Capacitive */
{
*Voltage = (float)(0.00014076*(float)adc_data - 0.00753319);
}
}
else /* Power supply: 3.3V */
{
if ((Mode&0xFUL) == 0UL) /* No divider */
{
*Voltage = (float)(0.00003680*(float)adc_data + 0.00205011);
}
else if ((Mode&0xFUL) == 1UL) /* Resistive */
{
*Voltage = (float)(0.00016425*(float)adc_data + 0.03739179);
}
else /* Capacitive */
{
*Voltage = (float)(0.00014051*(float)adc_data - 0.00023322);
}
}
}
}
else
{
*Voltage = (float)(parameter.aParameter*(float)adc_data + parameter.bParameter);
}
return 0;
}
/**
* @brief Get VDD Voltage(takes 244us).
* @note This function costs about 170us when SystemClock is 26M.
* ADC data refresh time is 117us.
* @note This function will release ADC resource(write ADC registers with their
* default reset values).
* @note ADC configurarion:
* - Trigger mode: manual mode
* - Conversion mode: single channel mode(VDD channel 1)
* - ADC clock: 3.2M
* - Skip samples: Skip 2 samples
* - Down sampling rate: 1/64
* @param [in]Division
ADC_BAT_CAPDIV (Cap division 1/4)
ADC_BAT_RESDIV (Resistance division 1/4)
[out]CalResults.VDDVoltage The value of VDD Voltage
[out]CalResults.BATRTCVoltage is ignored
[out]CalResults.Temperature is ignored
* @retval 1 NVR BAT-offset information checksum error.
0 Function successed.
*/
uint32_t ADC_GetVDDVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults)
{
float Vbatcap;
float Vbatres;
NVR_BATMEARES BAT_OffsetInfo;
int16_t data;
assert_parameters(IS_ADC_BATDIV(Division));
/* Get NVR BAT offset information */
if (NVR_GetBATOffset(&BAT_OffsetInfo))
{
return (1);
}
else
{
Vbatcap = BAT_OffsetInfo.BATCAPResult;
Vbatres = BAT_OffsetInfo.BATRESResult;
}
/* ADC initialization */
ADC_DeInit();
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
ANA->ADCCTRL = 0x06C00101;
/* Enable division */
ANA->REG1 |= Division;
/* Enable ADC */
ana_reg3_tmp |= ANA_REG3_ADCPDN;
ANA->REG3 = ana_reg3_tmp;
/* Start a manual ADC conversion */
ADC_StartManual();
/* Waiting last operation done */
ADC_WaitForManual();
data = ANA->ADCDATA1;
/* Calculate the voltage of VDD */
if (Division & ADC_BAT_CAPDIV)
{
CalResults->VDDVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap;
}
else
{
CalResults->VDDVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres;
}
/* ADC resource release */
ADC_DeInit();
return (0);
}
/**
* @brief Get VDD Voltage(takes 3.3ms).
* @note This function costs about 3.3ms when SystemClock is 26M.
* ADC data refresh time is about 3.2ms.
* @note This function will release ADC resource(write ADC registers with their
* default reset values).
* @note ADC configurarion:
* - Trigger mode: manual mode
* - Conversion mode: single channel mode(VDD channel 1)
* - ADC clock: 1.6M
* - Skip samples: Skip first 4 samples
* - Down sampling rate: 1/512
* @param [in]Division
ADC_BAT_CAPDIV (Cap division 1/4)
ADC_BAT_RESDIV (Resistance division 1/4)
[out]CalResults.VDDVoltage The value of VDD Voltage
[out]CalResults.BATRTCVoltage is ignored
[out]CalResults.Temperature is ignored
* @retval 1 NVR BAT-offset information checksum error.
0 Function successed.
*/
uint32_t ADC_GetVDDVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults)
{
float Vbatcap;
float Vbatres;
NVR_BATMEARES BAT_OffsetInfo;
ADCInitType ADC_InitStruct;
int16_t data;
assert_parameters(IS_ADC_BATDIV(Division));
/* Get NVR BAT offset information */
if (NVR_GetBATOffset(&BAT_OffsetInfo))
{
return (1);
}
else
{
Vbatcap = BAT_OffsetInfo.BATCAPResult;
Vbatres = BAT_OffsetInfo.BATRESResult;
}
/* ADC initialization */
ADC_DeInit();
ADC_InitStruct.TrigMode = ADC_TRIGMODE_MANUAL;
ADC_InitStruct.ConvMode = ADC_CONVMODE_SINGLECHANNEL;
ADC_InitStruct.Channel = ADC_CHANNEL1;
ADC_InitStruct.ClockDivider = ADC_CLKDIV_4;
ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH;
ADC_Init(&ADC_InitStruct);
/* Enable division */
ANA->REG1 |= Division;
/* Enable ADC */
ana_reg3_tmp |= ANA_REG3_ADCPDN;
ANA->REG3 = ana_reg3_tmp;
/* Start a manual ADC conversion */
ADC_StartManual();
/* Waiting last operation done */
ADC_WaitForManual();
data = ANA->ADCDATA1;
/* Calculate the voltage of VDD */
if (Division & ADC_BAT_CAPDIV)
{
CalResults->VDDVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap;
}
else
{
CalResults->VDDVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres;
}
/* ADC resource release */
ADC_DeInit();
return (0);
}
/**
* @brief Get BATRTC Voltage(takes 244us).
* @note This function takes about 244us when SystemClock is 26M.
* ADC data refresh time is 117us.
* @note This function will release ADC resource(write ADC registers with their
* default reset values).
* @note ADC configurarion:
* - Trigger mode: manual mode
* - Conversion mode: single channel mode(BATRTC channel 2)
* - ADC clock: 3.2M
* - Skip samples: Skip 2 samples
* - Down sampling rate: 1/64
* @param [in]Division
ADC_BAT_CAPDIV (Cap division 1/4)
ADC_BAT_RESDIV (Resistance division 1/4)
[out]CalResults.VDDVoltage is ignored
[out]CalResults.BATRTCVoltage The value of BATRTC Voltage
[out]CalResults.Temperature is ignored
* @retval 1 NVR BAT-offset or BGP-gain information checksum error.
0 Function successed.
*/
uint32_t ADC_GetBATRTCVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults)
{
float Vbatcap;
float Vbatres;
NVR_BATMEARES BAT_OffsetInfo;
int16_t data;
assert_parameters(IS_ADC_BATDIV(Division));
/* Get NVR BAT offset information */
if (NVR_GetBATOffset(&BAT_OffsetInfo))
{
return (1);
}
else
{
Vbatcap = BAT_OffsetInfo.BATCAPResult;
Vbatres = BAT_OffsetInfo.BATRESResult;
}
/* ADC initialization */
ADC_DeInit();
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
ANA->ADCCTRL = 0x06C00102;
/* Enable division */
ANA->REG1 |= Division;
/* Enable ADC */
ana_reg3_tmp |= ANA_REG3_ADCPDN;
ANA->REG3 = ana_reg3_tmp;
/* Start a manual ADC conversion */
ADC_StartManual();
/* Waiting last operation done */
ADC_WaitForManual();
data = ANA->ADCDATA2;
/* Calculate the voltage of BAT1 */
if (Division & ADC_BAT_CAPDIV)
{
CalResults->BATRTCVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap;
}
else
{
CalResults->BATRTCVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres;
}
/* ADC resource release */
ADC_DeInit();
return (0);
}
/**
* @brief Get BATRTC Voltage(takes 3.3ms).
* @note This function takes about 3.3ms when SystemClock is 26M.
* ADC data refresh time is about 3.2ms.
* @note This function will release ADC resource(write ADC registers with their
* default reset values).
* @note ADC configurarion:
* - Trigger mode: manual mode
* - Conversion mode: single channel mode(BATRTC channel 2)
* - ADC clock: 1.6M
* - Skip samples: Skip first 4 samples
* - Down sampling rate: 1/512
* @param [in]Division
ADC_BAT_CAPDIV (Capacitance division 1/4)
ADC_BAT_RESDIV (Resistance division 1/4)
[out]CalResults.VDDVoltage is ignored
[out]CalResults.BATRTCVoltage The value of BATRTC Voltage
[out]CalResults.Temperature is ignored
* @retval 1 NVR BAT-offset information checksum error.
0 Function successed.
*/
uint32_t ADC_GetBATRTCVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults)
{
float Vbatcap;
float Vbatres;
NVR_BATMEARES BAT_OffsetInfo;
ADCInitType ADC_InitStruct;
int16_t data;
assert_parameters(IS_ADC_BATDIV(Division));
/* Get NVR BAT offset information */
if (NVR_GetBATOffset(&BAT_OffsetInfo))
{
return (1);
}
else
{
Vbatcap = BAT_OffsetInfo.BATCAPResult;
Vbatres = BAT_OffsetInfo.BATRESResult;
}
/* ADC initialization */
ADC_DeInit();
ADC_InitStruct.TrigMode = ADC_TRIGMODE_MANUAL;
ADC_InitStruct.ConvMode = ADC_CONVMODE_SINGLECHANNEL;
ADC_InitStruct.Channel = ADC_CHANNEL2;
ADC_InitStruct.ClockDivider = ADC_CLKDIV_4;
ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH;
ADC_Init(&ADC_InitStruct);
/* Enable division */
ANA->REG1 |= Division;
/* Enable ADC */
ana_reg3_tmp |= ANA_REG3_ADCPDN;
ANA->REG3 = ana_reg3_tmp;
/* Start a manual ADC conversion */
ADC_StartManual();
/* Waiting last operation done */
ADC_WaitForManual();
data = ANA->ADCDATA2;
/* Calculate the voltage of BAT1 */
if (Division & ADC_BAT_CAPDIV)
{
CalResults->BATRTCVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap;
}
else
{
CalResults->BATRTCVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres;
}
/* ADC resource release */
ADC_DeInit();
return (0);
}
/**
* @brief Get Temperature(takes 6.5ms).
* @note This function costs about 6.5ms when SystemClock is 26M.
* ADC data refresh time is about 3.2ms.
* @note This function will release ADC resource(write ADC registers with their
* default reset values).
* @note ADC configurarion:
* - Trigger mode: manual mode
* - Conversion mode: single channel mode(Temperature channel 10)
* - ADC clock: 1.6M
* - Skip samples: Skip first 4 samples
* - Down sampling rate: 1/512
* @param [out]CalResults.VDDVoltage is ignored
[out]CalResults.BATRTCVoltage is ignored
[out]CalResults.Temperature The value of Temperature
* @retval 1 Temperature delta information checksum error.
0 Function successed.
*/
uint32_t ADC_GetTemperature(ADC_CalResType *CalResults)
{
int32_t P2;
int16_t P1, P0;
int16_t adc_data;
uint32_t retval;
NVR_RTCINFO RTC_DataStruct;
ADCInitType ADC_InitStruct;
/* Get RTC Px parameters */
retval = NVR_GetInfo_LoadRTCData(&RTC_DataStruct);
if (retval & 0x1U)
{
return (1);
}
else
{
P0 = RTC_DataStruct.RTCTempP0;
P1 = RTC_DataStruct.RTCTempP1;
P2 = RTC_DataStruct.RTCTempP2;
}
/* ADC initialization */
ADC_DeInit();
ADC_InitStruct.TrigMode = ADC_TRIGMODE_MANUAL;
ADC_InitStruct.ConvMode = ADC_CONVMODE_SINGLECHANNEL;
ADC_InitStruct.Channel = ADC_CHANNEL10;
ADC_InitStruct.ClockDivider = ADC_CLKDIV_4;
ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH;
ADC_Init(&ADC_InitStruct);
/* Configure 1/512 down-sampling rate */
ADC_CICDownSamRateConfig(ADC_SDRSEL_DIV512);
/* Enable ADC */
ADC_Cmd(ENABLE);
/*---------- Get ADC data1 ----------*/
/* Starts a manual ADC conversion */
ADC_StartManual();
/* Waiting Manual ADC conversion done */
ADC_WaitForManual();
adc_data = (int16_t)ADC_GetADCConversionValue(ADC_CHANNEL10);
/* ADC resource release */
ADC_DeInit();
/* Calculate temperature */
CalResults->Temperature = (float)((((P0 * ((adc_data*adc_data)>>16)) + P1*adc_data + P2) >> 8) / 256.0);
return (0);
}
/**
* @brief ADC power control.
* @note When DISABLE is selected, the automatic triggering of the ADC must be turned off by calling
* ADC_TrigSourceConfig(ADC_TRIGSOURCE_OFF) before using this function.
* @param NewState
ENABLE
DISABLE
* @retval 0: Function succeeded
* 1: Function failded, the automatic triggering be enabled when DISABLE selected
*/
uint32_t ADC_Cmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == DISABLE)
{
if (ANA->ADCCTRL & ANA_ADCCTRL_AEN)
{
return 1;
}
else
{
ana_reg3_tmp &= ~ANA_REG3_ADCPDN;
}
}
else
{
ana_reg3_tmp |= ANA_REG3_ADCPDN;
}
ANA->REG3 = ana_reg3_tmp;
return 0;
}
/**
* @brief Manual ADC trigger
* @param None
* @retval None
*/
void ADC_StartManual(void)
{
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
ANA->ADCCTRL |= ANA_ADCCTRL_MTRIG;
}
/**
* @brief Wait for the last Manual ADC conversion done.
* @param None
* @retval None
*/
void ADC_WaitForManual(void)
{
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG)
{
}
}
/**
* @brief ADC auto mode trigger source configure.
* @param TrigSource:
ADC_TRIGSOURCE_OFF
ADC_TRIGSOURCE_TIM0
ADC_TRIGSOURCE_TIM1
ADC_TRIGSOURCE_TIM2
ADC_TRIGSOURCE_TIM3
* @retval None
*/
void ADC_TrigSourceConfig(uint32_t TrigSource)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADC_TRIGSOURCE(TrigSource));
tmp = ANA->ADCCTRL;
tmp &= ~ANA_ADCCTRL_AEN;
tmp |= TrigSource;
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
ANA->ADCCTRL = tmp;
}
/**
* @brief Resistance division enable control.
* @param NewState
ENABLE (x1/4)
DISABLE (x1)
* @retval None
*/
void ADC_RESDivisionCmd(uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = ANA->REG1;
if (NewState == ENABLE)
{
tmp &= ~ANA_REG1_GDE4;
tmp |=ANA_REG1_RESDIV;
}
else
{
tmp &= ~ANA_REG1_RESDIV;
}
ANA->REG1 = tmp;
}
/**
* @brief Capacitance division enable control.
* @param NewState
ENABLE (x1/4)
DISABLE (x1)
* @retval None
*/
void ADC_CAPDivisionCmd(uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = ANA->REG1;
if (NewState == ENABLE)
{
tmp &= ~ANA_REG1_RESDIV;
tmp |=ANA_REG1_GDE4;
}
else
{
tmp &= ~ANA_REG1_GDE4;
}
ANA->REG1 = tmp;
}
/**
* @brief CIC filter always on control.
* @param NewState
ENABLE (CIC filter always on)
DISABLE (CIC filter will be disabled when no ADC sample process is ongoing.)
* @retval None
*/
void ADC_CICAlwaysOnCmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
if (NewState == ENABLE)
ANA->ADCCTRL |= ANA_ADCCTRL_CICAON;
else
ANA->ADCCTRL &= ~ANA_ADCCTRL_CICAON;
}
/**
* @brief CIC filter input inversion control.
* @param NewState
ENABLE
DISABLE
* @retval None
*/
void ADC_CICINVCmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
if (NewState == ENABLE)
ANA->ADCCTRL |= ANA_ADCCTRL_CICINV;
else
ANA->ADCCTRL &= ~ANA_ADCCTRL_CICINV;
}
/**
* @brief CIC output scale-down configure.
* @param ScaleDown:
ADC_SCA_NONE
ADC_SCA_DIV2
* @retval None
*/
void ADC_CICScaleDownConfig(uint32_t ScaleDown)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADC_SCA(ScaleDown));
tmp = ANA->ADCCTRL;
tmp &= ~ANA_ADCCTRL_CICSCA;
tmp |= ScaleDown;
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
ANA->ADCCTRL = tmp;
}
/**
* @brief CIC output skip control.
* @param Skip:
ADC_SKIP_4
ADC_SKIP_5
ADC_SKIP_6
ADC_SKIP_7
ADC_SKIP_0
ADC_SKIP_1
ADC_SKIP_2
ADC_SKIP_3
* @retval None
*/
void ADC_CICSkipConfig(uint32_t Skip)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADC_SKIP(Skip));
tmp = ANA->ADCCTRL;
tmp &= ~ANA_ADCCTRL_CICSKIP;
tmp |= Skip;
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
ANA->ADCCTRL = tmp;
}
/**
* @brief CIC down sampling rate control.
* @param DSRSelection:
ADC_SDRSEL_DIV512
ADC_SDRSEL_DIV256
ADC_SDRSEL_DIV128
ADC_SDRSEL_DIV64
* @retval None
*/
void ADC_CICDownSamRateConfig(uint32_t DSRSelection)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADC_SDR(DSRSelection));
tmp = ANA->ADCCTRL;
tmp &= ~ANA_ADCCTRL_DSRSEL;
tmp |= DSRSelection;
while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG);
ANA->ADCCTRL = tmp;
}
/**
* @brief Get ADC vonversion value.
* @param Channel:
ADC_CHANNEL0
ADC_CHANNEL1
ADC_CHANNEL2
ADC_CHANNEL3
ADC_CHANNEL4
ADC_CHANNEL5
ADC_CHANNEL6
ADC_CHANNEL7
ADC_CHANNEL8
ADC_CHANNEL9
ADC_CHANNEL10
ADC_CHANNEL11
* @retval ADC conversion value.
*/
int16_t ADC_GetADCConversionValue(uint32_t Channel)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_ADC_CHANNEL(Channel));
addr = &ANA->ADCDATA0 + Channel;
return *addr;
}
/**
* @brief ADC interrupt control.
* @param INTMask:
ADC_INT_AUTODONE
ADC_INT_MANUALDONE
NewState
ENABLE
DISABLE
* @retval None
*/
void ADC_INTConfig(uint32_t INTMask, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
assert_parameters(IS_ADC_INT(INTMask));
if (NewState == ENABLE)
ANA->INTEN |= INTMask;
else
ANA->INTEN &= ~INTMask;
}
/**
* @brief Get auto done flag
* @param None
* @retval 1 flag set
* 0 flag reset.
*/
uint8_t ADC_GetAutoDoneFlag(void)
{
if(ANA->INTSTS & ANA_INTSTS_INTSTS1)
return 1;
else
return 0;
}
/**
* @brief Get manual done flag
* @param None
* @retval 1 flag set
* 0 flag reset.
*/
uint8_t ADC_GetManualDoneFlag(void)
{
if(ANA->INTSTS & ANA_INTSTS_INTSTS0)
return 1;
else
return 0;
}
/**
* @brief Clear auto done flag
* @param None
* @retval None
*/
void ADC_ClearAutoDoneFlag(void)
{
ANA->INTSTS = ANA_INTSTS_INTSTS1;
}
/**
* @brief Clear manual done flag
* @param None
* @retval None
*/
void ADC_ClearManualDoneFlag(void)
{
ANA->INTSTS = ANA_INTSTS_INTSTS0;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_adc_tiny.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief ADC_TINY library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_adc_tiny.h"
#define ANA_REGF_RSTValue (0U)
/**
* @brief Initializes the Tiny ADC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void TADC_DeInit(void)
{
ANA->REGF = ANA_REGF_RSTValue;
ANA->INTSTS = ANA_INTSTS_INTSTS13;
ANA->MISC_A &= ~ANA_MISC_TADCTH;
}
/**
* @brief Fills each TADC_InitStruct member with its default value.
* @param TADC_InitStruct: pointer to an TADCInitType structure which will be initialized.
* @retval None
*/
void TADC_StructInit(TADCInitType* TADC_InitStruct)
{
/*--------------- Reset TADC init structure parameters values ---------------*/
/* Initialize the SignalSel member */
TADC_InitStruct->SignalSel = ADCTINY_SIGNALSEL_IOE6;
/* Initialize the ADTREF1 member */
TADC_InitStruct->ADTREF1 = ADCTINY_REF1_0_9;
/* Initialize the ADTREF2 member */
TADC_InitStruct->ADTREF2 = ADCTINY_REF2_1_8;
/* Initialize the ADTREF3 member */
TADC_InitStruct->ADTREF3 = ADCTINY_REF3_2_7;
}
/**
* @brief Tiny ADC initialization.
* @param TADC_InitStruct
SelADT:
ADCTINY_SIGNALSEL_IOE6
ADCTINY_SIGNALSEL_IOE7
ADTREF1:
ADCTINY_REF1_0_9
ADCTINY_REF1_0_7
ADTREF2:
ADCTINY_REF2_1_8
ADCTINY_REF2_1_6
ADTREF3:
ADCTINY_REF3_2_7
ADCTINY_REF3_2_5
* @retval None
*/
void TADC_Init(TADCInitType* TADC_InitStruct)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADCTINY_SELADT(TADC_InitStruct->SignalSel));
assert_parameters(IS_ADCTINY_ADTREF1(TADC_InitStruct->ADTREF1));
assert_parameters(IS_ADCTINY_ADTREF2(TADC_InitStruct->ADTREF2));
assert_parameters(IS_ADCTINY_ADTREF3(TADC_InitStruct->ADTREF3));
tmp = ANA->REGF;
tmp &= ~(ANA_REGF_SELADT \
|ANA_REGF_ADTREF1SEL\
|ANA_REGF_ADTREF2SEL\
|ANA_REGF_ADTREF3SEL);
tmp |= (TADC_InitStruct->SignalSel \
|TADC_InitStruct->ADTREF1\
|TADC_InitStruct->ADTREF2\
|TADC_InitStruct->ADTREF3);
ANA->REGF = tmp;
}
/**
* @brief TADC enable control.
* @param NewState
ENABLE
DISABLE
* @retval None
*/
void TADC_Cmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
ANA->REGF |= ANA_REGF_PDNADT;
else
ANA->REGF &= ~ANA_REGF_PDNADT;
}
/**
* @brief Get TADC output.
* @param None
* @retval Output of Tiny ADC(0 ~ 3).
*/
uint8_t TADC_GetOutput(void)
{
return ((ANA->COMPOUT & ANA_COMPOUT_TADCO) >> ANA_COMPOUT_TADCO_Pos);
}
/**
* @brief Configure Tiny ADC interrupt threshold.
* @param THSel:
ADCTINY_THSEL_0
ADCTINY_THSEL_1
ADCTINY_THSEL_2
ADCTINY_THSEL_3
* @retval None.
*/
void TADC_IntTHConfig(uint32_t THSel)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ADCTINY_THSEL(THSel));
tmp = ANA->MISC_A;
tmp &= ~ANA_MISC_TADCTH;
tmp |= THSel;
ANA->MISC_A = tmp;
}
/**
* @brief TADC interrupt enable control.
* @param NewState
ENABLE
DISABLE
* @retval None
*/
void TADC_INTConfig(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
ANA->INTEN |= ANA_INTEN_INTEN13;
else
ANA->INTEN &= ~ANA_INTEN_INTEN13;
}
/**
* @brief Get Tiny ADC interrupt status.
* @param None
* @retval Interrupt status.
*/
uint8_t TADC_GetINTStatus(void)
{
if (ANA->INTSTS & ANA_INTSTS_INTSTS13)
return 1;
else
return 0;
}
/**
* @brief Clear Tiny ADC interrupt status.
* @param None
* @retval None
*/
void TADC_ClearINTStatus(void)
{
ANA->INTSTS = ANA_INTSTS_INTSTS13;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_ana.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Analog library.
******************************************************************************
* @attention
*
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_ana.h"
/**
* @brief Get analog status.
* @param StatusMask:
ANA_STATUS_AVCCLV
ANA_STATUS_VDCINDROP
ANA_STATUS_VDDALARM
ANA_STATUS_COMP2
ANA_STATUS_COMP1
ANA_STATUS_LOCKL
ANA_STATUS_LOCKH
* @retval Analog status
*/
uint8_t ANA_GetStatus(uint32_t StatusMask)
{
/* Check parameters */
assert_parameters(IS_ANA_STATUS(StatusMask));
if (ANA->COMPOUT & StatusMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Get interrupt status.
* @param IntMask:
ANA_INT_TADC_OVER
ANA_INT_REGERR
ANA_INT_SME
ANA_INT_AVCCLV
ANA_INT_VDCINDROP
ANA_INT_VDDALARM
ANA_INT_COMP2
ANA_INT_COMP1
ANA_INT_ADCA
ANA_INT_ADCM
* @retval interrupt status.
*/
uint8_t ANA_GetINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_ANA_INTSTSR(IntMask));
if (ANA->INTSTS&IntMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear interrupt status.
* @param IntMask:
ANA_INT_TADC_OVER
ANA_INT_REGERR
ANA_INT_SME
ANA_INT_AVCCLV
ANA_INT_VDCINDROP
ANA_INT_VDDALARM
ANA_INT_COMP2
ANA_INT_COMP1
ANA_INT_ADCA
ANA_INT_ADCM
* @retval None
*/
void ANA_ClearINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_ANA_INTSTSC(IntMask));
ANA->INTSTS = IntMask;
}
/**
* @brief ANA interrupt configure.
* @param IntMask:
ANA_INT_REGERR
ANA_INT_SME
ANA_INT_AVCCLV
ANA_INT_VDCINDROP
ANA_INT_VDDALARM
ANA_INT_COMP2
ANA_INT_COMP1
ANA_INT_ADCA
ANA_INT_ADCM
NewState:
ENABLE
DISABLE
* @retval None
*/
void ANA_INTConfig(uint32_t IntMask, uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ANA_INT(IntMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = ANA->INTEN;
if (NewState == ENABLE)
{
tmp |= IntMask;
}
else
{
tmp &= ~IntMask;
}
ANA->INTEN = tmp;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_clk.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Clock library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_clk.h"
__IO uint32_t ana_reg3_tmp;
/**
* @brief Initializes the CPU, AHB and APB buses clocks according to the specified
* parameters in the CLK_ClkInitStruct.
*
* @note This function performs the following:
* 1. If want to switch AHB clock source, enable BGP, enable 6.5M RC,
* AHB clock source switch to RCH first.
* 2. configure clock (except AHB clock source configuration). - optional
* 3. configure AHB clock source. - optional
* 4. HCLK/PCLK divider configuration. - optional
*
* @note CLK_InitTypeDef *CLK_ClkInitStruct
* [in]CLK_ClkInitStruct->ClockType, can use the ¡®|¡¯ operator, the selection of parameters is as follows
* CLK_TYPE_ALL
* CLK_TYPE_AHBSRC
* CLK_TYPE_PLLL
* CLK_TYPE_PLLH
* CLK_TYPE_XTALH
* CLK_TYPE_RTCCLK
* CLK_TYPE_HCLK
* CLK_TYPE_PCLK
*
* CLK_TYPE_ALL All clocks' configurations is valid
* CLK_TYPE_AHBSRC CLK_ClkInitStruct->AHBSource(AHB Clock source configuration) is valid
* [in]CLK_ClkInitStruct->AHBSource:
* CLK_AHBSEL_6_5MRC
* CLK_AHBSEL_6_5MXTAL
* CLK_AHBSEL_HSPLL
* CLK_AHBSEL_RTCCLK
* CLK_AHBSEL_LSPLL
* CLK_TYPE_PLLL CLK_ClkInitStruct->PLLL(PLLL configuration) is valid
* [in]CLK_ClkInitStruct->PLLL.State:
* CLK_PLLL_ON (PLLL.Source/Frequency configuration is valid)
* CLK_PLLL_OFF (PLLL.Source/Frequency configuration is not valid)
* [in]CLK_ClkInitStruct->PLLL.Source:
* CLK_PLLLSRC_RCL
* CLK_PLLLSRC_XTALL
* [in]CLK_ClkInitStruct->PLLL.Frequency:
* CLK_PLLL_26_2144MHz
* CLK_PLLL_13_1072MHz
* CLK_PLLL_6_5536MHz
* CLK_PLLL_3_2768MHz
* CLK_PLLL_1_6384MHz
* CLK_PLLL_0_8192MHz
* CLK_PLLL_0_4096MHz
* CLK_PLLL_0_2048MHz
* CLK_TYPE_PLLH CLK_ClkInitStruct->PLLH(PLLH configuration) is valid
* [in]CLK_ClkInitStruct->PLLH.State:
* CLK_PLLH_ON (PLLH.Source/Frequency configuration is valid)
* CLK_PLLH_OFF (PLLH.Source/Frequency configuration is not valid)
* [in]CLK_ClkInitStruct->PLLH.Source:
* CLK_PLLHSRC_RCH
* CLK_PLLHSRC_XTALH
* [in]CLK_ClkInitStruct->PLLH.Frequency:
* CLK_PLLH_13_1072MHz
* CLK_PLLH_16_384MHz
* CLK_PLLH_19_6608MHz
* CLK_PLLH_22_9376MHz
* CLK_PLLH_26_2144MHz
* CLK_PLLH_29_4912MHz
* CLK_PLLH_32_768MHz
* CLK_PLLH_36_0448MHz
* CLK_PLLH_39_3216MHz
* CLK_PLLH_42_5984MHz
* CLK_PLLH_45_8752MHz
* CLK_PLLH_49_152MHz
* CLK_TYPE_XTALH CLK_ClkInitStruct->XTALH(XTALH configuration) is valid
* [in]CLK_ClkInitStruct->XTALH.State:
* CLK_XTALH_ON
* CLK_XTALH_OFF
* CLK_TYPE_RTCCLK CLK_ClkInitStruct->RTCCLK(RTCCLK configuration) is valid
* [in]CLK_ClkInitStruct->RTCCLK.Source:
* CLK_RTCCLKSRC_XTALL
* CLK_RTCCLKSRC_RCL
* [in]CLK_ClkInitStruct->RTCCLK.Divider:
* CLK_RTCCLKDIV_1
* CLK_RTCCLKDIV_4
* CLK_TYPE_HCLK CLK_ClkInitStruct->HCLK(AHB Clock(divider) configuration) is valid
* [in]CLK_ClkInitStruct->HCLK.Divider:
* 1 ~ 256
* CLK_TYPE_PCLK CLK_ClkInitStruct->PCLK(APB Clock(divider) configuration) is valid
* [in]CLK_ClkInitStruct->PCLK.Divider:
* 1 ~ 256
*
* @param CLK_ClkInitStruct pointer to an CLK_InitTypeDef structure that
* contains the configuration information for the clocks.
*
* @retval None
*/
void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct)
{
uint32_t tmp;
assert_parameters(IS_CLK_TYPE(CLK_ClkInitStruct->ClockType));
if (CLK_ClkInitStruct->ClockType & CLK_TYPE_AHBSRC)
{
/* Enable BGP */
ana_reg3_tmp &= ~ANA_REG3_BGPPD;
/* Enable 6.5M RC */
ana_reg3_tmp &= ~ANA_REG3_RCHPD;
ANA->REG3 = ana_reg3_tmp;
/* AHB clock source switch to RCH */
MISC2->CLKSEL = 0;
}
ANA->REGA &= ~BIT6;
ANA->REG2 &= ~BIT7;
/*---------- XTALH configuration ----------*/
if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_XTALH)
{
assert_parameters(IS_CLK_XTALHSTA(CLK_ClkInitStruct->XTALH.State));
/* XTALH state configure */
ana_reg3_tmp &= ~ANA_REG3_XOHPDN;
ana_reg3_tmp |= CLK_ClkInitStruct->XTALH.State;
ANA->REG3 = ana_reg3_tmp;
}
/*-------------------- PLLL configuration --------------------*/
if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLL)
{
assert_parameters(IS_CLK_PLLLSRC(CLK_ClkInitStruct->PLLL.Source));
assert_parameters(IS_CLK_PLLLSTA(CLK_ClkInitStruct->PLLL.State));
assert_parameters(IS_CLK_PLLLFRQ(CLK_ClkInitStruct->PLLL.Frequency));
/* XTALL power up */
tmp = ANA->REG2;
tmp &= ~BIT7;
ANA->REG2 = tmp;
/* PLLL state configure */
if (CLK_ClkInitStruct->PLLL.State == CLK_PLLL_ON)
{
/* power up PLLL */
ana_reg3_tmp |= ANA_REG3_PLLLPDN;
ANA->REG3 = ana_reg3_tmp;
/* Configure PLLL frequency */
tmp = ANA->REG9;
tmp &= ~ANA_REG9_PLLLSEL;
tmp |= CLK_ClkInitStruct->PLLL.Frequency;
ANA->REG9 = tmp;
/* Configure PLLL input clock selection */
tmp = PMU->CONTROL;
tmp &= ~PMU_CONTROL_PLLL_SEL;
tmp |= CLK_ClkInitStruct->PLLL.Source;
PMU->CONTROL = tmp;
}
else
{
/* power down PLLL */
ana_reg3_tmp &= ~ANA_REG3_PLLLPDN;
ANA->REG3 = ana_reg3_tmp;
}
}
/*-------------------- PLLH configuration --------------------*/
if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLH)
{
assert_parameters(IS_CLK_PLLHSRC(CLK_ClkInitStruct->PLLH.Source));
assert_parameters(IS_CLK_PLLHSTA(CLK_ClkInitStruct->PLLH.State));
assert_parameters(IS_CLK_PLLHFRQ(CLK_ClkInitStruct->PLLH.Frequency));
/* PLLH state configure */
if (CLK_ClkInitStruct->PLLH.State == CLK_PLLH_ON)
{
/* Power up PLLH */
ana_reg3_tmp |= ANA_REG3_PLLHPDN;
ANA->REG3 = ana_reg3_tmp;
/* Configure PLLH frequency */
tmp = ANA->REG9;
tmp &= ~ANA_REG9_PLLHSEL;
tmp |= CLK_ClkInitStruct->PLLH.Frequency;
ANA->REG9 = tmp;
/* Clock input source, XTALH, XOH power on*/
if (CLK_ClkInitStruct->PLLH.Source == CLK_PLLHSRC_XTALH)
{
ana_reg3_tmp |= ANA_REG3_XOHPDN;
ANA->REG3 = ana_reg3_tmp;
}
/* Configure PLLH input clock selection */
tmp = PMU->CONTROL;
tmp &= ~PMU_CONTROL_PLLH_SEL;
tmp |= CLK_ClkInitStruct->PLLH.Source;
PMU->CONTROL = tmp;
}
else
{
/* Power down PLLH */
ana_reg3_tmp &= ~ANA_REG3_PLLHPDN;
ANA->REG3 = ana_reg3_tmp;
}
}
/*---------- RTCCLK configuration ----------*/
if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_RTCCLK)
{
assert_parameters(IS_CLK_RTCSRC(CLK_ClkInitStruct->RTCCLK.Source));
assert_parameters(IS_CLK_RTCDIV(CLK_ClkInitStruct->RTCCLK.Divider));
/* RTCCLK source(optional) */
tmp = PMU->CONTROL;
tmp &= ~PMU_CONTROL_RTCLK_SEL;
tmp |= CLK_ClkInitStruct->RTCCLK.Source;
PMU->CONTROL = tmp;
/*----- RTCCLK Divider -----*/
RTC_PrescalerConfig(CLK_ClkInitStruct->RTCCLK.Divider);
}
/*---------- AHB clock source configuration ----------*/
if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_AHBSRC)
{
assert_parameters(IS_CLK_AHBSRC(CLK_ClkInitStruct->AHBSource));
/* clock source: 6.5M RC */
if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MRC)
{
/* clock source configuration */
MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
}
/* clock source: 6_5MXTAL */
else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MXTAL)
{
/* Power up 6.5M xtal */
ana_reg3_tmp |= ANA_REG3_XOHPDN;
ANA->REG3 = ana_reg3_tmp;
/* clock source configuration */
MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
}
/* clock source: PLLH */
else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_HSPLL)
{
/* Power up PLLH */
ana_reg3_tmp |= ANA_REG3_PLLHPDN;
ANA->REG3 = ana_reg3_tmp;
/* while loop until PLLL is lock */
while (!(ANA->COMPOUT & ANA_COMPOUT_LOCKH))
{
}
/* clock source configuration */
MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
}
/* clock source: PLLL */
else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_LSPLL)
{
/* Power up PLLL */
ana_reg3_tmp |= ANA_REG3_PLLLPDN;
ANA->REG3 = ana_reg3_tmp;
/* while loop until PLLL is lock */
while (!(ANA->COMPOUT & ANA_COMPOUT_LOCKL))
{
}
/* clock source configuration */
MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
}
/* clock source: RTCCLK */
else
{
/* clock source configuration */
MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
}
}
/*---------- HCLK configuration ----------*/
if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_HCLK)
{
assert_parameters(IS_CLK_HCLKDIV(CLK_ClkInitStruct->HCLK.Divider));
MISC2->CLKDIVH = (CLK_ClkInitStruct->HCLK.Divider) - 1;
}
/*---------- PCLK configuration ----------*/
if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PCLK)
{
assert_parameters(IS_CLK_PCLKDIV(CLK_ClkInitStruct->PCLK.Divider));
MISC2->CLKDIVP = (CLK_ClkInitStruct->PCLK.Divider) - 1;
}
}
/**
* @brief AHB Periphral clock control.
* @param Periphral: can use the ¡®|¡¯ operator
CLK_AHBPERIPHRAL_DMA
CLK_AHBPERIPHRAL_GPIO
CLK_AHBPERIPHRAL_LCD
CLK_AHBPERIPHRAL_CRYPT
NewState:
ENABLE
DISABLE
* @retval None.
*/
void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_CLK_AHBPERIPHRAL(Periphral));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
MISC2->HCLKEN |= Periphral;
}
else
{
MISC2->HCLKEN &= ~Periphral;
}
}
/**
* @brief APB Periphral clock control.
* @param Periphral: can use the ¡®|¡¯ operator
CLK_APBPERIPHRAL_DMA
CLK_APBPERIPHRAL_I2C
CLK_APBPERIPHRAL_SPI1
CLK_APBPERIPHRAL_SPI2
CLK_APBPERIPHRAL_UART0
CLK_APBPERIPHRAL_UART1
CLK_APBPERIPHRAL_UART2
CLK_APBPERIPHRAL_UART3
CLK_APBPERIPHRAL_UART4
CLK_APBPERIPHRAL_UART5
CLK_APBPERIPHRAL_ISO78160
CLK_APBPERIPHRAL_ISO78161
CLK_APBPERIPHRAL_TIMER
CLK_APBPERIPHRAL_MISC
CLK_APBPERIPHRAL_MISC2
CLK_APBPERIPHRAL_PMU
CLK_APBPERIPHRAL_RTC
CLK_APBPERIPHRAL_ANA
CLK_APBPERIPHRAL_U32K0
CLK_APBPERIPHRAL_U32K1
NewState:
ENABLE
DISABLE
* @retval None.
*/
void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_CLK_APBPERIPHRAL(Periphral));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
MISC2->PCLKEN |= Periphral;
}
else
{
MISC2->PCLKEN &= ~Periphral;
}
}
/**
* @brief Returns the HCLK frequency
* @param None
* @retval HCLK frequency
*/
uint32_t CLK_GetHCLKFreq(void)
{
uint32_t ahb_clksrc;
uint32_t ahb_div;
uint32_t pllh_frq;
uint32_t plll_frq;
uint32_t rtcclk_div;
uint32_t hclk;
/* Get current AHB clock source */
ahb_clksrc = MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL;
/* Get AHB clock divider */
ahb_div = (MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1;
switch (ahb_clksrc)
{
/* AHB Clock source : 6.5M RC */
case MISC2_CLKSEL_CLKSEL_RCOH:
hclk = 6553600 / ahb_div;
break;
/* AHB Clock source : 6.5M XTAL */
case MISC2_CLKSEL_CLKSEL_XOH:
hclk = 6553600 / ahb_div;
break;
/* AHB Clock source : PLLH */
case MISC2_CLKSEL_CLKSEL_PLLH:
/* Get PLLH Frequency */
pllh_frq = ANA->REG9 & ANA_REG9_PLLHSEL;
switch (pllh_frq)
{
case ANA_REG9_PLLHSEL_X2:
hclk = 13107200 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X2_5:
hclk = 16384000 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X3:
hclk = 19660800 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X3_5:
hclk = 22937600 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X4:
hclk = 26214400 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X4_5:
hclk = 29491200 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X5:
hclk = 32768000 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X5_5:
hclk = 36044800 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X6:
hclk = 39321600 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X6_5:
hclk = 42598400 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X7:
hclk = 45875200 / ahb_div;
break;
case ANA_REG9_PLLHSEL_X7_5:
hclk = 49152000 / ahb_div;
break;
default:
hclk = 0;
break;
}
break;
/* AHB Clock source : RTCCLK */
case MISC2_CLKSEL_CLKSEL_RTCCLK:
/* Get current RTC clock divider */
rtcclk_div = RTC->PSCA & RTC_PSCA_PSCA;
if (rtcclk_div == RTC_PSCA_PSCA_0)
{
hclk = 32768 / ahb_div;
}
else if (rtcclk_div == RTC_PSCA_PSCA_1)
{
hclk = 8192 / ahb_div;
}
else
{
hclk = 0;
}
break;
/* AHB Clock source : PLLL */
case MISC2_CLKSEL_CLKSEL_PLLL:
/* Get PLLL Frequency */
plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL;
switch (plll_frq)
{
case ANA_REG9_PLLLSEL_26M:
hclk = 26214400 / ahb_div;
break;
case ANA_REG9_PLLLSEL_13M:
hclk = 13107200 / ahb_div;
break;
case ANA_REG9_PLLLSEL_6_5M:
hclk = 6553600 / ahb_div;
break;
case ANA_REG9_PLLLSEL_3_2M:
hclk = 3276800 / ahb_div;
break;
case ANA_REG9_PLLLSEL_1_6M:
hclk = 1638400 / ahb_div;
break;
case ANA_REG9_PLLLSEL_800K:
hclk = 819200 / ahb_div;
break;
case ANA_REG9_PLLLSEL_400K:
hclk = 409600 / ahb_div;
break;
case ANA_REG9_PLLLSEL_200K:
hclk = 204800 / ahb_div;
break;
default:
hclk = 0;
break;
}
break;
default:
hclk = 0;
break;
}
return (hclk);
}
/**
* @brief Returns the PCLK frequency
* @param None
* @retval PCLK frequency
*/
uint32_t CLK_GetPCLKFreq(void)
{
return ((CLK_GetHCLKFreq()) / ((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1));
}
/**
* @brief Get the CLK_ClkInitStruct according to the internal
* Clock configuration registers.
*
* @param CLK_ClkInitStruct pointer to an CLK_ClkInitStruct structure that
* contains the current clock configuration.
*
* @retval None
*/
void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct)
{
/* Set all possible values for the Clock type parameter --------------------*/
CLK_ClkInitStruct->ClockType = CLK_TYPE_ALL;
/* Get AHB clock source ----------------------------------------------------*/
CLK_ClkInitStruct->AHBSource = (uint32_t)(MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL);
/* Get PLLL clock configration ---------------------------------------------*/
CLK_ClkInitStruct->PLLL.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLL_SEL);
CLK_ClkInitStruct->PLLL.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLLSEL);
CLK_ClkInitStruct->PLLL.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLLPDN);
/* Get PLLH clock configuration --------------------------------------------*/
CLK_ClkInitStruct->PLLH.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLH_SEL);
CLK_ClkInitStruct->PLLH.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLHSEL);
CLK_ClkInitStruct->PLLH.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLHPDN);
/* Get XTALH configuration -------------------------------------------------*/
CLK_ClkInitStruct->XTALH.State = (uint32_t)(ANA->REG3 & ANA_REG3_XOHPDN);
/* Get HCLK(Divider) configuration -----------------------------------------*/
CLK_ClkInitStruct->HCLK.Divider = (uint32_t)((MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1);
/* Get PCLK((Divider) configuration ----------------------------------------*/
CLK_ClkInitStruct->PCLK.Divider = (uint32_t)((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1);
}
/**
* @brief Get current external 6.5M crystal status.
*
* @param None
*
* @retval 6.5M crystal status
* 0: 6.5536M crystal is absent.
* 1: 6.5536M crystal is present.
*/
uint8_t CLK_GetXTALHStatus(void)
{
if (PMU->STS & PMU_STS_EXIST_6M)
return (1);
else
return (0);
}
/**
* @brief Get current external 32K crystal status.
*
* @param None
*
* @retval 32K crystal status
* 0: 32K crystal is absent
* 1: 32K crystal is present.
*/
uint8_t CLK_GetXTALLStatus(void)
{
if (PMU->STS & PMU_STS_EXIST_32K)
return (1);
else
return (0);
}
/**
* @brief Get PLL lock status.
* @param PLLStatus:
* CLK_STATUS_LOCKL
* CLK_STATUS_LOCKH
* @retval PLL lock status
* 0 PLL is not locked.
* 1 PLL is locked.
*/
uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus)
{
/* Check parameters */
assert_parameters(IS_CLK_PLLLOCK(PLLStatus));
if (ANA->COMPOUT & PLLStatus)
return 1;
else
return 0;
}
/*********************************** END OF FILE ******************************/

337
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/**
******************************************************************************
* @file lib_comp.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief COMP library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_comp.h"
extern __IO uint32_t ana_reg3_tmp;
/**
* @brief Comparator debounce configure.
* @param COMPx:
COMP_1
COMP_2
Debounce:
COMP_DEB_0
COMP_DEB_1
COMP_DEB_2
COMP_DEB_3
* @retval None
*/
void COMP_DEBConfig(uint32_t COMPx, uint32_t Debounce)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_DEB(Debounce));
tmp = ANA->CTRL;
tmp &= ~(ANA_CTRL_CMP1DEB << COMPx);
tmp |= Debounce << COMPx;
ANA->CTRL = tmp;
}
/**
* @brief Comparator mode configure.
* @param COMPx:
COMP_1
COMP_2
Mode:
COMP_MODE_OFF
COMP_MODE_RISING
COMP_MODE_FALLING
COMP_MODE_BOTH
* @retval None
*/
void COMP_ModeConfig(uint32_t COMPx, uint32_t Mode)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_MODE(Mode));
tmp = ANA->CTRL;
tmp &= ~(ANA_CTRL_COMP1_SEL << COMPx);
tmp |= Mode << COMPx;
ANA->CTRL = tmp;
}
/**
* @brief Configure signal source.
* @param COMPx:
* COMP_1
* COMP_2
* SourceSelect:
* COMP_SIGNALSRC_P_TO_REF
* COMP_SIGNALSRC_N_TO_REF
* COMP_SIGNALSRC_P_TO_N
* @retval None
*/
void COMP_SignalSourceConfig(uint32_t COMPx, uint32_t SourceSelect)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_SIGNALSRC(SourceSelect));
tmp = ANA->REG2;
tmp &= ~(ANA_REG2_CMP1_SEL << COMPx);
tmp |= SourceSelect << COMPx;
ANA->REG2 = tmp;
}
/**
* @brief Comparator configure REF selection.
* @param COMPx:
* COMP_1
* COMP_2
* REFSelect:
* COMP_REF_VREF
* COMP_REF_BGPREF
* @retval None
*/
void COMP_REFConfig(uint32_t COMPx, uint32_t REFSelect)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_REF(REFSelect));
tmp = ANA->REG2;
tmp &= ~(ANA_REG2_REFSEL_CMP1 << (COMPx / 2));
tmp |= REFSelect << (COMPx / 2);
ANA->REG2 = tmp;
}
/**
* @brief Comparator configure Bias current selection.
* @param COMPx:
* COMP_1
* COMP_2
* BiasSel:
* COMP_BIAS_20nA
* COMP_BIAS_100nA
* COMP_BIAS_500nA
* @retval None
*/
void COMP_BiasConfig(uint32_t COMPx, uint32_t BiasSel)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_COMP_BIAS(BiasSel));
tmp = ANA->REG5;
tmp &= ~(ANA_REG5_IT_CMP1 << COMPx);
tmp |= BiasSel << COMPx;
ANA->REG5 = tmp;
}
/**
* @brief Get comparator count value.
* @param COMPx:
COMP_1
COMP_2
* @retval Comparator count value.
*/
uint32_t COMP_GetCNTValue(uint32_t COMPx)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
addr = &ANA->CMPCNT1 + (COMPx / 2);
return (*addr);
}
/**
* @brief Clear comparator counter value.
* @param COMPx:
COMP_1
COMP_2
* @retval None
*/
void COMP_ClearCNTValue(uint32_t COMPx)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
addr = &ANA->CMPCNT1 + (COMPx / 2);
*addr = 0;
}
/**
* @brief comparator output enable control.
* @param COMPx:
COMP_1
COMP_2
NewState:
ENABLE
DISABLE
* @retval None
*/
void COMP_Output_Cmd(uint32_t COMPx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
if (COMPx == COMP_1)
GPIOAF->SELE |= IOE_SEL_SEL7;
else
PMU->IOASEL |= PMU_IOASEL_SEL6;
}
else
{
if (COMPx == COMP_1)
GPIOAF->SELE &= ~IOE_SEL_SEL7;
else
PMU->IOASEL &= ~PMU_IOASEL_SEL6;
}
}
/**
* @brief Comparator enable control.
* @param COMPx:
COMP_1
COMP_2
NewState:
ENABLE
DISABLE
* @retval None
*/
void COMP_Cmd(uint32_t COMPx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (COMPx == COMP_1)
{
if (NewState == ENABLE)
ana_reg3_tmp |= ANA_REG3_CMP1PDN;
else
ana_reg3_tmp &= ~ANA_REG3_CMP1PDN;
}
else
{
if (NewState == ENABLE)
ana_reg3_tmp |= ANA_REG3_CMP2PDN;
else
ana_reg3_tmp &= ~ANA_REG3_CMP2PDN;
}
ANA->REG3 = ana_reg3_tmp;
}
/**
* @brief Get comparator 1 output level
* @param None
* @retval None
*/
uint8_t COMP1_GetOutputLevel(void)
{
if (ANA->COMPOUT & ANA_COMPOUT_COMP1)
return 1;
else
return 0;
}
/**
* @brief Get comparator 2 output level
* @param None
* @retval None
*/
uint8_t COMP2_GetOutputLevel(void)
{
if (ANA->COMPOUT & ANA_COMPOUT_COMP2)
return 1;
else
return 0;
}
/**
* @brief Comparator interrupt enable control.
* @param COMPx:
* COMP_1
* COMP_2
* NewState:
* ENABLE
* DISABLE
* @retval None
*/
void COMP_INTConfig(uint32_t COMPx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
if (NewState == ENABLE)
{
ANA->INTEN |= ANA_INTEN_INTEN2 << (COMPx/2);
}
else
{
ANA->INTEN &= ~(ANA_INTEN_INTEN2 << (COMPx/2));
}
}
/**
* @brief Get comparator interrupt flag status.
* @param COMPx:
* COMP_1
* COMP_2
* @retval flag status
* 0: status not set
* 1: status set
*/
uint8_t COMP_GetINTStatus(uint32_t COMPx)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
if (ANA->INTSTS & (ANA_INTSTS_INTSTS2 << (COMPx/2)))
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear comparator interrupt flag.
* @param COMPx:
* COMP_1
* COMP_2
* @retval None
*/
void COMP_ClearINTStatus(uint32_t COMPx)
{
/* Check parameters */
assert_parameters(IS_COMP(COMPx));
ANA->INTSTS = ANA_INTSTS_INTSTS2 << (COMPx/2);
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_crypt.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief CRYPT library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_crypt.h"
/**
* @brief Configure PTRA register, data in this address will be read out to do
* the CRYPT calculation
* @param AddrA: the SRAM address(Bit 14:0)
* @retval None
*/
void CRYPT_AddressAConfig(uint16_t AddrA)
{
/* Check parameters */
assert_parameters(IS_CRYPT_ADDR(AddrA));
CRYPT->PTRA = AddrA & CRYPT_PTRA_PTRA;
}
/**
* @brief Configure PTRB register, data in this address will be read out to do
* the CRYPT calculation
* @param AddrB: the SRAM address(Bit 14:0)
* @retval None
*/
void CRYPT_AddressBConfig(uint16_t AddrB)
{
/* Check parameters */
assert_parameters(IS_CRYPT_ADDR(AddrB));
CRYPT->PTRB = AddrB & CRYPT_PTRB_PTRB;
}
/**
* @brief Configure PTRO register, The CRYPT engine will write calculation
* result into this address
* @param AddrO: the SRAM address(Bit 14:0)
* @retval None
*/
void CRYPT_AddressOConfig(uint16_t AddrO)
{
/* Check parameters */
assert_parameters(IS_CRYPT_ADDR(AddrO));
CRYPT->PTRO = AddrO & CRYPT_PTRO_PTRO;
}
/**
* @brief Get carry/borrow bit of add/sub operation.
* @param None
* @retval carry/borrow bit value
*/
uint8_t CRYPT_GetCarryBorrowBit(void)
{
if (CRYPT->CARRY & CRYPT_CARRY_CARRY)
return (1);
else
return (0);
}
/**
* @brief Start addition operation.
* @param Length:
* CRYPT_LENGTH_32
* CRYPT_LENGTH_64
* CRYPT_LENGTH_96
* CRYPT_LENGTH_128
* CRYPT_LENGTH_160
* CRYPT_LENGTH_192
* CRYPT_LENGTH_224
* CRYPT_LENGTH_256
* CRYPT_LENGTH_288
* CRYPT_LENGTH_320
* CRYPT_LENGTH_352
* CRYPT_LENGTH_384
* CRYPT_LENGTH_416
* CRYPT_LENGTH_448
* CRYPT_LENGTH_480
* CRYPT_LENGTH_512
* Nostop:
* CRYPT_STOPCPU
* CRYPT_NOSTOPCPU
* @retval None
*/
void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop)
{
/* Check parameters */
assert_parameters(IS_CRYPT_LENGTH(Length));
assert_parameters(IS_CRYPT_NOSTOP(Nostop));
CRYPT->CTRL = (Nostop \
|Length \
|CRYPT_CTRL_MODE_ADD \
|CRYPT_CTRL_ACT);
}
/**
* @brief Start multiplication operation.
* @param Length:
* CRYPT_LENGTH_32
* CRYPT_LENGTH_64
* CRYPT_LENGTH_96
* CRYPT_LENGTH_128
* CRYPT_LENGTH_160
* CRYPT_LENGTH_192
* CRYPT_LENGTH_224
* CRYPT_LENGTH_256
* CRYPT_LENGTH_288
* CRYPT_LENGTH_320
* CRYPT_LENGTH_352
* CRYPT_LENGTH_384
* CRYPT_LENGTH_416
* CRYPT_LENGTH_448
* CRYPT_LENGTH_480
* CRYPT_LENGTH_512
* Nostop:
* CRYPT_STOPCPU
* CRYPT_NOSTOPCPU
* @retval None
*/
void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop)
{
/* Check parameters */
assert_parameters(IS_CRYPT_LENGTH(Length));
assert_parameters(IS_CRYPT_NOSTOP(Nostop));
CRYPT->CTRL = (Nostop \
|Length \
|CRYPT_CTRL_MODE_MULTIPLY \
|CRYPT_CTRL_ACT);
}
/**
* @brief Start subtraction operation.
* @param Length:
* CRYPT_LENGTH_32
* CRYPT_LENGTH_64
* CRYPT_LENGTH_96
* CRYPT_LENGTH_128
* CRYPT_LENGTH_160
* CRYPT_LENGTH_192
* CRYPT_LENGTH_224
* CRYPT_LENGTH_256
* CRYPT_LENGTH_288
* CRYPT_LENGTH_320
* CRYPT_LENGTH_352
* CRYPT_LENGTH_384
* CRYPT_LENGTH_416
* CRYPT_LENGTH_448
* CRYPT_LENGTH_480
* CRYPT_LENGTH_512
* Nostop:
* CRYPT_STOPCPU
* CRYPT_NOSTOPCPU
* @retval None
*/
void CRYPT_StartSub(uint32_t Length, uint32_t Nostop)
{
/* Check parameters */
assert_parameters(IS_CRYPT_LENGTH(Length));
assert_parameters(IS_CRYPT_NOSTOP(Nostop));
CRYPT->CTRL = (Nostop \
|Length \
|CRYPT_CTRL_MODE_SUB \
|CRYPT_CTRL_ACT);
}
/**
* @brief Start rigth shift 1-bit operation.
* @param Length:
* CRYPT_LENGTH_32
* CRYPT_LENGTH_64
* CRYPT_LENGTH_96
* CRYPT_LENGTH_128
* CRYPT_LENGTH_160
* CRYPT_LENGTH_192
* CRYPT_LENGTH_224
* CRYPT_LENGTH_256
* CRYPT_LENGTH_288
* CRYPT_LENGTH_320
* CRYPT_LENGTH_352
* CRYPT_LENGTH_384
* CRYPT_LENGTH_416
* CRYPT_LENGTH_448
* CRYPT_LENGTH_480
* CRYPT_LENGTH_512
* Nostop:
* CRYPT_STOPCPU
* CRYPT_NOSTOPCPU
* @retval None
*/
void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop)
{
/* Check parameters */
assert_parameters(IS_CRYPT_LENGTH(Length));
assert_parameters(IS_CRYPT_NOSTOP(Nostop));
CRYPT->CTRL = (Nostop \
|Length \
|CRYPT_CTRL_MODE_RSHIFT1 \
|CRYPT_CTRL_ACT);
}
/**
* @brief Waiting for last operation to complete.
* @param None
* @retval None
*/
void CRYPT_WaitForLastOperation(void)
{
while (CRYPT->CTRL & CRYPT_CTRL_ACT)
{
}
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_dma.c
* @author Application Team
* @version V4.4.0
* @date 22018-09-27
* @brief DMA library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_dma.h"
//registers default reset values
#define DMA_CxCTL_RSTValue (0UL)
#define DMA_CxSRC_RSTValue (0UL)
#define DMA_CxDST_RSTValue (0UL)
#define DMA_AESCTL_RSTValue (0UL)
#define DMA_AESKEY_RSTValue (0UL)
/**
* @brief Initializes the DMA Cx peripheral registers to their default reset values.
* @param Channel: DMA_CHANNEL_0~DMA_CHANNEL_3
* @retval None
*/
void DMA_DeInit(uint32_t Channel)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
/* channel x disable, clear stop */
addr = &DMA->C0CTL + Channel*4;
*addr &= ~(DMA_CxCTL_EN | DMA_CTL_STOP);
/* interrupt disable */
DMA->IE &= ~((1<<(Channel))\
|(1<<(Channel+4))\
|(1<<(Channel+8)));
/* interrupt state clear */
DMA->STS = (1<<(Channel+4))\
|(1<<(Channel+8))\
|(1<<(Channel+12));
/* DMA_CxCTL */
addr = &DMA->C0CTL + Channel*4;
*addr = DMA_CxCTL_RSTValue;
/* DMA_CxSRC */
addr = &DMA->C0SRC + Channel*4;
*addr = DMA_CxSRC_RSTValue;
/* DMA_CxDST */
addr = &DMA->C0DST + Channel*4;
*addr = DMA_CxDST_RSTValue;
}
/**
* @brief DMA channel x initialization.
* @param InitStruct: DMA configuration.
DestAddr : destination address
SrcAddr : source address
FrameLen : Frame length (Ranges 0~255, actual length FrameLen+1)
PackLen : Package length (Ranges 0~255, actual length PackLen+1)
ContMode:
DMA_CONTMODE_ENABLE
DMA_CONTMODE_DISABLE
TransMode:
DMA_TRANSMODE_SINGLE
DMA_TRANSMODE_PACK
ReqSrc:
DMA_REQSRC_SOFT
DMA_REQSRC_UART0TX
DMA_REQSRC_UART0RX
DMA_REQSRC_UART1TX
DMA_REQSRC_UART1RX
DMA_REQSRC_UART2TX
DMA_REQSRC_UART2RX
DMA_REQSRC_UART3TX
DMA_REQSRC_UART3RX
DMA_REQSRC_UART4TX
DMA_REQSRC_UART4RX
DMA_REQSRC_UART5TX
DMA_REQSRC_UART5RX
DMA_REQSRC_ISO78160TX
DMA_REQSRC_ISO78160RX
DMA_REQSRC_ISO78161TX
DMA_REQSRC_ISO78161RX
DMA_REQSRC_TIMER0
DMA_REQSRC_TIMER1
DMA_REQSRC_TIMER2
DMA_REQSRC_TIMER3
DMA_REQSRC_SPI1TX
DMA_REQSRC_SPI1RX
DMA_REQSRC_U32K0
DMA_REQSRC_U32K1
DMA_REQSRC_CMP1
DMA_REQSRC_CMP2
DMA_REQSRC_SPI2TX
DMA_REQSRC_SPI2RX
DestAddrMode:
DMA_DESTADDRMODE_FIX
DMA_DESTADDRMODE_PEND
DMA_DESTADDRMODE_FEND
SrcAddrMode:
DMA_SRCADDRMODE_FIX
DMA_SRCADDRMODE_PEND
DMA_SRCADDRMODE_FEND
TransSize:
DMA_TRANSSIZE_BYTE
DMA_TRANSSIZE_HWORD
DMA_TRANSSIZE_WORD
Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
* @retval None
*/
void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel)
{
uint32_t tmp;
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
assert_parameters(IS_DMA_CONTMOD(InitStruct->ContMode));
assert_parameters(IS_DMA_TRANSMOD(InitStruct->TransMode));
assert_parameters(IS_DMA_REQSRC(InitStruct->ReqSrc));
assert_parameters(IS_DMA_DESTADDRMOD(InitStruct->DestAddrMode));
assert_parameters(IS_DMA_SRCADDRMOD(InitStruct->SrcAddrMode));
assert_parameters(IS_DMA_TRANSSIZE(InitStruct->TransSize));
if (InitStruct->TransSize == DMA_TRANSSIZE_HWORD)
{
assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->SrcAddr));
assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->DestAddr));
}
if (InitStruct->TransSize == DMA_TRANSSIZE_WORD)
{
assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->SrcAddr));
assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->DestAddr));
}
addr = &DMA->C0DST + Channel*4;
*addr = InitStruct->DestAddr;
addr = &DMA->C0SRC + Channel*4;
*addr = InitStruct->SrcAddr;
addr = &DMA->C0CTL + Channel*4;
tmp = *addr;
tmp &= ~(DMA_CTL_FLEN\
|DMA_CTL_PLEN\
|DMA_CTL_CONT\
|DMA_CTL_TMODE\
|DMA_CTL_DMASEL\
|DMA_CxCTL_DMODE\
|DMA_CxCTL_SMODE\
|DMA_CxCTL_SIZE);
tmp |= ((InitStruct->FrameLen<<DMA_CTL_FLEN_Pos)\
|(InitStruct->PackLen<<DMA_CTL_PLEN_Pos)\
|(InitStruct->ContMode)\
|(InitStruct->TransMode)\
|(InitStruct->ReqSrc)\
|(InitStruct->DestAddrMode)\
|(InitStruct->SrcAddrMode)\
|(InitStruct->TransSize));
*addr = tmp;
}
/**
* @brief Initializes the DMA AES channel3 registers to their default reset values.
* @param None
* @retval None
*/
void DMA_AESDeInit(void)
{
DMA->AESCTL = DMA_AESCTL_RSTValue;
DMA->AESKEY0 = DMA_AESKEY_RSTValue;
DMA->AESKEY1 = DMA_AESKEY_RSTValue;
DMA->AESKEY2 = DMA_AESKEY_RSTValue;
DMA->AESKEY3 = DMA_AESKEY_RSTValue;
DMA->AESKEY4 = DMA_AESKEY_RSTValue;
DMA->AESKEY5 = DMA_AESKEY_RSTValue;
DMA->AESKEY6 = DMA_AESKEY_RSTValue;
DMA->AESKEY7 = DMA_AESKEY_RSTValue;
}
/**
* @brief AES initialization.
* @param InitStruct: AES configuration.
Mode:
DMA_AESMODE_128
DMA_AESMODE_192
DMA_AESMODE_256
Direction:
DMA_AESDIRECTION_ENCODE
DMA_AESDIRECTION_DECODE
KeyStr: the pointer to DMA_AESKEYx register
* @retval None
*/
void DMA_AESInit(DMA_AESInitType *InitStruct)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_DMA_AESMOD(InitStruct->Mode));
assert_parameters(IS_DMA_AESDIR(InitStruct->Direction));
tmp = DMA->AESCTL;
tmp &= ~(DMA_AESCTL_MODE\
|DMA_AESCTL_ENC);
tmp |= (InitStruct->Mode\
|InitStruct->Direction);
DMA->AESCTL = tmp;
DMA->AESKEY0 = InitStruct->KeyStr[0];
DMA->AESKEY1 = InitStruct->KeyStr[1];
DMA->AESKEY2 = InitStruct->KeyStr[2];
DMA->AESKEY3 = InitStruct->KeyStr[3];
if ((InitStruct->Mode == DMA_AESMODE_192) ||\
(InitStruct->Mode == DMA_AESMODE_256))
{
DMA->AESKEY4 = InitStruct->KeyStr[4];
DMA->AESKEY5 = InitStruct->KeyStr[5];
}
if (InitStruct->Mode == DMA_AESMODE_256)
{
DMA->AESKEY6 = InitStruct->KeyStr[6];
DMA->AESKEY7 = InitStruct->KeyStr[7];
}
}
/**
* @brief Interrupt configure.
* @param INTMask: can use the ¡®|¡¯ operator
DMA_INT_C3DA
DMA_INT_C2DA
DMA_INT_C1DA
DMA_INT_C0DA
DMA_INT_C3FE
DMA_INT_C2FE
DMA_INT_C1FE
DMA_INT_C0FE
DMA_INT_C3PE
DMA_INT_C2PE
DMA_INT_C1PE
DMA_INT_C0PE
NewState:
ENABLE
DISABLE
* @retval None
*/
void DMA_INTConfig(uint32_t INTMask, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_DMA_INT(INTMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
DMA->IE |= INTMask;
else
DMA->IE &= ~INTMask;
}
/**
* @brief Get interrupt status.
* @param INTMask:
DMA_INTSTS_C3DA
DMA_INTSTS_C2DA
DMA_INTSTS_C1DA
DMA_INTSTS_C0DA
DMA_INTSTS_C3FE
DMA_INTSTS_C2FE
DMA_INTSTS_C1FE
DMA_INTSTS_C0FE
DMA_INTSTS_C3PE
DMA_INTSTS_C2PE
DMA_INTSTS_C1PE
DMA_INTSTS_C0PE
DMA_INTSTS_C3BUSY
DMA_INTSTS_C2BUSY
DMA_INTSTS_C1BUSY
DMA_INTSTS_C0BUSY
* @retval interrupt status.
*/
uint8_t DMA_GetINTStatus(uint32_t INTMask)
{
/* Check parameters */
assert_parameters(IS_DMA_INTFLAGR(INTMask));
if (DMA->STS&INTMask)
return 1;
else
return 0;
}
/**
* @brief Clear interrupt status.
* @param INTMask: can use the ¡®|¡¯ operator
DMA_INTSTS_C3DA
DMA_INTSTS_C2DA
DMA_INTSTS_C1DA
DMA_INTSTS_C0DA
DMA_INTSTS_C3FE
DMA_INTSTS_C2FE
DMA_INTSTS_C1FE
DMA_INTSTS_C0FE
DMA_INTSTS_C3PE
DMA_INTSTS_C2PE
DMA_INTSTS_C1PE
DMA_INTSTS_C0PE
* @retval None
*/
void DMA_ClearINTStatus(uint32_t INTMask)
{
/* Check parameters */
assert_parameters(IS_DMA_INTFLAGC(INTMask));
DMA->STS = INTMask;
}
/**
* @brief DMA channel enable.
* @param Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
NewState:
ENABLE
DISABLE
* @retval None
*/
void DMA_Cmd(uint32_t Channel, uint32_t NewState)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
addr = &DMA->C0CTL + Channel*4;
if (NewState == ENABLE)
*addr |= DMA_CxCTL_EN;
else
*addr &= ~DMA_CxCTL_EN;
}
/**
* @brief Enable AES encrypt/decrypt function of DMA channel3.
* @param NewState:
ENABLE
DISABLE
* @retval None
*/
void DMA_AESCmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
DMA->C3CTL |= DMA_CTL_AESEN;
else
DMA->C3CTL &= ~DMA_CTL_AESEN;
}
/**
* @brief DMA stop transmit.
* @param Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
NewState:
ENABLE
DISABLE
* @retval None
*/
void DMA_StopTransmit(uint32_t Channel, uint32_t NewState)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
addr = &DMA->C0CTL + Channel*4;
if (NewState == ENABLE)
*addr |= DMA_CTL_STOP;
else
*addr &= ~DMA_CTL_STOP;
}
/**
* @brief Get current frame transferred length.
* @param Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
* @retval Current frame transferred length.
*/
uint8_t DMA_GetFrameLenTransferred(uint32_t Channel)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
addr = &DMA->C0LEN + Channel*4;
return ((*addr&0xFF00)>>8);
}
/**
* @brief Get current package transferred length.
* @param Channel:
DMA_CHANNEL_0
DMA_CHANNEL_1
DMA_CHANNEL_2
DMA_CHANNEL_3
* @retval Current package transferred length.
*/
uint8_t DMA_GetPackLenTransferred(uint32_t Channel)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_DMA_CHANNEL(Channel));
addr = &DMA->C0LEN + Channel*4;
return (*addr&0xFF);
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_flash.c
* @author Application Team
* @version V4.3.0
* @date 2018-09-27
* @brief FLASH library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_flash.h"
#include "lib_clk.h"
/* FLASH Keys */
#define FLASH_PASS_KEY 0x55AAAA55
#define FLASH_SERASE_KEY 0xAA5555AA
#define FLASH_CERASE_KEY 0xAA5555AA
#define FLASH_DSTB_KEY 0xAA5555AA
#define FLASH_MODE_MASK 0x1F3
/**
* @brief FLASH mode initialization.
* @param CSMode:
FLASH_CSMODE_DISABLE
FLASH_CSMODE_ALWAYSON
FLASH_CSMODE_TIM2OF
FLASH_CSMODE_RTC
* @retval None
*/
void FLASH_Init(uint32_t CSMode)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_FLASH_CSMODE(CSMode));
tmp = FLASH->CTRL;
tmp &= ~FLASH_MODE_MASK;
tmp |= CSMode;
FLASH->CTRL = tmp;
}
/**
* @brief Configure FLASH interrupt.
* @param IntMask:
FLASH_INT_CS
NewState:
ENABLE
DISABLE
* @retval None
*/
void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_FLASH_INT(IntMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = FLASH->CTRL;
tmp &= ~IntMask;
if (NewState == ENABLE)
{
tmp |= IntMask;
}
FLASH->CTRL = tmp;
}
/**
* @brief Init FLASH 1USCYCLE.
* @param None
* @retval None
*/
void FLASH_CycleInit(void)
{
uint32_t hclk;
hclk = CLK_GetHCLKFreq();
if (hclk > 1000000)
MISC2->FLASHWC = (hclk/1000000)<<8;
else
MISC2->FLASHWC = 0;
}
/**
* @brief Erase FLASH sector.
* @param SectorAddr: sector address.
* @retval None
*/
void FLASH_SectorErase(uint32_t SectorAddr)
{
/* Check parameters */
assert_parameters(IS_FLASH_ADDRESS(SectorAddr));
/* Unlock flash */
FLASH->PASS = FLASH_PASS_KEY;
FLASH->PGADDR = SectorAddr;
FLASH->SERASE = FLASH_SERASE_KEY;
while (FLASH->SERASE != 0);
/* Lock flash */
FLASH->PASS = 0;
}
/**
* @brief FLASH word program.
* @param Addr: program start address
WordBuffer: word's buffer pointer to write
Length: The length of WordBuffer
* @retval None
*/
void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length)
{
uint32_t i;
/* Check parameters */
assert_parameters(IS_FLASH_ADRRW(Addr));
/* Unlock flash */
FLASH->PASS = FLASH_PASS_KEY;
FLASH->PGADDR = Addr;
for (i=0; i<Length; i++)
{
FLASH->PGDATA = *(WordBuffer++);
}
while (FLASH->STS != 1);
/* Lock flash */
FLASH->PASS = 0;
}
/**
* @brief FLASH half-word progarm.
* @param Addr: program start address
HWordBuffer: half-word's buffer pointer to write
Length: The length of HWordBuffer
* @retval None
*/
void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length)
{
uint32_t i;
/* Check parameters */
assert_parameters(IS_FLASH_ADRRHW(Addr));
/* Unlock flash */
FLASH->PASS = FLASH_PASS_KEY;
FLASH->PGADDR = Addr;
for (i=0; i<Length; i++)
{
if (((Addr + 2*i)&0x3) == 0)
*((__IO uint16_t*)(&FLASH->PGDATA)) = *(HWordBuffer++);
else
*((__IO uint16_t*)(&FLASH->PGDATA ) + 1) = *(HWordBuffer++);
}
while (FLASH->STS != 1);
/* Lock flash */
FLASH->PASS = 0;
}
/**
* @brief FLASH byte progarm.
* @param Addr: program start address
ByteBuffer: byte's buffer pointer to write
Length: The length of ByteBuffer
* @retval None
*/
void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length)
{
uint32_t i;
/* Check parameters */
assert_parameters(IS_FLASH_ADDRESS(Addr));
/* Unlock flash */
FLASH->PASS = FLASH_PASS_KEY;
FLASH->PGADDR = Addr;
for (i=0; i<Length; i++)
{
if (((Addr + i)&0x3) == 0)
*((__IO uint8_t*)(&FLASH->PGDATA)) = *(ByteBuffer++);
else if (((Addr + i)&0x3) == 1)
*((__IO uint8_t*)(&FLASH->PGDATA) + 1) = *(ByteBuffer++);
else if (((Addr + i)&0x3) == 2)
*((__IO uint8_t*)(&FLASH->PGDATA) + 2) = *(ByteBuffer++);
else
*((__IO uint8_t*)(&FLASH->PGDATA) + 3) = *(ByteBuffer++);
}
while (FLASH->STS != 1);
/* Lock flash */
FLASH->PASS = 0;
}
/**
* @brief Get Write status.
* @param None.
* @retval FLASH_WSTA_BUSY
FLASH_WSTA_FINISH
*/
uint32_t FLASH_GetWriteStatus(void)
{
if (FLASH->STS == 1)
{
return FLASH_WSTA_FINISH;
}
else
{
return FLASH_WSTA_BUSY;
}
}
/**
* @brief Set checksum range.
* @param AddrStart: checksum start address
AddrEnd: checksum end address
* @retval None
*/
void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd)
{
/* Check parameters */
assert_parameters(IS_FLASH_CHECKSUMADDR(AddrStart,AddrEnd));
FLASH->CSSADDR = AddrStart;
FLASH->CSEADDR = AddrEnd;
}
/**
* @brief Set checksum compare value.
* @param Checksum: checksum compare value
* @retval None
*/
void FLASH_SetCheckSumCompValue(uint32_t Checksum)
{
FLASH->CSCVALUE = Checksum;
}
/**
* @brief Get FLASH checksum value.
* @param None
* @retval Checksum
*/
uint32_t FLASH_GetCheckSum(void)
{
return FLASH->CSVALUE;
}
/**
* @brief Get FLASH interrupt status.
* @param IntMask:
FLASH_INT_CS
* @retval 1: interrupt status set
0: interrupt status reset
*/
uint8_t FLASH_GetINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_FLASH_INT(IntMask));
if (FLASH->INT&FLASH_INT_CSERR)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear FLASH interrupt status.
* @param IntMask:
FLASH_INT_CS
* @retval None
*/
void FLASH_ClearINTStatus(uint32_t IntMask)
{
/* Check parameters */
assert_parameters(IS_FLASH_INT(IntMask));
if (IntMask == FLASH_INT_CS)
{
FLASH->INT = FLASH_INT_CSERR;
}
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_gpio.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief GPIO library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_gpio.h"
/**
* @brief GPIO initialization.
* @param GPIOx: GPIOB~GPIOF
InitStruct:GPIO configuration.
GPIO_Pin: can use the ¡®|¡¯ operator
GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All
GPIO_Mode:
GPIO_Mode_INPUT
GPIO_Mode_OUTPUT_CMOS
GPIO_Mode_OUTPUT_OD
GPIO_Mode_INOUT_OD
GPIO_Mode_INOUT_CMOS
GPIO_Mode_FORBIDDEN
* @retval None
*/
void GPIOBToF_Init(GPIO_TypeDef *GPIOx, GPIO_InitType *InitStruct)
{
uint32_t tmp_reg1, tmp_reg2;
/* Check parameters */
assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin));
assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode));
if (GPIOF == GPIOx)
InitStruct->GPIO_Pin &= ~(GPIO_Pin_2);
/* Configure ATT */
if (InitStruct->GPIO_Mode & 0x2U)
{
tmp_reg1 = GPIOx->ATT;
tmp_reg1 &= ~InitStruct->GPIO_Pin;
if (InitStruct->GPIO_Mode & 0x1U)
{
tmp_reg1 |= InitStruct->GPIO_Pin;
}
GPIOx->ATT = tmp_reg1;
}
/* Configure output/input mode */
tmp_reg1 = GPIOx->OEN;
tmp_reg1 &= ~InitStruct->GPIO_Pin;
tmp_reg2 = GPIOx->IE;
tmp_reg2 &= ~InitStruct->GPIO_Pin;
if (InitStruct->GPIO_Mode & 0x8U)
{
tmp_reg2 |= InitStruct->GPIO_Pin;
}
if (InitStruct->GPIO_Mode & 0x4U)
{
tmp_reg1 |= InitStruct->GPIO_Pin;
}
GPIOx->OEN = tmp_reg1;
GPIOx->IE = tmp_reg2;
}
/**
* @brief GPIOA initialization.
* @param GPIOx: GPIOA
InitStruct:GPIO configuration.
GPIO_Pin: can use the ¡®|¡¯ operator
GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All
GPIO_Mode:
GPIO_Mode_INPUT
GPIO_Mode_OUTPUT_CMOS
GPIO_Mode_OUTPUT_OD
GPIO_Mode_INOUT_OD
GPIO_Mode_FORBIDDEN
* @retval None
*/
void GPIOA_Init(GPIOA_TypeDef *GPIOx, GPIO_InitType *InitStruct)
{
uint32_t tmp_reg1, tmp_reg2;
/* Check parameters */
assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin));
assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode));
/* Configure ATT */
if (InitStruct->GPIO_Mode & 0x2U)
{
tmp_reg1 = GPIOx->ATT;
tmp_reg1 &= ~InitStruct->GPIO_Pin;
if (InitStruct->GPIO_Mode & 0x1U)
{
tmp_reg1 |= InitStruct->GPIO_Pin;
}
GPIOx->ATT = tmp_reg1;
}
/* Configure output/input mode */
tmp_reg1 = GPIOx->OEN;
tmp_reg1 &= ~InitStruct->GPIO_Pin;
tmp_reg2 = GPIOx->IE;
tmp_reg2 &= ~InitStruct->GPIO_Pin;
if (InitStruct->GPIO_Mode & 0x8U)
{
tmp_reg2 |= InitStruct->GPIO_Pin;
}
if (InitStruct->GPIO_Mode & 0x4U)
{
tmp_reg1 |= InitStruct->GPIO_Pin;
}
GPIOx->OEN = tmp_reg1;
GPIOx->IE = tmp_reg2;
}
/**
* @brief Read input data register bit.
* @param GPIOx: GPIOB~GPIOF
GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15.
* @retval input pin value.
*/
uint8_t GPIOBToF_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PINR(GPIO_Pin));
tmp = GPIOx->STS;
tmp &= GPIO_Pin;
if (tmp)
return 1;
else
return 0;
}
/**
* @brief Read input data register bit.
* @param GPIOx: GPIOA
GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15.
* @retval input pin value.
*/
uint8_t GPIOA_ReadInputDataBit(GPIOA_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PINR(GPIO_Pin));
tmp = GPIOx->STS;
tmp &= GPIO_Pin;
if (tmp)
return 1;
else
return 0;
}
/**
* @brief Read input data register.
* @param GPIOx: GPIOB~GPIOF
* @retval input port value.
*/
uint16_t GPIOBToF_ReadInputData(GPIO_TypeDef* GPIOx)
{
/* Check parameters */
assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
return GPIOx->STS;
}
/**
* @brief Read input data register.
* @param GPIOx: GPIOA
* @retval input port value.
*/
uint16_t GPIOA_ReadInputData(GPIOA_TypeDef* GPIOx)
{
/* Check parameters */
assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
return GPIOx->STS;
}
/**
* @brief Read output data register bit.
* @param GPIOx: GPIOB~GPIOF
GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15
* @retval output pin value.
*/
uint8_t GPIOBToF_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PINR(GPIO_Pin));
tmp = GPIOx->DAT;
tmp &= GPIO_Pin;
if (tmp)
return 1;
else
return 0;
}
/**
* @brief Read output data register bit.
* @param GPIOx: GPIOA
GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15
* @retval output pin value.
*/
uint8_t GPIOA_ReadOutputDataBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PINR(GPIO_Pin));
tmp = GPIOx->DAT;
tmp &= GPIO_Pin;
if (tmp)
return 1;
else
return 0;
}
/**
* @brief Read output data register.
* @param GPIOx: GPIOB~GPIOF
* @retval Output port value.
*/
uint16_t GPIOBToF_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check parameters */
assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
return GPIOx->DAT;
}
/**
* @brief Read output data register.
* @param GPIOx: GPIOA
* @retval Output port value.
*/
uint16_t GPIOA_ReadOutputData(GPIOA_TypeDef* GPIOx)
{
/* Check parameters */
assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
return GPIOx->DAT;
}
/**
* @brief Set output data register bit.
* @param GPIOx: GPIOB~GPIOF
GPIO_Pin: can use the ¡®|¡¯ operator
GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All
* @retval None.
*/
void GPIOBToF_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check parameters */
assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PIN(GPIO_Pin));
GPIOx->DAT |= GPIO_Pin;
}
/**
* @brief Set output data register bit.
* @param GPIOx: GPIOA
GPIO_Pin: can use the ¡®|¡¯ operator
GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All
* @retval None.
*/
void GPIOA_SetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check parameters */
assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PIN(GPIO_Pin));
GPIOx->DAT |= GPIO_Pin;
}
/**
* @brief Reset output data register bit.
* @param GPIOx: GPIOB~GPIOF
GPIO_Pin: can use the ¡®|¡¯ operator
GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All
* @retval None.
*/
void GPIOBToF_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check parameters */
assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PIN(GPIO_Pin));
GPIOx->DAT &= ~GPIO_Pin;
}
/**
* @brief Reset output data register bit.
* @param GPIOx: GPIOA
GPIO_Pin: can use the ¡®|¡¯ operator
GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All
* @retval None.
*/
void GPIOA_ResetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check parameters */
assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PIN(GPIO_Pin));
GPIOx->DAT &= ~GPIO_Pin;
}
/**
* @brief Write output data register bit.
* @param GPIOx: GPIOB~GPIOF
GPIO_Pin: can use the ¡®|¡¯ operator
GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All
val:value write to register bit.
* @retval None.
*/
void GPIOBToF_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val)
{
/* Check parameters */
assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PIN(GPIO_Pin));
assert_parameters(IS_GPIO_BITVAL(val));
if (val == 1)
{
GPIOx->DAT |= GPIO_Pin;
}
else
{
GPIOx->DAT &= ~GPIO_Pin;
}
}
/**
* @brief Write output data register bit.
* @param GPIOx: GPIOA
GPIO_Pin: can use the ¡®|¡¯ operator
GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All
val:value write to register bit.
* @retval None.
*/
void GPIOA_WriteBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val)
{
/* Check parameters */
assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_PIN(GPIO_Pin));
assert_parameters(IS_GPIO_BITVAL(val));
if (val == 1)
{
GPIOx->DAT |= GPIO_Pin;
}
else
{
GPIOx->DAT &= ~GPIO_Pin;
}
}
/**
* @brief Write output data register.
* @param GPIOx: GPIOB~GPIOF
val:value write to register.
* @retval None.
*/
void GPIOBToF_Write(GPIO_TypeDef* GPIOx, uint16_t val)
{
/* Check parameters */
assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx));
GPIOx->DAT = val;
}
/**
* @brief Write output data register.
* @param GPIOx: GPIOA
val:value write to register.
* @retval None.
*/
void GPIOA_Write(GPIOA_TypeDef* GPIOx, uint16_t val)
{
/* Check parameters */
assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx));
GPIOx->DAT = val;
}
/**
* @brief GPIO AF configure.
* @param GPIOx:GPIOB GPIOE
GPIO_AFx:
GPIOB_AF_PLLHDIV
GPIOB_AF_OSC
GPIOB_AF_PLLLOUT
GPIOE_AF_CMP1O
NewState:
ENABLE
DISABLE
* @retval None.
*/
void GPIOBToF_AFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_AFx, uint8_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_GPIOAF_ALL_INSTANCE(GPIOx));
assert_parameters(IS_GPIO_GPIOAF(GPIO_AFx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (GPIOx == GPIOB)
{
tmp = GPIOAF->SELB;
if (NewState != DISABLE)
{
tmp |= GPIO_AFx;
}
else
{
tmp &= ~GPIO_AFx;
}
GPIOAF->SELB = tmp;
}
if (GPIOx == GPIOE)
{
tmp = GPIOAF->SELE;
if (NewState != DISABLE)
{
tmp |= GPIO_AFx;
}
else
{
tmp &= ~GPIO_AFx;
}
GPIOAF->SELE = tmp;
}
}
/**
* @brief GPIO AF configure.
* @param PMUIO_AFx:
PMUIO7_AF_PLLDIV
PMUIO_AF_CMP2O
PMUIO3_AF_PLLDIV
NewState:
ENABLE
DISABLE
* @retval None.
*/
void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState)
{
/* Check parameters */
assert_parameters(IS_GPIO_PMUIOAF(PMUIO_AFx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
GPIOA->SEL |= PMUIO_AFx;
}
else
{
GPIOA->SEL &= ~PMUIO_AFx;
}
}
/**
* @brief GPIO pin remap.
* @param GPIO_Remap:
GPIO_REMAP_I2C
NewState:
ENABLE
DISABLE
* @retval None.
*/
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_GPIO_REMAP(GPIO_Remap));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = GPIOAF->_MISC;
tmp &= ~GPIO_Remap;
if (NewState == ENABLE)
tmp |= GPIO_Remap;
GPIOAF->_MISC = tmp;
}
/**
* @brief GPIO PLLDIV configure.
* @param Divider:
GPIO_PLLDIV_1
GPIO_PLLDIV_2
GPIO_PLLDIV_4
GPIO_PLLDIV_8
GPIO_PLLDIV_16
* @retval None.
*/
void GPIO_PLLDIV_Config(uint32_t Divider)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_GPIO_PLLDIV(Divider));
tmp = GPIOAF->_MISC;
tmp &= ~IO_MISC_PLLHDIV;
tmp |= Divider;
GPIOAF->_MISC = tmp;
}
/**
* @brief GPIOA de-glitch circuit control.
* @param GPIO_Pin: can use the ¡®|¡¯ operator
GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All
NewState:
ENABLE
DISABLE
* @retval None.
*/
void GPIOA_NoDeg_Cmd( uint16_t GPIO_Pin, uint8_t NewState)
{
uint16_t tmp;
/* Check parameters */
assert_parameters(IS_GPIO_PIN(GPIO_Pin));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = GPIOA->IOANODEG;
/*IOA wake-up signal will not go through de-glitch circuit.*/
if (NewState != DISABLE)
{
tmp |= GPIO_Pin;
}
/*IOA wake-up signal will go through de-glitch circuit.*/
else
{
tmp &= ~GPIO_Pin;
}
GPIOA->IOANODEG = tmp;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_i2c.c
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief IIC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_i2c.h"
//registers default reset values
#define I2C_ADDR_RSTValue 0
#define I2C_CTRL_RSTValue 0
#define I2C_CTRL2_RSTValue 0
/* Private Functions -------------------------------------------------------- */
static uint16_t I2C_CheckState(uint8_t State);
static void I2C_SendStart(void);
static void I2C_SendRestart(void);
static void I2C_SendByte(uint8_t dat);
static void I2C_SendStop(void);
static uint8_t I2C_ReceiveByte(void);
static void I2C_ClearBus(uint32_t remap);
static void I2C_WaitForCrossPage(uint8_t sla);
/**
* @brief Check required state.
* @param State:
Required state.
* @retval 0: state OK
!0: state Error, [15:8]Required status code, [7:0] real status code.
*/
static uint16_t I2C_CheckState(uint8_t State)
{
uint16_t ret;
if (I2C_GetStatusCode() != State)
{
ret = (State<<8)|(I2C_GetStatusCode());
return ret;
}
else
{
return 0;
}
}
/**
* @brief Send start signal.
* @param None
* @retval None
*/
static void I2C_SendStart(void)
{
I2C_GenerateSTART(ENABLE);
while (I2C_GetINTStatus() == 0);
I2C_GenerateSTART(DISABLE);
}
/**
* @brief Send restart signal.
* @param None
* @retval None
*/
static void I2C_SendRestart(void)
{
I2C_GenerateSTART(ENABLE);
I2C_ClearINTStatus();
while (I2C_GetINTStatus() == 0);
I2C_GenerateSTART(DISABLE);
}
/**
* @brief Send stop signal.
* @param None
* @retval None
*/
static void I2C_SendStop(void)
{
I2C_GenerateSTOP(ENABLE);
I2C_ClearINTStatus();
I2C_GenerateSTOP(DISABLE);
}
/**
* @brief Send data.
* @param dat:data to send.
* @retval None
*/
static void I2C_SendByte(uint8_t dat)
{
I2C_SendData(dat);
I2C_ClearINTStatus();
while (I2C_GetINTStatus() == 0);
}
/**
* @brief Receive byte.
* @param None
* @retval Byte received
*/
static uint8_t I2C_ReceiveByte(void)
{
I2C_ClearINTStatus();
while (I2C_GetINTStatus() == 0);
return I2C_ReceiveData();
}
/**
* @brief Wait for cross page operation done.
* @param None
* @retval None
*/
static void I2C_WaitForCrossPage(uint8_t sla)
{
do
{
I2C_SendRestart();
I2C_SendByte(sla); //device address
}while (I2C_GetStatusCode() !=0x18);
I2C_SendStop(); //stop
}
static void I2C_ClearBus(uint32_t remap)
{
__IO uint8_t i, j;
if (remap) // I2C remap enable, SCL IOC4
{
GPIOC->DAT &= ~BIT4;
GPIOC->ATT |= BIT4;
GPIOC->OEN &= ~BIT4;
for (i=0; i<9; i++)
{
GPIOC->DAT |= BIT4;
for (j=0; j<100; j++)
__NOP();
GPIOC->DAT &= ~BIT4;
for (j=0; j<100; j++)
__NOP();
}
GPIOC->DAT |= BIT4;
GPIOC->OEN |= BIT4;
GPIOC->IE &= ~BIT4;
}
else // I2C remap disable, SCL IOB13
{
GPIOB->DAT &= ~BIT13;
GPIOB->ATT |= BIT13;
GPIOB->OEN &= ~BIT13;
for (i=0; i<9; i++)
{
GPIOB->DAT |= BIT13;
for (j=0; j<100; j++)
__NOP();
GPIOB->DAT &= ~BIT13;
for (j=0; j<100; j++)
__NOP();
}
GPIOB->DAT |= BIT13;
GPIOB->OEN |= BIT13;
GPIOB->IE &= ~BIT13;
}
}
/* Exported Functions ------------------------------------------------------- */
/**
* @brief Initializes the I2C peripheral registers to their default reset values.
* @param remap: I2C_REMAP_ENABLE or I2C_REMAP_DISABLE
* @retval None
*/
void I2C_DeInit(uint32_t remap)
{
I2C->CTRL &= ~I2C_CTRL_EN;
I2C->ADDR = I2C_ADDR_RSTValue;
I2C->CTRL = I2C_CTRL_RSTValue;
I2C->CTRL2 = I2C_CTRL2_RSTValue;
I2C_ClearBus(remap);
}
/**
* @brief Fills each InitStruct member with its default value.
* @param InitStruct: pointer to an I2C_InitType structure which will be initialized.
* @retval None
*/
void I2C_StructInit(I2C_InitType *InitStruct)
{
/*--------------- Reset I2C init structure parameters values ---------------*/
/* Initialize the AssertAcknowledge member */
InitStruct->AssertAcknowledge = I2C_ASSERTACKNOWLEDGE_DISABLE;
/* Initialize the ClockSource member */
InitStruct->ClockSource = I2C_CLOCKSOURCE_APBD256;
/* Initialize the GeneralCallAck member */
InitStruct->GeneralCallAck = I2C_GENERALCALLACK_DISABLE;
/* Initialize the SlaveAddr member */
InitStruct->SlaveAddr = 0;
}
/**
* @brief I2C initialization.
* @param InitStruct: I2C configuration.
SlaveAddr: Own I2C slave address (7 bit)
GeneralCallAck:
I2C_GENERALCALLACK_ENABLE
I2C_GENERALCALLACK_DISABLE
AssertAcknowledge:
I2C_ASSERTACKNOWLEDGE_ENABLE
I2C_ASSERTACKNOWLEDGE_DISABLE
ClockSource:
I2C_CLOCKSOURCE_APBD256
I2C_CLOCKSOURCE_APBD224
I2C_CLOCKSOURCE_APBD192
I2C_CLOCKSOURCE_APBD160
I2C_CLOCKSOURCE_APBD960
I2C_CLOCKSOURCE_APBD120
I2C_CLOCKSOURCE_APBD60
I2C_CLOCKSOURCE_TIM3OFD8
* @retval None.
*/
void I2C_Init(I2C_InitType *InitStruct)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_I2C_GC(InitStruct->GeneralCallAck));
assert_parameters(IS_I2C_AA(InitStruct->AssertAcknowledge));
assert_parameters(IS_I2C_CLKSRC(InitStruct->ClockSource));
I2C->ADDR = InitStruct->SlaveAddr\
|InitStruct->GeneralCallAck;
tmp = I2C->CTRL;
tmp &= ~(I2C_CTRL_CR\
|I2C_CTRL_AA);
tmp |= (InitStruct->ClockSource\
|InitStruct->AssertAcknowledge);
I2C->CTRL = tmp;
}
/**
* @brief Interrupt configure.
* @param NewState:
ENABLE
DISABLE
* @retval None.
*/
void I2C_INTConfig(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
I2C->CTRL2 |= I2C_CTRL2_INTEN;
else
I2C->CTRL2 &= ~I2C_CTRL2_INTEN;
}
/**
* @brief Get interrupt status.
* @param None
* @retval Interrupt status.
*/
uint8_t I2C_GetINTStatus(void)
{
if (I2C->CTRL&I2C_CTRL_SI)
return 1;
else
return 0;
}
/**
* @brief Clear interrupt status.
* @param None
* @retval None.
*/
void I2C_ClearINTStatus(void)
{
I2C->CTRL &= ~I2C_CTRL_SI;
}
/**
* @brief Read a packge of data from slave device.
* @param InitStruct: I2C_WRType
SlaveAddr : Slave device address
SubAddress : start of slave device sub-address
PageRange : maximum range of page to Read operation
pBuffer : Read data pointer
Length : sum of Read datas
SubAddrType:
I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte)
I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes)
I2C_SUBADDR_OTHER (Slave device sub-address type: othres)
* @retval 0: true
£¡0£ºstatus code
bit15~8 status code(true)
bit7~0 status code(false)
*/
uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct)
{
uint32_t i;
uint16_t ret_val;
/* Check parameters */
assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType));
I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA
/*-------------------------------- START -----------------------------------*/
I2C_SendStart();
ret_val = I2C_CheckState(0x08);
if (ret_val) return ret_val;
/*------------------------------ Send SLA+W --------------------------------*/
/* Slave device sub-address type: 1 byte */
if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE)
{
I2C_SendByte(InitStruct->SlaveAddr);
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte(InitStruct->SubAddress&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
/* Slave device sub-address type: 2 bytes */
if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE)
{
I2C_SendByte(InitStruct->SlaveAddr);
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte((InitStruct->SubAddress>>8)&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
I2C_SendByte(InitStruct->SubAddress&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
/* Slave device sub-address type: othres */
if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER)
{
if (InitStruct->PageRange < 256) // 8 + x
{
I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE));
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte(InitStruct->SubAddress&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
else // 16 + x
{
I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE));
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte((InitStruct->SubAddress>>8)&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
I2C_SendByte(InitStruct->SubAddress&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
}
/*------------------------------- Restart ----------------------------------*/
I2C_SendRestart(); //restart
ret_val = I2C_CheckState(0x10);
if (ret_val) return ret_val;
/*----------------------------- Send SLA+R ---------------------------------*/
/* Slave device sub-address type: othres */
if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER)
{
if (InitStruct->PageRange < 256) // 8 + x
I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>7)&0xE));
else // 16 + x
I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>15)&0xE));
}
else
I2C_SendByte(InitStruct->SlaveAddr|0x01);
ret_val = I2C_CheckState(0x40);
if (ret_val) return ret_val;
/*----------------------------- Read datas ---------------------------------*/
for (i=0; i<(InitStruct->Length-1); i++)
{
*InitStruct->pBuffer = I2C_ReceiveByte();
InitStruct->pBuffer++;
ret_val = I2C_CheckState(0x50);
if (ret_val) return ret_val;
}
/*-------------------- Read the last data, disable AA ----------------------*/
I2C_AssertAcknowledgeConfig(DISABLE);
*InitStruct->pBuffer = I2C_ReceiveByte();
ret_val = I2C_CheckState(0x58);
if (ret_val) return ret_val;
/*--------------------------------- Stop -----------------------------------*/
I2C_SendStop(); //stop
return 0;
}
/**
* @brief Write a packge of data to slave device.
* @param InitStruct: I2C_WRType
SlaveAddr : Slave device address
SubAddress : start of slave device sub-address
PageRange : maximum range of page to write operation
pBuffer : write data pointer
Length : sum of write datas
SubAddrType:
I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte)
I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes)
I2C_SUBADDR_OTHER (Slave device sub-address type: othres)
* @retval 0: true
£¡0£ºstatus code
bit15~8 status code(true)
bit7~0 status code(false)
*/
uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct)
{
uint16_t ret_val;
uint32_t i;
/* Check parameters */
assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType));
I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA
/*-------------------------------- START -----------------------------------*/
I2C_SendStart();
ret_val = I2C_CheckState(0x08);
if (ret_val) return ret_val;
/*------------------------------ Send SLA+W --------------------------------*/
/* Slave device sub-address type: 1 byte */
if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE)
{
I2C_SendByte(InitStruct->SlaveAddr);
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte(InitStruct->SubAddress&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
/* Slave device sub-address type: 2 bytes */
else if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE)
{
I2C_SendByte(InitStruct->SlaveAddr); //device address
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); //first word address
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
I2C_SendByte(InitStruct->SubAddress&0xFF); //second word address
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
/* Slave device sub-address type: othres */
else
{
if (InitStruct->PageRange < 256) // 8 + x
{
I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE));
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte(InitStruct->SubAddress&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
else // 16 + x
{
I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE));
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte((InitStruct->SubAddress>>8)&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
I2C_SendByte(InitStruct->SubAddress&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
}
/*----------------------------- Write datas --------------------------------*/
for (i=0; i<(InitStruct->Length); i++)
{
/* Reach the page boundary */
if ((i > 0) && ((InitStruct->SubAddress+i)%InitStruct->PageRange == 0))
{
I2C_SendStop();
I2C_WaitForCrossPage(InitStruct->SlaveAddr);
I2C_SendStart(); //start
ret_val = I2C_CheckState(0x08);
if (ret_val) return ret_val;
/* WriteAddr: 1 byte */
if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE)
{
I2C_SendByte(InitStruct->SlaveAddr);
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte((InitStruct->SubAddress+i)&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
/* WriteAddr: 2 byte */
if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE)
{
I2C_SendByte(InitStruct->SlaveAddr); //device address
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF); //first word address
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
I2C_SendByte((InitStruct->SubAddress+i)&0xFF); //second word address
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
/* WriteAddr: (16 or 8)+x*/
if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER)
{
if (InitStruct->PageRange < 256) // 8 + x
{
I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>7)&0xE));
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte((InitStruct->SubAddress+i)&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
else // 16 + x
{
I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>15)&0xE));
ret_val = I2C_CheckState(0x18);
if (ret_val) return ret_val;
I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
I2C_SendByte((InitStruct->SubAddress+i)&0xFF);
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
}
I2C_SendByte(*InitStruct->pBuffer);
InitStruct->pBuffer++;
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
/* Not reaching the page boundary */
else
{
I2C_SendByte(*InitStruct->pBuffer);
InitStruct->pBuffer++;
ret_val = I2C_CheckState(0x28);
if (ret_val) return ret_val;
}
}
I2C_SendStop();
I2C_WaitForCrossPage(InitStruct->SlaveAddr);
return 0;
}
/**
* @brief I2C enable.
* @param NewState:
ENABLE
DISABLE
* @retval None.
*/
void I2C_Cmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
I2C->CTRL |= I2C_CTRL_EN;
else
I2C->CTRL &= ~I2C_CTRL_EN;
}
/* I2C Exported Functions Group5:
Others ------------------------------------*/
/**
* @brief Assert acknowledge configure.
* @param NewState:
ENABLE
DISABLE
* @retval None.
*/
void I2C_AssertAcknowledgeConfig(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
I2C->CTRL |= I2C_CTRL_AA;
else
I2C->CTRL &= ~I2C_CTRL_AA;
}
/**
* @brief Receive a byte data.
* @param None.
* @retval Data received.
*/
uint8_t I2C_ReceiveData(void)
{
return I2C->DATA;
}
/**
* @brief Sends a byte data.
* @param Dat:data to transmit.
* @retval None
*/
void I2C_SendData(uint8_t Dat)
{
I2C->DATA = Dat;
}
/**
* @brief Generate start signal.
* @param NewState:
ENABLE
DISABLE
* @retval None.
*/
void I2C_GenerateSTART(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
I2C->CTRL |= I2C_CTRL_STA;
else
I2C->CTRL &= ~I2C_CTRL_STA;
}
/**
* @brief Generate stop signal.
* @param NewState:
ENABLE
DISABLE
* @retval None.
*/
void I2C_GenerateSTOP(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
I2C->CTRL |= I2C_CTRL_STO;
else
I2C->CTRL &= ~I2C_CTRL_STO;
}
/**
* @brief Get status code.
* @param None
* @retval status code.
*/
uint8_t I2C_GetStatusCode(void)
{
return (I2C->STS&I2C_STS_STS);
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_iso7816.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief ISO7816 library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_iso7816.h"
#include "lib_clk.h"
//registers default reset values
#define ISO7816_BAUDDIVL_RSTValue 0
#define ISO7816_BAUDDIVH_RSTValue 0
#define ISO7816_CFG_RSTValue 0
#define ISO7816_CLK_RSTValue 0
#define ISO7816_INFO_RC_MASK (0xECUL) //R/C
#define ISO7816_INFO_RW_MASK (0x13UL) //R/W
/**
* @brief ISO7816 initialization.
* @param ISO7816x: ISO78160~ISO78161
Init_Struct:iso7816 configuration.
FirstBit:
ISO7816_FIRSTBIT_LSB
ISO7816_FIRSTBIT_MSB
ACKLen:
ISO7816_ACKLEN_1
ISO7816_ACKLEN_2
Parity:
ISO7816_PARITY_EVEN
ISO7816_PARITY_ODD
Baudrate: Baud rate value
* @retval None
*/
void ISO7816_Init(ISO7816_TypeDef *ISO7816x, ISO7816_InitType *Init_Struct)
{
uint32_t tmp;
uint16_t div;
uint32_t pclk;
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_ISO7816_FIRSTBIT(Init_Struct->FirstBit));
assert_parameters(IS_ISO7816_ACKLEN(Init_Struct->ACKLen));
assert_parameters(IS_ISO7816_PARITY(Init_Struct->Parity));
assert_parameters(IS_ISO7816_BAUDRATE(Init_Struct->Baudrate));
tmp = ISO7816x->INFO;
tmp &= ~(ISO7816_INFO_LSB|ISO7816_INFO_RC_MASK);
tmp |= Init_Struct->FirstBit;
ISO7816x->INFO = tmp;
tmp = ISO7816x->CFG;
tmp &= ~(ISO7816_CFG_ACKLEN\
|BIT3\
|BIT2\
|ISO7816_CFG_CHKP);
tmp |= (Init_Struct->ACKLen\
|Init_Struct->Parity);
ISO7816x->CFG = tmp;
pclk = CLK_GetPCLKFreq();
div = 0x10000 - (pclk/Init_Struct->Baudrate);
ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH;
ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL;
}
/**
* @brief Fills each InitStruct member with its default value.
* @param InitStruct: pointer to an ISO7816_InitType structure which will be initialized.
* @retval None
*/
void ISO7816_StructInit(ISO7816_InitType *InitStruct)
{
/*--------------- Reset ISO7816 init structure parameters values ---------------*/
/* Initialize the ACKLen member */
InitStruct->ACKLen = ISO7816_ACKLEN_1;
/* Initialize the Baudrate member */
InitStruct->Baudrate = 9600;
/* Initialize the FirstBit member */
InitStruct->FirstBit = ISO7816_FIRSTBIT_MSB;
/* Initialize the Parity member */
InitStruct->Parity = ISO7816_PARITY_EVEN;
}
/**
* @brief Initializes the ISO7816 peripheral registers to their default reset
values.
* @param ISO7816x: ISO78160~ISO78161
* @retval None
*/
void ISO7816_DeInit(ISO7816_TypeDef *ISO7816x)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
ISO7816x->CFG &= ~ISO7816_CFG_EN;
/* clear interrupt flag */
ISO7816x->INFO = ISO7816_INFO_RC_MASK;
ISO7816x->BAUDDIVH = ISO7816_BAUDDIVH_RSTValue;
ISO7816x->BAUDDIVL = ISO7816_BAUDDIVL_RSTValue;
ISO7816x->CFG = ISO7816_CFG_RSTValue;
ISO7816x->CLK = ISO7816_CLK_RSTValue;
}
/**
* @brief ISO7816 enable control.
* @param ISO7816x: ISO78160~ISO78161
NewState:
ENABLE
DISABLE
* @retval None.
*/
void ISO7816_Cmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
ISO7816x->CFG |= ISO7816_CFG_EN;
}
else
{
ISO7816x->CFG &= ~ISO7816_CFG_EN;
}
}
/**
* @brief ISO7816 Baudrate control.
* @param ISO7816x: ISO78160~ISO78161
BaudRate:
* @retval None
*/
void ISO7816_BaudrateConfig(ISO7816_TypeDef *ISO7816x, uint32_t BaudRate)
{
uint32_t pclk;
uint16_t div;
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_ISO7816_BAUDRATE(BaudRate));
pclk = CLK_GetPCLKFreq();
div = 0x10000 - (pclk/BaudRate);
ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH;
ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL;
}
/**
* @brief ISO7816 clock divider configure.
* @param ISO7816x: ISO78160~ISO78161
Prescaler:1~128
* @retval None
*/
void ISO7816_CLKDIVConfig(ISO7816_TypeDef *ISO7816x, uint32_t Prescaler)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_ISO7816_PRESCALER(Prescaler));
tmp = ISO7816x->CLK;
tmp &= ~ISO7816_CLK_CLKDIV;
tmp |= ((Prescaler - 1) & ISO7816_CLK_CLKDIV);
ISO7816x->CLK = tmp;
}
/**
* @brief ISO7816 clock output enable control.
* @param ISO7816x: ISO78160~ISO78161
NewState:
ENABLE
DISABLE
* @retval None
*/
void ISO7816_CLKOutputCmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
ISO7816x->CLK |= ISO7816_CLK_CLKEN;
}
else
{
ISO7816x->CLK &= ~ISO7816_CLK_CLKEN;
}
}
/**
* @brief Read data.
* @param ISO7816: ISO78160~ISO78161
* @retval The received data.
*/
uint8_t ISO7816_ReceiveData(ISO7816_TypeDef *ISO7816x)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
return ISO7816x->DATA;
}
/**
* @brief Write data.
* @param ISO7816x: ISO78160~ISO78161
* @retval None
*/
void ISO7816_SendData(ISO7816_TypeDef *ISO7816x, uint8_t ch)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
ISO7816x->DATA = ch;
}
/**
* @brief Interrupt configure.
* @param ISO7816x: ISO78160~ISO78161
INTMask:
This parameter can be any combination of the following values
ISO7816_INT_RXOV
ISO7816_INT_RX
ISO7816_INT_TX
NewState:
ENABLE
DISABLE
* @retval None
*/
void ISO7816_INTConfig(ISO7816_TypeDef *ISO7816x, uint32_t INTMask, uint8_t NewState)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_ISO7816_INT(INTMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
ISO7816x->CFG |= INTMask;
}
else
{
ISO7816x->CFG &= ~INTMask;
}
}
/**
* @brief Get interrupt state
* @param ISO7816x: ISO78160~ISO78161
INTMask:
ISO7816_INTSTS_RXOV
ISO7816_INTSTS_RX
ISO7816_INTSTS_TX
* @retval 1: state set
0: state reset
*/
uint8_t ISO7816_GetINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_ISO7816_INTFLAGR(INTMask));
if (ISO7816x->INFO & INTMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear interrupt state.
* @param ISO7816x: ISO78160~ISO78161
INTMask:
This parameter can be any combination of the following values
ISO7816_INTSTS_RXOV
ISO7816_INTSTS_RX
ISO7816_INTSTS_TX
* @retval None
*/
void ISO7816_ClearINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_ISO7816_INTFLAGC(INTMask));
tmp = ISO7816x->INFO;
tmp &= ~ISO7816_INFO_RC_MASK;
tmp |= INTMask;
ISO7816x->INFO = tmp;
}
/**
* @brief Get peripheral flag.
* @param ISO7816x: ISO78160~ISO78161
FlagMask:
ISO7816_FLAG_SDERR
ISO7816_FLAG_RCERR
* @retval 1: state set
0: state reset
*/
uint8_t ISO7816_GetFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_ISO7816_FLAGR(FlagMask));
if (ISO7816x->INFO&FlagMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear peripheral flag.
* @param ISO7816x: ISO78160~ISO78161
FlagMask:
This parameter can be any combination of the following values
ISO7816_FLAG_SDERR
ISO7816_FLAG_RCERR
* @retval None
*/
void ISO7816_ClearFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
assert_parameters(IS_ISO7816_FLAGC(FlagMask));
tmp = ISO7816x->INFO;
tmp &= ~ISO7816_INFO_RC_MASK;
tmp |= FlagMask;
ISO7816x->INFO = tmp;
}
/**
* @brief Get last transmit ACK.
* @param ISO7816: ISO78160~ISO78161
* @retval ACK value
*/
uint8_t ISO7816_GetLastTransmitACK(ISO7816_TypeDef *ISO7816x)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
if (ISO7816x->INFO&ISO7816_INFO_RCACK)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Get last receive check sum bit.
* @param ISO7816: ISO78160~ISO78161
* @retval CHKSUM bit value
*/
uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_TypeDef *ISO7816x)
{
/* Check parameters */
assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x));
if (ISO7816x->INFO&ISO7816_INFO_CHKSUM)
{
return 1;
}
else
{
return 0;
}
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_lcd.c
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief LCD library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_lcd.h"
#include "lib_LoadNVR.h"
//registers default reset values
#define LCD_CTRL_RSTValue 0
#define LCD_CTRL2_RSTValue 0
#define LCD_SEGCTRL0_RSTValue 0
#define LCD_SEGCTRL1_RSTValue 0
#define LCD_SEGCTRL2_RSTValue 0
/* COMx IO */
const LCD_SEGIO lcd_comio[] =
{
{&GPIOD->OEN, GPIO_Pin_0},
{&GPIOD->OEN, GPIO_Pin_1},
{&GPIOD->OEN, GPIO_Pin_2},
{&GPIOD->OEN, GPIO_Pin_3},
{&GPIOD->OEN, GPIO_Pin_4},
{&GPIOD->OEN, GPIO_Pin_5},
{&GPIOD->OEN, GPIO_Pin_6},
{&GPIOD->OEN, GPIO_Pin_7},
};
/* SEGx IO */
const LCD_SEGIO lcd_segio[] =
{ /**************************/
/* SEG | GPIO | Pin */
{&GPIOD->OEN, GPIO_Pin_4}, /* 0 D 4 */
{&GPIOD->OEN, GPIO_Pin_5}, /* 1 D 5 */
{&GPIOD->OEN, GPIO_Pin_6}, /* 2 D 6 */
{&GPIOD->OEN, GPIO_Pin_7}, /* 3 D 7 */
{&GPIOD->OEN, GPIO_Pin_8}, /* 4 D 8 */
{&GPIOD->OEN, GPIO_Pin_9}, /* 5 D 9 */
{&GPIOD->OEN, GPIO_Pin_10}, /* 6 D 10 */
{&GPIOD->OEN, GPIO_Pin_11}, /* 7 D 11 */
{&GPIOD->OEN, GPIO_Pin_12}, /* 8 D 12 */
{&GPIOD->OEN, GPIO_Pin_13}, /* 9 D 13 */
{&GPIOD->OEN, GPIO_Pin_14}, /* 10 D 14 */
{&GPIOD->OEN, GPIO_Pin_15}, /* 11 D 15 */
{&GPIOB->OEN, GPIO_Pin_4}, /* 12 B 4 */
{&GPIOA->OEN, GPIO_Pin_14}, /* 13 A 14 */
{&GPIOB->OEN, GPIO_Pin_5}, /* 14 B 5 */
{&GPIOA->OEN, GPIO_Pin_15}, /* 15 A 15 */
{&GPIOC->OEN, GPIO_Pin_0}, /* 16 C 0 */
{&GPIOC->OEN, GPIO_Pin_1}, /* 17 C 1 */
{&GPIOC->OEN, GPIO_Pin_2}, /* 18 C 2 */
{&GPIOC->OEN, GPIO_Pin_3}, /* 19 C 3 */
{&GPIOC->OEN, GPIO_Pin_4}, /* 20 C 4 */
{&GPIOC->OEN, GPIO_Pin_5}, /* 21 C 5 */
{&GPIOC->OEN, GPIO_Pin_6}, /* 22 C 6 */
{&GPIOC->OEN, GPIO_Pin_7}, /* 23 C 7 */
{&GPIOC->OEN, GPIO_Pin_8}, /* 24 C 8 */
{&GPIOC->OEN, GPIO_Pin_9}, /* 25 C 9 */
{&GPIOC->OEN, GPIO_Pin_10}, /* 26 C 10 */
{&GPIOC->OEN, GPIO_Pin_11}, /* 27 C 11 */
{&GPIOC->OEN, GPIO_Pin_12}, /* 28 C 12 */
{&GPIOC->OEN, GPIO_Pin_13}, /* 29 C 13 */
{&GPIOC->OEN, GPIO_Pin_14}, /* 30 C 14 */
{&GPIOC->OEN, GPIO_Pin_15}, /* 31 C 15 */
{&GPIOE->OEN, GPIO_Pin_10}, /* 32 E 10 */
{&GPIOE->OEN, GPIO_Pin_11}, /* 33 E 11 */
{&GPIOE->OEN, GPIO_Pin_12}, /* 34 E 12 */
{&GPIOB->OEN, GPIO_Pin_8}, /* 35 B 8 */
{&GPIOB->OEN, GPIO_Pin_9}, /* 36 B 9 */
{&GPIOB->OEN, GPIO_Pin_10}, /* 37 B 10 */
{&GPIOB->OEN, GPIO_Pin_11}, /* 38 B 11 */
{&GPIOB->OEN, GPIO_Pin_12}, /* 39 B 12 */
{&GPIOB->OEN, GPIO_Pin_13}, /* 40 B 13 */
{&GPIOB->OEN, GPIO_Pin_14}, /* 41 B 14 */
{&GPIOB->OEN, GPIO_Pin_15}, /* 42 B 15 */
{&GPIOB->OEN, GPIO_Pin_0}, /* 43 B 0 */
{&GPIOB->OEN, GPIO_Pin_6}, /* 44 B 6 */
{&GPIOB->OEN, GPIO_Pin_1}, /* 45 B 1 */
{&GPIOB->OEN, GPIO_Pin_7}, /* 46 B 7 */
{&GPIOA->OEN, GPIO_Pin_11}, /* 47 A 11 */
{&GPIOA->OEN, GPIO_Pin_10}, /* 48 A 10 */
{&GPIOA->OEN, GPIO_Pin_9}, /* 49 A 9 */
{&GPIOA->OEN, GPIO_Pin_8}, /* 50 A 8 */
{&GPIOA->OEN, GPIO_Pin_3}, /* 51 A 3 */
{&GPIOA->OEN, GPIO_Pin_2}, /* 52 A 2 */
{&GPIOA->OEN, GPIO_Pin_1}, /* 53 A 1 */
{&GPIOA->OEN, GPIO_Pin_0}, /* 54 A 0 */
{&GPIOE->OEN, GPIO_Pin_13}, /* 55 E 13 */
{&GPIOE->OEN, GPIO_Pin_14}, /* 56 E 14 */
{&GPIOE->OEN, GPIO_Pin_15}, /* 57 E 15 */
{&GPIOE->OEN, GPIO_Pin_9}, /* 58 E 9 */
{&GPIOE->OEN, GPIO_Pin_8}, /* 59 E 8 */
{&GPIOE->OEN, GPIO_Pin_7}, /* 60 E 7 */
{&GPIOE->OEN, GPIO_Pin_6}, /* 61 E 6 */
{&GPIOE->OEN, GPIO_Pin_5}, /* 62 E 5 */
{&GPIOE->OEN, GPIO_Pin_4}, /* 63 E 4 */
{&GPIOE->OEN, 0}, /* 64 NC NC */
{&GPIOE->OEN, 0}, /* 65 NC NC */
{&GPIOA->OEN, GPIO_Pin_4}, /* 66 A 4 */
{&GPIOA->OEN, GPIO_Pin_5}, /* 67 A 5 */
{&GPIOA->OEN, GPIO_Pin_6}, /* 68 A 6 */
{&GPIOA->OEN, GPIO_Pin_7}, /* 69 A 7 */
{&GPIOB->OEN, GPIO_Pin_2}, /* 70 B 2 */
{&GPIOA->OEN, GPIO_Pin_12}, /* 71 A 12 */
{&GPIOB->OEN, GPIO_Pin_3}, /* 72 B 3 */
{&GPIOA->OEN, GPIO_Pin_13}, /* 73 A 13 */
{&GPIOE->OEN, GPIO_Pin_0}, /* 74 E 0 */
{&GPIOE->OEN, GPIO_Pin_1}, /* 75 E 1 */
{&GPIOE->OEN, GPIO_Pin_2}, /* 76 E 2 */
{&GPIOE->OEN, GPIO_Pin_3}, /* 77 E 3 */
{&GPIOE->OEN, 0}, /* 78 NC NC */
{&GPIOE->OEN, 0} /* 79 NC NC */
};
/**
* @brief LCD initialization.
* @param InitStruct: LCD configuration.
Type:
LCD_TYPE_4COM
LCD_TYPE_6COM
LCD_TYPE_8COM
Drv:
LCD_DRV_300
LCD_DRV_600
LCD_DRV_150
LCD_DRV_200
FRQ:
LCD_FRQ_64H
LCD_FRQ_128H
LCD_FRQ_256H
LCD_FRQ_512H
SWPR: Frame buffer switch period(0.5 sec * (SWPR + 1)).
FBMODE:
LCD_FBMODE_BUFA
LCD_FBMODE_BUFAB
LCD_FBMODE_BUFABLANK
BKFILL:
LCD_BKFILL_1
LCD_BKFILL_0
* @retval None
*/
void LCD_Init(LCD_InitType *InitStruct)
{
uint32_t tmp_reg1, tmp_reg2;
/* Check parameters */
assert_parameters(IS_LCD_TYPE(InitStruct->Type));
assert_parameters(IS_LCD_DRV(InitStruct->Drv));
assert_parameters(IS_LCD_FRQ(InitStruct->FRQ));
assert_parameters(IS_LCD_SWPR(InitStruct->SWPR));
assert_parameters(IS_LCD_FBMODE(InitStruct->FBMODE));
assert_parameters(IS_LCD_BKFILL(InitStruct->BKFILL));
tmp_reg1 = LCD->CTRL;
tmp_reg2 = LCD->CTRL2;
tmp_reg1 &= ~(LCD_CTRL_TYPE\
|LCD_CTRL_DRV\
|LCD_CTRL_FRQ);
tmp_reg1 |= (InitStruct->Type\
|InitStruct->Drv\
|InitStruct->FRQ);
tmp_reg2 &= ~(LCD_CTRL2_SWPR\
|LCD_CTRL2_FBMODE\
|LCD_CTRL2_BKFILL);
tmp_reg2 |= ((InitStruct->SWPR << 8)\
|InitStruct->FBMODE\
|InitStruct->BKFILL);
LCD->CTRL = tmp_reg1;
LCD->CTRL2 = tmp_reg2;
}
/**
* @brief Fills each LCD_InitStruct member with its default value.
* @param LCD_InitStruct: pointer to an LCD_InitType structure which will be initialized.
* @retval None
*/
void LCD_StructInit(LCD_InitType *LCD_InitStruct)
{
/*--------------- Reset LCD init structure parameters values ---------------*/
/* Initialize the BKFILL member */
LCD_InitStruct->BKFILL = LCD_BKFILL_0;
/* Initialize the Drv member */
LCD_InitStruct->Drv = LCD_DRV_300;
/* Initialize the FBMODE member */
LCD_InitStruct->FBMODE = LCD_FBMODE_BUFA;
/* Initialize the FRQ member */
LCD_InitStruct->FRQ = LCD_FRQ_64H;
/* Initialize the SWPR member */
LCD_InitStruct->SWPR = 0;
/* Initialize the Type member */
LCD_InitStruct->Type = LCD_TYPE_4COM;
}
/**
* @brief Initializes the LCD registers to their default reset values.
* @param None
* @retval None
*/
void LCD_DeInit(void)
{
LCD->CTRL &= ~LCD_CTRL_EN;
LCD->CTRL = LCD_CTRL_RSTValue;
LCD->CTRL2 = LCD_CTRL2_RSTValue;
LCD->SEGCTRL0 = LCD_SEGCTRL0_RSTValue;
LCD->SEGCTRL1 = LCD_SEGCTRL1_RSTValue;
LCD->SEGCTRL2 = LCD_SEGCTRL2_RSTValue;
}
/**
* @brief LCD controller enable.
* @param NewState:
ENABLE
DISABLE
* @retval None
*/
void LCD_Cmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
LCD->CTRL |= LCD_CTRL_EN;
}
else
{
LCD->CTRL &= ~LCD_CTRL_EN;
}
}
/**
* @brief Configure LCD COMs'/SEGs' IOs.
* @param ComMode:
LCD_COMMOD_4COM : Control the COM0~3 IO configuration
LCD_COMMOD_6COM : Control the COM0~5 IO configuration
LCD_COMMOD_8COM : Control the COM0~7 IO configuration
* @param SEGVal0 SEGVal1 SEGVal2 : Each bit control the SEGs' IO configuration
* @param NewState:
ENABLE : The corresponded IOs be set to forbidden mode(disable output/disable input), enable SEGs' output and LCD function.
DISABLE : LCD be disabled and the corresponded IOs be set to output(low) mode.
* @retval None
*/
void LCD_IOConfig(uint32_t ComMode, uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2, uint32_t NewState)
{
uint32_t position, segcurrent;
/* Check parameters */
assert_parameters(IS_LCD_COMMOD(ComMode));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == DISABLE)
{
/* Disable LCD */
LCD->CTRL &= ~LCD_CTRL_EN;
/* COMs' IO configuration : ouput low */
*(lcd_comio[0].GPIO+2) &= ~lcd_comio[0].Pin;
*lcd_comio[0].GPIO &= ~lcd_comio[0].Pin;
*(lcd_comio[1].GPIO+2) &= ~lcd_comio[1].Pin;
*lcd_comio[1].GPIO &= ~lcd_comio[1].Pin;
*(lcd_comio[2].GPIO+2) &= ~lcd_comio[2].Pin;
*lcd_comio[2].GPIO &= ~lcd_comio[2].Pin;
*(lcd_comio[3].GPIO+2) &= ~lcd_comio[3].Pin;
*lcd_comio[3].GPIO &= ~lcd_comio[3].Pin;
if (ComMode & 2UL)
{
*(lcd_comio[4].GPIO+2) &= ~lcd_comio[4].Pin;
*lcd_comio[4].GPIO &= ~lcd_comio[4].Pin;
*(lcd_comio[5].GPIO+2) &= ~lcd_comio[5].Pin;
*lcd_comio[5].GPIO &= ~lcd_comio[5].Pin;
}
if (ComMode & 4UL)
{
*(lcd_comio[6].GPIO+2) &= ~lcd_comio[6].Pin;
*lcd_comio[6].GPIO &= ~lcd_comio[6].Pin;
*(lcd_comio[7].GPIO+2) &= ~lcd_comio[7].Pin;
*lcd_comio[7].GPIO &= ~lcd_comio[7].Pin;
}
/* SEG0~31 IO Configuration : ouput low */
position = 0;
while ((SEGVal0 >> position) != 0UL)
{
segcurrent = SEGVal0 & (1U << position);
if (segcurrent)
{
*(lcd_segio[position].GPIO + 2) &= ~lcd_segio[position].Pin;
*lcd_segio[position].GPIO &= ~lcd_segio[position].Pin;
}
position++;
}
/* SEG32~63 IO Configuration : ouput low */
position = 0;
while ((SEGVal1 >> position) != 0UL)
{
segcurrent = SEGVal1 & (1U << position);
if (segcurrent)
{
*(lcd_segio[position + 32].GPIO + 2) &= ~lcd_segio[position + 32].Pin;
*lcd_segio[position + 32].GPIO &= ~lcd_segio[position + 32].Pin;
}
position++;
}
/* SEG64~79 IO Configuration : ouput low */
position = 0;
while ((SEGVal2 >> position) != 0UL)
{
segcurrent = SEGVal2 & (1U << position);
if (segcurrent)
{
*(lcd_segio[position + 64].GPIO + 2) &= ~lcd_segio[position + 64].Pin;
*lcd_segio[position + 64].GPIO &= ~lcd_segio[position + 64].Pin;
}
position++;
}
}
else
{
/* COMs' IO configuration : forbidden */
*lcd_comio[0].GPIO |= lcd_comio[0].Pin;
*(lcd_comio[0].GPIO+1) &= ~lcd_comio[0].Pin;
*lcd_comio[1].GPIO |= lcd_comio[1].Pin;
*(lcd_comio[1].GPIO+1) &= ~lcd_comio[1].Pin;
*lcd_comio[2].GPIO |= lcd_comio[2].Pin;
*(lcd_comio[2].GPIO+1) &= ~lcd_comio[2].Pin;
*lcd_comio[3].GPIO |= lcd_comio[3].Pin;
*(lcd_comio[3].GPIO+1) &= ~lcd_comio[3].Pin;
if (ComMode & 2UL)
{
*lcd_comio[4].GPIO |= lcd_comio[4].Pin;
*(lcd_comio[4].GPIO+1) &= ~lcd_comio[4].Pin;
*lcd_comio[5].GPIO |= lcd_comio[5].Pin;
*(lcd_comio[5].GPIO+1) &= ~lcd_comio[5].Pin;
}
if (ComMode & 4UL)
{
*lcd_comio[6].GPIO |= lcd_comio[6].Pin;
*(lcd_comio[6].GPIO+1) &= ~lcd_comio[6].Pin;
*lcd_comio[7].GPIO |= lcd_comio[7].Pin;
*(lcd_comio[7].GPIO+1) &= ~lcd_comio[7].Pin;
}
/* SEG0~31 IO Configuration */
position = 0;
while ((SEGVal0 >> position) != 0UL)
{
segcurrent = SEGVal0 & (1U << position);
if (segcurrent)
{
/* Disable output */
*lcd_segio[position].GPIO |= lcd_segio[position].Pin;
/* Disable input */
*(lcd_segio[position].GPIO + 1) &= ~lcd_segio[position].Pin;
}
position++;
}
/* SEG32~63 IO Configuration */
position = 0;
while ((SEGVal1 >> position) != 0UL)
{
segcurrent = SEGVal1 & (1U << position);
if (segcurrent)
{
/* Disable output */
*lcd_segio[position + 32].GPIO |= lcd_segio[position + 32].Pin;
/* Disable input */
*(lcd_segio[position + 32].GPIO + 1) &= ~lcd_segio[position + 32].Pin;
}
position++;
}
/* SEG64~79 IO Configuration */
position = 0;
while ((SEGVal2 >> position) != 0UL)
{
segcurrent = SEGVal2 & (1U << position);
if (segcurrent)
{
/* Disable output */
*lcd_segio[position + 64].GPIO |= lcd_segio[position + 64].Pin;
/* Disable input */
*(lcd_segio[position + 64].GPIO + 1) &= ~lcd_segio[position + 64].Pin;
}
position++;
}
/* Enable SEGs' function of IOs */
LCD->SEGCTRL0 = SEGVal0;
LCD->SEGCTRL1 = SEGVal1;
LCD->SEGCTRL2 = SEGVal2 & 0xFFFE;
/* Enable LCD */
LCD->CTRL |= LCD_CTRL_EN;
}
}
/**
* @brief LCD SEGx enable.
* @param SEGVal0 SEGVal1 SEGVal2
* @retval None
*/
void LCD_SetSEG(uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2)
{
uint32_t position;
uint32_t segcurrent;
/* SEG0~31 IO Configuration */
position = 0;
while ((SEGVal0 >> position) != 0UL)
{
segcurrent = SEGVal0 & (1U << position);
if (segcurrent)
{
/* Disable output */
*lcd_segio[position].GPIO |= lcd_segio[position].Pin;
/* Disable input */
*(lcd_segio[position].GPIO + 1) &= ~lcd_segio[position].Pin;
}
position++;
}
/* SEG32~63 IO Configuration */
position = 0;
while ((SEGVal1 >> position) != 0UL)
{
segcurrent = SEGVal1 & (1U << position);
if (segcurrent)
{
/* Disable output */
*lcd_segio[position + 32].GPIO |= lcd_segio[position + 32].Pin;
/* Disable input */
*(lcd_segio[position + 32].GPIO + 1) &= ~lcd_segio[position + 32].Pin;
}
position++;
}
/* SEG64~79 IO Configuration */
position = 0;
while ((SEGVal2 >> position) != 0UL)
{
segcurrent = SEGVal2 & (1U << position);
if (segcurrent)
{
/* Disable output */
*lcd_segio[position + 64].GPIO |= lcd_segio[position + 64].Pin;
/* Disable input */
*(lcd_segio[position + 64].GPIO + 1) &= ~lcd_segio[position + 64].Pin;
}
position++;
}
LCD->SEGCTRL0 = SEGVal0;
LCD->SEGCTRL1 = SEGVal1;
LCD->SEGCTRL2 = SEGVal2 & 0xFFFE;
}
/**
* @brief LCD BIAS mode configure.
* @param BiasSelection:
LCD_BMODE_DIV3
LCD_BMODE_DIV4
* @retval None
*/
void LCD_BiasModeConfig(uint32_t BiasSelection)
{
uint32_t tmp;
assert_parameters(IS_LCD_BMODE(BiasSelection));
tmp = ANA->REG6;
tmp &= ~ANA_REG6_LCD_BMODE;
tmp |= BiasSelection;
ANA->REG6 = tmp;
}
/**
* @brief LCD driving voltage configure.
* @note The LCD driving voltage's configuration in NVR will be load to register
* (ANA_REG6[4:1]) in startup_target.s file.
* ex:
* The VLCD information in NVR[0x40D94] 10<<1(-300mV)
* 1. When LCD_VLCD_DEC60MV is selected
* 11<<1(-360mV) will be configured to ANA_REG6[4:1], return 0
* 2. When LCD_VLCD_DEC360MV is selected(out of range)
* 15<<1(-600mV) will be configured to ANA_REG6[4:1], return 2
* @param VLCDSelection:
LCD_VLCD_0
LCD_VLCD_INC60MV
LCD_VLCD_INC120MV
LCD_VLCD_INC180MV
LCD_VLCD_INC240MV
LCD_VLCD_INC300MV
LCD_VLCD_DEC60MV
LCD_VLCD_DEC120MV
LCD_VLCD_DEC180MV
LCD_VLCD_DEC240MV
LCD_VLCD_DEC300MV
LCD_VLCD_DEC360MV
LCD_VLCD_DEC420MV
LCD_VLCD_DEC480MV
LCD_VLCD_DEC540MV
LCD_VLCD_DEC600MV
* @retval 0 Function successed.
1 NVR LCD information checksum error.
2 LCD driving voltage's configuration out of range.
*/
uint32_t LCD_VoltageConfig(uint32_t VLCDSelection)
{
uint32_t lcd_vol;
uint32_t lcd_vol_tmp;
uint32_t tmp;
NVR_LCDINFO LCD_InfoStruct;
assert_parameters(IS_LCD_VLCD(VLCDSelection));
/* Get NVR LCD information */
if (NVR_GetLCDInfo(&LCD_InfoStruct))
return (1);
else
lcd_vol_tmp = LCD_InfoStruct.MEALCDVol;
tmp = ANA->REG6;
tmp &= ~ANA_REG6_VLCD;
lcd_vol = lcd_vol_tmp<<ANA_REG6_VLCD_Pos;
/*Adjust voltage is postive*/
if ( (lcd_vol_tmp <= 0x5U) && (VLCDSelection <= 0x5U) )
{
/*Adjust voltage is out of range(+300mv)*/
if ((lcd_vol_tmp + VLCDSelection)>0x5U)
{
tmp |= LCD_VLCD_INC300MV << ANA_REG6_VLCD_Pos;
ANA->REG6 = tmp;
return (2);
}
else
{
tmp |= (lcd_vol + (VLCDSelection << ANA_REG6_VLCD_Pos));
ANA->REG6 = tmp;
return (0);
}
}
/*Adjust voltage is negtive*/
else if ( (lcd_vol_tmp > 0x5U) && (VLCDSelection > 0x5U) )
{
/*Adjust voltage is out of range(-600mv)*/
if ((lcd_vol_tmp + VLCDSelection - 5)>0xFU)
{
tmp |= LCD_VLCD_DEC600MV << ANA_REG6_VLCD_Pos;
ANA->REG6 = tmp;
return (2);
}
else
{
tmp |= (lcd_vol + ((VLCDSelection -0x5)<< ANA_REG6_VLCD_Pos));
ANA->REG6 = tmp;
return (0);
}
}
else if ( (lcd_vol_tmp > 0x5U) && (VLCDSelection <= 0x5U) )
{
/*Adjust voltage is postive or 0*/
if ((lcd_vol_tmp - 5) <= VLCDSelection)
{
tmp |= (((VLCDSelection + 0x5) << ANA_REG6_VLCD_Pos) - lcd_vol);
ANA->REG6 = tmp;
return (0);
}
/*Adjust voltage is negtive*/
else
{
tmp |= (lcd_vol - ((VLCDSelection) << ANA_REG6_VLCD_Pos));
ANA->REG6 = tmp;
return (0);
}
}
else
{
/*Adjust voltage is postive or 0*/
if ((VLCDSelection - 5) <= lcd_vol_tmp)
{
tmp |= (lcd_vol - ((VLCDSelection - 0x5) << ANA_REG6_VLCD_Pos));
ANA->REG6 = tmp;
return (0);
}
/*Adjust voltage is negtive*/
else
{
tmp |= ((VLCDSelection << ANA_REG6_VLCD_Pos) - lcd_vol);
ANA->REG6 = tmp;
return (0);
}
}
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_misc.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief MISC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_misc.h"
/**
* @brief Get flag status.
* @param FlagMask:
MISC_FLAG_LOCKUP
MISC_FLAG_PIAC
MISC_FLAG_HIAC
MISC_FLAG_PERR
* @retval Flag status.
*/
uint8_t MISC_GetFlag(uint32_t FlagMask)
{
/* Check parameters */
assert_parameters(IS_MISC_FLAGR(FlagMask));
if (MISC->SRAMINT&FlagMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear flag status.
* @param FlagMask: can use the ¡®|¡¯ operator
MISC_FLAG_LOCKUP
MISC_FLAG_PIAC
MISC_FLAG_HIAC
MISC_FLAG_PERR
* @retval None
*/
void MISC_ClearFlag(uint32_t FlagMask)
{
/* Check parameters */
assert_parameters(IS_MISC_FLAGC(FlagMask));
MISC->SRAMINT = FlagMask;
}
/**
* @brief Interrupt configure.
* @param INTMask: can use the ¡®|¡¯ operator
MISC_INT_LOCK
MISC_INT_PIAC
MISC_INT_HIAC
MISC_INT_PERR
NewState:
ENABLE
DISABLE
* @retval None
*/
void MISC_INTConfig(uint32_t INTMask, uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_MISC_INT(INTMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = MISC->SRAMINIT;
if (NewState == ENABLE)
{
tmp |= INTMask;
}
else
{
tmp &= ~INTMask;
}
MISC->SRAMINIT = tmp;
}
/**
* @brief sram parity contrl.
* @param NewState:
ENABLE
DISABLE
* @retval None
*/
void MISC_SRAMParityCmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
MISC->SRAMINIT |= MISC_SRAMINIT_PEN;
}
else
{
MISC->SRAMINIT &= ~MISC_SRAMINIT_PEN;
}
}
/**
* @brief Get sram parity error address.
* @param None
* @retval parity error address.
*/
uint32_t MISC_GetSRAMPEAddr(void)
{
uint32_t tmp;
tmp = MISC->PARERR;
tmp = tmp*4 + 0x20000000;
return tmp;
}
/**
* @brief Get APB error address.
* @param None
* @retval APB error address.
*/
uint32_t MISC_GetAPBErrAddr(void)
{
uint32_t tmp;
tmp = MISC->PIADDR;
tmp = tmp + 0x40010000;
return tmp;
}
/**
* @brief Get AHB error address.
* @param None
* @retval AHB error address.
*/
uint32_t MISC_GetAHBErrAddr(void)
{
uint32_t tmp;
tmp = MISC->HIADDR;
tmp = tmp + 0x40000000;
return tmp;
}
/**
* @brief IR control.
* @param IRx:
MISC_IREN_TX0
MISC_IREN_TX1
MISC_IREN_TX2
MISC_IREN_TX3
MISC_IREN_TX4
MISC_IREN_TX5
NewState:
ENABLE
DISABLE
* @retval None
*/
void MISC_IRCmd(uint32_t IRx, uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
assert_parameters(IS_MISC_IREN(IRx));
tmp = MISC->IREN;
if (NewState == ENABLE)
{
tmp |= IRx;
}
else
{
tmp &= ~IRx;
}
MISC->IREN = tmp;
}
/**
* @brief IR duty configure.
* @param DutyHigh
The high pulse width will be (DUTYH + 1)*APBCLK period.
DutyLow
The low pulse width will be (DUTYL + 1)*APBCLK period.
* @retval None
*/
void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow)
{
MISC->DUTYH = DutyHigh;
MISC->DUTYL = DutyLow;
}
/**
* @brief Hardfault generation configure.
* @param NewState:
ENABLE
DISABLE
* @retval None
*/
void MISC_HardFaultCmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
MISC->IRQLAT &= ~MISC_IRQLAT_NOHARDFAULT;
}
else
{
MISC->IRQLAT |= MISC_IRQLAT_NOHARDFAULT;
}
}
/**
* @brief Control if the lockup will issue a system reset.
* @param NewState:
ENABLE
DISABLE
* @retval None
*/
void MISC_LockResetCmd(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
MISC->IRQLAT |= MISC_IRQLAT_LOCKRESET;
}
else
{
MISC->IRQLAT &= ~MISC_IRQLAT_LOCKRESET;
}
}
/**
* @brief IRQLAT configure.
* @param Latency:0~255
* @retval None
*/
void MISC_IRQLATConfig(uint8_t Latency)
{
uint32_t tmp;
tmp = MISC->IRQLAT;
tmp &= ~MISC_IRQLAT_IRQLAT;
tmp |= Latency;
MISC->IRQLAT = tmp;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_pwm.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief PWM library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_pwm.h"
/**
* @brief PWM timebase initialization.
* @param PWMx: PWM0~PWM3
InitStruct:PWM BASE configuration.
ClockDivision:
PWM_CLKDIV_2
PWM_CLKDIV_4
PWM_CLKDIV_8
PWM_CLKDIV_16
Mode:
PWM_MODE_STOP
PWM_MODE_UPCOUNT
PWM_MODE_CONTINUOUS
PWM_MODE_UPDOWN
ClockSource:
PWM_CLKSRC_APB
PWM_CLKSRC_APBD128
* @retval None
*/
void PWM_BaseInit(PWM_TypeDef *PWMx, PWM_BaseInitType *InitStruct)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_CLKDIV(InitStruct->ClockDivision));
assert_parameters(IS_PWM_CNTMODE(InitStruct->Mode));
assert_parameters(IS_PWM_CLKSRC(InitStruct->ClockSource));
tmp = PWMx->CTL;
tmp &= ~(PWM_CTL_ID\
|PWM_CTL_MC\
|PWM_CTL_TESL);
tmp |= (InitStruct->ClockDivision\
|InitStruct->Mode\
|InitStruct->ClockSource);
PWMx->CTL = tmp;
}
/**
* @brief Fills each PWM_BaseInitType member with its default value.
* @param InitStruct: pointer to an PWM_BaseInitType structure which will be initialized.
* @retval None
*/
void PWM_BaseStructInit(PWM_BaseInitType *InitStruct)
{
/*------------ Reset PWM base init structure parameters values ------------*/
/* Initialize the ClockDivision member */
InitStruct->ClockDivision = PWM_CLKDIV_2;
/* Initialize the ClockSource member */
InitStruct->ClockSource = PWM_CLKSRC_APBD128;
/* Initialize the Mode member */
InitStruct->Mode = PWM_MODE_STOP;
}
/**
* @brief Fills each PWM_OCInitType member with its default value.
* @param OCInitType: pointer to an PWM_OCInitType structure which will be initialized.
* @retval None
*/
void PWM_OCStructInit(PWM_OCInitType *OCInitType)
{
/*------- Reset PWM output channel init structure parameters values --------*/
/* Initialize the OutMode member */
OCInitType->OutMode = PWM_OUTMOD_CONST;
/* Initialize the Period member */
OCInitType->Period = 0;
}
/**
* @brief PWM output compare channel 0.
* @param PWMx: PWM0~PWM3
OCInitType:PWM output compare configuration.
OutMode:
PWM_OUTMOD_CONST
PWM_OUTMOD_SET
PWM_OUTMOD_TOGGLE_RESET
PWM_OUTMOD_SET_RESET
PWM_OUTMOD_TOGGLE
PWM_OUTMOD_RESET
PWM_OUTMOD_TOGGLE_SET
PWM_OUTMOD_RESET_SET
Period: 0 ~ 0xFFFF
* @retval None
*/
void PWM_OC0Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode));
assert_parameters(IS_PWM_CCR(OCInitType->Period));
tmp = PWMx->CCTL0;
tmp &= ~(PWM_CCTL_OUTMOD | PWM_CCTL_CCIGG);
tmp |= OCInitType->OutMode;
PWMx->CCTL0 = tmp;
PWMx->CCR0 = OCInitType->Period;
}
/**
* @brief PWM output compare channel 1.
* @param PWMx: PWM0~PWM3
OCInitType:PWM output compare configuration.
OutMode:
PWM_OUTMOD_CONST
PWM_OUTMOD_SET
PWM_OUTMOD_TOGGLE_RESET
PWM_OUTMOD_SET_RESET
PWM_OUTMOD_TOGGLE
PWM_OUTMOD_RESET
PWM_OUTMOD_TOGGLE_SET
PWM_OUTMOD_RESET_SET
Period: 0 ~ 0xFFFF
* @retval None
*/
void PWM_OC1Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode));
assert_parameters(IS_PWM_CCR(OCInitType->Period));
tmp = PWMx->CCTL1;
tmp &= ~(PWM_CCTL_OUTMOD | PWM_CCTL_CCIGG);
tmp |= OCInitType->OutMode;
PWMx->CCTL1 = tmp;
PWMx->CCR1 = OCInitType->Period;
}
/**
* @brief PWM output compare channel 2.
* @param PWMx: PWM0~PWM3
OCInitType:PWM output compare configuration.
OutMode:
PWM_OUTMOD_CONST
PWM_OUTMOD_SET
PWM_OUTMOD_TOGGLE_RESET
PWM_OUTMOD_SET_RESET
PWM_OUTMOD_TOGGLE
PWM_OUTMOD_RESET
PWM_OUTMOD_TOGGLE_SET
PWM_OUTMOD_RESET_SET
Period: 0 ~ 0xFFFF
* @retval None
*/
void PWM_OC2Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode));
assert_parameters(IS_PWM_CCR(OCInitType->Period));
tmp = PWMx->CCTL2;
tmp &= ~(PWM_CCTL_OUTMOD | PWM_CCTL_CCIGG);
tmp |= OCInitType->OutMode;
PWMx->CCTL2 = tmp;
PWMx->CCR2 = OCInitType->Period;
}
/**
* @brief PWM base interrupt configure.
* @param PWMx: PWM0~PWM3
NewState:
ENABLE
DISABLE
* @retval None
*/
void PWM_BaseINTConfig(PWM_TypeDef *PWMx, uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = PWMx->CTL;
tmp &= ~(PWM_CTL_IE | PWM_CTL_IFG);
if (NewState == ENABLE)
{
tmp |= PWM_CTL_IE;
}
PWMx->CTL = tmp;
}
/**
* @brief Get PWM base interrupt status.
* @param PWMx: PWM0~PWM3
* @retval interrupt status.
*/
uint8_t PWM_GetBaseINTStatus(PWM_TypeDef *PWMx)
{
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
if (PWMx->CTL&PWM_CTL_IFG)
return 1;
else
return 0;
}
/**
* @brief Clear PWM base interrupt status.
* @param PWMx: PWM0~PWM3
* @retval None.
*/
void PWM_ClearBaseINTStatus(PWM_TypeDef *PWMx)
{
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
PWMx->CTL |= PWM_CTL_IFG;
}
/**
* @brief channel interrupt configure.
* @param PWMx: PWM0~PWM3
Channel:
PWM_CHANNEL_0
PWM_CHANNEL_1
PWM_CHANNEL_2
NewState:
ENABLE
DISABLE
* @retval None
*/
void PWM_ChannelINTConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState)
{
__IO uint32_t *addr;
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_CHANNEL(Channel));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
addr = &PWMx->CCTL0 + Channel;
tmp = *addr;
tmp &= ~(PWM_CCTL_CCIE | PWM_CCTL_CCIGG);
if (NewState == ENABLE)
{
tmp |= PWM_CCTL_CCIE;
}
*addr = tmp;
}
/**
* @brief Get channel interrupt status.
* @param PWMx: PWM0~PWM3
Channel:
PWM_CHANNEL_0
PWM_CHANNEL_1
PWM_CHANNEL_2
* @retval interrupt status
*/
uint8_t PWM_GetChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel)
{
__IO uint32_t *addr;
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_CHANNEL(Channel));
addr = &PWMx->CCTL0 + Channel;
tmp = *addr;
if (tmp & PWM_CCTL_CCIGG)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear channel interrupt status.
* @param PWMx: PWM0~PWM3
Channel:
PWM_CHANNEL_0
PWM_CHANNEL_1
PWM_CHANNEL_2
* @retval None
*/
void PWM_ClearChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel)
{
__IO uint32_t *addr;
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_CHANNEL(Channel));
addr = &PWMx->CCTL0 + Channel;
tmp = *addr;
tmp &= ~PWM_CCTL_CCIGG;
tmp |= PWM_CCTL_CCIGG;
*addr = tmp;
}
/**
* @brief PWM clear counter.
* @param PWMx: PWM0~PWM3
* @retval None
*/
void PWM_ClearCounter(PWM_TypeDef *PWMx)
{
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
PWMx->CTL |= PWM_CTL_CLR;
}
/**
* @brief Configure PWMx channelx's CCR value.
* @param PWMx: PWM0~PWM3
Channel:
PWM_CHANNEL_0
PWM_CHANNEL_1
PWM_CHANNEL_2
Period: 0 ~ 0xFFFF
* @retval None
*/
void PWM_CCRConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint16_t Period)
{
__IO uint32_t *addr;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_CHANNEL(Channel));
addr = &PWMx->CCR0 + Channel;
*addr = Period;
}
/**
* @brief pwm output line selection.
* @param OutSelection:
PWM0_OUT0
PWM0_OUT1
PWM0_OUT2
PWM1_OUT0
PWM1_OUT1
PWM1_OUT2
PWM2_OUT0
PWM2_OUT1
PWM2_OUT2
PWM3_OUT0
PWM3_OUT1
PWM3_OUT2
OLine: can use the ¡®|¡¯ operator
PWM_OLINE_0
PWM_OLINE_1
PWM_OLINE_2
PWM_OLINE_3
* @note PWM Single channel's output waveform can be output on multiple output lines.
* Multiple-line configuration can be performed by using the ¡®|¡¯ operator.
* ex: PWM_OLineConfig(PWM0_OUT0, PWM_OLINE_0 | PWM_OLINE_2)
* PWM0 channel0 output by PWM0&PWM2's lien.
* @retval None
*/
void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine)
{
uint32_t tmp;
uint32_t position = 0;
/* Check parameters */
assert_parameters(IS_PWM_OUTLINE(OLine));
assert_parameters(IS_PWM_OUTSEL(OutSelection));
tmp = PWMMUX->OSEL;
while ((OLine >> position) != 0UL)
{
if ((OLine >> position) & 1UL)
{
tmp &= ~(PWM_O_SEL_O_SEL0 << (position * 4));
tmp |= (OutSelection << (position * 4));
}
position++;
}
PWMMUX->OSEL = tmp;
}
/**
* @brief PWM output enable.
* @param PWMx: PWM0~PWM3
Channel:
PWM_CHANNEL_0
PWM_CHANNEL_1
PWM_CHANNEL_2
NewState:
ENABLE
DISABLE
* @retval None
*/
void PWM_OutputCmd(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState)
{
__IO uint32_t *addr;
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_CHANNEL(Channel));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
addr = &PWMx->CCTL0 + Channel;
tmp = *addr;
tmp &= ~PWM_CCTL_CCIGG;
if (NewState == ENABLE)
tmp |= PWM_CCTL_OUTEN;
else
tmp &= ~PWM_CCTL_OUTEN;
*addr = tmp;
}
/**
* @brief Set channel output level.
* @param PWMx: PWM0~PWM3
Channel:
PWM_CHANNEL_0
PWM_CHANNEL_1
PWM_CHANNEL_2
Level:
PWM_LEVEL_HIGH
PWM_LEVEL_LOW
* @retval None
*/
void PWM_SetOutLevel(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t Level)
{
__IO uint32_t *addr;
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_PWM_ALL_INSTANCE(PWMx));
assert_parameters(IS_PWM_CHANNEL(Channel));
assert_parameters(IS_PWM_OUTLVL(Level));
addr = &PWMx->CCTL0 + Channel;
tmp = *addr;
tmp &= ~(PWM_CCTL_OUT | PWM_CCTL_CCIGG);
tmp |= Level;
*addr = tmp;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_rtc.c
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief RTC library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_rtc.h"
#define RTCPWD_KEY 0x5AA55AA5
#define RTCCE_SETKEY 0xA55AA55B
#define RTCCE_CLRKEY 0xA55AA55A
/**
* @brief RTC registers write protection control.
* @param NewState:
* ENABLE
* DISABLE
* @retval None
*/
void RTC_WriteProtection(uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
/* Enable RTC Write-Protection */
if (NewState != DISABLE)
{
RTC->PWD = RTCPWD_KEY;
RTC->CE = RTCCE_CLRKEY;
}
/* Disable RTC Write-Protection */
else
{
RTC->PWD = RTCPWD_KEY;
RTC->CE = RTCCE_SETKEY;
}
}
/**
* @brief Wait until the RTC registers (be W/R protected) are synchronized
* with RTC APB clock.
*
* @note The RTC Resynchronization mode is write protected, use the
* RTC_WriteProtection(DISABLE) before calling this function.
* Write-Operation process as follows:
* 1. RTC_WriteProtection(DISABLE);
* 2. RTC Registers write operation(only first write-operation be
* valid on the same register).
* 3. RTC_WriteProtection(ENABLE);
* 4. RTC_WaitForSynchro(); Wait until the RTC registers be
* synchronized by calling this function.
* @retval None
*/
void RTC_WaitForSynchro(void)
{
while (RTC->CE & RTC_CE_BSY)
{
}
}
/**
* @brief Write RTC registers(continuous/be write-protected).
* @param[in] StartAddr the start address of registers be written
* @param[in] wBuffer pointer to write
* @param[in] Len number of registers be written
* @retval None
*/
void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len)
{
uint8_t cnt;
/* Parameter check */
assert_parameters(IS_RTC_REGOP_STARTADDR(StartAddr));
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
/* Write registers */
for (cnt=0; cnt<Len; cnt++)
{
*(volatile uint32_t *)(StartAddr) = *(wBuffer++);
StartAddr += 4;
}
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/**
* @brief Read RTC registers(continuous/be read-protected).
* @param[in] StartAddr the start address of registers be read
* @param[out] rBuffer pointer to read
* @param[in] Len number of registers be read
* @retval None
*/
void RTC_ReadRegisters(uint32_t StartAddr, uint32_t *rBuffer, uint8_t Len)
{
__IO uint32_t tmp;
uint8_t cnt;
/* Parameter check */
assert_parameters(IS_RTC_REGOP_STARTADDR(StartAddr));
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Dummy read-operation to RTC->LOAD */
tmp = RTC->LOAD;
tmp += 1;
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Read registers */
for (cnt=0; cnt<Len; cnt++)
{
*(rBuffer++) = *(volatile uint32_t *)(StartAddr);
StartAddr += 4;
}
}
/**
* @brief Set RTC current time.
* @param sTime: Pointer to Time structure
* @retval None
*/
void RTC_SetTime(RTC_TimeTypeDef *sTime)
{
/* Parameter check */
assert_parameters(IS_RTC_TIME_YEAR(sTime->Year));
assert_parameters(IS_RTC_TIME_MONTH(sTime->Month));
assert_parameters(IS_RTC_TIME_DATE(sTime->Date));
assert_parameters(IS_RTC_TIME_WEEKDAY(sTime->WeekDay));
assert_parameters(IS_RTC_TIME_HOURS(sTime->Hours));
assert_parameters(IS_RTC_TIME_MINS(sTime->Minutes));
assert_parameters(IS_RTC_TIME_SECS(sTime->Seconds));
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
/* Write RTC time registers */
RTC->SEC = sTime->Seconds;
RTC->MIN = sTime->Minutes;
RTC->HOUR = sTime->Hours;
RTC->DAY = sTime->Date;
RTC->WEEK = sTime->WeekDay;
RTC->MON = sTime->Month;
RTC->YEAR = sTime->Year;
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/**
* @brief Get RTC current time.
* @param gTime: Pointer to Time structure
* @retval None
*/
void RTC_GetTime(RTC_TimeTypeDef *gTime)
{
__IO uint32_t dummy_data = 0;
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Dummy read-operation to RTC->LOAD register */
dummy_data = RTC->LOAD;
dummy_data += 1;
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Read RTC time registers */
gTime->Seconds = RTC->SEC;
gTime->Minutes = RTC->MIN;
gTime->Hours = RTC->HOUR;
gTime->Date = RTC->DAY;
gTime->WeekDay = RTC->WEEK;
gTime->Month = RTC->MON;
gTime->Year = RTC->YEAR;
}
/**
* @brief Interrupt configure.
* @param INTMask: can use the ¡®|¡¯ operator
RTC_INT_CEILLE
RTC_INT_ACDONE
RTC_INT_WKUCNT
RTC_INT_MIDNIGHT
RTC_INT_WKUHOUR
RTC_INT_WKUMIN
RTC_INT_WKUSEC
RTC_INT_TIMEILLE
NewState:
ENABLE
DISABLE
* @retval None
*/
void RTC_INTConfig(uint32_t INTMask, uint32_t NewState)
{
uint32_t tmp;
/* Parameter check */
assert_parameters(IS_RTC_INT(INTMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = RTC->INTEN;
tmp &= ~(0x1UL);
if (NewState == ENABLE)
tmp |= INTMask;
else
tmp &= ~INTMask;
RTC->INTEN = tmp;
}
/**
* @brief Get interrupt status.
* @param INTMask:
RTC_INTSTS_CEILLE
RTC_INTSTS_ACDONE
RTC_INTSTS_WKUCNT
RTC_INTSTS_MIDNIGHT
RTC_INTSTS_WKUHOUR
RTC_INTSTS_WKUMIN
RTC_INTSTS_WKUSEC
RTC_INTSTS_TIMEILLE
* @retval 1: status set
0: status reset.
*/
uint8_t RTC_GetINTStatus(uint32_t FlagMask)
{
/* Parameter check */
assert_parameters(IS_RTC_INTFLAGR(FlagMask));
if (RTC->INTSTS&FlagMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear interrupt status.
* @param INTMask: can use the ¡®|¡¯ operator
RTC_INTSTS_CEILLE
RTC_INTSTS_ACDONE
RTC_INTSTS_WKUCNT
RTC_INTSTS_MIDNIGHT
RTC_INTSTS_WKUHOUR
RTC_INTSTS_WKUMIN
RTC_INTSTS_WKUSEC
RTC_INTSTS_TIMEILLE
* @retval None
*/
void RTC_ClearINTStatus(uint32_t FlagMask)
{
/* Parameter check */
assert_parameters(IS_RTC_INTFLAGC(FlagMask));
RTC->INTSTS = FlagMask;
}
/**
* @brief Fills each RTCAC_InitStruct member with its default value.
* @param RTCAC_InitStruct: pointer to an RTC_AutCalType structure which will be initialized.
* @retval None
*/
void RTC_AutoCalStructInit(RTC_AutCalType *RTCAC_InitStruct)
{
/*------------ Reset RTC AutCal init structure parameters values -----------*/
/* Initialize the ADCSource member */
RTCAC_InitStruct->ADCSource = RTC_ADCS_DATA;
/* Initialize the ATClockSource member */
RTCAC_InitStruct->ATClockSource = RTC_ATCS_DISABLE;
/* Initialize the ATDelay member */
RTCAC_InitStruct->ATDelay = RTC_ATDELAY_15MS;
/* Initialize the Period member */
RTCAC_InitStruct->Period = 0;
}
/**
* @brief Auto calibration initialization.
* @param InitStruct: pointer to AutoCal_InitType Auto calibration configuration.
* ATDelay:
* RTC_ATDELAY_15MS
* RTC_ATDELAY_31MS
* RTC_ATDELAY_62MS
* RTC_ATDELAY_125MS
* ATClockSource:
* RTC_ATCS_DISABLE
* RTC_ATCS_SEC
* RTC_ATCS_MIN
* RTC_ATCS_HOUR
* ADCSource:
* RTC_ADCS_DATA
* RTC_ADCS_PORT
* Period: 0 ~ 63
* @note Auto trigger period is (Period+1)*1, unit is set by ATClockSource.
* Auto trigger function is not valid when ATClockSource is RTC_ATCS_DISABLE.
* @retval None
*/
void RTC_AutoCalInit(RTC_AutCalType *InitStruct)
{
uint32_t tmp;
/* Parameter check */
assert_parameters(IS_RTC_AUTOCAL_ATDLY(InitStruct->ATDelay));
assert_parameters(IS_RTC_AUTOCAL_ATCS(InitStruct->ATClockSource));
assert_parameters(IS_RTC_AUTOCAL_ADCSRC(InitStruct->ADCSource));
assert_parameters(IS_RTC_AUTOCAL_PERIOD(InitStruct->Period));
tmp = RTC->ACCTRL;
tmp &= ~(RTC_ACCTRL_ACPER\
|RTC_ACCTRL_ACDEL\
|RTC_ACCTRL_ACCLK\
|RTC_ACCTRL_ADCSEL);
tmp |= (InitStruct->ADCSource\
|InitStruct->ATClockSource\
|InitStruct->ATDelay\
|((InitStruct->Period << RTC_ACCTRL_ACPER_Pos) & RTC_ACCTRL_ACPER));
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
RTC->ACCTRL = tmp;
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/**
* @brief RTC automatic calibration auto-trigger source configure.
* @param TrigSource:
* RTC_ATCS_DISABLE
* RTC_ATCS_SEC
* RTC_ATCS_MIN
* RTC_ATCS_HOUR
* Period: 0 ~ 63
* @retval None
*/
void RTC_TrigSourceConfig(uint32_t TrigSource, uint32_t Period)
{
uint32_t tmp;
/* Parameter check */
assert_parameters(IS_RTC_AUTOCAL_ATCS(TrigSource));
assert_parameters(IS_RTC_AUTOCAL_PERIOD(Period));
tmp = RTC->ACCTRL;
tmp &= ~(RTC_ACCTRL_ACPER | RTC_ACCTRL_ACCLK);
tmp |= (TrigSource | (Period << RTC_ACCTRL_ACPER_Pos));
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
RTC->ACCTRL = tmp;
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/**
* @brief ADC Auto-calibration enable control.
* @note When DISABLE is selected, the automatic triggering of the RTC-auto-calibration must be turned off by calling
* RTC_TrigSourceConfig(RTC_ATCS_DISABLE, 0) before using this function.
* @param NewState:
* ENABLE
* DISABLE
* @retval 0: Function succeeded
* 1: Function failded, the automatic triggering be enabled when DISABLE selected
*/
uint32_t RTC_AutoCalCmd(uint32_t NewState)
{
uint32_t tmp;
/* Parameter check */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = RTC->ACCTRL;
if (NewState == DISABLE)
{
if (tmp & RTC_ACCTRL_ACCLK)
return 1;
else
tmp &= ~RTC_ACCTRL_ACEN;
}
else
{
tmp |= RTC_ACCTRL_ACEN;
}
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
RTC->ACCTRL = tmp;
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
return 0;
}
/**
* @brief Start RTC Auto-calibration manually.
* @param None
* @retval None
*/
void RTC_StartAutoCalManual(void)
{
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
/* manual trigger Auto-calibration */
RTC->ACCTRL |= RTC_ACCTRL_MANU;
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/**
* @brief Wait until Auto-calibration manual is done.
* @param None
* @retval None
*/
void RTC_WaitForAutoCalManual(void)
{
while (RTC->ACCTRL&RTC_ACCTRL_MANU)
{
}
}
/**
* @brief Get auto-calibration busy flag.
* @param None
* @retval 1 flag set
* 0 flag reset.
*/
uint8_t RTC_GetACBusyFlag(void)
{
if (RTC->INTSTS & RTC_INTSTS_ACBSY) return (1);
else return (0);
}
/*
* @brief Multi-second wake up configure.
* @param nPeriod£ºN seconds interval.
* @note For the first interrupt generated by calling this function, it may
* have < 1 sec error if the new WKUSEC number(parameter) is not equal
* to current WKUSEC number. If the new WKUSEC is equal to current WKUSEC,
* the first interrupt time may have 0~(WKUSEC +1) variation.
* To avoid this problem, set an alternative parameter (like 1) by calling
* this function, then set the correct parameter to it.
* @retval None
*/
void RTC_WKUSecondsConfig(uint8_t nPeriod)
{
/* Parameter check */
assert_parameters(IS_RTC_WKUSEC_PERIOD(nPeriod));
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
/* Write registers */
RTC->WKUSEC = nPeriod - 1;
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/*
* @brief Multi-minute wake up configure.
* @param nPeriod£ºN minute interval.
* @note For the first interrupt generated by calling this function, it may
* have < 1 min error if the new WKUMIN number(parameter) is not equal
* to current WKUMIN number. If the new WKUMIN is equal to current WKUMIN,
* the first interrupt time may have 0~(WKUMIN +1) variation.
* To avoid this problem, set an alternative parameter (like 1) by calling
* this function, then set the correct parameter to it.
* @retval None
*/
void RTC_WKUMinutesConfig(uint8_t nPeriod)
{
/* Parameter check */
assert_parameters(IS_RTC_WKUMIN_PERIOD(nPeriod));
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
/* Write registers */
RTC->WKUMIN = nPeriod - 1;
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/*
* @brief Multi-hour wake up configure.
* @param nPeriod£ºN hour interval.
* @note For the first interrupt generated by calling this function, it may
* have < 1 hour error if the new WKUHOUR number(parameter) is not equal
* to current WKUHOUR number. If the new WKUHOUR is equal to current WKUHOUR,
* the first interrupt time may have 0~(WKUHOUR +1) variation.
* To avoid this problem, set an alternative parameter (like 1) by calling
* this function, then set the correct parameter to it.
* @retval None
*/
void RTC_WKUHoursConfig(uint8_t nPeriod)
{
/* Parameter check */
assert_parameters(IS_RTC_WKUHOUR_PERIOD(nPeriod));
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
/* Write registers */
RTC->WKUHOUR = nPeriod - 1;
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/**
* @brief RTC counter wake up configure.
* @param nClock: 1 ~ 0x1000000
CNTCLK:
RTC_WKUCNT_RTCCLK
RTC_WKUCNT_2048
RTC_WKUCNT_512
RTC_WKUCNT_128
* @retval None
*/
void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK)
{
/* Parameter check */
assert_parameters(IS_RTC_WKUCNT_PERIOD(nClock));
assert_parameters(IS_RTC_WKUCNT_CNTSEL(CNTCLK));
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
/* Write registers */
RTC->WKUCNT = (CNTCLK & RTC_WKUCNT_CNTSEL) | (nClock -1 );
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/**
* @brief Gets RTC wake-up counter value.
* @retval RTC wake-up counter value
*/
uint32_t RTC_GetWKUCounterValue(void)
{
return RTC->WKUCNTR;
}
/**
* @brief RTC clock prescaler configure.
* @param[in] Prescaler:
* RTC_CLKDIV_1
* RTC_CLKDIV_4
* @retval None
*/
void RTC_PrescalerConfig(uint32_t Prescaler)
{
uint32_t tmp;
/* Parameter check */
assert_parameters(IS_RTC_CLKDIV(Prescaler));
tmp = RTC->PSCA;
tmp &= ~RTC_PSCA_PSCA;
tmp |= Prescaler;
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
RTC->PSCA = tmp;
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
}
/**
* @brief RTC PLLDIV frequency configure.
* @param nfrequency(HZ): the frequency of RTC PLLDIV output configuration.
* @note Ensure clocks be configured by calling function CLK_ClockConfig(),
* get correct PCLK frequency by calling function CLK_GetPCLKFreq().
* @retval None
*/
void RTC_PLLDIVConfig(uint32_t nfrequency)
{
RTC->DIV = CLK_GetPCLKFreq()/2/nfrequency - 1;
}
/**
* @brief RTC PLLDIV output enable.
* @param NewState:
* ENABLE
* DISABLE
* @retval None
*/
void RTC_PLLDIVOutputCmd(uint8_t NewState)
{
/* Parameter check */
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE) RTC->CTL |= RTC_CTL_RTCPLLOE;
else RTC->CTL &= ~RTC_CTL_RTCPLLOE;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_spi.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief SPI library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_spi.h"
#define SPI_MISC_RSTValue (0UL)
/**
* @brief Reset SPI controller.
* @param SPIx:SPI1~SPI2
* @retval None
*/
void SPI_DeviceInit(SPI_TypeDef *SPIx)
{
__IO uint32_t dummy_data = 0UL;
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
/* Disable SPI */
SPIx->CTRL = 0;
/* SPI soft reset */
SPIx->CTRL |= SPI_CTRL_SPIRST;
SPIx->CTRL &= ~SPI_CTRL_SPIRST;
/* Clear flag */
dummy_data = SPIx->RXDAT;
dummy_data += 1;
SPIx->TXSTS = SPI_TXSTS_TXIF;
SPIx->RXSTS = SPI_RXSTS_RXIF;
/* write default values */
SPIx->MISC_ = SPI_MISC_RSTValue;
}
/**
* @brief Fills each SPI_InitType member with its default value.
* @param InitStruct: pointer to an SPI_InitType structure which will be initialized.
* @retval None
*/
void SPI_StructInit(SPI_InitType *InitStruct)
{
/*--------------- Reset SPI init structure parameters values ---------------*/
/* Initialize the ClockDivision member */
InitStruct->ClockDivision = SPI_CLKDIV_2;
/* Initialize the CSNSoft member */
InitStruct->CSNSoft = SPI_CSNSOFT_DISABLE;
/* Initialize the Mode member */
InitStruct->Mode = SPI_MODE_MASTER;
/* Initialize the SPH member */
InitStruct->SPH = SPI_SPH_0;
/* Initialize the SPO member */
InitStruct->SPO = SPI_SPO_0;
/* Initialize the SWAP member */
InitStruct->SWAP = SPI_SWAP_DISABLE;
}
/**
* @brief SPI initialization.
* @param SPIx:SPI1~SPI2
InitStruct: SPI configuration.
Mode:
SPI_MODE_MASTER
SPI_MODE_SLAVE
SPH:
SPI_SPH_0
SPI_SPH_1
SPO:
SPI_SPO_0
SPI_SPO_1
ClockDivision:
SPI_CLKDIV_2
SPI_CLKDIV_4
SPI_CLKDIV_8
SPI_CLKDIV_16
SPI_CLKDIV_32
SPI_CLKDIV_64
SPI_CLKDIV_128
CSNSoft:
SPI_CSNSOFT_ENABLE
SPI_CSNSOFT_DISABLE
SWAP:
SPI_SWAP_ENABLE
SPI_SWAP_DISABLE
* @retval None
*/
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitType *InitStruct)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
assert_parameters(IS_SPI_MODE(InitStruct->Mode));
assert_parameters(IS_SPI_SPH(InitStruct->SPH));
assert_parameters(IS_SPI_SPO(InitStruct->SPO));
assert_parameters(IS_SPI_CLKDIV(InitStruct->ClockDivision));
assert_parameters(IS_SPI_CSN(InitStruct->CSNSoft));
assert_parameters(IS_SPI_SWAP(InitStruct->SWAP));
tmp = SPIx->CTRL;
tmp &= ~(SPI_CTRL_MOD\
|SPI_CTRL_SCKPHA\
|SPI_CTRL_SCKPOL\
|SPI_CTRL_CSGPIO\
|SPI_CTRL_SWAP\
|SPI_CTRL_SCKSEL);
tmp |= (InitStruct->Mode\
|InitStruct->SPH\
|InitStruct->SPO\
|InitStruct->CSNSoft\
|InitStruct->SWAP\
|InitStruct->ClockDivision);
SPIx->CTRL = tmp;
}
/**
* @brief Enables or disables SPI.
* @param SPIx:SPI1~SPI2
NewState:
ENABLE
DISABLE
* @retval None
*/
void SPI_Cmd(SPI_TypeDef *SPIx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
SPIx->CTRL |= SPI_CTRL_SPIEN;
else
SPIx->CTRL &= ~SPI_CTRL_SPIEN;
}
/**
* @brief SPI interrupt config.
* @param SPIx:SPI1~SPI2
INTMask: can use the ¡®|¡¯ operator
SPI_INT_TX
SPI_INT_RX
NewState:
ENABLE
DISABLE
* @retval None
*/
void SPI_INTConfig(SPI_TypeDef *SPIx, uint32_t INTMask, uint32_t NewState)
{
uint32_t tmp, tmp_INTMask;
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
assert_parameters(IS_SPI_INT(INTMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp_INTMask = INTMask;
if (tmp_INTMask & 0x80000000)
{
INTMask &= 0xFFFF;
tmp = SPIx->TXSTS;
tmp &= ~SPI_TXSTS_TXIF;
if (NewState == ENABLE)
{
tmp |= INTMask;
SPIx->TXSTS = tmp;
}
else
{
tmp &= ~INTMask;
SPIx->TXSTS = tmp;
}
}
if (tmp_INTMask & 0x40000000)
{
INTMask &= 0xFFFF;
tmp = SPIx->RXSTS;
tmp &= ~SPI_RXSTS_RXIF;
if (NewState == ENABLE)
{
tmp |= INTMask;
SPIx->RXSTS = tmp;
}
else
{
tmp &= ~INTMask;
SPIx->RXSTS = tmp;
}
}
}
/**
* @brief Get status flag.
* @param SPIx:SPI1~SPI2
Status:
SPI_STS_TXIF
SPI_STS_TXEMPTY
SPI_STS_TXFUR
SPI_STS_RXIF
SPI_STS_RXFULL
SPI_STS_RXFOV
SPI_STS_BSY
SPI_STS_RFF
SPI_STS_RNE
SPI_STS_TNF
SPI_STS_TFE
* @retval Flag status.
*/
uint8_t SPI_GetStatus(SPI_TypeDef *SPIx, uint32_t Status)
{
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
assert_parameters(IS_SPI_STSR(Status));
if ((Status&0xE0000000) == 0x80000000)
{
if (Status&SPIx->TXSTS)
return 1;
else
return 0;
}
else if ((Status&0xE0000000) == 0x40000000)
{
if (Status&SPIx->RXSTS)
return 1;
else
return 0;
}
else
{
if (Status&SPIx->MISC_)
return 1;
else
return 0;
}
}
/**
* @brief Clear status flag.
* @param SPIx:SPI1~SPI2
Status: can use the ¡®|¡¯ operator
SPI_STS_TXIF
SPI_STS_RXIF
* @retval None
*/
void SPI_ClearStatus(SPI_TypeDef *SPIx, uint32_t Status)
{
uint32_t tmp_status;
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
assert_parameters(IS_SPI_STSC(Status));
tmp_status = Status;
if (tmp_status & 0x80000000)
{
Status &= 0xFFFF;
SPIx->TXSTS |= Status;
}
if (tmp_status & 0x40000000)
{
Status &= 0xFFFF;
SPIx->RXSTS |= Status;
}
}
/**
* @brief Load send data register.
* @param SPIx:SPI1~SPI2
ch: data write to send data register
* @retval None
*/
void SPI_SendData(SPI_TypeDef *SPIx, uint8_t ch)
{
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
SPIx->TXDAT = ch;
}
/**
* @brief Read receive data register.
* @param SPIx:SPI1~SPI2
* @retval receive data value
*/
uint8_t SPI_ReceiveData(SPI_TypeDef *SPIx)
{
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
return (SPIx->RXDAT);
}
/**
* @brief Transmit fifo level configure.
* @param SPIx:SPI1~SPI2
FIFOLevel:
SPI_TXFLEV_0
SPI_TXFLEV_1
SPI_TXFLEV_2
SPI_TXFLEV_3
SPI_TXFLEV_4
SPI_TXFLEV_5
SPI_TXFLEV_6
SPI_TXFLEV_7
* @retval None
*/
void SPI_TransmitFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
assert_parameters(IS_SPI_TXFLEV(FIFOLevel));
tmp = SPIx->TXSTS;
tmp &= ~(SPI_TXSTS_TXFLEV | SPI_TXSTS_TXIF);
tmp |= FIFOLevel;
SPIx->TXSTS = tmp;
}
/**
* @brief Receive fifo level configure.
* @param SPIx:SPI1~SPI2
FIFOLevel:
SPI_RXFLEV_0
SPI_RXFLEV_1
SPI_RXFLEV_2
SPI_RXFLEV_3
SPI_RXFLEV_4
SPI_RXFLEV_5
SPI_RXFLEV_6
SPI_RXFLEV_7
* @retval None
*/
void SPI_ReceiveFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
assert_parameters(IS_SPI_RXFLEV(FIFOLevel));
tmp = SPIx->RXSTS;
tmp &= ~(SPI_RXSTS_RXFLEV | SPI_RXSTS_RXIF);
tmp |= FIFOLevel;
SPIx->RXSTS = tmp;
}
/**
* @brief Get transmit fifo level.
* @param SPIx:SPI1~SPI2
* @retval Transmit fifo level.
*/
uint8_t SPI_GetTransmitFIFOLevel(SPI_TypeDef *SPIx)
{
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
return (SPIx->TXSTS & SPI_TXSTS_TXFFLAG);
}
/**
* @brief Get receive fifo level.
* @param SPIx:SPI1~SPI2
* @retval Receive fifo level.
*/
uint8_t SPI_GetReceiveFIFOLevel(SPI_TypeDef *SPIx)
{
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
return (SPIx->RXSTS & SPI_RXSTS_RXFFLAG);
}
/**
* @brief FIFO smart mode.
* @param SPIx:SPI1~SPI2
NewState:
ENABLE
DISABLE
* @retval None
*/
void SPI_SmartModeCmd(SPI_TypeDef *SPIx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
SPIx->MISC_ |= SPI_MISC_SMART;
}
else
{
SPIx->MISC_ &= ~SPI_MISC_SMART;
}
}
/**
* @brief FIFO over write mode.
* @param SPIx:SPI1~SPI2
NewState:
ENABLE
DISABLE
* @retval None
*/
void SPI_OverWriteModeCmd(SPI_TypeDef *SPIx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_SPI_ALL_INSTANCE(SPIx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
SPIx->MISC_ |= SPI_MISC_OVER;
}
else
{
SPIx->MISC_ &= ~SPI_MISC_OVER;
}
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_tmr.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Timer library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_tmr.h"
#define TMR_CTRL_RSTValue (0UL)
#define TMR_VALUE_RSTValue (0UL)
#define TMR_RELOAD_RSTValue (0UL)
/**
* @brief Initializes the TMRx peripheral registers to their default reset values.
* @param TMRx:
TMR0 ~ TMR3
* @retval None
*/
void TMR_DeInit(TMR_TypeDef *TMRx)
{
/* Check parameters */
assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
/* Disable timer */
TMRx->CTRL &= ~TMR_CTRL_EN;
/* clear interrupt status */
TMRx->INT = TMR_INT_INT;
/* write default reset values */
TMRx->CTRL = TMR_CTRL_RSTValue;
TMRx->RELOAD = TMR_RELOAD_RSTValue;
TMRx->VALUE = TMR_VALUE_RSTValue;
}
/**
* @brief TMR initialization.
* @param TMRx:
TMR0 ~ TMR3
InitStruct: Timer configuration.
ClockSource:
TMR_CLKSRC_INTERNAL
TMR_CLKSRC_EXTERNAL
EXTGT:
TMR_EXTGT_DISABLE
TMR_EXTGT_ENABLE
Period: the auto-reload value
* @retval None
*/
void TMR_Init(TMR_TypeDef *TMRx, TMR_InitType *InitStruct)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
assert_parameters(IS_TMR_CLKSRC(InitStruct->ClockSource));
assert_parameters(IS_TMR_EXTGT(InitStruct->EXTGT));
tmp = TMRx->CTRL;
tmp &= ~(TMR_CTRL_EXTCLK|TMR_CTRL_EXTEN);
tmp |= (InitStruct->ClockSource|InitStruct->EXTGT);
TMRx->CTRL = tmp;
TMRx->VALUE = InitStruct->Period;
TMRx->RELOAD = InitStruct->Period;
}
/**
* @brief Fills each TMR_InitType member with its default value.
* @param InitStruct: pointer to an TMR_InitType structure which will be initialized.
* @retval None
*/
void TMR_StructInit(TMR_InitType *InitStruct)
{
/*--------------- Reset TMR init structure parameters values ---------------*/
/* Initialize the ClockSource member */
InitStruct->ClockSource = TMR_CLKSRC_INTERNAL;
/* Initialize the EXTGT member */
InitStruct->EXTGT = TMR_EXTGT_DISABLE;
/* Initialize the Period member */
InitStruct->Period = 0;
}
/**
* @brief Interrupt configuration.
* @param TMRx:
TMR0~TMR3
NewState:
ENABLE
DISABLE
* @retval None
*/
void TMR_INTConfig(TMR_TypeDef *TMRx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
TMRx->CTRL |= TMR_CTRL_INTEN;
}
else
{
TMRx->CTRL &= ~TMR_CTRL_INTEN;
}
}
/**
* @brief Get timer interrupt status.
* @param TMRx:
TMR0~TMR3
* @retval Interrupt status.
*/
uint8_t TMR_GetINTStatus(TMR_TypeDef *TMRx)
{
/* Check parameters */
assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
if (TMRx->INT&TMR_INT_INT)
return 1;
else
return 0;
}
/**
* @brief Clear timer interrupt status bit.
* @param TMRx:
TMR0~TMR3
* @retval None.
*/
void TMR_ClearINTStatus(TMR_TypeDef *TMRx)
{
/* Check parameters */
assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
TMRx->INT = TMR_INT_INT;
}
/**
* @brief TMRER enable.
* @param TMRx:
TMR0~TMR3
NewState:
ENABLE
DISABLE
* @retval None
*/
void TMR_Cmd(TMR_TypeDef *TMRx, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
TMRx->CTRL |= TMR_CTRL_EN;
else
TMRx->CTRL &= ~TMR_CTRL_EN;
}
/**
* @brief Get TMRx current value.
* @param TMRx:
TMR0~TMR3
* @retval timer value.
*/
uint32_t TMR_GetCurrentValue(TMR_TypeDef *TMRx)
{
/* Check parameters */
assert_parameters(IS_TMR_ALL_INSTANCE(TMRx));
return (TMRx->VALUE);
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_u32k.c
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief UART 32K library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_u32k.h"
#define U32K_STS_Msk (0x7UL)
#define U32K_CTRL0_RSTValue (0UL)
#define U32K_CTRL1_RSTValue (0UL)
#define U32K_PHASE_RSTValue (0x4B00UL)
/**
* @brief Initializes the U32Kx peripheral registers to their default reset
values.
* @param U32Kx: U32K0~U32K1
* @retval None
*/
void U32K_DeInit(U32K_TypeDef *U32Kx)
{
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
/* Disable U32K */
U32Kx->CTRL0 &= ~U32K_CTRL0_EN;
/* clear interrupt status */
U32Kx->STS = U32K_STS_Msk;
/* write default reset values */
U32Kx->CTRL0 = U32K_CTRL0_RSTValue;
U32Kx->CTRL1 = U32K_CTRL1_RSTValue;
U32Kx->PHASE = U32K_PHASE_RSTValue;
}
/**
* @brief U32K initialization.
* @param U32Kx:
U32K0~U32K1
InitStruct: U32K configuration
Debsel:
U32K_DEBSEL_0
U32K_DEBSEL_1
U32K_DEBSEL_2
U32K_DEBSEL_3
Parity:
U32K_PARITY_EVEN
U32K_PARITY_ODD
U32K_PARITY_0
U32K_PARITY_1
U32K_PARITY_NONE
WordLen:
U32K_WORDLEN_8B
U32K_WORDLEN_9B
FirstBit:
U32K_FIRSTBIT_LSB
U32K_FIRSTBIT_MSB
AutoCal:
U32K_AUTOCAL_ON
U32K_AUTOCAL_OFF
LineSel:
U32K_LINE_RX0
U32K_LINE_RX1
U32K_LINE_RX2
U32K_LINE_RX3
Baudrate: Baudrate value
* @retval None
*/
void U32K_Init(U32K_TypeDef *U32Kx, U32K_InitType *InitStruct)
{
uint32_t tmp_reg1, tmp_reg2;
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
assert_parameters(IS_U32K_DEBSEL(InitStruct->Debsel));
assert_parameters(IS_U32K_PARITY(InitStruct->Parity));
assert_parameters(IS_U32K_WORDLEN(InitStruct->WordLen));
assert_parameters(IS_U32K_FIRSTBIT(InitStruct->FirstBit));
assert_parameters(IS_U32K_AUTOCAL(InitStruct->AutoCal));
assert_parameters(IS_U32K_LINE(InitStruct->LineSel));
assert_parameters(IS_U32K_BAUDRATE(InitStruct->Baudrate));
tmp_reg1 = U32Kx->CTRL0;
tmp_reg1 &= ~(U32K_CTRL0_DEBSEL\
|U32K_CTRL0_PMODE\
|U32K_CTRL0_MODE\
|U32K_CTRL0_MSB\
|U32K_CTRL0_ACOFF);
tmp_reg1 |= (InitStruct->Debsel\
|InitStruct->Parity\
|InitStruct->WordLen\
|InitStruct->FirstBit\
|InitStruct->AutoCal);
U32Kx->CTRL0 = tmp_reg1;
if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz
U32Kx->PHASE = 65536*InitStruct->Baudrate/32768;
else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz
U32Kx->PHASE = 65536*InitStruct->Baudrate/8192;
else
assert_parameters(0);
tmp_reg2 = U32Kx->CTRL1;
tmp_reg2 &= ~(U32K_CTRL1_RXSEL);
tmp_reg2 |= (InitStruct->LineSel);
U32Kx->CTRL1 = tmp_reg2;
}
/**
* @brief Fills each U32K_InitType member with its default value.
* @param InitStruct: pointer to an U32K_InitType structure which will be initialized.
* @retval None
*/
void U32K_StructInit(U32K_InitType *InitStruct)
{
/*-------------- Reset U32K init structure parameters values ---------------*/
/* Initialize the AutoCal member */
InitStruct->AutoCal = U32K_AUTOCAL_ON;
/* Initialize the Baudrate member */
InitStruct->Baudrate = 9600;
/* Initialize the Debsel member */
InitStruct->Debsel = U32K_DEBSEL_0;
/* Initialize the FirstBit member */
InitStruct->FirstBit = U32K_FIRSTBIT_LSB;
/* Initialize the LineSel member */
InitStruct->LineSel = U32K_LINE_RX0;
/* Initialize the Parity member */
InitStruct->Parity = U32K_PARITY_NONE;
/* Initialize the Parity member */
InitStruct->WordLen = U32K_WORDLEN_8B;
}
/**
* @brief U32K interrupt configuration.
* @param U32Kx:
U32K0~U32K1
INTMask: can use the ¡®|¡¯ operator
U32K_INT_RXOV
U32K_INT_RXPE
U32K_INT_RX
NewState:
ENABLE
DISABLE
* @retval None
*/
void U32K_INTConfig(U32K_TypeDef *U32Kx, uint32_t INTMask, uint8_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
assert_parameters(IS_U32K_INT(INTMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = U32Kx->CTRL1;
tmp &= ~INTMask;
if (NewState == ENABLE)
{
tmp |= INTMask;
}
U32Kx->CTRL1 = tmp;
}
/**
* @brief Get interrupt flag status.
* @param U32Kx:
U32K0~U32K1
INTMask:
U32K_INTSTS_RXOV
U32K_INTSTS_RXPE
U32K_INTSTS_RX
* @retval Flag status
*/
uint8_t U32K_GetINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask)
{
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
assert_parameters(IS_U32K_INTFLAGR(INTMask));
if (U32Kx->STS&INTMask)
return 1;
else
return 0;
}
/**
* @brief Clear flag status.
* @param U32Kx:
U32K0~U32K1
INTMask: can use the ¡®|¡¯ operator
U32K_INTSTS_RXOV
U32K_INTSTS_RXPE
U32K_INTSTS_RX
* @retval None
*/
void U32K_ClearINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask)
{
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
assert_parameters(IS_U32K_INTFLAGC(INTMask));
U32Kx->STS = INTMask;
}
/**
* @brief Read receive data register.
* @param U32Kx:
U32K0~U32K1
* @retval Receive data value
*/
uint8_t U32K_ReceiveData(U32K_TypeDef *U32Kx)
{
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
return (U32Kx->DATA);
}
/**
* @brief U32K Baudrate control.
* @param U32Kx: U32K0~U32K1
BaudRate: Baudrate value
* @retval None
*/
void U32K_BaudrateConfig(U32K_TypeDef *U32Kx, uint32_t BaudRate)
{
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
assert_parameters(IS_U32K_BAUDRATE(BaudRate));
if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz
U32Kx->PHASE = 65536*BaudRate/32768;
else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz
U32Kx->PHASE = 65536*BaudRate/8192;
else
assert_parameters(0);
}
/**
* @brief U32K controlller enable.
* @param U32Kx:
U32K0~U32K1
NewState:
ENABLE
DISABLE
* @retval None
*/
void U32K_Cmd(U32K_TypeDef *U32Kx, uint32_t NewState)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
tmp = U32Kx->CTRL0;
tmp &= ~(U32K_CTRL0_EN);
if (NewState == ENABLE)
{
tmp |= U32K_CTRL0_EN;
}
U32Kx->CTRL0 = tmp;
}
/**
* @brief U32K receive line selection.
* @param U32Kx:
U32K0~U32K1
Line:
U32K_LINE_RX0
U32K_LINE_RX1
U32K_LINE_RX2
U32K_LINE_RX3
* @retval None
*/
void U32K_LineConfig(U32K_TypeDef *U32Kx, uint32_t Line)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
assert_parameters(IS_U32K_LINE(Line));
tmp = U32Kx->CTRL1;
tmp &= ~U32K_CTRL1_RXSEL;
tmp |= Line;
U32Kx->CTRL1 = tmp;
}
/**
* @brief Wake-up mode configure.
* @param U32Kx:
U32K0~U32K1
WKUMode:
U32K_WKUMOD_RX
U32K_WKUMOD_PC
* @retval None
*/
void U32K_WKUModeConfig(U32K_TypeDef *U32Kx, uint32_t WKUMode)
{
uint32_t tmp;
/* Check parameters */
assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx));
assert_parameters(IS_U32K_WKUMODE(WKUMode));
tmp = U32Kx->CTRL0;
tmp &= ~U32K_CTRL0_WKUMODE;
tmp |= WKUMode;
U32Kx->CTRL0 = tmp;
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_uart.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief UART library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_uart.h"
#include "lib_clk.h"
#define UART_STATE_RCMsk (0x3CUL)
#define UART_INTSTS_RCMsk (0x3FUL)
#define UART_BAUDDIV_RSTValue (0UL)
#define UART_CTRL_RSTValue (0UL)
#define UART_CTRL2_RSTValue (0UL)
/**
* @brief Iinitializes the UARTx peripheral registers to their default reset
values.
* @param UARTx: UART0~UART5
* @retval None
*/
void UART_DeInit(UART_TypeDef *UARTx)
{
__IO uint32_t dummy_data = 0UL;
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
/* read data, clear RXFULL flag */
dummy_data = UARTx->DATA;
dummy_data += 1;
UARTx->INTSTS = UART_INTSTS_RCMsk;
UARTx->STATE = UART_STATE_RCMsk;
UARTx->BAUDDIV = UART_BAUDDIV_RSTValue;
UARTx->CTRL2 = UART_CTRL2_RSTValue;
UARTx->CTRL = UART_CTRL_RSTValue;
}
/**
* @brief UART initialization.
* @param UARTx: UART0~UART5
InitStruct:UART configuration.
Mode: (between UART_MODE_RX and UART_MODE_TX, can use the ¡®|¡¯ operator)
UART_MODE_RX
UART_MODE_TX
UART_MODE_OFF
Parity:
UART_PARITY_EVEN
UART_PARITY_ODD
UART_PARITY_0
UART_PARITY_1
UART_PARITY_NONE
WordLen:
UART_WORDLEN_8B
UART_WORDLEN_9B
FirstBit:
UART_FIRSTBIT_LSB
UART_FIRSTBIT_MSB
Baudrate: Baudrate value
* @retval None
*/
void UART_Init(UART_TypeDef *UARTx, UART_InitType *InitStruct)
{
uint32_t pclk;
uint32_t div;
uint32_t tmp_reg1, tmp_reg2;
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
assert_parameters(IS_UART_MODE(InitStruct->Mode));
assert_parameters(IS_UART_PARITY(InitStruct->Parity));
assert_parameters(IS_UART_WORDLEN(InitStruct->WordLen));
assert_parameters(IS_UART_FIRSTBIT(InitStruct->FirstBit));
assert_parameters(IS_UART_BAUDRATE(InitStruct->Baudrate));
tmp_reg1 = UARTx->CTRL;
tmp_reg1 &= ~(UART_CTRL_RXEN\
|UART_CTRL_TXEN);
tmp_reg1 |= (InitStruct->Mode);
tmp_reg2 = UARTx->CTRL2;
tmp_reg2 &= ~(UART_CTRL2_MSB \
|UART_CTRL2_MODE \
|UART_CTRL2_PMODE);
tmp_reg2 |= (InitStruct->Parity\
|InitStruct->WordLen\
|InitStruct->FirstBit);
UARTx->CTRL2 = tmp_reg2;
pclk = CLK_GetPCLKFreq();
div = pclk/InitStruct->Baudrate;
if ((pclk%InitStruct->Baudrate) > (InitStruct->Baudrate/2))
{
div++;
}
UARTx->BAUDDIV = div;
UARTx->CTRL = tmp_reg1;
}
/**
* @brief Fills each UART_InitType member with its default value.
* @param InitStruct: pointer to an UART_InitType structure which will be initialized.
* @retval None
*/
void UART_StructInit(UART_InitType *InitStruct)
{
/*-------------- Reset UART init structure parameters values ---------------*/
/* Initialize the Baudrate member */
InitStruct->Baudrate = 9600;
/* Initialize the FirstBit member */
InitStruct->FirstBit = UART_FIRSTBIT_LSB;
/* Initialize the Mode member */
InitStruct->Mode = UART_MODE_OFF;
/* Initialize the Parity member */
InitStruct->Parity = UART_PARITY_NONE;
/* Initialize the WordLen member */
InitStruct->WordLen = UART_WORDLEN_8B;
}
/**
* @brief Get peripheral flag.
* @param UARTx: UART0~UART5
FlagMask: flag to get.
--UART_FLAG_RXPARITY
--UART_FLAG_TXDONE
--UART_FLAG_RXPE
--UART_FLAG_RXOV
--UART_FLAG_TXOV
--UART_FLAG_RXFULL
* @retval 1:flag set
0:flag reset
*/
uint8_t UART_GetFlag(UART_TypeDef *UARTx, uint32_t FlagMask)
{
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
assert_parameters(IS_UART_FLAGR(FlagMask));
if (UARTx->STATE&FlagMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear peripheral flag.
* @param UARTx: UART0~UART5
FlagMask: status to clear, can use the ¡®|¡¯ operator.
--UART_FLAG_TXDONE
--UART_FLAG_RXPE
--UART_FLAG_RXOV
--UART_FLAG_TXOV
* @retval None
*/
void UART_ClearFlag(UART_TypeDef *UARTx, uint32_t FlagMask)
{
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
assert_parameters(IS_UART_FLAGC(FlagMask));
UARTx->STATE = FlagMask;
}
/**
* @brief Enable or disable the specified UART interrupts.
* @param UARTx: UART0~UART5
INTMask: can use the ¡®|¡¯ operator.
--UART_INT_TXDONE
--UART_INT_RXPE
--UART_INT_RXOV
--UART_INT_TXOV
--UART_INT_RX
NewState:New status of interrupt mask.
* @retval None
*/
void UART_INTConfig(UART_TypeDef *UARTx, uint32_t INTMask, uint8_t NewState)
{
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
assert_parameters(IS_UART_INT(INTMask));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
UARTx->CTRL |= INTMask;
}
else
{
UARTx->CTRL &= ~INTMask;
}
}
/**
* @brief Get interrupt status.
* @param UARTx: UART0~UART5
INTMask: status to get.
--UART_INTSTS_TXDONE
--UART_INTSTS_RXPE
--UART_INTSTS_RXOV
--UART_INTSTS_TXOV
--UART_INTSTS_RX
* @retval 1:status set
0:status reset
*/
uint8_t UART_GetINTStatus(UART_TypeDef *UARTx, uint32_t INTMask)
{
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
assert_parameters(IS_UART_INTFLAGR(INTMask));
if (UARTx->INTSTS&INTMask)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief Clear interrupt status.
* @param UARTx: UART0~UART5
INTMask: status to clear, can use the ¡®|¡¯ operator.
--UART_INTSTS_TXDONE
--UART_INTSTS_RXPE
--UART_INTSTS_RXOV
--UART_INTSTS_TXOV
--UART_INTSTS_RX
* @retval None
*/
void UART_ClearINTStatus(UART_TypeDef *UARTx, uint32_t INTMask)
{
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
assert_parameters(IS_UART_INTFLAGC(INTMask));
UARTx->INTSTS = INTMask;
}
/**
* @brief Load send data register.
* @param UARTx: UART0~USART5
DAT: data to send.
* @retval None
*/
void UART_SendData(UART_TypeDef *UARTx, uint8_t ch)
{
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
UARTx->DATA = ch;
}
/**
* @brief Read receive data register.
* @param UARTx: UART0~UART5
* @retval The received data.
*/
uint8_t UART_ReceiveData(UART_TypeDef *UARTx)
{
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
return UARTx->DATA;
}
/**
* @brief UART Baudrate control.
* @param UARTx: UART0~UART5
BaudRate: Baudrate value
* @retval None
*/
void UART_BaudrateConfig(UART_TypeDef *UARTx, uint32_t BaudRate)
{
uint32_t pclk;
uint32_t div;
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
assert_parameters(IS_UART_BAUDRATE(BaudRate));
pclk = CLK_GetPCLKFreq();
div = pclk/BaudRate;
if ((pclk%BaudRate) > (BaudRate/2))
{
div++;
}
UARTx->BAUDDIV = div;
}
/**
* @brief UART Transmit/Receive enable control.
* @param UARTx: UART0~UART5
Mode:
UART_MODE_RX
UART_MODE_TX
NewState:
ENABLE
DISABLE
* @retval None
*/
void UART_Cmd(UART_TypeDef *UARTx, uint32_t Mode, uint32_t NewState)
{
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
assert_parameters(IS_UART_MODE(Mode));
assert_parameters(IS_FUNCTIONAL_STATE(NewState));
if (NewState == ENABLE)
{
UARTx->CTRL |= Mode;
}
else
{
UARTx->CTRL &= ~Mode;
}
}
/**
* @brief Get UART configure information.
* @param UARTx: UART0~UART5
* ConfigInfo: The pointer of UART configuration.
* @retval None
*/
void UART_GetConfigINFO(UART_TypeDef *UARTx, UART_ConfigINFOType *ConfigInfo)
{
uint32_t tmp1, tmp2, tmp3;
uint32_t pclk;
/* Check parameters */
assert_parameters(IS_UART_ALL_INSTANCE(UARTx));
tmp1 = UARTx->CTRL;
tmp2 = UARTx->BAUDDIV;
pclk = CLK_GetPCLKFreq();
tmp3 = UARTx->CTRL2;
/* Mode_Transmit */
if (tmp1 & UART_CTRL_TXEN)
ConfigInfo->Mode_Transmit = 1;
else
ConfigInfo->Mode_Transmit = 0;
/* Mode_Receive */
if (tmp1 & UART_CTRL_RXEN)
ConfigInfo->Mode_Receive = 1;
else
ConfigInfo->Mode_Receive = 0;
/* Baudrate */
ConfigInfo->Baudrate = pclk / tmp2;
/* LSB/MSB */
if (tmp3 & UART_CTRL2_MSB)
ConfigInfo->FirstBit = 1;
else
ConfigInfo->FirstBit = 0;
/* WordLen */
if (tmp3 & UART_CTRL2_MODE)
ConfigInfo->WordLen = 9;
else
ConfigInfo->WordLen = 8;
/* Parity */
if ((tmp3 & UART_CTRL2_PMODE) == UART_CTRL2_PMODE_0)
ConfigInfo->Parity = 0;
else if ((tmp3 & UART_CTRL2_PMODE) == UART_CTRL2_PMODE_1)
ConfigInfo->Parity = 1;
else if ((tmp3 & UART_CTRL2_PMODE) == UART_CTRL2_PMODE_EVEN)
ConfigInfo->Parity = 2;
else
ConfigInfo->Parity = 3;
}
/*********************************** END OF FILE ******************************/

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/**
*******************************************************************************
* @file lib_version.c
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief Version library.
*******************************************************************************/
#include "lib_version.h"
#define Target_DriveVersion DRIVER_VERSION(4, 7)
/**
* @brief Get Target driver's current version.
* @param None
* @retval Version value
* Bit[15:8] : Major version
* Bit[7:0] : Minor version
*/
uint16_t Target_GetDriveVersion(void)
{
return (Target_DriveVersion);
}
/*********************************** END OF FILE ******************************/

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/**
******************************************************************************
* @file lib_wdt.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief WDT library.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "lib_wdt.h"
#define WDTPASS_KEY 0xAA5555AA
#define WDTCLR_KEY 0x55AAAA55
/**
* @brief Enable WDT timer.
* @param None
* @retval None
*/
void WDT_Enable(void)
{
PMU->WDTPASS = WDTPASS_KEY;
PMU->WDTEN |= PMU_WDTEN_WDTEN;
PMU->WDTPASS = WDTPASS_KEY;
PMU->WDTEN |= PMU_WDTEN_WDTEN;
}
/**
* @brief Disable WDT timer.
* @param None
* @retval None
*/
void WDT_Disable(void)
{
PMU->WDTPASS = WDTPASS_KEY;
PMU->WDTEN &= ~PMU_WDTEN_WDTEN;
PMU->WDTPASS = WDTPASS_KEY;
PMU->WDTEN &= ~PMU_WDTEN_WDTEN;
}
/**
* @brief Clear WDT counter.
* @param None
* @retval None
*/
void WDT_Clear(void)
{
PMU->WDTCLR = WDTCLR_KEY;
}
/**
* @brief Set WDT counting period.
* @param counting period:
WDT_2_SECS
WDT_1_SECS
WDT_0_5_SECS
WDT_0_25_SECS
* @retval None
*/
void WDT_SetPeriod(uint32_t period)
{
uint32_t tmp;
assert_parameters(IS_WDT_PERIOD(period));
tmp = PMU->WDTEN;
tmp &= ~PMU_WDTEN_WDTSEL;
tmp |= period;
PMU->WDTPASS = WDTPASS_KEY;
PMU->WDTEN = tmp;
}
/**
* @brief Get WDT counter value.
* @param None
* @retval current counter value.
*/
uint16_t WDT_GetCounterValue(void)
{
return (PMU->WDTCLR & PMU_WDTCLR_WDTCNT);
}
/*********************************** END OF FILE ******************************/

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# VANGOV85XX-EVAL
## 简介
VANGOV85XX-EVAL是-杭州万高科技推出的一款基于V85XX的评估板，板载资源主要如下：
| 硬件 | 描述 |
| --------- | ------------- |
| 芯片型号 | V8530 |
| CPU | ARM Cortex M0 |
| 主频 | 26M |
| 片内SRAM | 32K |
| 片内FLASH | 256K |
## 数据手册
[产品页面](http://www.vangotech.com/product.php?areas=0&bigs=1&smalls=4&id=14)
[datasheet](http://www.vangotech.com/uploadpic/162798006058.pdf)
## 编译说明
VANGOV85XX-EVAL板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息：
| IDE/编译器 | 已测试版本 |
| ---------- | ---------------------------- |
| GCC |gcc version 6.2.1 20161205 (release) |
## 烧写及执行
供电方式：开发板使用 USB TypeA 接口或者 DC-005 连接器提供 5V 电源。
下载程序：下载程序到开发板需要一套 JLink 或者使用 SD612 工具。
串口连接：使用串口线连接到COM1(UART0)，或者使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)。
### 运行结果
如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build Jan 4 2021
2006 - 2021 Copyright by rt-thread team
msh />
```
## 驱动支持情况及计划
| 驱动 | 支持情况 | 备注 |
| --------- | -------- | :------------------------: |
| UART | 支持 | UART0~4 |
| GPIO | 支持 | GPIOB~F |
| ADC | 未支持 | ADC0~7 |
| HWTIMER | 未支持 | TIMER0~3 |
| RTC | 未支持 | RTC |
| WDT | 未支持 | Free watchdog timer |
| IIC | 未支持 | I2C0 |
| SPI | 未支持 | SPI0~1 |
| LCD | 未支持 | |
| SDRAM | 未支持 | |
| SPI FLASH | 未支持 | |
### IO在板级支持包中的映射情况
| IO号 | 板级包中的定义 |
| ---- | -------------- |
| PC0 | LED1 |
| PC2 | LED2 |
| PE0 | LED3 |
| PE1 | LED4 |
| PA0 | KEY1 |
| PC13 | KEY2 |
| PB14 | KEY3 |
## 联系人信息
维护人：[idk500](https://github.com/idk500)

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# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread-VangoV85xx.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
define symbol __Reset_Handler_text_start__ = 0x000000C0;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

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/*
*****************************************************************************
**
** File : Target_FLASH.ld
**
** Abstract : Linker script for Target Device with
** 256KByte FLASH, 32KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Date : 2019-01-07
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20008000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x400; /* required amount of heap */
_Min_Stack_Size = 0x1000; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector : AT(0)
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
.chipinit_section : AT(0xC0)
{
. = ALIGN(4);
*(.chipinit_section) /* .text sections (code) */
*(.chipinit_section*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

17
bsp/Vango_V85xx/Target_FLASH.sct Normal file
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@ -0,0 +1,17 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00010000 { ; load region size_region
ER_IROM1 0x00000000 0x00010000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00002000 { ; RW data
lib_CodeRAM.o (+RO +ZI +RW)
.ANY (+RW +ZI)
}
}

BIN
bsp/Vango_V85xx/Vango.V85XX.4.0.2.pack Normal file
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Binary file not shown.

11
bsp/Vango_V85xx/applications/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

53
bsp/Vango_V85xx/applications/main.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-04 iysheng first version
*/
#include <board.h>
#include <drivers/adc.h>
#include <rtdbg.h>
#include <stdio.h>
#include <rtthread.h>
#include "board.h"
#define LED1 GET_PIN(C, 0)
int main(void)
{
rt_pin_mode(LED1, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(LED1, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED1, PIN_LOW);
rt_thread_mdelay(500);
}
return 0;
}
#ifndef ASSERT_NDEBUG
/**
* @brief Reports the name of the source file and the source line number
* where the assert_errhandler error has occurred.
* @param file: pointer to the source file name
* @param line: assert_errhandler error line source number
* @retval None
*/
void assert_errhandler(uint8_t* file, uint32_t line)
{
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* Infinite loop */
while (1)
{
}
}
#endif

38
bsp/Vango_V85xx/drivers/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'drivers')
# add the general drivers.
src = Split("""
board.c
""")
CPPPATH = [cwd]
# add uart drivers.
if GetDepend('RT_USING_SERIAL'):
src += ['drv_usart.c']
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('RT_USING_ADC'):
src += ['drv_adc.c']
if GetDepend('RT_USING_HWTIMER'):
src += ['drv_hwtimer.c']
if GetDepend('RT_USING_RTC'):
src += ['drv_rtc.c']
if GetDepend('RT_USING_WDT'):
src += ['drv_iwdt.c']
if GetDepend('RT_USING_SPI'):
src += ['drv_spi.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

109
bsp/Vango_V85xx/drivers/board.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-04 iysheng first version
* 2021-09-07 idk500 suit for Vango V85xx
* 2021-09-08 ZhuXW add delay function
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include <target.h>
#include <board.h>
#include <drv_usart.h>
/*
* System Clock Configuration
*/
void SystemClock_Config(void)
{
// SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
NVIC_SetPriority(SysTick_IRQn, 0);
CLK_InitTypeDef CLK_Struct;
CLK_Struct.ClockType = CLK_TYPE_AHBSRC \
|CLK_TYPE_PLLL \
|CLK_TYPE_HCLK \
|CLK_TYPE_PCLK;
CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL;
CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz;
CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL;
CLK_Struct.PLLL.State = CLK_PLLL_ON;
CLK_Struct.HCLK.Divider = 1;
CLK_Struct.PCLK.Divider = 2;
CLK_ClockConfig(&CLK_Struct);
}
/*
* This is the timer interrupt service routine.
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial V85xx board.
*/
void rt_hw_board_init()
{
SystemClock_Config();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef BSP_USING_SDRAM
rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
#else
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
/*@}*/

44
bsp/Vango_V85xx/drivers/board.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-04 iysheng first version
* 2021-09-07 FuC Suit for Vango V85xx
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <target.h>
#include "drv_gpio.h"
#include "drv_spi.h"
/* Internal SRAM memory size[Kbytes] <8-64>, Default: 32*/
#define V85XX_SRAM_SIZE 32
#define V85XX_SRAM_END (0x20000000 + V85XX_SRAM_SIZE * 1024)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END V85XX_SRAM_END
/* #define DEBUG */
#ifdef DEBUG
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define DEBUG_PRINTF(...)
#endif
#endif

27
bsp/Vango_V85xx/drivers/drv_comm.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 iysheng first version
*/
#ifndef __DRV_COMM_H__
#define __DRV_COMM_H__
#ifdef __cplusplus
extern "C" {
#endif
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DRV_HWTIMER_H__ */

447
bsp/Vango_V85xx/drivers/drv_gpio.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-27 iysheng first version
* 2021-01-01 iysheng support exti interrupt
* 2021-09-07 FuC Suit for Vango V85xx
* 2021-09-09 ZhuXW Add GPIO interrupt
*/
#include <board.h>
#include "drv_gpio.h"
#ifdef RT_USING_PIN
#if defined(GPIOF)
#define __V85XX_PORT_MAX 6u
#elif defined(GPIOE)
#define __V85XX_PORT_MAX 5u
#elif defined(GPIOD)
#define __V85XX_PORT_MAX 4u
#elif defined(GPIOC)
#define __V85XX_PORT_MAX 3u
#elif defined(GPIOB)
#define __V85XX_PORT_MAX 2u
#elif defined(GPIOA)
#define __V85XX_PORT_MAX 1u
#else
#define __V85XX_PORT_MAX 0u
#error Unsupported V85XX GPIO peripheral.
#endif
#define PIN_V85XXPORT_MAX __V85XX_PORT_MAX
#define PIN_V85XXPORT_A 0u
static const struct pin_irq_map pin_irq_map[] =
{
#if defined(SOC_SERIES_V85XX)
{GPIO_Pin_0, PMU_IRQn},
{GPIO_Pin_1, PMU_IRQn},
{GPIO_Pin_2, PMU_IRQn},
{GPIO_Pin_3, PMU_IRQn},
{GPIO_Pin_4, PMU_IRQn},
{GPIO_Pin_5, PMU_IRQn},
{GPIO_Pin_6, PMU_IRQn},
{GPIO_Pin_7, PMU_IRQn},
{GPIO_Pin_8, PMU_IRQn},
{GPIO_Pin_9, PMU_IRQn},
{GPIO_Pin_10, PMU_IRQn},
{GPIO_Pin_11, PMU_IRQn},
{GPIO_Pin_12, PMU_IRQn},
{GPIO_Pin_13, PMU_IRQn},
{GPIO_Pin_14, PMU_IRQn},
{GPIO_Pin_15, PMU_IRQn},
#else
#error "Unsupported soc series"
#endif
};
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
static uint32_t pin_irq_enable_mask = 0;
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static rt_base_t v85xx_pin_get(const char *name)
{
rt_base_t pin = 0;
int hw_port_num, hw_pin_num = 0;
int i, name_len;
name_len = rt_strlen(name);
if ((name_len < 4) || (name_len >= 6))
{
return -RT_EINVAL;
}
if ((name[0] != 'P') || (name[2] != '.'))
{
return -RT_EINVAL;
}
if ((name[1] >= 'A') && (name[1] <= 'F'))
{
hw_port_num = (int)(name[1] - 'A');
}
else
{
return -RT_EINVAL;
}
for (i = 3; i < name_len; i++)
{
hw_pin_num *= 10;
hw_pin_num += name[i] - '0';
}
pin = PIN_NUM(hw_port_num, hw_pin_num);
return pin;
}
static void v85xx_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
GPIO_TypeDef *gpio_port;
uint16_t gpio_pin;
if (PIN_PORT(pin) == PIN_V85XXPORT_A)
{
gpio_pin = PIN_V85XXPIN(pin);
GPIOA_WriteBit(GPIOA, gpio_pin, (BitState)value);
}
else if (PIN_PORT(pin) < PIN_V85XXPORT_MAX)
{
gpio_port = PIN_V85XXPORT(pin);
gpio_pin = PIN_V85XXPIN(pin);
GPIOBToF_WriteBit(gpio_port, gpio_pin, (BitState)value);
}
}
static int v85xx_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_TypeDef *gpio_port;
uint16_t gpio_pin;
int value = PIN_LOW;
if (PIN_PORT(pin) == PIN_V85XXPORT_A)
{
gpio_pin = PIN_V85XXPIN(pin);
value = GPIOA_ReadInputDataBit(GPIOA, gpio_pin);
}
else if (PIN_PORT(pin) < PIN_V85XXPORT_MAX)
{
gpio_port = PIN_V85XXPORT(pin);
gpio_pin = PIN_V85XXPIN(pin);
value = GPIOBToF_ReadInputDataBit(gpio_port, gpio_pin);
}
return value;
}
static void v85xx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
GPIO_InitType GPIO_InitStruct = {0};
if (PIN_PORT(pin) >= PIN_V85XXPORT_MAX)
{
return;
}
/* Configure GPIO_InitStructure */
GPIO_InitStruct.GPIO_Pin = PIN_V85XXPIN(pin);
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT;
switch (mode)
{
case PIN_MODE_OUTPUT:
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUTPUT_CMOS;
break;
case PIN_MODE_INPUT:
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT;
break;
case PIN_MODE_INPUT_PULLUP:
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INOUT_CMOS;
break;
case PIN_MODE_INPUT_PULLDOWN:
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INOUT_OD;
break;
case PIN_MODE_OUTPUT_OD:
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INOUT_OD;
break;
default:
break;
}
if (PIN_PORT(pin) == PIN_V85XXPORT_A)
{
GPIOA_Init(GPIOA, &GPIO_InitStruct);
}
else if (PIN_PORT(pin) < PIN_V85XXPORT_MAX)
{
GPIOBToF_Init(PIN_V85XXPORT(pin), &GPIO_InitStruct);
}
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
int i;
for (i = 0; i < 32; i++)
{
if ((0x01 << i) == bit)
{
return i;
}
}
return -1;
}
static rt_err_t v85xx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
rt_base_t level;
rt_int32_t irqindex = -1;
if (PIN_PORT(pin) > PIN_V85XXPORT_A)
{
return -RT_ENOSYS;
}
irqindex = bit2bitno(PIN_V85XXPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return RT_EBUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
pin_irq_hdr_tab[irqindex].mode = mode;
pin_irq_hdr_tab[irqindex].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t v85xx_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_base_t level;
rt_int32_t irqindex = -1;
if (PIN_PORT(pin) > PIN_V85XXPORT_A)
{
return -RT_ENOSYS;
}
irqindex = bit2bitno(PIN_V85XXPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
pin_irq_hdr_tab[irqindex].pin = -1;
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
pin_irq_hdr_tab[irqindex].mode = 0;
pin_irq_hdr_tab[irqindex].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t v85xx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
GPIO_InitType GPIO_InitStruct = {0};
if (PIN_PORT(pin) > PIN_V85XXPORT_A)
{
return -RT_ENOSYS;
}
GPIO_InitStruct.GPIO_Pin = PIN_V85XXPIN(pin);
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(PIN_V85XXPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_ENOSYS;
}
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT;
GPIO_InitStruct.GPIO_Pin = PIN_V85XXPIN(pin);
GPIOA_Init(GPIOA, &GPIO_InitStruct);
irqmap = &pin_irq_map[irqindex];
switch (pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_RISING);
break;
case PIN_IRQ_MODE_FALLING:
PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_FALLING);
break;
case PIN_IRQ_MODE_RISING_FALLING:
PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_EDGEBOTH);
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_HIGH);
break;
case PIN_IRQ_MODE_LOW_LEVEL:
PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_LOW);
break;
default:
break;
}
PMU_INTConfig(PMU_INT_IOAEN, ENABLE);
NVIC_SetPriority(irqmap->irqno, 0);
NVIC_EnableIRQ(irqmap->irqno);
pin_irq_enable_mask |= irqmap->pinbit;
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
level = rt_hw_interrupt_disable();
PMU_INTConfig(PMU_INT_IOAEN, DISABLE);
NVIC_DisableIRQ(irqmap->irqno);
rt_hw_interrupt_enable(level);
}
else
{
return -RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops _v85xx_pin_ops =
{
v85xx_pin_mode,
v85xx_pin_write,
v85xx_pin_read,
v85xx_pin_attach_irq,
v85xx_pin_detach_irq,
v85xx_pin_irq_enable,
v85xx_pin_get,
};
rt_inline void pin_irq_hdr(int irqno)
{
if (pin_irq_hdr_tab[irqno].hdr)
{
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
}
}
void v85xx_pin_exti_irqhandler()
{
rt_base_t intsts=0;
int i=0;
intsts = PMU_GetIOAAllINTStatus();
for(i=0; i<16; i++)
{
if((1<<i) & intsts)
{
PMU_ClearIOAINTStatus(1<<i);
pin_irq_hdr(bit2bitno(1<<i));
return;
}
}
}
void PMU_IRQHandler()
{
rt_interrupt_enter();
v85xx_pin_exti_irqhandler();
rt_interrupt_leave();
}
int rt_hw_pin_init(void)
{
GPIO_InitType GPIO_InitStruct;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT;
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_All;
#if defined(GPIOF)
GPIOBToF_Init(GPIOF, &GPIO_InitStruct);
#endif
#if defined(GPIOE)
GPIOBToF_Init(GPIOE, &GPIO_InitStruct);
#endif
#if defined(GPIOD)
GPIOBToF_Init(GPIOD, &GPIO_InitStruct);
#endif
#if defined(GPIOC)
GPIOBToF_Init(GPIOC, &GPIO_InitStruct);
#endif
#if defined(GPIOB)
GPIOBToF_Init(GPIOB, &GPIO_InitStruct);
#endif
#if defined(GPIOA)
GPIOA_Init(GPIOA, &GPIO_InitStruct);
#endif
return rt_device_pin_register("pin", &_v85xx_pin_ops, RT_NULL);
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
#endif /* RT_USING_PIN */

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-27 iysheng first release
* 2021-09-10 ZhuXW add V85XX support
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#define __V85XX_PORT(port) GPIO##port##_BASE
#define GET_PIN(PORTx,PIN) (__V85XX_PORT(PORTx)==GPIOA_BASE) ? (rt_base_t)(0 + PIN):(rt_base_t)((16 * ( ((rt_base_t)__V85XX_PORT(PORTx) - (rt_base_t)GPIOB_BASE)/(0x0400UL) +1)) + PIN)
#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_V85XXPORT(pin) ((GPIO_TypeDef *)(GPIOB_BASE + (0x400u * PIN_PORT(pin))))
#define PIN_V85XXPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
struct pin_irq_map
{
rt_uint16_t pinbit;
IRQn_Type irqno;
};
#ifdef __cplusplus
}
#endif
#endif /* __DRV_GPIO_H__ */

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-06-05 tanek first implementation.
* 2018-04-19 misonyo Porting for v85xxf30x
* 2019-03-31 xuzhuoyi Porting for v85xxe230
* 2021-09-21 zhuxw Porting for v85xx
*/
#include "drv_spi.h"
#include "board.h"
#include <rtthread.h>
#if defined(RT_USING_SPI) && defined(RT_USING_PIN)
#include <rtdevice.h>
#if !defined(RT_USING_SPI1) && !defined(RT_USING_SPI2)
#error "Please define at least one SPIx"
#endif
/* private rt-thread spi ops function */
static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
static struct rt_spi_ops v85xx_spi_ops =
{
configure,
xfer
};
static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
{
SPI_InitType spi_init_struct;
rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
if(configuration->data_width > 8)
{
return RT_EIO;
}
{
rt_uint32_t spi_apb_clock;
rt_uint32_t max_hz;
max_hz = configuration->max_hz;
spi_apb_clock = CLK_GetPCLKFreq();
if(max_hz >= spi_apb_clock/2)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_2;
}
else if (max_hz >= spi_apb_clock/4)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_4;
}
else if (max_hz >= spi_apb_clock/8)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_8;
}
else if (max_hz >= spi_apb_clock/16)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_16;
}
else if (max_hz >= spi_apb_clock/32)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_32;
}
else if (max_hz >= spi_apb_clock/64)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_64;
}
else
{
/* min prescaler 128 */
spi_init_struct.ClockDivision = SPI_CLKDIV_128;
}
} /* baudrate */
switch(configuration->mode & RT_SPI_MODE_3)
{
case RT_SPI_MODE_0:
spi_init_struct.SPH = SPI_SPH_0;
spi_init_struct.SPO = SPI_SPO_0;
break;
case RT_SPI_MODE_1:
spi_init_struct.SPH = SPI_SPH_1;
spi_init_struct.SPO = SPI_SPO_0;
break;
case RT_SPI_MODE_2:
spi_init_struct.SPH = SPI_SPH_0;
spi_init_struct.SPO = SPI_SPO_1;
break;
case RT_SPI_MODE_3:
spi_init_struct.SPH = SPI_SPH_1;
spi_init_struct.SPO = SPI_SPO_1;
break;
}
if(!(configuration->mode & RT_SPI_MSB))
{
return RT_EIO;
}
spi_init_struct.Mode = SPI_MODE_MASTER;
spi_init_struct.CSNSoft = SPI_CSNSOFT_ENABLE;
SPI_Init((SPI_TypeDef*)spi_periph, &spi_init_struct);
SPI_Cmd((SPI_TypeDef*)spi_periph, ENABLE);
return RT_EOK;
};
static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
{
rt_base_t v85xx_cs_pin = (rt_base_t)device->parent.user_data;
rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
struct rt_spi_configuration * config = &device->config;
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
/* take CS */
if(message->cs_take)
{
rt_pin_write(v85xx_cs_pin, PIN_LOW);
DEBUG_PRINTF("spi take cs\n");
}
{
if(config->data_width <= 8)
{
const rt_uint8_t * send_ptr = message->send_buf;
rt_uint8_t * recv_ptr = message->recv_buf;
rt_uint32_t size = message->length;
DEBUG_PRINTF("spi poll transfer start: %d\n", size);
while(size--)
{
rt_uint8_t data = 0xFF;
if(send_ptr != RT_NULL)
{
data = *send_ptr++;
}
//Wait until the transmit buffer is empty
while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_TXEMPTY));
// Send the byte
SPI_SendData((SPI_TypeDef*)spi_periph, data);
//Wait until a data is received
while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_RNE));
// Get the received data
data = SPI_ReceiveData((SPI_TypeDef*)spi_periph);
if(recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
}
}
DEBUG_PRINTF("spi poll transfer finsh\n");
}
}
/* release CS */
if(message->cs_release)
{
rt_pin_write(v85xx_cs_pin, PIN_HIGH);
DEBUG_PRINTF("spi release cs\n");
}
return message->length;
};
int v85xx_hw_spi_init(void)
{
int result = 0;
#ifdef RT_USING_SPI1
static struct rt_spi_bus spi_bus0;
spi_bus0.parent.user_data = (void *)SPI1;
result = rt_spi_bus_register(&spi_bus0, "spi1", &v85xx_spi_ops);
#endif
#ifdef RT_USING_SPI2
static struct rt_spi_bus spi_bus1;
spi_bus1.parent.user_data = (void *)SPI2;
result = rt_spi_bus_register(&spi_bus1, "spi2", &v85xx_spi_ops);
#endif
return result;
}
INIT_BOARD_EXPORT(v85xx_hw_spi_init);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-01-01 aozima first implementation.
* 2021-09-21 zhuxw add vango v85xx spi drivers
*
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#endif // __DRV_SPI_H__

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-04 iysheng first version
* 2021-09-07 FuC Suit for Vango V85XX
* 2021·09-12 ZhuXW fix UART5
*/
#include <target.h>
#include <drv_usart.h>
#include <board.h>
#ifdef RT_USING_SERIAL
#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \
!defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
!defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
#error "Please define at least one UARTx"
#endif
#include <rtdevice.h>
static void uart_isr(struct rt_serial_device *serial);
#if defined(BSP_USING_UART0)
struct rt_serial_device serial0;
void UART0_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial0);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART0 */
#if defined(BSP_USING_UART1)
struct rt_serial_device serial1;
void UART1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial1);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
struct rt_serial_device serial2;
void UART2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial2);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
struct rt_serial_device serial3;
void UART3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial3);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
struct rt_serial_device serial4;
void UART4_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial4);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
struct rt_serial_device serial5;
void UART5_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial5);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART4 */
static const struct V85xx_uart uarts[] =
{
#ifdef BSP_USING_UART0
{
UART0, /* uart peripheral index */
UART0_IRQn, /* uart iqrn */
&serial0,
"uart0",
},
#endif
#ifdef BSP_USING_UART1
{
UART1, /* uart peripheral index */
UART1_IRQn, /* uart iqrn */
&serial1,
"uart1",
},
#endif
#ifdef BSP_USING_UART2
{
UART2, /* uart peripheral index */
UART2_IRQn, /* uart iqrn */
&serial2,
"uart2",
},
#endif
#ifdef BSP_USING_UART3
{
UART3, /* uart peripheral index */
UART3_IRQn, /* uart iqrn */
&serial3,
"uart3",
},
#endif
#ifdef BSP_USING_UART4
{
UART4, /* uart peripheral index */
UART4_IRQn, /* uart iqrn */
&serial4,
"uart4",
},
#endif
#ifdef BSP_USING_UART5
{
UART5, /* uart peripheral index */
UART5_IRQn, /* uart iqrn */
&serial5,
"uart5",
},
#endif
};
static rt_err_t V85xx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct V85xx_uart *uart;
UART_TypeDef *UARTx;
UART_InitType UART_InitParaStruct = {0};
UART_StructInit(&UART_InitParaStruct);
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct V85xx_uart *)serial->parent.user_data;
UARTx = (UART_TypeDef *)uart->uart_periph;
UART_InitParaStruct.Baudrate = cfg->baud_rate;
switch (cfg->data_bits)
{
case DATA_BITS_9:
UART_InitParaStruct.WordLen = UART_WORDLEN_9B;
break;
default:
UART_InitParaStruct.WordLen = UART_WORDLEN_8B;
break;
}
switch (cfg->parity)
{
case PARITY_ODD:
UART_InitParaStruct.Parity = UART_PARITY_ODD;
break;
case PARITY_EVEN:
UART_InitParaStruct.Parity = UART_PARITY_EVEN;
break;
default:
UART_InitParaStruct.Parity = UART_PARITY_NONE;
break;
}
UART_InitParaStruct.Mode = UART_MODE_RX | UART_MODE_TX;
UART_Init(UARTx, &UART_InitParaStruct);
UART_Cmd(UARTx, UART_InitParaStruct.Mode, ENABLE);
return RT_EOK;
}
static rt_err_t V85xx_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct V85xx_uart *uart;
UART_TypeDef *UARTx;
RT_ASSERT(serial != RT_NULL);
uart = (struct V85xx_uart *)serial->parent.user_data;
UARTx = (UART_TypeDef *)uart->uart_periph;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
NVIC_DisableIRQ(uart->irqn);
/* disable interrupt */
UART_INTConfig(UARTx, UART_INT_RX, DISABLE);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
NVIC_EnableIRQ(uart->irqn);
/* enable interrupt */
UART_INTConfig(UARTx, UART_INT_RX, ENABLE);
break;
}
return RT_EOK;
}
static int V85xx_putc(struct rt_serial_device *serial, char ch)
{
struct V85xx_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct V85xx_uart *)serial->parent.user_data;
UART_SendData((UART_TypeDef *)uart->uart_periph, ch);
while ((UART_GetFlag((UART_TypeDef *)uart->uart_periph, UART_FLAG_TXDONE) == RESET));
UART_ClearFlag((UART_TypeDef *)uart->uart_periph, UART_FLAG_TXDONE);
return 1;
}
static int V85xx_getc(struct rt_serial_device *serial)
{
int ch;
struct V85xx_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct V85xx_uart *)serial->parent.user_data;
ch = -1;
if (UART_GetFlag((UART_TypeDef *)uart->uart_periph, UART_FLAG_RXFULL) != RESET)
ch = UART_ReceiveData((UART_TypeDef *)uart->uart_periph);
return ch;
}
/**
* Uart common interrupt process. This need add to uart ISR.
*
* @param serial serial device
*/
static void uart_isr(struct rt_serial_device *serial)
{
struct V85xx_uart *uart = (struct V85xx_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
if ((UART_GetINTStatus((UART_TypeDef *)uart->uart_periph, UART_INTSTS_RX) != RESET) &&
(UART_GetFlag((UART_TypeDef *)uart->uart_periph, UART_FLAG_RXFULL) != RESET))
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
/* Clear RXNE interrupt flag */
UART_ClearINTStatus((UART_TypeDef *)uart->uart_periph, UART_INTSTS_RX);
}
}
static const struct rt_uart_ops V85xx_uart_ops =
{
V85xx_configure,
V85xx_control,
V85xx_putc,
V85xx_getc,
};
int V85xx_hw_usart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
int i;
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{
uarts[i].serial->ops = &V85xx_uart_ops;
uarts[i].serial->config = config;
/* register UART device */
rt_hw_serial_register(uarts[i].serial,
uarts[i].device_name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
(void *)&uarts[i]);
}
return 0;
}
INIT_BOARD_EXPORT(V85xx_hw_usart_init);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-04 iysheng first version
*/
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
#include <rthw.h>
#include <rtthread.h>
/* V85XX uart driver */
struct V85xx_uart {
UART_TypeDef * uart_periph;
IRQn_Type irqn;
struct rt_serial_device *serial;
char *device_name;
};
#endif

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bsp/Vango_V85xx/project.uvprojx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>V85XX</Device>
<Vendor>Generic</Vendor>
<PackID>Vango.V85XX.4.0.2</PackID>
<Cpu>IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:V85XX$Device\Include\V85XX.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:V85XX$SVD\V85XX.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>template</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
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</RTE>
</Project>

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice optimization */
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart"
#define RT_VER_NUM 0x40004
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_SPI
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_POSIX
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* AI packages */
/* miscellaneous packages */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
#define SOC_SERIES_V85XX
#define SOC_V85XX
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART2
#define RT_USING_SPI1
#define RT_USING_SPI2
#endif

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import os
# toolchains options
ARCH='arm'
CPU='cortex-m0'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# tool-chains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-v85xx.map,-cref,-u,Reset_Handler -T Target_FLASH.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M0'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-v85xx.map --scatter Target_FLASH.sct'
LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)'
EXEC_PATH += '/ARM/ARMCC/bin'
print(EXEC_PATH)
CFLAGS += ' --c99'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D VANGOV85XXDEV'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --debug'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M0'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
AFLAGS = ''
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M0'
AFLAGS += ' --fpu None'
LFLAGS = ' --config Target_FLASH.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH += '/arm/bin/'
POST_ACTION = ''

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>V85XX</Device>
<Vendor>Generic</Vendor>
<PackID>Vango.V85XX.4.0.2</PackID>
<Cpu>IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:V85XX$Device\Include\V85XX.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:V85XX$SVD\V85XX.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>template</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x8000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>1</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>

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bsp/apm32/apm32f103xe-minibroard/.config Normal file
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#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40001
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M3=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
#
# Using WiFi
#
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
#
# peripheral libraries and drivers
#
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F1=y
#
# Hardware Drivers Config
#
CONFIG_SOC_STM32F103ZE=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDCARD is not set
# CONFIG_BSP_USING_SPI_FLASH is not set
# CONFIG_BSP_USING_EEPROM is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C2 is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_SDIO is not set
#
# Board extended module Drivers
#

42
bsp/apm32/apm32f103xe-minibroard/.gitignore vendored Normal file
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*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

22
bsp/apm32/apm32f103xe-minibroard/Kconfig Normal file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "board/Kconfig"

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bsp/apm32/apm32f103xe-minibroard/README.md Normal file
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# APM32F103ZE MINI BOARD BSP 说明
## 简介
本文档为 APM32F103ZE MINI 开发板（MINI BOARD）的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
## 开发板介绍
APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO。开发板外观如下图所示：
![board](figures/APM32F103ZE.png)
该开发板常用 **板载资源** 如下：
- MCU：APM32F103C8T6，主频 96MHz，512KB FLASH ，128KB RAM
- 外部 RAM：无
- 外部 FLASH：无
- 常用外设
- LED：2个，（黄色，PE5/PE6）
- 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13）
- 常用接口：RS232转串口、、USB SLAVE
- 调试接口：标准 JTAG/SWD
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :------------------------------------ |
| RS232转串口 | 支持 | 使用 UART1/ UART2(通过跳线选择) |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA0, PA1... PG15 ---> PIN: 0, 1...143 |
| UART | 支持 | UART1/2 |
## 使用说明
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
### 快速上手
本 BSP 为开发者提供MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后，系统会自动运行，LED 闪烁
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.4 build Aug 20 2021
2006 - 2021 Copyright by rt-thread team
msh >
```
## 注意事项
- 可在极海官方网站进行所需资料下载，如pack安装包和MINI开发板原理图等（www.geehy.com）;
## 联系人信息
-[abbbcc ](https://gitee.com/abbbcc)

15
bsp/apm32/apm32f103xe-minibroard/SConscript Normal file
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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

60
bsp/apm32/apm32f103xe-minibroard/SConstruct Normal file
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
apm32_library = 'APM32F10x_Library'
rtconfig.BSP_LIBRARY_TYPE = apm32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, apm32_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

11
bsp/apm32/apm32f103xe-minibroard/applications/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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