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add apm32F0 serie MCU support (#6789) 

* add apm32F0 serie MCU support
add apm32f072vb-miniboard bsp
update F103/F407 bsp

* replace apm32f072vb picture

* Update action.yml
This commit is contained in:
luobeihai 2023-01-05 14:15:02 +08:00 committed by GitHub
parent b99769f686
commit 24575c4486
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
258 changed files with 85038 additions and 6328 deletions
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2
.github/workflows/action.yml vendored
View File

@ -37,6 +37,8 @@ jobs:
- {RTT_BSP: "acm32/acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "apm32/apm32f103xe-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "apm32/apm32f407ig-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "apm32/apm32f072vb-miniboard", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
# - {RTT_BSP: "ft2004", RTT_TOOL_CHAIN: "sourcery-arm"}

985
bsp/apm32/apm32f072vb-miniboard/.config Normal file
View File

@ -0,0 +1,985 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50000
# CONFIG_RT_USING_CACHE is not set
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M0=y
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
# CONFIG_RT_USING_DFS is not set
# CONFIG_RT_USING_FAL is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# C/C++ and POSIX layer
#
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LWIP is not set
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_LIBHYDROGEN is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
#
# JSON: JavaScript Object Notation, a lightweight data-interchange format
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
#
# XML: Extensible Markup Language
#
# CONFIG_PKG_USING_SIMPLE_XML is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
# CONFIG_PKG_USING_RTT_RUST is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_CHERRYUSB is not set
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_UKAL is not set
#
# miscellaneous packages
#
#
# project laboratory
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_HEATSHRINK is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_CONTROLLER is not set
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
CONFIG_SOC_FAMILY_APM32=y
CONFIG_SOC_SERIES_APM32F0=y
#
# Hardware Drivers Config
#
CONFIG_SOC_APM32F072VB=y
#
# Onboard Peripheral Drivers
#
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_WDT is not set
#
# Board extended module Drivers
#

42
bsp/apm32/apm32f072vb-miniboard/.gitignore vendored Normal file
View File

@ -0,0 +1,42 @@
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

22
bsp/apm32/apm32f072vb-miniboard/Kconfig Normal file
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@ -0,0 +1,22 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "board/Kconfig"

116
bsp/apm32/apm32f072vb-miniboard/README.md Normal file
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# APM32F072VB MINI BOARD BSP 说明
## 简介
本文档为 APM32F072VB MINI 开发板（MINI BOARD）的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
## 开发板介绍
APM32F072VB MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO。开发板外观如下图所示：
<img src="figures/APM32F072VB.png" alt="image-20221227141551541" style="zoom:50%;" />
- 有关开发板和芯片的详情可至极海官网查阅。[官网开发板链接 ](https://www.geehy.com/support/apm32?id=192)
该开发板常用 **板载资源** 如下：
- MCU：APM32F072VBT6，主频 48MHz，128KB FLASH ，16KB RAM
- 外部 RAM：无
- 外部 FLASH：无
- 常用外设
- LED：2个，（黄色，PE5/PE6）
- 按键：2个，K1（PA1），K2（PA0）
- 常用接口：RS232转串口、USB SLAVE
- 调试接口：标准 JTAG/SWD
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :------------------------------------ |
| RS232转串口 | 支持 | 使用 UART1/ UART2(通过跳线选择) |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA0, PA1... PF10 ---> PIN: 0, 1...89 |
| UART | 支持 | UART1/2 |
| ADC | 支持 | ADC1 |
| DAC | 支持 | DAC1 |
| RTC | 支持 | 支持外部晶振和内部低速时钟 |
| TMR | 支持 | TMR1/2/3/6/7/14/15/16/17 |
| PWM | 支持 | TMR3 ->CH1/2/3/4 |
| I2C | 支持 | 软件I2C |
| SPI | 支持 | SPI1/2 |
| WDT | 支持 | IWDT |
## 使用说明
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
### 快速上手
本 BSP 为开发者提供MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
- 方式一：MDK
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
- 方式二：J-Flash下载
通过ENV工具的scons指令或MDK编译出bin文件后，再使用J-Flash工具将bin文件下载至开发板即可，大致步骤如下：
##### 1、建立J-Flash工程
![board](figures/JFlash_Leader_01.png)
**注意**：步骤4选择芯片型号时，要根据自己的开发板所用的芯片型号进行选择。比如本开发板，则选择对应的 **APM32F072VBT6** 。
##### 2、连接开发板
![board](figures/JFlash_Leader_02.png)
##### 3、将bin文件拖至工程，起始地址设为0x8000000
![board](figures/JFlash_Leader_03.png)
##### 4、点击下载
![board](figures/JFlash_Leader_04.png)
#### 运行结果
下载程序成功之后，系统会自动运行，LED 闪烁
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.1.0 build Aug 20 2021
2006 - 2021 Copyright by rt-thread team
msh >
```
## 注意事项
- 可在极海官方网站进行所需资料下载，如pack安装包和MINI开发板原理图等（www.geehy.com）;
## 联系人信息
-[abbbcc ](https://gitee.com/abbbcc)
-[stevetong459 ](https://github.com/stevetong459)
-[luobeihai](https://github.com/luobeihai)

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
apm32_library = 'APM32F0xx_Library'
rtconfig.BSP_LIBRARY_TYPE = apm32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, apm32_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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from building import *
import os
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 zylx first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
/* defined the LED2 pin: PE6 */
#define LED2_PIN GET_PIN(E, 6)
int main(void)
{
int count = 1;
/* set LED2 pin mode to output */
rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
while (count++)
{
rt_pin_write(LED2_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED2_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
return RT_EOK;
}

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menu "Hardware Drivers Config"
config SOC_APM32F072VB
bool
select SOC_SERIES_APM32F0
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_UART2
bool "Enable UART2"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_DAC
bool "Enable DAC"
default n
select RT_USING_DAC
if BSP_USING_DAC
config BSP_USING_DAC1
bool "Enable DAC1"
default n
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_ONCHIP_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
config BSP_USING_I2C1
bool "Enable I2C1 BUS"
if BSP_USING_I2C1
comment "Notice: PB10 --> 26; PB11 --> 27"
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 0 63
default 26
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0 63
default 27
endif
config BSP_USING_I2C2
bool "Enable I2C2 BUS"
if BSP_USING_I2C2
comment "Notice: PA0 --> 0; PA1 --> 1"
config BSP_I2C2_SCL_PIN
int "i2c2 scl pin number"
range 0 63
default 22
config BSP_I2C2_SDA_PIN
int "I2C2 sda pin number"
range 0 63
default 23
endif
config BSP_USING_I2C3
bool "Enable I2C3 BUS"
if BSP_USING_I2C3
comment "Notice: PB0 --> 16; PB1 --> 17"
config BSP_I2C3_SCL_PIN
int "i2c3 scl pin number"
range 0 63
default 8
config BSP_I2C3_SDA_PIN
int "I2C3 sda pin number"
range 0 63
default 41
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1"
default n
config BSP_USING_SPI2
bool "Enable SPI2"
default n
endif
menuconfig BSP_USING_TMR
bool "Enable Timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TMR
config BSP_USING_TMR1
bool "Enable TMR1"
default n
config BSP_USING_TMR2
bool "Enable TMR2"
default n
config BSP_USING_TMR3
bool "Enable TMR3"
default n
config BSP_USING_TMR6
bool "Enable TMR6"
default n
config BSP_USING_TMR7
bool "Enable TMR7"
default n
config BSP_USING_TMR14
bool "Enable TMR14"
default n
config BSP_USING_TMR15
bool "Enable TMR15"
default n
config BSP_USING_TMR16
bool "Enable TMR16"
default n
config BSP_USING_TMR17
bool "Enable TMR17"
default n
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
menuconfig BSP_USING_PWM3
bool "Enable timer3 output PWM"
default n
if BSP_USING_PWM3
config BSP_USING_PWM3_CH1
bool "Enable PWM3 channel1"
default n
config BSP_USING_PWM3_CH2
bool "Enable PWM3 channel2"
default n
config BSP_USING_PWM3_CH3
bool "Enable PWM3 channel3"
default n
config BSP_USING_PWM3_CH4
bool "Enable PWM3 channel4"
default n
endif
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
''')
path = [cwd]
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f072.s']
if rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f072.s']
if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix + '/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f072.S']
# APM32F030x6 || APM32F030x8 || APM32F030xC
# APM32F051x6 || APM32F051x8
# APM32F070xB
# APM32F071x8 || APM32F071xB
# APM32F072x8 || APM32F072xB
# APM32F091xB || APM32F091xC
# You can select chips from the list above
CPPDEFINES = ['APM32F072xB']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-21 zylx first version
*/
#include "board.h"
void apm32_usart_init(void)
{
GPIO_Config_T GPIO_ConfigStruct;
#ifdef BSP_USING_UART1
RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA);
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_USART1);
/* Connect PXx to USARTx_Tx */
GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_9, GPIO_AF_PIN1);
/* Connect PXx to USARRX_Rx */
GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_10, GPIO_AF_PIN1);
/* Configure USART Tx/Rx as alternate function push-pull */
GPIO_ConfigStruct.mode = GPIO_MODE_AF;
GPIO_ConfigStruct.pin = GPIO_PIN_9;
GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
GPIO_ConfigStruct.outtype = GPIO_OUT_TYPE_PP;
GPIO_ConfigStruct.pupd = GPIO_PUPD_PU;
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
GPIO_ConfigStruct.pin = GPIO_PIN_10;
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
#endif
#ifdef BSP_USING_UART2
RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA);
RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2);
/* Connect PXx to USARTx_Tx */
GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_2, GPIO_AF_PIN1);
/* Connect PXx to USARRX_Rx */
GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_3, GPIO_AF_PIN1);
/* Configure USART Tx/Rx as alternate function push-pull */
GPIO_ConfigStruct.mode = GPIO_MODE_AF;
GPIO_ConfigStruct.pin = GPIO_PIN_2;
GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
GPIO_ConfigStruct.outtype = GPIO_OUT_TYPE_PP;
GPIO_ConfigStruct.pupd = GPIO_PUPD_PU;
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
GPIO_ConfigStruct.pin = GPIO_PIN_3;
GPIO_Config(GPIOA, &GPIO_ConfigStruct);
#endif
}
void apm32_msp_spi_init(void *Instance)
{
#ifdef BSP_USING_SPI
GPIO_Config_T GPIO_InitStructure;
SPI_T *spi_x = (SPI_T *)Instance;
if(spi_x == SPI1)
{
/* Enable related Clock */
RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOE);
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SPI1);
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SYSCFG);
/* Config SPI PinAF */
GPIO_ConfigPinAF(GPIOE, GPIO_PIN_SOURCE_15, GPIO_AF_PIN1);
GPIO_ConfigPinAF(GPIOE, GPIO_PIN_SOURCE_14, GPIO_AF_PIN1);
GPIO_ConfigPinAF(GPIOE, GPIO_PIN_SOURCE_13, GPIO_AF_PIN1);
/* Config SPI GPIO*/
GPIO_ConfigStructInit(&GPIO_InitStructure);
GPIO_InitStructure.pin = GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
GPIO_InitStructure.speed = GPIO_SPEED_50MHz;
GPIO_InitStructure.mode = GPIO_MODE_AF;
GPIO_InitStructure.outtype = GPIO_OUT_TYPE_PP;
GPIO_InitStructure.pupd = GPIO_PUPD_NO;
GPIO_Config(GPIOE, &GPIO_InitStructure);
}
#endif
}
void apm32_msp_timer_init(void *Instance)
{
#ifdef BSP_USING_PWM
GPIO_Config_T gpio_config;
TMR_T *tmr_x = (TMR_T *)Instance;
if (tmr_x == TMR3)
{
RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR3);
/* TMR3 channel 1 gpio init */
GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_6, GPIO_AF_PIN0);
gpio_config.pin = GPIO_PIN_6;
gpio_config.mode = GPIO_MODE_AF;
gpio_config.outtype = GPIO_OUT_TYPE_PP;
gpio_config.pupd = GPIO_PUPD_NO;
gpio_config.speed = GPIO_SPEED_50MHz;
GPIO_Config(GPIOC, &gpio_config);
/* TMR3 channel 2 gpio init */
GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_7, GPIO_AF_PIN0);
gpio_config.pin = GPIO_PIN_7;
GPIO_Config(GPIOC, &gpio_config);
/* TMR3 channel 3 gpio init */
GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_8, GPIO_AF_PIN0);
gpio_config.pin = GPIO_PIN_8;
GPIO_Config(GPIOC, &gpio_config);
/* TMR3 channel 4 gpio init */
GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_9, GPIO_AF_PIN0);
gpio_config.pin = GPIO_PIN_9;
GPIO_Config(GPIOC, &gpio_config);
}
#endif
}

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-20 Abbcc first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include <apm32f0xx.h>
#include "apm32f0xx_gpio.h"
#include "apm32f0xx_syscfg.h"
#include "apm32f0xx_rcm.h"
#include "apm32f0xx_misc.h"
#include "apm32f0xx_eint.h"
#include "apm32f0xx_usart.h"
#if defined(RT_USING_ADC)
#include "apm32f0xx_adc.h"
#endif
#if defined(RT_USING_DAC)
#include "apm32f0xx_dac.h"
#endif
#if defined(RT_USING_RTC)
#include "apm32f0xx_rtc.h"
#include "apm32f0xx_pmu.h"
#endif
#if defined(RT_USING_SPI)
#include "apm32f0xx_spi.h"
#endif
#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM)
#include "apm32f0xx_tmr.h"
#endif
#if defined(RT_USING_WDT)
#include "apm32f0xx_iwdt.h"
#include "apm32f0xx_wwdt.h"
#endif
#include "drv_common.h"
#include "drv_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define APM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define APM32_FLASH_SIZE (128 * 1024)
#define APM32_FLASH_END_ADDRESS ((uint32_t)(APM32_FLASH_START_ADRESS + APM32_FLASH_SIZE))
/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64 */
#define APM32_SRAM_SIZE 16
#define APM32_SRAM_END (0x20000000 + APM32_SRAM_SIZE * 1024)
#if defined(__ARMCC_VERSION)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END APM32_SRAM_END
void SystemClock_Config(void);
void apm32_usart_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H__ */

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0400;
define symbol __ICFEDIT_size_heap__ = 0x000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK};

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/*
* linker script for APM32F0xx with GNU ld
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* 128KB flash */
RAM (rw) : ORIGIN = 0x20000000, LENGTH = 16K /* 16K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x400;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
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bsp/apm32/apm32f072vb-miniboard/project.uvprojx Normal file
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<Size>0x4000</Size>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
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<oTime>0</oTime>
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<uThumb>0</uThumb>
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<uC99>1</uC99>
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<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, APM32F072xB</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\stdio;applications;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension;.;..\..\..\include;..\..\..\components\drivers\include;..\libraries\APM32F0xx_Library\CMSIS\Include;..\..\..\components\libc\posix\ipc;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board</IncludePath>
</VariousControls>
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<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
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<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Applications</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>applications\main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Compiler</GroupName>
<Files>
<File>
<FileName>syscall_mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
</File>
<File>
<FileName>syscalls.c</FileName>
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<FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
</File>
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<FilePath>..\..\..\components\libc\compilers\common\cctype.c</FilePath>
</File>
<File>
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<FilePath>..\..\..\components\libc\compilers\common\cstdio.c</FilePath>
</File>
<File>
<FileName>cstdlib.c</FileName>
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<FilePath>..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
</File>
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<FileName>cstring.c</FileName>
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<FilePath>..\..\..\components\libc\compilers\common\cstring.c</FilePath>
</File>
<File>
<FileName>ctime.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
</File>
<File>
<FileName>cwchar.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cwchar.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>div0.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
</File>
<File>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
</File>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m0\context_rvds.S</FilePath>
</File>
<File>
<FileName>cpuport.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m0\cpuport.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
</File>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
</File>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
</File>
<File>
<FileName>ringblk_buf.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
</File>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
</File>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
</File>
<File>
<FileName>workqueue.c</FileName>
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<FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
</File>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
</File>
<File>
<FileName>startup_apm32f072.s</FileName>
<FileType>2</FileType>
<FilePath>..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Source\arm\startup_apm32f072.s</FilePath>
</File>
<File>
<FileName>drv_common.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_common.c</FilePath>
</File>
<File>
<FileName>drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_gpio.c</FilePath>
</File>
<File>
<FileName>drv_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_usart.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
<File>
<FileName>msh_parse.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
</File>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\clock.c</FilePath>
</File>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\components.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\device.c</FilePath>
</File>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\idle.c</FilePath>
</File>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath>
</File>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\irq.c</FilePath>
</File>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\kservice.c</FilePath>
</File>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mem.c</FilePath>
</File>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mempool.c</FilePath>
</File>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath>
</File>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\scheduler.c</FilePath>
</File>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\thread.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\timer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Libraries</GroupName>
<Files>
<File>
<FileName>apm32f0xx_eint.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_eint.c</FilePath>
</File>
<File>
<FileName>apm32f0xx_misc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_misc.c</FilePath>
</File>
<File>
<FileName>apm32f0xx_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_gpio.c</FilePath>
</File>
<File>
<FileName>system_apm32f0xx.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Source\system_apm32f0xx.c</FilePath>
</File>
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<FileName>apm32f0xx_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_usart.c</FilePath>
</File>
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<FileName>apm32f0xx_syscfg.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_syscfg.c</FilePath>
</File>
<File>
<FileName>apm32f0xx_rcm.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_rcm.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>template</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

241
bsp/apm32/apm32f072vb-miniboard/rtconfig.h Normal file
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@ -0,0 +1,241 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50000
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M0
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
#define SOC_FAMILY_APM32
#define SOC_SERIES_APM32F0
/* Hardware Drivers Config */
#define SOC_APM32F072VB
/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
/* Board extended module Drivers */
#endif

184
bsp/apm32/apm32f072vb-miniboard/rtconfig.py Normal file
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@ -0,0 +1,184 @@
import os
# toolchains options
ARCH='arm'
CPU='cortex-m0'
CROSS_TOOL='gcc'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
EXEC_PATH = r'D:/IAR'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M0 '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'armclang':
# toolchains
CC = 'armclang'
CXX = 'armclang'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M0 '
CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m0 '
CFLAGS += ' -mcpu=cortex-m0 '
CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
CFLAGS += ' -gdwarf-3 -ffunction-sections '
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
LFLAGS += ' --list rt-thread.map '
LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
EXEC_PATH += '/ARM/ARMCLANG/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O1' # armclang recommend
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iccarm':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M0'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M0'
AFLAGS += ' --fpu None'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

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bsp/apm32/apm32f072vb-miniboard/template.eww Normal file
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\keil\List\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0APM32F0xx_128.FLM -FS08000000 -FL020000 -FP0($$Device:APM32F072VB$Flash\APM32F0xx_128.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:APM32F072VB$Flash\APM32F0xx_128.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Group 1</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
</ProjectOpt>

405
bsp/apm32/apm32f072vb-miniboard/template.uvprojx Normal file
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@ -0,0 +1,405 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>APM32F072VB</Device>
<Vendor>Geehy</Vendor>
<PackID>Geehy.APM32F0xx_DFP.1.0.7</PackID>
<PackURL>https://www.geehy.com/uploads/tool/</PackURL>
<Cpu>IRAM(0x20000000,0x4000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:APM32F072VB$Flash\APM32F0xx_128.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:APM32F072VB$Device\Device\Geehy\APM32F0xx\Include\apm32f0xx.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:APM32F072VB$SVD\APM32F072.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
<OutputName>rt-thread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0+"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x4000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x20000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x4000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>template</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

368
bsp/apm32/apm32f103xe-minibroard/.config
View File

@ -8,6 +8,7 @@
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
@ -77,16 +78,19 @@ CONFIG_RT_USING_HEAP=y
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40101
CONFIG_ARCH_ARM=y
CONFIG_RT_VER_NUM=0x50000
# CONFIG_RT_USING_CACHE is not set
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M3=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
@ -121,14 +125,16 @@ CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
@ -143,10 +149,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
@ -154,10 +164,13 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
@ -302,6 +315,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -309,6 +323,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
#
# security packages
@ -399,7 +414,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
@ -433,8 +447,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
@ -470,7 +484,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_RTDUINO is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
@ -505,19 +518,93 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@ -540,12 +627,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
@ -560,7 +644,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
@ -591,10 +674,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
#
# AI packages
@ -609,6 +693,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_UKAL is not set
#
# miscellaneous packages
#
@ -660,7 +750,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
@ -671,63 +760,212 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
#
# Privated Packages of RealThread
# Arduino libraries
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_MPLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
# CONFIG_PKG_USING_RTDUINO is not set
#
# Network Utilities
# Projects
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
# CONFIG_RT_USING_TESTCASE is not set
# CONFIG_PKG_USING_NGHTTP2 is not set
# CONFIG_PKG_USING_AVS is not set
# CONFIG_PKG_USING_ALI_LINKKIT is not set
# CONFIG_PKG_USING_STS is not set
# CONFIG_PKG_USING_DLMS is not set
# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
# CONFIG_PKG_USING_ZBAR is not set
# CONFIG_PKG_USING_MCF is not set
# CONFIG_PKG_USING_URPC is not set
# CONFIG_PKG_USING_DCM is not set
# CONFIG_PKG_USING_EMQ is not set
# CONFIG_PKG_USING_CFGM is not set
# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
# CONFIG_PKG_USING_SMODULE is not set
# CONFIG_PKG_USING_SNFD is not set
# CONFIG_PKG_USING_UDBD is not set
# CONFIG_PKG_USING_BENCHMARK is not set
# CONFIG_PKG_USING_UBJSON is not set
# CONFIG_PKG_USING_DATATYPE is not set
# CONFIG_PKG_USING_FASTFS is not set
# CONFIG_PKG_USING_RIL is not set
# CONFIG_PKG_USING_WATCH_DCM_SVC is not set
# CONFIG_PKG_USING_WATCH_APP_FWK is not set
# CONFIG_PKG_USING_GUI_TEST is not set
# CONFIG_PKG_USING_PMEM is not set
# CONFIG_PKG_USING_LWRDP is not set
# CONFIG_PKG_USING_MASAN is not set
# CONFIG_PKG_USING_BSDIFF_LIB is not set
# CONFIG_PKG_USING_PRC_DIFF is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# RT-Thread Smart
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
# CONFIG_PKG_USING_UKERNEL is not set
# CONFIG_PKG_USING_TRACE_AGENT is not set
CONFIG_SOC_FAMILY_APM32=y
CONFIG_SOC_SERIES_APM32F1=y
@ -746,6 +984,8 @@ CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_RTC_USING_LSE is not set
# CONFIG_BSP_RTC_USING_LSI is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_TMR is not set

5
bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds
View File

@ -57,6 +57,7 @@ SECTIONS
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
_start_address_init_data = .;
} > CODE
__exidx_end = .;
@ -67,6 +68,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
_start_address_data = .;
*(.data)
*(.data.*)
@ -75,6 +77,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
_end_address_data = .;
} >DATA
.stack :
@ -85,6 +88,7 @@ SECTIONS
} >DATA
__bss_start = .;
_start_address_bss = .;
.bss :
{
. = ALIGN(4);
@ -102,6 +106,7 @@ SECTIONS
*(.bss.init)
} > DATA
__bss_end = .;
_end_address_bss = .;
_end = .;

739
bsp/apm32/apm32f103xe-minibroard/project.uvoptx
View File

@ -10,7 +10,7 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
@ -73,11 +73,11 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>0</CpuCode>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@ -171,15 +171,746 @@
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>1</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
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<GroupName>Source Group 1</GroupName>
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<PathWithFileName>applications\main.c</PathWithFileName>
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213
bsp/apm32/apm32f103xe-minibroard/project.uvprojx
View File

@ -1,43 +1,46 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>APM32F103ZE</Device>
<Vendor>Geehy</Vendor>
<PackID>Geehy.APM32F1xx_DFP.1.0.8</PackID>
<PackID>Geehy.APM32F1xx_DFP.1.0.9</PackID>
<PackURL>https://www.geehy.com/uploads/tool/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec />
<StartupFile />
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:APM32F103ZE$Device\Include\apm32f10x.h</RegisterFile>
<MemoryEnv />
<Cmp />
<Asm />
<Linker />
<OHString />
<InfinionOptionDll />
<SLE66CMisc />
<SLE66AMisc />
<SLE66LinkerMisc />
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:APM32F103ZE$SVD\APM32F103xx.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath />
<IncludePath />
<LibPath />
<RegisterFilePath />
<DBRegisterFilePath />
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
@ -49,9 +52,9 @@
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
@ -59,8 +62,8 @@
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
@ -69,8 +72,8 @@
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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<nStopB1X>0</nStopB1X>
@ -80,14 +83,14 @@
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name />
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
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<CommonProperty>
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@ -101,8 +104,8 @@
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument />
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<CustomArgument></CustomArgument>
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<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
@ -111,7 +114,7 @@
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments />
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
@ -135,11 +138,11 @@
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3 />
<Flash4 />
<pFcarmOut />
<pFcarmGrp />
<pFcArmRoot />
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
@ -172,7 +175,7 @@
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName />
<RvctDeviceName></RvctDeviceName>
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<uocRom>0</uocRom>
<uocRam>0</uocRam>
@ -182,6 +185,7 @@
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -305,7 +309,7 @@
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector />
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
@ -332,10 +336,10 @@
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls />
<Define>__STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARM_LIBC, APM32F10X_HD</Define>
<Undefine />
<IncludePath>applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
<MiscControls></MiscControls>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, APM32F10X_HD</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\finsh;..\..\..\components\libc\posix\io\poll;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\stdio;applications;..\..\..\components\dfs\include;..\libraries\Drivers\config;..\..\..\components\drivers\include;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;.</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -348,12 +352,12 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
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<Define />
<Undefine />
<IncludePath />
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
@ -365,13 +369,13 @@
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase />
<pXoBase></pXoBase>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs />
<IncludeLibsPath />
<Misc />
<LinkerInputFile />
<DisabledWarnings />
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
@ -394,50 +398,36 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
</File>
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<FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
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@ -447,35 +437,22 @@
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<GroupName>CPU</GroupName>
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@ -491,57 +468,41 @@
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<FileName>dfs_file.c</FileName>
<FileType>1</FileType>
@ -626,29 +573,21 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_parse.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_file.c</FileName>
<FileType>1</FileType>
@ -664,85 +603,61 @@
<FileType>1</FileType>
<FilePath>..\..\..\src\clock.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\components.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\device.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\idle.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\irq.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\kservice.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mem.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mempool.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\scheduler.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\thread.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
@ -758,36 +673,26 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_rcm.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_misc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_eint.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f10x_gpio.c</FileName>
<FileType>1</FileType>
@ -798,9 +703,11 @@
</Groups>
</Target>
</Targets>
<RTE>
<apis />
<components />
<files />
<apis/>
<components/>
<files/>
</RTE>
</Project>

44
bsp/apm32/apm32f103xe-minibroard/rtconfig.h
View File

@ -47,9 +47,9 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40101
#define ARCH_ARM
#define RT_VER_NUM 0x50000
#define RT_USING_CPU_FFS
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M3
@ -82,6 +82,7 @@
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
@ -170,6 +171,11 @@
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
@ -177,6 +183,9 @@
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
@ -187,13 +196,38 @@
/* entertainment: terminal games and other interesting software packages */
/* Privated Packages of RealThread */
/* Arduino libraries */
/* Network Utilities */
/* Projects */
/* RT-Thread Smart */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
#define SOC_FAMILY_APM32
#define SOC_SERIES_APM32F1

366
bsp/apm32/apm32f407ig-minibroard/.config
View File

@ -8,6 +8,7 @@
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
@ -77,16 +78,19 @@ CONFIG_RT_USING_HEAP=y
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40101
CONFIG_ARCH_ARM=y
CONFIG_RT_VER_NUM=0x50000
# CONFIG_RT_USING_CACHE is not set
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
@ -121,14 +125,16 @@ CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
@ -143,10 +149,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
@ -154,10 +164,13 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
@ -302,6 +315,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -309,6 +323,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
#
# security packages
@ -400,7 +415,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
@ -434,8 +448,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
@ -471,7 +485,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_RTDUINO is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
@ -506,19 +519,93 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@ -541,12 +628,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
@ -561,7 +645,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
@ -592,10 +675,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
#
# AI packages
@ -610,6 +694,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_UKAL is not set
#
# miscellaneous packages
#
@ -661,7 +751,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
@ -672,63 +761,212 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
#
# Privated Packages of RealThread
# Arduino libraries
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_MPLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
# CONFIG_PKG_USING_RTDUINO is not set
#
# Network Utilities
# Projects
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
# CONFIG_RT_USING_TESTCASE is not set
# CONFIG_PKG_USING_NGHTTP2 is not set
# CONFIG_PKG_USING_AVS is not set
# CONFIG_PKG_USING_ALI_LINKKIT is not set
# CONFIG_PKG_USING_STS is not set
# CONFIG_PKG_USING_DLMS is not set
# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
# CONFIG_PKG_USING_ZBAR is not set
# CONFIG_PKG_USING_MCF is not set
# CONFIG_PKG_USING_URPC is not set
# CONFIG_PKG_USING_DCM is not set
# CONFIG_PKG_USING_EMQ is not set
# CONFIG_PKG_USING_CFGM is not set
# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
# CONFIG_PKG_USING_SMODULE is not set
# CONFIG_PKG_USING_SNFD is not set
# CONFIG_PKG_USING_UDBD is not set
# CONFIG_PKG_USING_BENCHMARK is not set
# CONFIG_PKG_USING_UBJSON is not set
# CONFIG_PKG_USING_DATATYPE is not set
# CONFIG_PKG_USING_FASTFS is not set
# CONFIG_PKG_USING_RIL is not set
# CONFIG_PKG_USING_WATCH_DCM_SVC is not set
# CONFIG_PKG_USING_WATCH_APP_FWK is not set
# CONFIG_PKG_USING_GUI_TEST is not set
# CONFIG_PKG_USING_PMEM is not set
# CONFIG_PKG_USING_LWRDP is not set
# CONFIG_PKG_USING_MASAN is not set
# CONFIG_PKG_USING_BSDIFF_LIB is not set
# CONFIG_PKG_USING_PRC_DIFF is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# RT-Thread Smart
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
# CONFIG_PKG_USING_UKERNEL is not set
# CONFIG_PKG_USING_TRACE_AGENT is not set
CONFIG_SOC_FAMILY_APM32=y
CONFIG_SOC_SERIES_APM32F4=y

1
bsp/apm32/apm32f407ig-minibroard/board/board.h
View File

@ -15,6 +15,7 @@
#include <apm32f4xx.h>
#include "apm32f4xx_gpio.h"
#include "apm32f4xx_syscfg.h"
#include "apm32f4xx_rcm.h"
#include "apm32f4xx_misc.h"
#include "apm32f4xx_rcm.h"

740
bsp/apm32/apm32f407ig-minibroard/project.uvoptx
View File

@ -10,7 +10,7 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
@ -175,11 +175,747 @@
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214
bsp/apm32/apm32f407ig-minibroard/project.uvprojx
View File

@ -1,43 +1,46 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>APM32F407IG</Device>
<Vendor>Geehy</Vendor>
<PackID>Geehy.APM32F4xx_DFP.1.0.1</PackID>
<PackID>Geehy.APM32F4xx_DFP.1.0.2</PackID>
<PackURL>https://www.geehy.com/uploads/tool/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec />
<StartupFile />
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F4xx_1024 -FS08000000 -FL080000 -FP0($$Device:APM32F407IG$Flash\APM32F4xx_1024.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile />
<MemoryEnv />
<Cmp />
<Asm />
<Linker />
<OHString />
<InfinionOptionDll />
<SLE66CMisc />
<SLE66AMisc />
<SLE66LinkerMisc />
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:APM32F407IG$SVD\APM32F40x.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath />
<IncludePath />
<LibPath />
<RegisterFilePath />
<DBRegisterFilePath />
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
@ -59,8 +62,8 @@
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
@ -69,8 +72,8 @@
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
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<nStopB1X>0</nStopB1X>
@ -80,14 +83,14 @@
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name />
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
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</AfterMake>
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<SVCSIdString />
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
@ -101,8 +104,8 @@
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument />
<IncludeLibraryModules />
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
@ -135,11 +138,11 @@
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3 />
<Flash4 />
<pFcarmOut />
<pFcarmGrp />
<pFcArmRoot />
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
@ -172,7 +175,7 @@
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName />
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
@ -182,6 +185,7 @@
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
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<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -305,7 +309,7 @@
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector />
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
@ -332,10 +336,10 @@
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls />
<Define>__STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, APM32F40X, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARM_LIBC</Define>
<Undefine />
<IncludePath>applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc;..\libraries\APM32F4xx_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
<MiscControls></MiscControls>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, APM32F40X, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;.;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F4xx_Library\CMSIS\Include;..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;..\..\..\components\drivers\include;board;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\stdio;..\..\..\components\dfs\include;applications;..\libraries\Drivers\config;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\drivers\include;..\libraries\APM32F4xx_Library\APM32F4xx_ETH_Driver\inc;..\..\..\components\libc\compilers\common\extension;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -348,12 +352,12 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls />
<Define />
<Undefine />
<IncludePath />
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
@ -365,13 +369,13 @@
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase />
<pXoBase></pXoBase>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs />
<IncludeLibsPath />
<Misc />
<LinkerInputFile />
<DisabledWarnings />
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
@ -394,50 +398,36 @@
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<FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
</File>
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<Files>
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<FileName>cstdio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstdio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cstdlib.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cstring.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstring.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ctime.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cwchar.c</FileName>
<FileType>1</FileType>
@ -447,35 +437,22 @@
</Group>
<Group>
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>div0.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cpuport.c</FileName>
<FileType>1</FileType>
@ -491,57 +468,41 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ringblk_buf.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
@ -557,29 +518,21 @@
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>startup_apm32f40x.s</FileName>
<FileType>2</FileType>
<FilePath>..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Source\arm\startup_apm32f40x.s</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>drv_common.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_common.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\Drivers\drv_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>drv_usart.c</FileName>
<FileType>1</FileType>
@ -595,22 +548,16 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs_posix.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs_fs.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs_fs.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\dfs\src\dfs.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>dfs_file.c</FileName>
<FileType>1</FileType>
@ -626,29 +573,21 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_parse.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>msh_file.c</FileName>
<FileType>1</FileType>
@ -664,85 +603,61 @@
<FileType>1</FileType>
<FilePath>..\..\..\src\clock.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\components.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\device.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\idle.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\irq.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\kservice.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mem.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mempool.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\scheduler.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\thread.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
@ -758,36 +673,31 @@
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_usart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f4xx_syscfg.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_syscfg.c</FilePath>
</File>
<File>
<FileName>apm32f4xx_rcm.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_rcm.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f4xx_eint.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_eint.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f4xx_misc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_misc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>apm32f4xx_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>system_apm32f4xx.c</FileName>
<FileType>1</FileType>
@ -798,9 +708,11 @@
</Groups>
</Target>
</Targets>
<RTE>
<apis />
<components />
<files />
<apis/>
<components/>
<files/>
</RTE>
</Project>

44
bsp/apm32/apm32f407ig-minibroard/rtconfig.h
View File

@ -47,9 +47,9 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40101
#define ARCH_ARM
#define RT_VER_NUM 0x50000
#define RT_USING_CPU_FFS
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
@ -82,6 +82,7 @@
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
@ -170,6 +171,11 @@
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
@ -177,6 +183,9 @@
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
@ -187,13 +196,38 @@
/* entertainment: terminal games and other interesting software packages */
/* Privated Packages of RealThread */
/* Arduino libraries */
/* Network Utilities */
/* Projects */
/* RT-Thread Smart */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
#define SOC_FAMILY_APM32
#define SOC_SERIES_APM32F4

364
bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_adc.h Normal file
View File

@ -0,0 +1,364 @@
/*!
* @file apm32f0xx_adc.h
*
* @brief This file contains all the functions prototypes for the ADC firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_ADC_H
#define __APM32F0XX_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup ADC_Driver
@{
*/
/** @defgroup ADC_Macros Macros
@{
*/
/* ADC_channels */
#define ADC_Channel_TempSensor ((uint32_t)ADC_CHANNEL_16) /*!< ADC TempSensor Channel definition */
#define ADC_Channel_Vrefint ((uint32_t)ADC_CHANNEL_17) /*!< ADC Vrefint Channel definition */
#define ADC_Channel_Vbat ((uint32_t)ADC_CHANNEL_18) /*!< ADC Vbat Channel definition */
/* ADC CFG mask */
#define CFG1_CLEAR_MASK ((uint32_t)0xFFFFD203)
/* Calibration time out */
#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000)
/**@} end of group ADC_Macros */
/** @defgroup ADC_Enumerations Enumerations
@{
*/
/**
* @brief ADC conversion mode
*/
typedef enum
{
ADC_CONVERSION_SINGLE = ((uint8_t)0), /*!< Single conversion mode */
ADC_CONVERSION_CONTINUOUS = ((uint8_t)1), /*!< Continuous conversion mode */
} ADC_CONVERSION_T;
/**
* @brief ADC Jitter
*/
typedef enum
{
ADC_JITTER_PCLKDIV2 = ((uint8_t)0x01), /*!< ADC clocked by PCLK div2 */
ADC_JITTER_PCLKDIV4 = ((uint8_t)0x02), /*!< ADC clocked by PCLK div4 */
} ADC_JITTER_T;
/**
* @brief ADC clock mode
*/
typedef enum
{
ADC_CLOCK_MODE_ASYNCLK = ((uint8_t)0x00), /*!< ADC Asynchronous clock mode */
ADC_CLOCK_MODE_SYNCLKDIV2 = ((uint8_t)0x01), /*!< Synchronous clock mode divided by 2 */
ADC_CLOCK_MODE_SYNCLKDIV4 = ((uint8_t)0x02), /*!< Synchronous clock mode divided by 4 */
} ADC_CLOCK_MODE_T;
/**
* @brief ADC data resolution
*/
typedef enum
{
ADC_RESOLUTION_12B = ((uint8_t)0x00), /*!< ADC Resolution is 12 bits */
ADC_RESOLUTION_10B = ((uint8_t)0x01), /*!< ADC Resolution is 10 bits */
ADC_RESOLUTION_8B = ((uint8_t)0x02), /*!< ADC Resolution is 8 bits */
ADC_RESOLUTION_6B = ((uint8_t)0x03), /*!< ADC Resolution is 6 bits */
} ADC_RESOLUTION_T;
/**
* @brief ADC data alignment
*/
typedef enum
{
ADC_DATA_ALIGN_RIGHT = ((uint8_t)0), /*!< Data alignment right */
ADC_DATA_ALIGN_LEFT = ((uint8_t)1), /*!< Data alignment left */
} ADC_DATA_ALIGN_T;
/**
* @brief ADC scan sequence direction
*/
typedef enum
{
ADC_SCAN_DIR_UPWARD = ((uint8_t)0), /*!< from CHSEL0 to CHSEL17 */
ADC_SCAN_DIR_BACKWARD = ((uint8_t)1), /*!< from CHSEL17 to CHSEL0 */
} ADC_SCAN_DIR_T;
/**
* @brief ADC DMA Mode
*/
typedef enum
{
ADC_DMA_MODE_ONESHOUT = ((uint8_t)0), /*!< ADC DMA Mode Select one shot */
ADC_DMA_MODE_CIRCULAR = ((uint8_t)1), /*!< ADC DMA Mode Select circular */
} ADC_DMA_MODE_T;
/**
* @brief ADC external conversion trigger edge selectio
*/
typedef enum
{
ADC_EXT_TRIG_EDGE_NONE = ((uint8_t)0x00), /*!< ADC External Trigger Conversion mode disabled */
ADC_EXT_TRIG_EDGE_RISING = ((uint8_t)0x01), /*!< ADC External Trigger Conversion mode rising edge */
ADC_EXT_TRIG_EDGE_FALLING = ((uint8_t)0x02), /*!< ADC External Trigger Conversion mode falling edge */
ADC_EXT_TRIG_EDGE_ALL = ((uint8_t)0x03), /*!< ADC External Trigger Conversion mode rising and falling edges */
} ADC_EXT_TRIG_EDGE_T;
/**
* @brief ADC external trigger sources selection
*/
typedef enum
{
ADC_EXT_TRIG_CONV_TRG0 = ((uint8_t)0x00), /*!< ADC External Trigger Conversion timer1 TRG0 */
ADC_EXT_TRIG_CONV_TRG1 = ((uint8_t)0x01), /*!< ADC External Trigger Conversion timer1 CC4 */
ADC_EXT_TRIG_CONV_TRG2 = ((uint8_t)0x02), /*!< ADC External Trigger Conversion timer2 TRGO */
ADC_EXT_TRIG_CONV_TRG3 = ((uint8_t)0x03), /*!< ADC External Trigger Conversion timer3 TRG0 */
ADC_EXT_TRIG_CONV_TRG4 = ((uint8_t)0x04), /*!< ADC External Trigger Conversion timer15 TRG0 */
} ADC_EXT_TRIG_CONV_T;
/**
* @brief ADC analog watchdog channel selection
*/
typedef enum
{
ADC_ANALG_WDT_CHANNEL_0 = ((uint8_t)0x00), /*!< AWD Channel 0 */
ADC_ANALG_WDT_CHANNEL_1 = ((uint8_t)0x01), /*!< AWD Channel 1 */
ADC_ANALG_WDT_CHANNEL_2 = ((uint8_t)0x02), /*!< AWD Channel 2 */
ADC_ANALG_WDT_CHANNEL_3 = ((uint8_t)0x03), /*!< AWD Channel 3 */
ADC_ANALG_WDT_CHANNEL_4 = ((uint8_t)0x04), /*!< AWD Channel 4 */
ADC_ANALG_WDT_CHANNEL_5 = ((uint8_t)0x05), /*!< AWD Channel 5 */
ADC_ANALG_WDT_CHANNEL_6 = ((uint8_t)0x06), /*!< AWD Channel 6 */
ADC_ANALG_WDT_CHANNEL_7 = ((uint8_t)0x07), /*!< AWD Channel 7 */
ADC_ANALG_WDT_CHANNEL_8 = ((uint8_t)0x08), /*!< AWD Channel 8 */
ADC_ANALG_WDT_CHANNEL_9 = ((uint8_t)0x09), /*!< AWD Channel 9 */
ADC_ANALG_WDT_CHANNEL_10 = ((uint8_t)0x0A), /*!< AWD Channel 10 */
ADC_ANALG_WDT_CHANNEL_11 = ((uint8_t)0x0B), /*!< AWD Channel 11 */
ADC_ANALG_WDT_CHANNEL_12 = ((uint8_t)0x0C), /*!< AWD Channel 12 */
ADC_ANALG_WDT_CHANNEL_13 = ((uint8_t)0x0D), /*!< AWD Channel 13 */
ADC_ANALG_WDT_CHANNEL_14 = ((uint8_t)0x0E), /*!< AWD Channel 14 */
ADC_ANALG_WDT_CHANNEL_15 = ((uint8_t)0x0F), /*!< AWD Channel 15 */
ADC_ANALG_WDT_CHANNEL_16 = ((uint8_t)0x10), /*!< AWD Channel 16 */
ADC_ANALG_WDT_CHANNEL_17 = ((uint8_t)0x11), /*!< AWD Channel 17 */
ADC_ANALG_WDT_CHANNEL_18 = ((uint8_t)0x12), /*!< AWD Channel 18 */
} ADC_ANALG_WDT_CHANNEL_T;
/**
* @brief ADC sampling times
*/
typedef enum
{
ADC_SAMPLE_TIME_1_5 = ((uint8_t)0x00), /*!< 1.5 ADC clock cycles */
ADC_SAMPLE_TIME_7_5 = ((uint8_t)0x01), /*!< 7.5 ADC clock cycles */
ADC_SAMPLE_TIME_13_5 = ((uint8_t)0x02), /*!< 13.5 ADC clock cycles */
ADC_SAMPLE_TIME_28_5 = ((uint8_t)0x03), /*!< 28.5 ADC clock cycles */
ADC_SAMPLE_TIME_41_5 = ((uint8_t)0x04), /*!< 41.5 ADC clock cycles */
ADC_SAMPLE_TIME_55_5 = ((uint8_t)0x05), /*!< 55.5 ADC clock cycles */
ADC_SAMPLE_TIME_71_5 = ((uint8_t)0x06), /*!< 71.5 ADC clock cycles */
ADC_SAMPLE_TIME_239_5 = ((uint8_t)0x07), /*!< 239.5 ADC clock cycles */
} ADC_SAMPLE_TIME_T;
/**
* @brief ADC channel selection
*/
typedef enum
{
ADC_CHANNEL_0 = ((uint32_t)0x00000001), /*!< ADC Channel 0 */
ADC_CHANNEL_1 = ((uint32_t)0x00000002), /*!< ADC Channel 1 */
ADC_CHANNEL_2 = ((uint32_t)0x00000004), /*!< ADC Channel 2 */
ADC_CHANNEL_3 = ((uint32_t)0x00000008), /*!< ADC Channel 3 */
ADC_CHANNEL_4 = ((uint32_t)0x00000010), /*!< ADC Channel 4 */
ADC_CHANNEL_5 = ((uint32_t)0x00000020), /*!< ADC Channel 5 */
ADC_CHANNEL_6 = ((uint32_t)0x00000040), /*!< ADC Channel 6 */
ADC_CHANNEL_7 = ((uint32_t)0x00000080), /*!< ADC Channel 7 */
ADC_CHANNEL_8 = ((uint32_t)0x00000100), /*!< ADC Channel 8 */
ADC_CHANNEL_9 = ((uint32_t)0x00000200), /*!< ADC Channel 9 */
ADC_CHANNEL_10 = ((uint32_t)0x00000400), /*!< ADC Channel 10 */
ADC_CHANNEL_11 = ((uint32_t)0x00000800), /*!< ADC Channel 11 */
ADC_CHANNEL_12 = ((uint32_t)0x00001000), /*!< ADC Channel 12 */
ADC_CHANNEL_13 = ((uint32_t)0x00002000), /*!< ADC Channel 13 */
ADC_CHANNEL_14 = ((uint32_t)0x00004000), /*!< ADC Channel 14 */
ADC_CHANNEL_15 = ((uint32_t)0x00008000), /*!< ADC Channel 15 */
ADC_CHANNEL_16 = ((uint32_t)0x00010000), /*!< ADC Channel 16 */
ADC_CHANNEL_17 = ((uint32_t)0x00020000), /*!< ADC Channel 17 */
ADC_CHANNEL_18 = ((uint32_t)0x00040000), /*!< ADC Channel 18 (Not for APM32F030 devices) */
} ADC_CHANNEL_T;
/**
* @brief ADC interrupts definition
*/
typedef enum
{
ADC_INT_ADRDY = ((uint8_t)0x01), /*!< ADC ready interrupt */
ADC_INT_CSMP = ((uint8_t)0x02), /*!< End of sampling interrupt */
ADC_INT_CC = ((uint8_t)0x04), /*!< End of conversion interrupt */
ADC_INT_CS = ((uint8_t)0x08), /*!< End of sequence interrupt */
ADC_INT_OVR = ((uint8_t)0x10), /*!< ADC overrun interrupt */
ADC_INT_AWD = ((uint8_t)0x80), /*!< Analog watchdog interrupt */
} ADC_INT_T;
/**
* @brief ADC Interrupt flag
*/
typedef enum
{
ADC_INT_FLAG_ADRDY = ((uint8_t)0x01), /*!< ADC ready interrupt flag */
ADC_INT_FLAG_CSMP = ((uint8_t)0x02), /*!< End of sampling interrupt flag */
ADC_INT_FLAG_CC = ((uint8_t)0x04), /*!< End of conversion interrupt flag */
ADC_INT_FLAG_CS = ((uint8_t)0x08), /*!< End of sequence interrupt flag */
ADC_INT_FLAG_OVR = ((uint8_t)0x10), /*!< ADC overrun interrupt flag */
ADC_INT_FLAG_AWD = ((uint8_t)0x80), /*!< Analog watchdog interrupt flag */
} ADC_INT_FLAG_T;
/**
* @brief ADC flag
*/
typedef enum
{
ADC_FLAG_ADCON = ((uint32_t)0x01000001), /*!< ADC enable flag */
ADC_FLAG_ADCOFF = ((uint32_t)0x01000002), /*!< ADC disable flag */
ADC_FLAG_ADCSTA = ((uint32_t)0x01000004), /*!< ADC start conversion flag */
ADC_FLAG_ADCSTOP = ((uint32_t)0x01000010), /*!< ADC stop conversion flag */
ADC_FLAG_ADCCAL = ((int) 0x81000000), /*!< ADC calibration flag */
ADC_FLAG_ADRDY = ((uint8_t)0x01), /*!< ADC ready flag */
ADC_FLAG_CSMP = ((uint8_t)0x02), /*!< End of sampling flag */
ADC_FLAG_CC = ((uint8_t)0x04), /*!< End of conversion flag */
ADC_FLAG_CS = ((uint8_t)0x08), /*!< End of sequence flag */
ADC_FLAG_OVR = ((uint8_t)0x10), /*!< ADC overrun flag */
ADC_FLAG_AWD = ((uint8_t)0x80), /*!< Analog watchdog flag */
} ADC_FLAG_T;
/**@} end of group ADC_Enumerations */
/** @defgroup ADC_Structures Structures
@{
*/
/**
* @brief ADC Config struct definition
*/
typedef struct
{
ADC_RESOLUTION_T resolution; /*!< Specifies the ADC data resolution */
ADC_DATA_ALIGN_T dataAlign; /*!< Specifies the data alignment mode */
ADC_SCAN_DIR_T scanDir; /*!< Specifies the scan mode */
ADC_CONVERSION_T convMode; /*!< Specifies the conversion mode */
ADC_EXT_TRIG_CONV_T extTrigConv; /*!< Specifies the external trigger sources */
ADC_EXT_TRIG_EDGE_T extTrigEdge; /*!< Specifies the external conversion trigger edge */
} ADC_Config_T;
/**@} end of group ADC_Structures */
/** @defgroup ADC_Variables Variables
@{
*/
/**@} end of group ADC_Variables */
/** @defgroup ADC_Functions Functions
@{
*/
/* ADC reset and configuration */
void ADC_Reset(void);
void ADC_Config(ADC_Config_T* adcConfig);
void ADC_ConfigStructInit(ADC_Config_T* adcConfig);
void ADC_Enable(void);
void ADC_Disable(void);
void ADC_EnableAutoPowerOff(void);
void ADC_DisableAutoPowerOff(void);
void ADC_EnableWaitMode(void);
void ADC_DisableWaitMode(void);
void ADC_ConfigChannel(uint32_t channel, uint8_t sampleTime);
void ADC_EnableContinuousMode(void);
void ADC_DisableContinuousMode(void);
void ADC_EnableDiscMode(void);
void ADC_DisableDiscMode(void);
void ADC_EnableOverrunMode(void);
void ADC_DisableOverrunMode(void);
void ADC_StopConversion(void);
void ADC_StartConversion(void);
void ADC_DMARequestMode(ADC_DMA_MODE_T DMARequestMode);
/* ADC clock and jitter */
void ADC_ClockMode(ADC_CLOCK_MODE_T clockMode);
void ADC_EnableJitter(ADC_JITTER_T jitter);
void ADC_DisableJitter(ADC_JITTER_T jitter);
/* ADC analog watchdog */
void ADC_EnableAnalogWatchdog(void);
void ADC_DisableAnalogWatchdog(void);
void ADC_AnalogWatchdogLowThreshold(uint16_t lowThreshold);
void ADC_AnalogWatchdogHighThreshold(uint16_t highThreshold);
void ADC_AnalogWatchdogSingleChannel(uint32_t channel);
void ADC_EnableAnalogWatchdogSingleChannel(void);
void ADC_DisableAnalogWatchdogSingleChannel(void);
/* ADC common configuration */
void ADC_EnableTempSensor(void);
void ADC_DisableTempSensor(void);
void ADC_EnableVrefint(void);
void ADC_DisableVrefint(void);
void ADC_EnableVbat(void); /*!< Not for APM32F030 devices */
void ADC_DisableVbat(void); /*!< Not for APM32F030 devices */
/* Read data */
uint32_t ADC_ReadCalibrationFactor(void);
uint16_t ADC_ReadConversionValue(void);
/* DMA */
void ADC_EnableDMA(void);
void ADC_DisableDMA(void);
/* Interrupt and flag */
void ADC_EnableInterrupt(uint8_t interrupt);
void ADC_DisableInterrupt(uint8_t interrupt);
uint8_t ADC_ReadStatusFlag(ADC_FLAG_T flag);
void ADC_ClearStatusFlag(uint32_t flag);
uint8_t ADC_ReadIntFlag(ADC_INT_FLAG_T flag);
void ADC_ClearIntFlag(uint32_t flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_ADC_H */
/**@} end of group ADC_Functions */
/**@} end of group ADC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_can.h
*
* @brief This file contains all the functions prototypes for the CAN firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_CAN_H
#define __APM32F0XX_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup CAN_Driver
@{
*/
/** @defgroup CAN_Macros Macros
@{
*/
/**@} end of group CAN_Macros */
/** @defgroup CAN_Enumerations Enumerations
@{
*/
/**
* @brief CAN operating mode
*/
typedef enum
{
CAN_OPERATING_MODE_INIT = ((uint8_t)00), /*!< Initialization mode */
CAN_OPERATING_MODE_NORMAL = ((uint8_t)01), /*!< Normal mode */
CAN_OPERATING_MODE_SLEEP = ((uint8_t)02), /*!< sleep mode */
} CAN_OPERATING_MODE_T;
/**
* @brief CAN test mode
*/
typedef enum
{
CAN_MODE_NORMAL = ((uint8_t)00), /*!< normal mode */
CAN_MODE_LOOPBACK = ((uint8_t)01), /*!< loopback mode */
CAN_MODE_SILENT = ((uint8_t)02), /*!< silent mode */
CAN_MODE_SILENT_LOOPBACK = ((uint8_t)03), /*!< loopback combined with silent mode */
} CAN_MODE_T;
/**
* @brief CAN filter mode
*/
typedef enum
{
CAN_FILTER_MODE_IDMASK = ((uint8_t)00), /*!< identifier/mask mode */
CAN_FILTER_MODE_IDLIST = ((uint8_t)01), /*!< identifier list mode */
} CAN_FILTER_MODE_T;
/**
* @brief CAN synchronisation jump width
*/
typedef enum
{
CAN_SJW_1 = ((uint8_t)00), /*!< 1 time quantum */
CAN_SJW_2 = ((uint8_t)01), /*!< 2 time quantum */
CAN_SJW_3 = ((uint8_t)02), /*!< 3 time quantum */
CAN_SJW_4 = ((uint8_t)03), /*!< 4 time quantum */
} CAN_SJW_T;
/**
* @brief CAN_time quantum in bit_segment_1
*/
typedef enum
{
CAN_TIME_SEGMENT1_1 = (uint8_t)0x00, /*!< 1 time quanta */
CAN_TIME_SEGMENT1_2 = (uint8_t)0x01, /*!< 2 time quanta */
CAN_TIME_SEGMENT1_3 = (uint8_t)0x02, /*!< 3 time quanta */
CAN_TIME_SEGMENT1_4 = (uint8_t)0x03, /*!< 4 time quanta */
CAN_TIME_SEGMENT1_5 = (uint8_t)0x04, /*!< 5 time quanta */
CAN_TIME_SEGMENT1_6 = (uint8_t)0x05, /*!< 6 time quanta */
CAN_TIME_SEGMENT1_7 = (uint8_t)0x06, /*!< 7 time quanta */
CAN_TIME_SEGMENT1_8 = (uint8_t)0x07, /*!< 8 time quanta */
CAN_TIME_SEGMENT1_9 = (uint8_t)0x08, /*!< 9 time quanta */
CAN_TIME_SEGMENT1_10 = (uint8_t)0x09, /*!< 10 time quanta */
CAN_TIME_SEGMENT1_11 = (uint8_t)0x0A, /*!< 11 time quanta */
CAN_TIME_SEGMENT1_12 = (uint8_t)0x0B, /*!< 12 time quanta */
CAN_TIME_SEGMENT1_13 = (uint8_t)0x0C, /*!< 13 time quanta */
CAN_TIME_SEGMENT1_14 = (uint8_t)0x0D, /*!< 14 time quanta */
CAN_TIME_SEGMENT1_15 = (uint8_t)0x0E, /*!< 15 time quanta */
CAN_TIME_SEGMENT1_16 = (uint8_t)0x0F, /*!< 16 time quanta */
} CAN_TIME_SEGMENT1_T;
/**
* @brief CAN_time_quantum_in_bit_segment_2
*/
typedef enum
{
CAN_TIME_SEGMENT2_1 = (uint8_t)0x00, /*!< 1 time quanta */
CAN_TIME_SEGMENT2_2 = (uint8_t)0x01, /*!< 2 time quanta */
CAN_TIME_SEGMENT2_3 = (uint8_t)0x02, /*!< 3 time quanta */
CAN_TIME_SEGMENT2_4 = (uint8_t)0x03, /*!< 4 time quanta */
CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, /*!< 5 time quanta */
CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, /*!< 6 time quanta */
CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, /*!< 7 time quanta */
CAN_TIME_SEGMENT2_8 = (uint8_t)0x07, /*!< 8 time quanta */
} CAN_TIME_SEGMENT2_T;
/**
* @brief CAN_filter_scale
*/
typedef enum
{
CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), /*!< Two 16-bit filters */
CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01), /*!< One 32-bit filter */
} CAN_FILTER_SCALE_T;
/**
* @brief CAN identifier type
*/
typedef enum
{
CAN_TYPEID_STD = ((uint32_t)0x00000000), /*!< Standard Id */
CAN_TYPEID_EXT = ((uint32_t)0x00000004), /*!< Extended Id */
} CAN_TYPEID_T;
/**
* @brief CAN_remote_transmission_request
*/
typedef enum
{
CAN_RTXR_DATA = ((uint32_t)0x00000000), /*!< Data frame */
CAN_RTXR_REMOTE = ((uint32_t)0x00000002), /*!< Remote frame */
} CAN_RTXR_T;
/**
* @brief CAN_transmit_constants
*/
typedef enum
{
CAN_TX_FAILED = ((uint8_t)0x00), /*!< CAN transmission failed */
CAN_TX_OK = ((uint8_t)0x01), /*!< CAN transmission succeeded */
CAN_TX_WAITING = ((uint8_t)0x02), /*!< CAN waiting for transmission */
CAN_TX_MAILBOX_FULL = ((uint8_t)0x04), /*!< CAN cell did not provide */
} CAN_TX_T;
/**
* @brief CAN sleep constants
*/
typedef enum
{
CAN_SLEEP_FAILED = ((uint8_t)0x00), /*!< CAN did not enter the sleep mode */
CAN_SLEEP_OK = ((uint8_t)0x01), /*!< CAN entered the sleep mode */
} CAN_SLEEP_T;
/**
* @brief CAN wake up constants
*/
typedef enum
{
CAN_WAKEUP_FAILED = ((uint8_t)0x00), /*!< CAN did not leave the sleep mode */
CAN_WAKEUP_OK = ((uint8_t)0x01), /*!< CAN leaved the sleep mode */
} CAN_WUP_T;
/**
* @brief CAN receive FIFO
*/
typedef enum
{
CAN_FIFO_0 = ((uint8_t)0x00), /*!< CAN FIFO 0 used to receive */
CAN_FIFO_1 = ((uint8_t)0x01), /*!< CAN FIFO 1 used to receive */
} CAN_FIFO_T;
/**
* @brief CAN_error_Code_constants
*/
typedef enum
{
CAN_ERROR_CODE_NOERR = ((uint8_t)0x00), /*!< No Error */
CAN_ERROR_CODE_STUFFERR = ((uint8_t)0x10), /*!< Stuff Error */
CAN_ERROR_CODE_FORMERR = ((uint8_t)0x20), /*!< Form Error */
CAN_ERROR_CODE_ACKERR = ((uint8_t)0x30), /*!< Acknowledgment Error */
CAN_ERROR_CODE_BITRECESSIVEERR = ((uint8_t)0x40), /*!< Bit Recessive Error */
CAN_ERROR_CODE_BITDOMINANTERR = ((uint8_t)0x50), /*!< Bit Dominant Error */
CAN_ERROR_CODE_CRCERR = ((uint8_t)0x60), /*!< CRC Error */
CAN_ERROR_CODE_SOFTWARESETERR = ((uint8_t)0x70), /*!< Software Set Error */
} CAN_ERROR_CODE_T;
/**
* @brief Flags
*/
typedef enum
{
/* Error Flags */
CAN_FLAG_EWF = ((uint32_t)0x10F00001), /*!< Error Warning Flag */
CAN_FLAG_EPF = ((uint32_t)0x10F00002), /*!< Error Passive Flag */
CAN_FLAG_BOF = ((uint32_t)0x10F00004), /*!< Bus-Off Flag */
CAN_FLAG_LEC = ((uint32_t)0x30F00070), /*!< Last error code Flag */
/* Operating Mode Flags */
CAN_FLAG_WUP = ((uint32_t)0x31000008), /*!< Wake up Flag */
CAN_FLAG_SLAK = ((uint32_t)0x31000012), /*!< Sleep acknowledge Flag */
/* Transmit Flags */
CAN_FLAG_RQCP0 = ((uint32_t)0x32000001), /*!< Request MailBox0 Flag */
CAN_FLAG_RQCP1 = ((uint32_t)0x32000100), /*!< Request MailBox1 Flag */
CAN_FLAG_RQCP2 = ((uint32_t)0x32010000), /*!< Request MailBox2 Flag */
/* Receive Flags */
CAN_FLAG_FMP0 = ((uint32_t)0x14000003), /*!< FIFO 0 Message Pending Flag */
CAN_FLAG_FF0 = ((uint32_t)0x34000008), /*!< FIFO 0 Full Flag */
CAN_FLAG_FOV0 = ((uint32_t)0x34000010), /*!< FIFO 0 Overrun Flag */
CAN_FLAG_FMP1 = ((uint32_t)0x18000003), /*!< FIFO 1 Message Pending Flag */
CAN_FLAG_FF1 = ((uint32_t)0x38000008), /*!< FIFO 1 Full Flag */
CAN_FLAG_FOV1 = ((uint32_t)0x38000010), /*!< FIFO 1 Overrun Flag */
} CAN_FLAG_T;
/**
* @brief CAN interrupts
*/
typedef enum
{
CAN_INT_TXME = BIT0, /*!< Transmit mailbox empty Interrupt */
CAN_INT_F0MP = BIT1, /*!< FIFO 0 message pending Interrupt */
CAN_INT_F0FUL = BIT2, /*!< FIFO 0 full Interrupt */
CAN_INT_F0OVR = BIT3, /*!< FIFO 0 overrun Interrupt */
CAN_INT_F1MP = BIT4, /*!< FIFO 1 message pending Interrupt */
CAN_INT_F1FUL = BIT5, /*!< FIFO 1 full Interrupt */
CAN_INT_F1OVR = BIT6, /*!< FIFO 1 overrun Interrupt */
CAN_INT_EWIE = BIT8, /*!< Error warning Interrupt */
CAN_INT_EPIE = BIT9, /*!< Error passive Interrupt */
CAN_INT_BOIE = BIT10, /*!< Bus-off Interrupt */
CAN_INT_LEC = BIT11, /*!< Last error code Interrupt */
CAN_INT_ERR = BIT15, /*!< Error Interrupt */
CAN_INT_WUP = BIT16, /*!< Wake-up Interrupt */
CAN_INT_SLE = BIT17, /*!< Sleep acknowledge Interrupt */
} CAN_INT_T;
typedef enum
{
CAN_FILTER_NUMBER_0 = 0, /*!< Number 0 of filters */
CAN_FILTER_NUMBER_1, /*!< Number 1 of filters */
CAN_FILTER_NUMBER_2, /*!< Number 2 of filters */
CAN_FILTER_NUMBER_3, /*!< Number 3 of filters */
CAN_FILTER_NUMBER_4, /*!< Number 4 of filters */
CAN_FILTER_NUMBER_5, /*!< Number 5 of filters */
CAN_FILTER_NUMBER_6, /*!< Number 6 of filters */
CAN_FILTER_NUMBER_7, /*!< Number 7 of filters */
CAN_FILTER_NUMBER_8, /*!< Number 8 of filters */
CAN_FILTER_NUMBER_9, /*!< Number 9 of filters */
CAN_FILTER_NUMBER_10, /*!< Number 10 of filters */
CAN_FILTER_NUMBER_11, /*!< Number 11 of filters */
CAN_FILTER_NUMBER_12, /*!< Number 12 of filters */
CAN_FILTER_NUMBER_13, /*!< Number 13 of filters */
} CAN_FILTER_NUMBER_T;
typedef enum
{
CAN_MAILBOX_0 = ((uint8_t)0x00), /*!< Tx mailbox0 */
CAN_MAILBOX_1 = ((uint8_t)0x01), /*!< Tx mailbox1 */
CAN_MAILBOX_2 = ((uint8_t)0x02), /*!< Tx mailbox2 */
} CAN_MAILBOX_T;
/**@} end of group CAN_Enumerations */
/** @defgroup CAN_Structures Structures
@{
*/
/**
* @brief CAN config structure definition
*/
typedef struct
{
uint8_t timeTrigComMode; /*!< Enable or disable the time triggered communication mode */
uint8_t autoBusOffManage; /*!< Enable or disable the automatic bus-off management */
uint8_t autoWakeUpMode; /*!< Enable or disable the automatic wake-up mode */
uint8_t nonAutoRetran; /*!< Enable or disable the non-automatic retransmission mode */
uint8_t rxFIFOLockMode; /*!< Enable or disable the Receive FIFO Locked mode */
uint32_t txFIFOPriority; /*!< Enable or disable the transmit FIFO priority */
CAN_MODE_T mode; /*!< Specifies the CAN operating mode */
CAN_SJW_T syncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
is allowed to lengthen or shorten a bit to perform resynchronization. */
CAN_TIME_SEGMENT1_T timeSegment1; /*!< Specifies the number of time quanta in Bit Segment 1 */
CAN_TIME_SEGMENT2_T timeSegment2; /*!< Specifies the number of time quanta in Bit Segment 2 */
uint16_t prescaler; /*!< Specifies the length of a time quantum. It can be 1 to 1024 */
} CAN_Config_T;
/**
* @brief CAN filter config structure definition
*/
typedef struct
{
uint16_t filterIdHigh; /*!< Specifies the filter identification number. */
uint16_t filterIdLow; /*!< Specifies the filter identification number. */
uint16_t filterMaskIdHigh; /*!< Specifies the filter mask number or identification number. */
uint16_t filterMaskIdLow; /*!< Specifies the filter mask number or identification number. */
CAN_FIFO_T filterFIFO; /*!< Specifies the FIFO which will be assigned to the filter. */
CAN_FILTER_NUMBER_T filterNumber; /*!< Specifies the filter which will be configured. It ranges from 0 to 13. */
CAN_FILTER_MODE_T filterMode; /*!< Specifies the filter mode to be configured. */
CAN_FILTER_SCALE_T filterScale; /*!< Specifies the filter scale. */
uint8_t filterActivation; /*!< Enable or disable the filter. */
} CAN_FilterConfig_T;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t stanID; /*!< Specifies the standard identifier. */
uint32_t extenID; /*!< Specifies the extended identifier. */
CAN_TYPEID_T typeID; /*!< Specifies the type of identifier for the message. */
CAN_RTXR_T remoteTxReq; /*!< Specifies the type of frame for the message. */
uint8_t dataLengthCode; /*!< Specifies the length of the frame. It can be a value between 0 to 8. */
uint8_t data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
} CAN_Tx_Message;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t stanID; /*!< Specifies the standard identifier. */
uint32_t extenID; /*!< Specifies the extended identifier. */
CAN_TYPEID_T typeID; /*!< Specifies the type of identifier for the message. */
CAN_RTXR_T remoteTxReq; /*!< Specifies the type of frame for the message. */
uint8_t dataLengthCode; /*!< Specifies the length of the frame. It can be a value between 0 to 8. */
uint8_t data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
uint8_t filterMatchIndex; /*!< Specifies the index of the filter the message stored in the mailbox passes through. */
} CAN_Rx_Message;
/**@} end of group CAN_Structures */
/** @defgroup CAN_Variables Variables
@{
*/
/**@} end of group CAN_Variables */
/** @defgroup CAN_Functions Functions
@{
*/
/* CAN reset and configuration */
void CAN_Reset(void);
uint8_t CAN_Config(CAN_Config_T* canConfig);
void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig);
void CAN_ConfigStructInit(CAN_Config_T* canConfig);
void CAN_StartBankSlave(uint8_t bankNumber);
void CAN_EnableDebugFreeze(void);
void CAN_DisableDebugFreeze(void);
void CAN_EnableTTComMode(void);
void CAN_DisableTTComMode(void);
/* CAN frames transmission */
uint8_t CAN_TxMessage(CAN_Tx_Message* TxMessage);
uint8_t CAN_TxMessageStatus(CAN_MAILBOX_T TxMailbox);
void CAN_CancelTx(CAN_MAILBOX_T TxMailbox);
/* CAN frames reception */
void CAN_RxMessage(uint8_t FIFONumber, CAN_Rx_Message* RxMessage);
void CAN_ReleaseFIFO(uint8_t FIFONumber);
uint8_t CAN_PendingMessage(uint8_t FIFONumber);
/* CAN operation modes */
uint8_t CAN_OperatingMode(CAN_OPERATING_MODE_T operatingMode);
uint8_t CAN_SleepMode(void);
uint8_t CAN_WakeUpMode(void);
/* CAN bus error management */
uint8_t CAN_ReadLastErrorCode(void);
uint8_t CAN_ReadRxErrorCounter(void);
uint8_t CAN_ReadLSBTxErrorCounter(void);
/* CAN interrupt and flag */
void CAN_EnableInterrupt(uint32_t interrupt);
void CAN_DisableInterrupt(uint32_t interrupt);
uint8_t CAN_ReadStatusFlag(CAN_FLAG_T CAN_FLAG);
void CAN_ClearStatusFlag(CAN_FLAG_T flag);
uint8_t CAN_ReadIntFlag(CAN_INT_T interrupt);
void CAN_ClearIntFlag(uint32_t interrupt);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_CAN_H */
/**@} end of group CAN_Functions */
/**@} end of group CAN_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_cec.h
*
* @brief This file contains all the functions prototypes for the CEC firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_CEC_H
#define __APM32F0XX_CEC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup CEC_Driver
@{
*/
/** @defgroup CEC_Macros Macros
@{
*/
/**@} end of group CEC_Macros */
/** @defgroup CEC_Enumerations Enumerations
@{
*/
/**
* @brief CEC_Signal_Free_Time
*/
typedef enum
{
CEC_SINGANL_FREETIME_STANDARD = 0x00, /*!< none nominal data bit periods */
CEC_SINGANL_FREETIME_1T = 0x01, /*!< 0.5 nominal data bit periods */
CEC_SINGANL_FREETIME_2T = 0x02, /*!< 1.5 nominal data bit periods */
CEC_SINGANL_FREETIME_3T = 0x03, /*!< 2.5 nominal data bit periods */
CEC_SINGANL_FREETIME_4T = 0x04, /*!< 3.5 nominal data bit periods */
CEC_SINGANL_FREETIME_5T = 0x05, /*!< 4.5 nominal data bit periods */
CEC_SINGANL_FREETIME_6T = 0x06, /*!< 5.5 nominal data bit periods */
CEC_SINGANL_FREETIME_7T = 0x07, /*!< 6.5 nominal data bit periods */
} CEC_SIGNAL_FREETIME_T;
/**
* @brief CEC_RxTolerance
*/
typedef enum
{
CEC_RX_TOLERANCE_STANDARD = 0x00, /*!< Standard tolerance margin */
CEC_RX_TOLERANCE_EXTENDED = 0x01 /*!< Extended Tolerance */
} CEC_RX_TOLERANCE_T;
/**
* @brief CEC_Stop_Reception
*/
typedef enum
{
CEC_STOP_RECEPTION_OFF, /*!< CEC Stop Reception Off */
CEC_STOP_RECEPTION_ON /*!< CEC Stop Reception On */
} CEC_STOP_RECEPTION_T;
/**
* @brief CEC_Bit_Rising_Error_Generation
*/
typedef enum
{
CEC_BIT_RISING_ERR_OFF, /*!< BRE detection does not generate an Error-Bit on the CEC line */
CEC_BIT_RISING_ERR_ON /*!< BRE detection generates an Error-Bit on the CEC line (if BRESTP is set) */
} CEC_BIT_RISING_ERR_T;
/**
* @brief CEC_Long_Bit_Error_Generation
*/
typedef enum
{
CEC_LONG_PERIOD_ERR_OFF, /*!< LBPE detection does not generate an Error-Bit on the CEC line */
CEC_LONG_PERIOD_ERR_ON /*!< LBPE detection generates an Error-Bit on the CEC line */
} CEC_LONG_PERIOD_ERR_T;
/**
* @brief CEC_BDR_No_Gen
*/
typedef enum
{
CEC_BROADCAST_NO_ERR_OFF, /*!< Broadcast Bit Rising Error generation turned Off */
CEC_BROADCAST_NO_ERR_ON /*!< Broadcast Bit Rising Error generation turned On */
} CEC_BROADCAST_NO_ERR_T;
/**
* @brief CEC_SFT_Option
*/
typedef enum
{
CEC_SIGNAL_FREETIME_OPTION_OFF, /*!< SFTCFG timer starts when TXSOM is set by software */
CEC_SIGNAL_FREETIME_OPTION_ON /*!< SFTCFG timer starts automatically at the end of message transmission/reception */
} CEC_SIGNAL_FREETIME_OPTION_T;
/**
* @brief CEC_Interrupt_Configuration_definition
*/
typedef enum
{
CEC_INT_RXBR = ((uint32_t)0x00000001), /*!< Rx-Byte Received Interrupt */
CEC_INT_RXEND = ((uint32_t)0x00000002), /*!< End Of Reception Interrupt */
CEC_INT_RXOVR = ((uint32_t)0x00000004), /*!< Rx-Buffer Overrun Interrupt */
CEC_INT_BRE = ((uint32_t)0x00000008), /*!< Bit Rising Error Interrupt */
CEC_INT_SBPE = ((uint32_t)0x00000010), /*!< Short Bit Period Error Interrupt */
CEC_INT_LBPE = ((uint32_t)0x00000020), /*!< Long Bit Period Error Interrupt */
CEC_INT_RXACKE = ((uint32_t)0x00000040), /*!< Rx-Missing Acknowledge Error Interrupt */
CEC_INT_ARBLST = ((uint32_t)0x00000080), /*!< Arbitration Lost Interrupt */
CEC_INT_TXBR = ((uint32_t)0x00000100), /*!< Tx-Byte Request Interrupt */
CEC_INT_TXEND = ((uint32_t)0x00000200), /*!< Tx-End Of Message Interrupt */
CEC_INT_TXUDR = ((uint32_t)0x00000400), /*!< Tx-Underrun Interrupt */
CEC_INT_TXERR = ((uint32_t)0x00000800), /*!< Tx-Error Interrupt */
CEC_INT_TXACKE = ((uint32_t)0x00001000), /*!< Tx-Missing Acknowledge Error Interrupt */
} CEC_INT_T;
/**
* @brief CEC_STS_register_flags_definition
*/
typedef enum
{
CEC_FLAG_RXBR = ((uint32_t)0x00000001), /*!< Rx-Byte Received Flag */
CEC_FLAG_RXEND = ((uint32_t)0x00000002), /*!< End Of Reception Flag */
CEC_FLAG_RXOVR = ((uint32_t)0x00000004), /*!< Rx-Buffer Overrun Flag */
CEC_FLAG_BRE = ((uint32_t)0x00000008), /*!< Bit Rising Error Flag */
CEC_FLAG_SBPE = ((uint32_t)0x00000010), /*!< Short Bit Period Error Flag */
CEC_FLAG_LBPE = ((uint32_t)0x00000020), /*!< Long Bit Period Error Flag */
CEC_FLAG_RXACKE = ((uint32_t)0x00000040), /*!< Rx-Missing Acknowledge Error Flag */
CEC_FLAG_ARBLST = ((uint32_t)0x00000080), /*!< Arbitration Lost Flag */
CEC_FLAG_TXBR = ((uint32_t)0x00000100), /*!< Tx-Byte Request Flag */
CEC_FLAG_TXEND = ((uint32_t)0x00000200), /*!< Tx-End Of Message Flag */
CEC_FLAG_TXUDR = ((uint32_t)0x00000400), /*!< Tx-Underrun Flag */
CEC_FLAG_TXERR = ((uint32_t)0x00000800), /*!< Tx-Error Flag */
CEC_FLAG_TXACKE = ((uint32_t)0x00001000), /*!< Tx-Missing Acknowledge Error Flag */
} CEC_FLAG_T;
/**@} end of group CEC_Enumerations */
/** @defgroup CEC_Structures Structures
@{
*/
/**
* @brief CEC Init structure definition
*/
typedef struct
{
CEC_SIGNAL_FREETIME_T signalFreeTime; /*!< Signal Free Time */
CEC_RX_TOLERANCE_T RxTolerance; /*!< Rx-Tolerance */
CEC_STOP_RECEPTION_T stopReception; /*!< Rx-Stop on Bit Rising Error */
CEC_BIT_RISING_ERR_T bitRisingError; /*!< Generate Error-Bit on Bit Rising Error */
CEC_LONG_PERIOD_ERR_T longPeriodError; /*!< Generate Error-Bit on Long Bit Period Error */
CEC_BROADCAST_NO_ERR_T broadcastrNoGen; /*!< Avoid Error-Bit Generation in Broadcast */
CEC_SIGNAL_FREETIME_OPTION_T signalFreeTimeOption;/*!< Signal Free Time optional */
} CEC_Config_T;
/**@} end of group CEC_Structures */
/** @defgroup CEC_Variables Variables
@{
*/
/**@} end of group CEC_Variables */
/** @defgroup CEC_Functions Functions
@{
*/
/* CEC reset and configuration */
void CEC_Reset(void);
void CEC_Config(CEC_Config_T* cecConfig);
void CEC_ConfigStructInit(CEC_Config_T* cecConfig);
void CEC_Enable(void);
void CEC_Disable(void);
void CEC_EnableListenMode(void);
void CEC_DisableListenMode(void);
void CEC_ConfigOwnAddress(uint8_t ownAddress);
void CEC_ClearQwnAddress(void);
/* Transmit and receive */
void CEC_TxData(uint8_t Data);
uint8_t CEC_RxData(void);
/* Config Message */
void CEC_StartNewMessage(void);
void CEC_CompleteMessage(void);
/* Interrupt and Flag*/
void CEC_EnableInterrupt(uint32_t interrupt);
void CEC_DisableInterrupt(uint32_t interrupt);
uint8_t CEC_ReadStatusFlag(uint32_t flag);
void CEC_ClearStatusFlag(uint32_t flag);
uint8_t CEC_ReadIntFlag(uint16_t flag);
void CEC_ClearIntFlag(uint16_t flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_CEC_H */
/**@} end of group CEC_Functions */
/**@} end of group CEC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_comp.h
*
* @brief This file contains all the functions prototypes for the COMP firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_COMP_H
#define __APM32F0XX_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup COMP_Driver
@{
*/
/** @defgroup COMP_Macros Macros
@{
*/
/* Macros description */
#define COMP_CSTS_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output state */
#define COMP_CSTS_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output state */
#define COMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00004000) /*!< COMP output level vaild high */
#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< COMP output level vaild low */
/**@} end of group COMP_Macros */
/** @defgroup COMP_Enumerations Enumerations
@{
*/
/**
* @brief COMP_Selection
*/
typedef enum
{
COMP_SELECT_COMP1 = ((uint32_t)0x00000000), /*!< COMP1 */
COMP_SELECT_COMP2 = ((uint32_t)0x00000010) /*!< COMP2 */
} COMP_SELECT_T;
/**
* @brief COMP_InvertingInput
*/
typedef enum
{
COMP_INVERTING_INPUT_1_4VREFINT = 0x00, /*!< 1/4 of VREFINT */
COMP_INVERTING_INPUT_1_2VREFINT = 0x01, /*!< 1/2 of VREFINT */
COMP_INVERTING_INPUT_3_4VREFINT = 0x02, /*!< 3/4 of VREFINT */
COMP_INVERTING_INPUT_VREFINT = 0x03, /*!< VREFINT */
COMP_INVERTING_INPUT_DAC1 = 0x04, /*!< COMP1_INM4 (PA4 with DAC_OUT1 if enabled) */
COMP_INVERTING_INPUT_DAC2 = 0x05, /*!< COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled, only for APM32F072 and APM32F091 devices) */
COMP_INVERTING_INPUT_IO = 0x06, /*!< COMP1_INM6 (PA0) */
} COMP_INVERTING_INPUT_T;
/**
* @brief COMP_Output
*/
typedef enum
{
COMP_OUTPUT_NONE = 0x00, /*!< no selection */
COMP_OUTPUT_TIM1BKIN = 0x01, /*!< Timer 1 break input */
COMP_OUTPUT_TIM1IC1 = 0x02, /*!< Timer 1 Input capture 1 */
COMP_OUTPUT_TIM1OCREFCLR = 0x03, /*!< Timer 1 OCrefclear input */
COMP_OUTPUT_TIM2IC4 = 0x04, /*!< Timer 2 input capture 4 */
COMP_OUTPUT_TIM2OCREFCLR = 0x05, /*!< Timer 2 OCrefclear input */
COMP_OUTPUT_TIM3IC1 = 0x06, /*!< Timer 3 input capture 1 */
COMP_OUTPUT_TIM3OCREFCLR = 0x07, /*!< Timer 3 OCrefclear input */
} COMP_OUTPUT_T;
/**
* @brief COMP_OutputPolarity
*/
typedef enum
{
COMP_OUTPUTPOL_NONINVERTED, /*!< output is not inverted */
COMP_OUTPUTPOL_INVERTED /*!< output is inverted */
} COMP_OUTPUTPOL_T;
/**
* @brief COMP_Hysteresis
*/
typedef enum
{
COMP_HYSTERRSIS_NO = 0x00, /*!< No hysteresis */
COMP_HYSTERRSIS_LOW = 0x01, /*!< Low hysteresis */
COMP_HYSTERRSIS_MEDIUM = 0x02, /*!< Medium hysteresis */
COMP_HYSTERRSIS_HIGH = 0x03, /*!< High hysteresis */
} COMP_HYSTERRSIS_T;
/**
* @brief COMP_Mode
*/
typedef enum
{
COMP_MODE_HIGHSPEED = 0x00, /*!< High speed / full power */
COMP_MODE_MEDIUMSPEED = 0x01, /*!< Medium speed / medium power */
COMP_MODE_LOWPOWER = 0x02, /*!< Low speed / low-power */
COMP_MODE_VERYLOW = 0x03 /*!< Very-low speed / ultra-low power */
} COMP_MODE_T;
/**@} end of group COMP_Enumerations*/
/** @defgroup COMP_Structures Structures
@{
*/
/**
* @brief OMP Config structure definition
*/
typedef struct
{
COMP_INVERTING_INPUT_T invertingInput; /*!< Comparator inverting input selection */
COMP_OUTPUT_T output; /*!< Comparator output selection */
COMP_OUTPUTPOL_T outputPol; /*!< Comparator output polarity */
COMP_HYSTERRSIS_T hysterrsis; /*!< Comparator hysteresis */
COMP_MODE_T mode; /*!< Comparator mode */
} COMP_Config_T;
/**@} end of group COMP_Structures */
/** @defgroup COMP_Variables Variables
@{
*/
/**@} end of group COMP_Variables */
/** @defgroup COMP_Functions Functions
@{
*/
/* COMP configuration */
void COMP_Reset(void);
void COMP_Config(COMP_SELECT_T compSelect, COMP_Config_T* compConfig);
void COMP_ConfigStructInit(COMP_Config_T* compConfig);
void COMP_Enable(COMP_SELECT_T compSelect);
void COMP_Disable(COMP_SELECT_T compSelect);
void COMP_EnableSwitch(void);
void COMP_DisableSwitch(void);
uint32_t COMP_ReadOutPutLevel(COMP_SELECT_T compSelect);
/* Window mode control */
void COMP_EnableWindow(void);
void COMP_DisnableWindow(void);
/* COMP configuration locking */
void COMP_ConfigLOCK(COMP_SELECT_T compSelect);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_COMP_H */
/**@} end of group COMP_Functions */
/**@} end of group COMP_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_crc.h
*
* @brief This file contains all the functions prototypes for the CRC firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_CRC_H
#define __APM32F0XX_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup CRC_Driver
@{
*/
/** @defgroup CRC_Macros Macros
@{
*/
/**@} end of group CRC_Macros */
/** @defgroup CRC_Enumerations Enumerations
@{
*/
/**
* @brief CRC Reverse Input Data
*/
typedef enum
{
CRC_REVERSE_INPUT_DATA_NO = ((uint8_t)0x00), /*!< Bit order not affected */
CRC_REVERSE_INPUT_DATA_8B = ((uint8_t)0x01), /*!< Bit reversal done by byte */
CRC_REVERSE_INPUT_DATA_16B = ((uint8_t)0x02), /*!< Bit reversal done by half-word */
CRC_REVERSE_INPUT_DATA_32B = ((uint8_t)0x03), /*!< Bit reversal done by word */
} CRC_REVERSE_INPUT_DATA_T;
/**
* @brief CRC Polynomial Size
*/
typedef enum
{
CRC_POLYNOMIAL_SIZE_7 = ((uint8_t)0x03), /*!< 7-bit polynomial for CRC calculation */
CRC_POLYNOMIAL_SIZE_8 = ((uint8_t)0x02), /*!< 8-bit polynomial for CRC calculation */
CRC_POLYNOMIAL_SIZE_16 = ((uint8_t)0x01), /*!< 16-bit polynomial for CRC calculation */
CRC_POLYNOMIAL_SIZE_32 = ((uint8_t)0x00), /*!< 32-bit polynomial for CRC calculation */
} CRC_POLYNOMIAL_SIZE_T;
/**@} end of group CRC_Enumerations*/
/** @defgroup CRC_Structures Structures
@{
*/
/**@} end of group CRC_Structures */
/** @defgroup CRC_Variables Variables
@{
*/
/**@} end of group CRC_Variables */
/** @defgroup CRC_Functions Functions
@{
*/
/* Reset CRC */
void CRC_Reset(void);
/* Reset DATA */
void CRC_ResetDATA(void);
/* CRC Polynomial Size */
void CRC_SetPolynomialSize(CRC_POLYNOMIAL_SIZE_T polynomialSize); /*!< Only for APM32F072 and APM32F091 devices */
void CRC_SetPolynomialValue(uint32_t polynomialValue); /*!< Only for APM32F072 and APM32F091 devices */
/* Performed on input data */
void CRC_SelectReverseInputData(CRC_REVERSE_INPUT_DATA_T revInData);
/* Enable and Disable Reverse Output Data */
void CRC_EnableReverseOutputData(void);
void CRC_DisableReverseOutputData(void);
/* Write INITVAL register */
void CRC_WriteInitRegister(uint32_t initValue);
/* Calculate CRC */
uint32_t CRC_CalculateCRC(uint32_t data);
uint32_t CRC_CalculateCRC8bits(uint8_t data); /*!< Only for APM32F072 and APM32F091 devices */
uint32_t CRC_CalculateCRC16bits(uint16_t data); /*!< Only for APM32F072 and APM32F091 devices */
uint32_t CRC_CalculateBlockCRC(uint32_t pBuffer[], uint32_t bufferLength);
/* Read CRC */
uint32_t CRC_ReadCRC(void);
/* Independent Data(ID) */
void CRC_WriteIDRegister(uint8_t IDValue);
uint8_t CRC_ReadIDRegister(void);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_CRC_H */
/**@} end of group CRC_Functions */
/**@} end of group CRC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_crs.h
*
* @brief This file contains all the functions prototypes for the CRS firmware library
*
* @note It's only for APM32F072 and APM32F091 devices
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_CRS_H
#define __APM32F0XX_CRS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup CRS_Driver
@{
*/
/** @defgroup CRS_Macros Macros
@{
*/
/**@} end of group CRS_Macros */
/** @defgroup CRS_Enumerations Enumerations
@{
*/
/**
* @brief CRS_Interrupt_Sources
*/
typedef enum
{
CRS_INT_SYNCOK = ((uint32_t)0x00000001), /*!<SYNC event OK interrupt */
CRS_INT_SYNCWARN = ((uint32_t)0x00000002), /*!<SYNC warning interrupt */
CRS_INT_ERR = ((uint32_t)0x00000004), /*!<Synchronization or trimming error interrupt */
CRS_INT_ESYNC = ((uint32_t)0x00000008), /*!<Expected SYNC interrupt */
CRS_INT_SYNCERR = ((uint32_t)0x00000100), /*!<SYNC error */
CRS_INT_SYNCMISS = ((uint32_t)0x00000200), /*!<SYNC missed */
CRS_INT_TRIMOVF = ((uint32_t)0x00000400), /*!<Trimming overflow or underflow */
} CRS_INT_T;
/**
* @brief CRS_Flags
*/
typedef enum
{
CRS_FLAG_SYNCOK = ((uint32_t)0x00000001), /*!<SYNC event OK flag */
CRS_FLAG_SYNCWARN = ((uint32_t)0x00000002), /*!<SYNC warning flag */
CRS_FLAG_ERR = ((uint32_t)0x00000004), /*!<Synchronization or trimming error flag */
CRS_FLAG_ESYNC = ((uint32_t)0x00000008), /*!<Expected SYNC flag */
CRS_FLAG_SYNCERR = ((uint32_t)0x00000100), /*!<SYNC error flag */
CRS_FLAG_SYNCMISS = ((uint32_t)0x00000200), /*!<SYNC missed flag */
CRS_FLAG_TRIMOVF = ((uint32_t)0x00000400), /*!<Trimming overflow or underflow falg */
} CRS_FLAG_T;
/**
* @brief CRS_Synchro_Source
*/
typedef enum
{
CRS_SYNC_SOURCE_GPIO = 0x00, /*!<GPIO selected as SYNC signal source */
CRS_SYNC_SOURCE_LSE = 0x01, /*!<LSE selected as SYNC signal source */
CRS_SYNC_SOURCE_USB = 0x02, /*!<USB SNFLG selected as SYNC signal source (default) */
} CRS_SYNC_SOURCE_T;
/**
* @brief CRS_Synchro_Source
*/
typedef enum
{
CRS_SYNC_DIV1 = 0x00, /*!<Synchro Signal not divided (default) */
CRS_SYNC_DIV2 = 0x01, /*!<Synchro Signal divided by 2 */
CRS_SYNC_DIV4 = 0x02, /*!<Synchro Signal divided by 4 */
CRS_SYNC_DIV8 = 0x03, /*!<Synchro Signal divided by 8 */
CRS_SYNC_DIV16 = 0x04, /*!<Synchro Signal divided by 16 */
CRS_SYNC_DIV32 = 0x05, /*!<Synchro Signal divided by 32 */
CRS_SYNC_DIV64 = 0x06, /*!<Synchro Signal divided by 64 */
CRS_SYNC_DIV128 = 0x07, /*!<Synchro Signal divided by 128 */
} CRS_SYNC_DIV_T;
/**@} end of group CRS_Enumerations */
/** @defgroup CRS_Structures Structures
@{
*/
/**
* @brief CRS_SynchroPolarity
*/
typedef enum
{
CRS_SYNC_POL_RISING, /*!<Synchro active on rising edge */
CRS_SYNC_POL_FALLING /*!<Synchro active on falling edge */
} CRS_SYNC_POL_T;
/**@} end of group CRS_Structures */
/** @defgroup CRS_Variables Variables
@{
*/
/**@} end of group CRS_Variables */
/** @defgroup CRS_Functions Functions
@{
*/
/* Configuration of the CRS */
void CRS_Reset(void);
void CRS_AdjustHSI48CalibrationValue(uint8_t calibrationVal);
void CRS_EnableFrequencyErrorCounter(void);
void CRS_DisableFrequencyErrorCounter(void);
void CRS_EnableAutomaticCalibration(void);
void CRS_DisableAutomaticCalibration(void);
void CRS_GenerateSoftwareSynchronization(void);
void CRS_FrequencyErrorCounterReloadValue(uint16_t reloadVal);
void CRS_ConfigFrequencyErrorLimit(uint8_t errLimitVal);
void CRS_ConfigSynchronizationPrescaler(CRS_SYNC_DIV_T div);
void CRS_ConfigSynchronizationSource(CRS_SYNC_SOURCE_T source);
void CRS_ConfigSynchronizationPolarity(CRS_SYNC_POL_T polarity);
uint32_t CRS_ReadReloadValue(void);
uint32_t CRS_ReadHSI48CalibrationValue(void);
uint32_t CRS_ReadFrequencyErrorValue(void);
uint32_t CRS_ReadFrequencyErrorDirection(void);
/* Interrupts and flags management functions */
void CRS_EnableInterrupt(CRS_INT_T interrupt);
void CRS_DisableInterrupt(CRS_INT_T interrupt);
uint8_t CRS_ReadStatusFlag(CRS_FLAG_T flag);
void CRS_ClearStatusFlag(CRS_FLAG_T flag);
uint8_t CRS_ReadIntFlag(CRS_INT_T flag);
void CRS_ClearIntFlag(CRS_INT_T intFlag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_CRS_H */
/**@} end of group CRS_Functions */
/**@} end of group CRS_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_dac.h
*
* @brief This file contains all the functions prototypes for the DAC firmware library
*
* @note It's only for APM32F051,APM32F072,APM32F091 devices
*
* @version V1.0.3
*
* @date 2022-02-21
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_DAC_H
#define __APM32F0XX_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup DAC_Driver DAC Driver
@{
*/
/** @defgroup DAC_Macros Macros
@{
*/
/* Macros description */
#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE) /*!< DAC CTRL register clear mask */
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) /*!< Enable software trigger for DAC's Channel1 and Channel2 */
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) /*!< Disable software trigger for DAC's Channel1 and Channel2 */
#define DH12RCH1_OFFSET ((uint32_t)0x00000008) /*!< DAC channel1 data holding register address offset */
#define DH12RCH2_OFFSET ((uint32_t)0x00000014) /*!< DAC channel2 data holding register address offset */
#define DH12RD_OFFSET ((uint32_t)0x00000020) /*!< DAC dual channel data holding register address offset */
#define DATOUT_OFFSET ((uint32_t)0x0000002C) /*!< DAC data output register address offset */
/**@} end of group DAC_Macros*/
/** @defgroup DAC_Enumerations Enumerations
@{
*/
/**
* @brief DAC_Trigger
*/
typedef enum
{
DAC_TRIGGER_NONE = ((uint32_t)0x00000000), /*!< None DAC Trigger */
DAC_TRIGGER_T2_TRGO = ((uint32_t)0x00000024), /*!< Timer 2 TRGO event */
DAC_TRIGGER_T3_TRGO = ((uint32_t)0x0000000C), /*!< Timer 3 TRGO event */
DAC_TRIGGER_T6_TRGO = ((uint32_t)0x00000004), /*!< Timer 6 TRGO event */
DAC_TRIGGER_T7_TRGO = ((uint32_t)0x00000014), /*!< Timer 7 TRGO event, applicable only for APM32F072 devices */
DAC_TRIGGER_T15_TRGO = ((uint32_t)0x0000001C), /*!< Timer 15 TRGO event */
DAC_TRIGGER_EINT_IT9 = ((uint32_t)0x00000034), /*!< EINT line9 */
DAC_TRIGGER_SOFTWARE = ((uint32_t)0x0000003C) /*!< Software trigger */
} DAC_TRIGGER_T;
/**
* @brief DAC_wave_generation, only applicable for APM32F072 devices
*/
typedef enum
{
DAC_WAVE_GENERATION_NONE = ((uint32_t)0x00000000), /*!< Wave generation disabled */
DAC_WAVE_GENERATION_NOISE = ((uint32_t)0x00000040), /*!< Noise wave generation enabled */
DAC_WAVE_GENERATION_TRIANGLE = ((uint32_t)0x00000080) /*!< Triangle wave generation enabled */
} DAC_WAVE_GENERATION_T;
/**
* @brief DAC channelx mask/amplitude selector, only applicable for APM32F072 devices
*/
typedef enum
{
DAC_LFSRUNAMASK_BIT0 = ((uint32_t)0x00000000), /*!< Unmask bit0 of LFSR/ triangle amplitude equal to 1 */
DAC_LFSRUNAMASK_BITS1_0 = ((uint32_t)0x00000100), /*!< Unmask bits[1:0] of LFSR to 3 */
DAC_LFSRUNAMASK_BITS2_0 = ((uint32_t)0x00000200), /*!< Unmask bits[2:0] of LFSR to 7 */
DAC_LFSRUNAMASK_BITS3_0 = ((uint32_t)0x00000300), /*!< Unmask bits[3:0] of LFSR to 15 */
DAC_LFSRUNAMASK_BITS4_0 = ((uint32_t)0x00000400), /*!< Unmask bits[4:0] of LFSR to 31 */
DAC_LFSRUNAMASK_BITS5_0 = ((uint32_t)0x00000500), /*!< Unmask bits[5:0] of LFSR to 63 */
DAC_LFSRUNAMASK_BITS6_0 = ((uint32_t)0x00000600), /*!< Unmask bits[6:0] of LFSR to 127 */
DAC_LFSRUNAMASK_BITS7_0 = ((uint32_t)0x00000700), /*!< Unmask bits[7:0] of LFSR to 255 */
DAC_LFSRUNAMASK_BITS8_0 = ((uint32_t)0x00000800), /*!< Unmask bits[8:0] of LFSR to 511 */
DAC_LFSRUNAMASK_BITS9_0 = ((uint32_t)0x00000900), /*!< Unmask bits[9:0] of LFSR to 1023 */
DAC_LFSRUNAMASK_BITS10_0 = ((uint32_t)0x00000A00), /*!< Unmask bits[10:0] of LFS to 2047 */
DAC_LFSRUNAMASK_BITS11_0 = ((uint32_t)0x00000B00), /*!< Unmask bits[11:0] of LFS to 4095 */
DAC_TRIANGLEAMPLITUDE_1 = ((uint32_t)0x00000000), /*!< Select max triangle amplitude of 1 */
DAC_TRIANGLEAMPLITUDE_3 = ((uint32_t)0x00000100), /*!< Select max triangle amplitude of 3 */
DAC_TRIANGLEAMPLITUDE_7 = ((uint32_t)0x00000200), /*!< Select max triangle amplitude of 7 */
DAC_TRIANGLEAMPLITUDE_15 = ((uint32_t)0x00000300), /*!< Select max triangle amplitude of 15 */
DAC_TRIANGLEAMPLITUDE_31 = ((uint32_t)0x00000400), /*!< Select max triangle amplitude of 31 */
DAC_TRIANGLEAMPLITUDE_63 = ((uint32_t)0x00000500), /*!< Select max triangle amplitude of 63 */
DAC_TRIANGLEAMPLITUDE_127 = ((uint32_t)0x00000600), /*!< Select max triangle amplitude of 127 */
DAC_TRIANGLEAMPLITUDE_255 = ((uint32_t)0x00000700), /*!< Select max triangle amplitude of 255 */
DAC_TRIANGLEAMPLITUDE_511 = ((uint32_t)0x00000800), /*!< Select max triangle amplitude of 511 */
DAC_TRIANGLEAMPLITUDE_1023 = ((uint32_t)0x00000900), /*!< Select max triangle amplitude of 1023 */
DAC_TRIANGLEAMPLITUDE_2047 = ((uint32_t)0x00000A00), /*!< Select max triangle amplitude of 2047 */
DAC_TRIANGLEAMPLITUDE_4095 = ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
} DAC_MASK_AMPLITUDE_SEL_T;
/**
* @brief DAC_OutputBuffer
*/
typedef enum
{
DAC_OUTPUTBUFF_ENABLE = ((uint32_t)0x00000000), /*!< DAC channel1 output buffer enabledDAC channel1 output buffer disabled */
DAC_OUTPUTBUFF_DISABLE = ((uint32_t)0x00000002) /*!< DAC channel1 output buffer enabledDAC channel1 output buffer disabled */
} DAC_OUTPUTBUFF_T;
/**
* @brief DAC_Channel_selection
*/
typedef enum
{
DAC_CHANNEL_1 = ((uint32_t)0x00000000), /*!< DAC channel1 */
DAC_CHANNEL_2 = ((uint32_t)0x00000010) /*!< DAC channel2 */
} DAC_CHANNEL_T;
/**
* @brief DAC_data_alignment
*/
typedef enum
{
DAC_ALIGN_12B_R = ((uint32_t)0x00000000), /*!< DAC 12-bit right-aligned data */
DAC_ALIGN_12B_L = ((uint32_t)0x00000004), /*!< DAC 12-bit left-aligned data */
DAC_ALIGN_8B_R = ((uint32_t)0x00000008) /*!< DAC 8-bit right-aligned data */
} DAC_DATA_ALIGN_T;
/**
* @brief DAC_interrupts_definition
*/
typedef enum
{
DAC_INT_CH1_DMAUDR = ((uint32_t)0x00002000), /*!< DAC channel1 DMA Underrun Interrupt */
DAC_INT_CH2_DMAUDR = ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt */
} DAC_INT_T;
/**
* @brief DAC_flags_definition
*/
typedef enum
{
DAC_FLAG_CH1_DMAUDR = ((uint32_t)0x00002000), /*!< DAC channel1 DMA Underrun Flag */
DAC_FLAG_CH2_DMAUDR = ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Flag */
} DAC_FLAG_T;
/**@} end of group DAC_Enumerations */
/** @defgroup DAC_Structures Structures
@{
*/
/**
* @brief DAC Config structure definition
*/
typedef struct
{
DAC_TRIGGER_T trigger; /*!< DAC trigger selection */
DAC_OUTPUTBUFF_T outputBuff; /*!< DAC output buffer disable */
DAC_WAVE_GENERATION_T waveGeneration; /*!< DAC noise/triangle wave generation selection */
DAC_MASK_AMPLITUDE_SEL_T maskAmplitudeSelect; /*!< DAC mask/amplitude selector */
} DAC_Config_T;
/**@} end of group DAC_Structures */
/** @defgroup DAC_Variables Variables
@{
*/
/**@} end of group DAC_Variables */
/** @defgroup DAC_Functions Functions
@{
*/
/* DAC reset and configuration */
void DAC_Reset(void);
void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig);
void DAC_ConfigStructInit(DAC_Config_T* dacConfig);
void DAC_Enable(DAC_CHANNEL_T channel);
void DAC_Disable(DAC_CHANNEL_T channel);
void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel);
void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel);
void DAC_EnableDualSoftwareTrigger(void); /*!< Only for APM32F072 and APM32F091 devices */
void DAC_DisableDualSoftwareTrigger(void); /*!< Only for APM32F072 and APM32F091 devices */
void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave); /*!< Only for APM32F072 and APM32F091 devices */
void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave); /*!< Only for APM32F072 and APM32F091 devices */
/* Read data */
void DAC_ConfigChannel1Data(DAC_DATA_ALIGN_T dataAlign, uint16_t data);
void DAC_ConfigChannel2Data(DAC_DATA_ALIGN_T dataAlign, uint16_t data); /*!< Only for APM32F072 and APM32F091 devices */
void DAC_ConfigDualChannelData(DAC_DATA_ALIGN_T dataAlign, uint16_t data2, uint16_t data1); /*!< Only for APM32F072 and APM32F091 devices */
uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel);
/* DMA */
void DAC_EnableDMA(DAC_CHANNEL_T channel);
void DAC_DisableDMA(DAC_CHANNEL_T channel);
/* Interrupt and flag */
void DAC_EnableInterrupt(DAC_CHANNEL_T channel);
void DAC_DisableInterrupt(DAC_CHANNEL_T channel);
uint8_t DAC_ReadStatusFlag(DAC_FLAG_T flag);
void DAC_ClearStatusFlag(DAC_FLAG_T flag);
uint8_t DAC_ReadIntFlag(DAC_INT_T intFlag);
void DAC_ClearIntFlag(DAC_INT_T intFlag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_DAC_H */
/**@} end of group DAC_Functions */
/**@} end of group DAC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_dbg.h
*
* @brief This file contains all the functions prototypes for the DBG firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_DBG_H
#define __APM32F0XX_DBG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup DBG_Driver
@{
*/
/** @defgroup DBG_Macros Macros
@{
*/
/**@} end of group DBG_Macros*/
/** @defgroup DBG_Enumerations Enumerations
@{
*/
/**
* @brief MCU Debug mode in the low power mode behavior
*/
typedef enum
{
DBG_MODE_STOP = ((uint32_t)0x02), /*!< Keep debugger connection during STOP mode */
DBG_MODE_STANDBY = ((uint32_t)0x04), /*!< Keep debugger connection during STANDBY mode */
} DBG_MODE_T;
/**
* @brief MCU Debug mode in the APB1 peripheral behavior
*/
typedef enum
{
DBG_APB1_PER_TMR2_STOP = ((uint32_t)0x01), /*!< TMR2 counter stopped when Core is halted (Only for APM32F072 and APM32F091 devices) */
DBG_APB1_PER_TMR3_STOP = ((uint32_t)0x02), /*!< TMR3 counter stopped when Core is halted */
DBG_APB1_PER_TMR6_STOP = ((uint32_t)0x10), /*!< TMR6 counter stopped when Core is halted */
DBG_APB1_PER_TMR7_STOP = ((uint32_t)0x20), /*!< TMR7 counter stopped when Core is halted (Only for APM32F072 and APM32F091 devices) */
DBG_APB1_PER_TMR14_STOP = ((uint32_t)0x100), /*!< TMR14 counter stopped when Core is halted */
DBG_APB1_PER_RTC_STOP = ((uint32_t)0x400), /*!< RTC counter stopped when Core is halted */
DBG_APB1_PER_WWDT_STOP = ((uint32_t)0x800), /*!< Debug WWDT stopped when Core is halted */
DBG_APB1_PER_IWDT_STOP = ((uint32_t)0x1000), /*!< Debug IWDT stopped when Core is halted */
DBG_APB1_PER_CAN_STOP = ((uint32_t)0x2000000), /*!< Debug CAN stopped when Core is halted (Only for APM32F072 and APM32F091 devices) */
DBG_APB1_PER_I2C1_SMBUS_TIMEOUT = ((uint32_t)0x200000), /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
} DBG_APB1_PER_T;
/**
* @brief MCU Debug mode in the APB2 peripheral behavior
*/
typedef enum
{
DBG_APB2_PER_TMR1_STOP = ((uint32_t)0x00800), /*!< TMR1 counter stopped when Core is halted */
DBG_APB2_PER_TMR15_STOP = ((uint32_t)0x10000), /*!< TMR15 counter stopped when Core is halted */
DBG_APB2_PER_TMR16_STOP = ((uint32_t)0x20000), /*!< TMR16 counter stopped when Core is halted */
DBG_APB2_PER_TMR17_STOP = ((uint32_t)0x40000), /*!< TMR17 counter stopped when Core is halted */
} DBG_APB2_PER_T;
/**@} end of group DBG_Enumerations */
/** @defgroup DBG_Structures Structures
@{
*/
/**@} end of group DBG_Structures */
/** @defgroup DBG_Variables Variables
@{
*/
/**@} end of group DBG_Variables */
/** @defgroup DBG_Functions Functions
@{
*/
/* Read MCU ID Code */
uint32_t DBG_ReadDevId(void);
uint32_t DBG_ReadRevId(void);
/* Debug Mode */
void DBG_EnableDebugMode(uint32_t mode);
void DBG_DisableDebugMode(uint32_t mode);
/* APB1 peripheral */
void DBG_EnableAPB1Periph(uint32_t peripheral);
void DBG_DisableAPB1Periph(uint32_t peripheral);
/* APB2 peripheral */
void DBG_EnableAPB2Periph(uint32_t peripheral);
void DBG_DisableAPB2Periph(uint32_t peripheral);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_DBG_H */
/**@} end of group DBG_Functions */
/**@} end of group DBG_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_dma.h
*
* @brief This file contains all the functions prototypes for the DMA firmware
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_DMA_H
#define __APM32F0XX_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup DMA_Driver
@{
*/
/** @defgroup DMA_Macros Macros
@{
*/
/**@} end of group DMA_Macros*/
/** @defgroup DMA_Enumerations Enumerations
@{
*/
/**
* @brief DMA data transfer direction
*/
typedef enum
{
DMA_DIR_PERIPHERAL = ((uint8_t)0), /*!< Peripheral to memory */
DMA_DIR_MEMORY = ((uint8_t)1), /*!< Memory to peripheral */
} DMA_DIR_T;
/**
* @brief DMA peripheral increment mode
*/
typedef enum
{
DMA_PERIPHERAL_INC_DISABLE = ((uint8_t)0), /*!< Disable peripheral address increment mode */
DMA_PERIPHERAL_INC_ENABLE = ((uint8_t)1), /*!< Enable peripheral address increment mode */
} DMA_PERIPHERAL_INC_T;
/**
* @brief DMA memory increment mode
*/
typedef enum
{
DMA_MEMORY_INC_DISABLE = ((uint8_t)0), /*!< Disable memory address increment mode */
DMA_MEMORY_INC_ENABLE = ((uint8_t)1), /*!< Enable memory address increment mode */
} DMA_MEMORY_INC_T;
/**
* @brief DMA peripheral data size
*/
typedef enum
{
DMA_PERIPHERAL_DATASIZE_BYTE = ((uint8_t)0x00), /*!< Set peripheral data size to byte */
DMA_PERIPHERAL_DATASIZE_HALFWORD = ((uint8_t)0x01), /*!< Set peripheral data size to half-word */
DMA_PERIPHERAL_DATASIZE_WORD = ((uint8_t)0x02), /*!< Set peripheral data size to word */
} DMA_PERIPHERAL_DATASIZE_T;
/**
* @brief DMA memory data size
*/
typedef enum
{
DMA_MEMORY_DATASIZE_BYTE = ((uint8_t)0x00), /*!< Set memory data size to byte */
DMA_MEMORY_DATASIZE_HALFWORD = ((uint8_t)0x01), /*!< Set memory data size to half-word */
DMA_MEMORY_DATASIZE_WORD = ((uint8_t)0x02), /*!< Set memory data size to word */
} DMA_MEMORY_DATASIZE_T;
/**
* @brief DMA circular mode
*/
typedef enum
{
DMA_CIRCULAR_DISABLE = ((uint8_t)0), /*!< Disable circular mode */
DMA_CIRCULAR_ENABLE = ((uint8_t)1), /*!< Enable circular mode */
} DMA_CIRCULAR_T;
/**
* @brief DMA priority level
*/
typedef enum
{
DMA_PRIORITY_LEVEL_LOW = ((uint8_t)0x00), /*!< Set priority level to low */
DMA_PRIORITY_LEVEL_MEDIUM = ((uint8_t)0x01), /*!< Set priority level to medium */
DMA_PRIORITY_LEVEL_HIGHT = ((uint8_t)0x02), /*!< Set priority level to high */
DMA_PRIORITY_LEVEL_VERYHIGH = ((uint8_t)0x03), /*!< Set priority level to very high */
} DMA_PRIORITY_LEVEL_T;
/**
* @brief DMA memory to memory
*/
typedef enum
{
DMA_M2M_DISABLE = ((uint8_t)0), /*!< Disable memory to memory mode */
DMA_M2M_ENABLE = ((uint8_t)1), /*!< Enable memory to memory mode */
} DMA_M2M_T;
/**
* @brief DMA channels remapping definition
*/
typedef enum
{
DMA1_CHANNEL1_DEFAULT = (uint32_t)0x00000000, /*!< DMA1 channel1 remapping DEFAULT */
DMA1_CHANNEL1_ADC = (uint32_t)0x00000001, /*!< DMA1 channel1 remapping ADC */
DMA1_CHANNEL1_TMR17_CH1 = (uint32_t)0x00000007, /*!< DMA1 channel1 remapping TMR17_CH1 */
DMA1_CHANNEL1_TMR17_UP = (uint32_t)0x00000007, /*!< DMA1 channel1 remapping TMR17_UP */
DMA1_CHANNEL1_USART1_RX = (uint32_t)0x00000008, /*!< DMA1 channel1 remapping USART1_RX */
DMA1_CHANNEL1_USART2_RX = (uint32_t)0x00000009, /*!< DMA1 channel1 remapping USART2_RX */
DMA1_CHANNEL1_USART3_RX = (uint32_t)0x0000000A, /*!< DMA1 channel1 remapping USART3_RX */
DMA1_CHANNEL1_USART4_RX = (uint32_t)0x0000000B, /*!< DMA1 channel1 remapping USART4_RX */
DMA1_CHANNEL1_USART5_RX = (uint32_t)0x0000000C, /*!< DMA1 channel1 remapping USART5_RX */
DMA1_CHANNEL1_USART6_RX = (uint32_t)0x0000000D, /*!< DMA1 channel1 remapping USART6_RX */
DMA1_CHANNEL1_USART7_RX = (uint32_t)0x0000000E, /*!< DMA1 channel1 remapping USART7_RX */
DMA1_CHANNEL1_USART8_RX = (uint32_t)0x0000000F, /*!< DMA1 channel1 remapping USART8_RX */
DMA1_CHANNEL2_DEFAULT = (uint32_t)0x10000000, /*!< DMA1 channel2 remapping DEFAULT */
DMA1_CHANNEL2_ADC = (uint32_t)0x10000010, /*!< DMA1 channel2 remapping ADC */
DMA1_CHANNEL2_I2C1_TX = (uint32_t)0x10000020, /*!< DMA1 channel2 remapping I2C1_TX */
DMA1_CHANNEL2_SPI1_RX = (uint32_t)0x10000030, /*!< DMA1 channel2 remapping SPI1_RX */
DMA1_CHANNEL2_TMR1_CH1 = (uint32_t)0x10000040, /*!< DMA1 channel2 remapping TMR1_CH1 */
DMA1_CHANNEL2_TMR17_CH1 = (uint32_t)0x10000070, /*!< DMA1 channel2 remapping TMR17_CH1 */
DMA1_CHANNEL2_TMR17_UP = (uint32_t)0x10000070, /*!< DMA1 channel2 remapping TMR17_UP */
DMA1_CHANNEL2_USART1_TX = (uint32_t)0x10000080, /*!< DMA1 channel2 remapping USART1_TX */
DMA1_CHANNEL2_USART2_TX = (uint32_t)0x10000090, /*!< DMA1 channel2 remapping USART2_TX */
DMA1_CHANNEL2_USART3_TX = (uint32_t)0x100000A0, /*!< DMA1 channel2 remapping USART3_TX */
DMA1_CHANNEL2_USART4_TX = (uint32_t)0x100000B0, /*!< DMA1 channel2 remapping USART4_TX */
DMA1_CHANNEL2_USART5_TX = (uint32_t)0x100000C0, /*!< DMA1 channel2 remapping USART5_TX */
DMA1_CHANNEL2_USART6_TX = (uint32_t)0x100000D0, /*!< DMA1 channel2 remapping USART6_TX */
DMA1_CHANNEL2_USART7_TX = (uint32_t)0x100000E0, /*!< DMA1 channel2 remapping USART7_TX */
DMA1_CHANNEL2_USART8_TX = (uint32_t)0x100000F0, /*!< DMA1 channel2 remapping USART8_TX */
DMA1_CHANNEL3_DEFAULT = (uint32_t)0x20000000, /*!< DMA1 channel3 remapping DEFAULT */
DMA1_CHANNEL3_TMR6_UP = (uint32_t)0x20000100, /*!< DMA1 channel3 remapping TMR6_UP */
DMA1_CHANNEL3_DAC_CH1 = (uint32_t)0x20000100, /*!< DMA1 channel3 remapping DAC_CH1 */
DMA1_CHANNEL3_I2C1_RX = (uint32_t)0x20000200, /*!< DMA1 channel3 remapping I2C1_RX */
DMA1_CHANNEL3_SPI1_TX = (uint32_t)0x20000300, /*!< DMA1 channel3 remapping SPI1_TX */
DMA1_CHANNEL3_TMR1_CH2 = (uint32_t)0x20000400, /*!< DMA1 channel3 remapping TMR1_CH2 */
DMA1_CHANNEL3_TMR2_CH2 = (uint32_t)0x20000500, /*!< DMA1 channel3 remapping TMR2_CH2 */
DMA1_CHANNEL3_TMR16_CH1 = (uint32_t)0x20000700, /*!< DMA1 channel3 remapping TMR16_CH1 */
DMA1_CHANNEL3_TMR16_UP = (uint32_t)0x20000700, /*!< DMA1 channel3 remapping TMR16_UP */
DMA1_CHANNEL3_USART1_RX = (uint32_t)0x20000800, /*!< DMA1 channel3 remapping USART1_RX */
DMA1_CHANNEL3_USART2_RX = (uint32_t)0x20000900, /*!< DMA1 channel3 remapping USART2_RX */
DMA1_CHANNEL3_USART3_RX = (uint32_t)0x20000A00, /*!< DMA1 channel3 remapping USART3_RX */
DMA1_CHANNEL3_USART4_RX = (uint32_t)0x20000B00, /*!< DMA1 channel3 remapping USART4_RX */
DMA1_CHANNEL3_USART5_RX = (uint32_t)0x20000C00, /*!< DMA1 channel3 remapping USART5_RX */
DMA1_CHANNEL3_USART6_RX = (uint32_t)0x20000D00, /*!< DMA1 channel3 remapping USART6_RX */
DMA1_CHANNEL3_USART7_RX = (uint32_t)0x20000E00, /*!< DMA1 channel3 remapping USART7_RX */
DMA1_CHANNEL3_USART8_RX = (uint32_t)0x20000F00, /*!< DMA1 channel3 remapping USART8_RX */
DMA1_CHANNEL4_DEFAULT = (uint32_t)0x30000000, /*!< DMA1 channel4 remapping DEFAULT */
DMA1_CHANNEL4_TMR7_UP = (uint32_t)0x30001000, /*!< DMA1 channel4 remapping TMR7_UP */
DMA1_CHANNEL4_DAC_CH2 = (uint32_t)0x30001000, /*!< DMA1 channel4 remapping DAC_CH2 */
DMA1_CHANNEL4_I2C2_TX = (uint32_t)0x30002000, /*!< DMA1 channel4 remapping I2C2_TX */
DMA1_CHANNEL4_SPI2_RX = (uint32_t)0x30003000, /*!< DMA1 channel4 remapping SPI2_RX */
DMA1_CHANNEL4_TMR2_CH4 = (uint32_t)0x30005000, /*!< DMA1 channel4 remapping TMR2_CH4 */
DMA1_CHANNEL4_TMR3_CH1 = (uint32_t)0x30006000, /*!< DMA1 channel4 remapping TMR3_CH1 */
DMA1_CHANNEL4_TMR3_TRIG = (uint32_t)0x30006000, /*!< DMA1 channel4 remapping TMR3_TRIG */
DMA1_CHANNEL4_TMR16_CH1 = (uint32_t)0x30007000, /*!< DMA1 channel4 remapping TMR16_CH1 */
DMA1_CHANNEL4_TMR16_UP = (uint32_t)0x30007000, /*!< DMA1 channel4 remapping TMR16_UP */
DMA1_CHANNEL4_USART1_TX = (uint32_t)0x30008000, /*!< DMA1 channel4 remapping USART1_TX */
DMA1_CHANNEL4_USART2_TX = (uint32_t)0x30009000, /*!< DMA1 channel4 remapping USART2_TX */
DMA1_CHANNEL4_USART3_TX = (uint32_t)0x3000A000, /*!< DMA1 channel4 remapping USART3_TX */
DMA1_CHANNEL4_USART4_TX = (uint32_t)0x3000B000, /*!< DMA1 channel4 remapping USART4_TX */
DMA1_CHANNEL4_USART5_TX = (uint32_t)0x3000C000, /*!< DMA1 channel4 remapping USART5_TX */
DMA1_CHANNEL4_USART6_TX = (uint32_t)0x3000D000, /*!< DMA1 channel4 remapping USART6_TX */
DMA1_CHANNEL4_USART7_TX = (uint32_t)0x3000E000, /*!< DMA1 channel4 remapping USART7_TX */
DMA1_CHANNEL4_USART8_TX = (uint32_t)0x3000F000, /*!< DMA1 channel4 remapping USART8_TX */
DMA1_CHANNEL5_DEFAULT = (uint32_t)0x40000000, /*!< DMA1 channel5 remapping DEFAULT */
DMA1_CHANNEL5_I2C2_RX = (uint32_t)0x40020000, /*!< DMA1 channel5 remapping I2C2_RX */
DMA1_CHANNEL5_SPI2_TX = (uint32_t)0x40030000, /*!< DMA1 channel5 remapping SPI2_TX */
DMA1_CHANNEL5_TMR1_CH3 = (uint32_t)0x40040000, /*!< DMA1 channel5 remapping TMR1_CH3 */
DMA1_CHANNEL5_USART1_RX = (uint32_t)0x40080000, /*!< DMA1 channel5 remapping USART1_RX */
DMA1_CHANNEL5_USART2_RX = (uint32_t)0x40090000, /*!< DMA1 channel5 remapping USART2_RX */
DMA1_CHANNEL5_USART3_RX = (uint32_t)0x400A0000, /*!< DMA1 channel5 remapping USART3_RX */
DMA1_CHANNEL5_USART4_RX = (uint32_t)0x400B0000, /*!< DMA1 channel5 remapping USART4_RX */
DMA1_CHANNEL5_USART5_RX = (uint32_t)0x400C0000, /*!< DMA1 channel5 remapping USART5_RX */
DMA1_CHANNEL5_USART6_RX = (uint32_t)0x400D0000, /*!< DMA1 channel5 remapping USART6_RX */
DMA1_CHANNEL5_USART7_RX = (uint32_t)0x400E0000, /*!< DMA1 channel5 remapping USART7_RX */
DMA1_CHANNEL5_USART8_RX = (uint32_t)0x400F0000, /*!< DMA1 channel5 remapping USART8_RX */
DMA1_CHANNEL6_DEFAULT = (uint32_t)0x50000000, /*!< DMA1 channel6 remapping DEFAULT */
DMA1_CHANNEL6_I2C1_TX = (uint32_t)0x50200000, /*!< DMA1 channel6 remapping I2C1_TX */
DMA1_CHANNEL6_SPI2_RX = (uint32_t)0x50300000, /*!< DMA1 channel6 remapping SPI2_RX */
DMA1_CHANNEL6_TMR1_CH1 = (uint32_t)0x50400000, /*!< DMA1 channel6 remapping TMR1_CH1 */
DMA1_CHANNEL6_TMR1_CH2 = (uint32_t)0x50400000, /*!< DMA1 channel6 remapping TMR1_CH2 */
DMA1_CHANNEL6_TMR1_CH3 = (uint32_t)0x50400000, /*!< DMA1 channel6 remapping TMR1_CH3 */
DMA1_CHANNEL6_TMR3_CH1 = (uint32_t)0x50600000, /*!< DMA1 channel6 remapping TMR3_CH1 */
DMA1_CHANNEL6_TMR3_TRIG = (uint32_t)0x50600000, /*!< DMA1 channel6 remapping TMR3_TRIG */
DMA1_CHANNEL6_TMR16_CH1 = (uint32_t)0x50700000, /*!< DMA1 channel6 remapping TMR16_CH1 */
DMA1_CHANNEL6_TMR16_UP = (uint32_t)0x50700000, /*!< DMA1 channel6 remapping TMR16_UP */
DMA1_CHANNEL6_USART1_RX = (uint32_t)0x50800000, /*!< DMA1 channel6 remapping USART1_RX */
DMA1_CHANNEL6_USART2_RX = (uint32_t)0x50900000, /*!< DMA1 channel6 remapping USART2_RX */
DMA1_CHANNEL6_USART3_RX = (uint32_t)0x50A00000, /*!< DMA1 channel6 remapping USART3_RX */
DMA1_CHANNEL6_USART4_RX = (uint32_t)0x50B00000, /*!< DMA1 channel6 remapping USART4_RX */
DMA1_CHANNEL6_USART5_RX = (uint32_t)0x50C00000, /*!< DMA1 channel6 remapping USART5_RX */
DMA1_CHANNEL6_USART6_RX = (uint32_t)0x50D00000, /*!< DMA1 channel6 remapping USART6_RX */
DMA1_CHANNEL6_USART7_RX = (uint32_t)0x50E00000, /*!< DMA1 channel6 remapping USART7_RX */
DMA1_CHANNEL6_USART8_RX = (uint32_t)0x50F00000, /*!< DMA1 channel6 remapping USART8_RX */
DMA1_CHANNEL7_DEFAULT = (uint32_t)0x60000000, /*!< DMA1 channel7 remapping DEFAULT */
DMA1_CHANNEL7_I2C1_RX = (uint32_t)0x62000000, /*!< DMA1 channel7 remapping I2C1_RX */
DMA1_CHANNEL7_SPI2_TX = (uint32_t)0x63000000, /*!< DMA1 channel7 remapping SPI2_TX */
DMA1_CHANNEL7_TMR2_CH2 = (uint32_t)0x65000000, /*!< DMA1 channel7 remapping TMR2_CH2 */
DMA1_CHANNEL7_TMR2_CH4 = (uint32_t)0x65000000, /*!< DMA1 channel7 remapping TMR2_CH4 */
DMA1_CHANNEL7_TMR17_CH1 = (uint32_t)0x67000000, /*!< DMA1 channel7 remapping TMR17_CH1 */
DMA1_CHANNEL7_TMR17_UP = (uint32_t)0x67000000, /*!< DMA1 channel7 remapping TMR17_UP */
DMA1_CHANNEL7_USART1_TX = (uint32_t)0x68000000, /*!< DMA1 channel7 remapping USART1_TX */
DMA1_CHANNEL7_USART2_TX = (uint32_t)0x69000000, /*!< DMA1 channel7 remapping USART2_TX */
DMA1_CHANNEL7_USART3_TX = (uint32_t)0x6A000000, /*!< DMA1 channel7 remapping USART3_TX */
DMA1_CHANNEL7_USART4_TX = (uint32_t)0x6B000000, /*!< DMA1 channel7 remapping USART4_TX */
DMA1_CHANNEL7_USART5_TX = (uint32_t)0x6C000000, /*!< DMA1 channel7 remapping USART5_TX */
DMA1_CHANNEL7_USART6_TX = (uint32_t)0x6D000000, /*!< DMA1 channel7 remapping USART6_TX */
DMA1_CHANNEL7_USART7_TX = (uint32_t)0x6E000000, /*!< DMA1 channel7 remapping USART7_TX */
DMA1_CHANNEL7_USART8_TX = (uint32_t)0x6F000000, /*!< DMA1 channel7 remapping USART8_TX */
DMA2_CHANNEL1_DEFAULT = (uint32_t)0x00000000, /*!< DMA2 channel1 remapping DEFAULT */
DMA2_CHANNEL1_I2C2_TX = (uint32_t)0x00000002, /*!< DMA2 channel1 remapping I2C2_TX */
DMA2_CHANNEL1_USART1_TX = (uint32_t)0x00000008, /*!< DMA2 channel1 remapping USART1_TX */
DMA2_CHANNEL1_USART2_TX = (uint32_t)0x00000009, /*!< DMA2 channel1 remapping USART2_TX */
DMA2_CHANNEL1_USART3_TX = (uint32_t)0x0000000A, /*!< DMA2 channel1 remapping USART3_TX */
DMA2_CHANNEL1_USART4_TX = (uint32_t)0x0000000B, /*!< DMA2 channel1 remapping USART4_TX */
DMA2_CHANNEL1_USART5_TX = (uint32_t)0x0000000C, /*!< DMA2 channel1 remapping USART5_TX */
DMA2_CHANNEL1_USART6_TX = (uint32_t)0x0000000D, /*!< DMA2 channel1 remapping USART6_TX */
DMA2_CHANNEL1_USART7_TX = (uint32_t)0x0000000E, /*!< DMA2 channel1 remapping USART7_TX */
DMA2_CHANNEL1_USART8_TX = (uint32_t)0x0000000F, /*!< DMA2 channel1 remapping USART8_TX */
DMA2_CHANNEL2_DEFAULT = (uint32_t)0x00000000, /*!< DMA2 channel2 remapping DEFAULT */
DMA2_CHANNEL2_I2C2_RX = (uint32_t)0x00000020, /*!< DMA2 channel2 remapping I2C2_RX */
DMA2_CHANNEL2_USART1_RX = (uint32_t)0x00000080, /*!< DMA2 channel2 remapping USART1_RX */
DMA2_CHANNEL2_USART2_RX = (uint32_t)0x00000090, /*!< DMA2 channel2 remapping USART2_RX */
DMA2_CHANNEL2_USART3_RX = (uint32_t)0x000000A0, /*!< DMA2 channel2 remapping USART3_RX */
DMA2_CHANNEL2_USART4_RX = (uint32_t)0x000000B0, /*!< DMA2 channel2 remapping USART4_RX */
DMA2_CHANNEL2_USART5_RX = (uint32_t)0x000000C0, /*!< DMA2 channel2 remapping USART5_RX */
DMA2_CHANNEL2_USART6_RX = (uint32_t)0x000000D0, /*!< DMA2 channel2 remapping USART6_RX */
DMA2_CHANNEL2_USART7_RX = (uint32_t)0x000000E0, /*!< DMA2 channel2 remapping USART7_RX */
DMA2_CHANNEL2_USART8_RX = (uint32_t)0x000000F0, /*!< DMA2 channel2 remapping USART8_RX */
DMA2_CHANNEL3_DEFAULT = (uint32_t)0x00000000, /*!< DMA2 channel3 remapping DEFAULT */
DMA2_CHANNEL3_TMR6_UP = (uint32_t)0x00000100, /*!< DMA2 channel3 remapping TMR6_UP */
DMA2_CHANNEL3_DAC_CH1 = (uint32_t)0x00000100, /*!< DMA2 channel3 remapping DAC_CH1 */
DMA2_CHANNEL3_SPI1_RX = (uint32_t)0x00000300, /*!< DMA2 channel3 remapping SPI1_RX */
DMA2_CHANNEL3_USART1_RX = (uint32_t)0x00000800, /*!< DMA2 channel3 remapping USART1_RX */
DMA2_CHANNEL3_USART2_RX = (uint32_t)0x00000900, /*!< DMA2 channel3 remapping USART2_RX */
DMA2_CHANNEL3_USART3_RX = (uint32_t)0x00000A00, /*!< DMA2 channel3 remapping USART3_RX */
DMA2_CHANNEL3_USART4_RX = (uint32_t)0x00000B00, /*!< DMA2 channel3 remapping USART4_RX */
DMA2_CHANNEL3_USART5_RX = (uint32_t)0x00000C00, /*!< DMA2 channel3 remapping USART5_RX */
DMA2_CHANNEL3_USART6_RX = (uint32_t)0x00000D00, /*!< DMA2 channel3 remapping USART6_RX */
DMA2_CHANNEL3_USART7_RX = (uint32_t)0x00000E00, /*!< DMA2 channel3 remapping USART7_RX */
DMA2_CHANNEL3_USART8_RX = (uint32_t)0x00000F00, /*!< DMA2 channel3 remapping USART8_RX */
DMA2_CHANNEL4_DEFAULT = (uint32_t)0x00000000, /*!< DMA2 channel4 remapping DEFAULT */
DMA2_CHANNEL4_TMR7_UP = (uint32_t)0x00001000, /*!< DMA2 channel4 remapping TMR7_UP */
DMA2_CHANNEL4_DAC_CH2 = (uint32_t)0x00001000, /*!< DMA2 channel4 remapping DAC_CH2 */
DMA2_CHANNEL4_SPI1_TX = (uint32_t)0x00003000, /*!< DMA2 channel4 remapping SPI1_TX */
DMA2_CHANNEL4_USART1_TX = (uint32_t)0x00008000, /*!< DMA2 channel4 remapping USART1_TX */
DMA2_CHANNEL4_USART2_TX = (uint32_t)0x00009000, /*!< DMA2 channel4 remapping USART2_TX */
DMA2_CHANNEL4_USART3_TX = (uint32_t)0x0000A000, /*!< DMA2 channel4 remapping USART3_TX */
DMA2_CHANNEL4_USART4_TX = (uint32_t)0x0000B000, /*!< DMA2 channel4 remapping USART4_TX */
DMA2_CHANNEL4_USART5_TX = (uint32_t)0x0000C000, /*!< DMA2 channel4 remapping USART5_TX */
DMA2_CHANNEL4_USART6_TX = (uint32_t)0x0000D000, /*!< DMA2 channel4 remapping USART6_TX */
DMA2_CHANNEL4_USART7_TX = (uint32_t)0x0000E000, /*!< DMA2 channel4 remapping USART7_TX */
DMA2_CHANNEL4_USART8_TX = (uint32_t)0x0000F000, /*!< DMA2 channel4 remapping USART8_TX */
DMA2_CHANNEL5_DEFAULT = (uint32_t)0x00000000, /*!< DMA2 channel5 remapping DEFAULT */
DMA2_CHANNEL5_ADC = (uint32_t)0x00010000, /*!< DMA2 channel5 remapping ADC */
DMA2_CHANNEL5_USART1_TX = (uint32_t)0x00080000, /*!< DMA2 channel5 remapping USART1_TX */
DMA2_CHANNEL5_USART2_TX = (uint32_t)0x00090000, /*!< DMA2 channel5 remapping USART2_TX */
DMA2_CHANNEL5_USART3_TX = (uint32_t)0x000A0000, /*!< DMA2 channel5 remapping USART3_TX */
DMA2_CHANNEL5_USART4_TX = (uint32_t)0x000B0000, /*!< DMA2 channel5 remapping USART4_TX */
DMA2_CHANNEL5_USART5_TX = (uint32_t)0x000C0000, /*!< DMA2 channel5 remapping USART5_TX */
DMA2_CHANNEL5_USART6_TX = (uint32_t)0x000D0000, /*!< DMA2 channel5 remapping USART6_TX */
DMA2_CHANNEL5_USART7_TX = (uint32_t)0x000E0000, /*!< DMA2 channel5 remapping USART7_TX */
DMA2_CHANNEL5_USART8_TX = (uint32_t)0x000F0000, /*!< DMA2 channel5 remapping USART8_TX */
} DMA_CHANNEL_REMAP_T;
/**
* @brief DMA flag definition
*/
typedef enum
{
DMA1_FLAG_AL1 = ((uint32_t)0x00000001), /*!< Channel 1 All flag */
DMA1_FLAG_TF1 = ((uint32_t)0X00000002), /*!< Channel 1 Transfer Complete flag */
DMA1_FLAG_HT1 = ((uint32_t)0X00000004), /*!< Channel 1 Half Transfer Complete flag */
DMA1_FLAG_TE1 = ((uint32_t)0X00000008), /*!< Channel 1 Transfer Error flag */
DMA1_FLAG_AL2 = ((uint32_t)0x00000010), /*!< Channel 2 All flag */
DMA1_FLAG_TF2 = ((uint32_t)0x00000020), /*!< Channel 2 Transfer Complete flag */
DMA1_FLAG_HT2 = ((uint32_t)0x00000040), /*!< Channel 2 Half Transfer Complete flag */
DMA1_FLAG_TE2 = ((uint32_t)0x00000080), /*!< Channel 2 Transfer Error flag */
DMA1_FLAG_AL3 = ((uint32_t)0x00000100), /*!< Channel 3 All flag */
DMA1_FLAG_TF3 = ((uint32_t)0x00000200), /*!< Channel 3 Transfer Complete flag */
DMA1_FLAG_HT3 = ((uint32_t)0x00000400), /*!< Channel 3 Half Transfer Complete flag */
DMA1_FLAG_TE3 = ((uint32_t)0x00000800), /*!< Channel 3 Transfer Error flag */
DMA1_FLAG_AL4 = ((uint32_t)0x00001000), /*!< Channel 4 All flag */
DMA1_FLAG_TF4 = ((uint32_t)0x00002000), /*!< Channel 4 Transfer Complete flag */
DMA1_FLAG_HT4 = ((uint32_t)0x00004000), /*!< Channel 4 Half Transfer Complete flag */
DMA1_FLAG_TE4 = ((uint32_t)0x00008000), /*!< Channel 4 Transfer Error flag */
DMA1_FLAG_AL5 = ((uint32_t)0x00010000), /*!< Channel 5 All flag */
DMA1_FLAG_TF5 = ((uint32_t)0x00020000), /*!< Channel 5 Transfer Complete flag */
DMA1_FLAG_HT5 = ((uint32_t)0x00040000), /*!< Channel 5 Half Transfer Complete flag */
DMA1_FLAG_TE5 = ((uint32_t)0x00080000), /*!< Channel 5 Transfer Error flag */
/* Only for APM32F072 and APM32F091 devices */
DMA1_FLAG_AL6 = ((uint32_t)0x00100000), /*!< Channel 6 All flag */
DMA1_FLAG_TF6 = ((uint32_t)0x00200000), /*!< Channel 6 Transfer Complete flag */
DMA1_FLAG_HT6 = ((uint32_t)0x00400000), /*!< Channel 6 Half Transfer Complete flag */
DMA1_FLAG_TE6 = ((uint32_t)0x00800000), /*!< Channel 6 Transfer Error flag */
/* Only for APM32F072 and APM32F091 devices */
DMA1_FLAG_AL7 = ((uint32_t)0x01000000), /*!< Channel 7 All flag */
DMA1_FLAG_TF7 = ((uint32_t)0x02000000), /*!< Channel 7 Transfer Complete flag */
DMA1_FLAG_HT7 = ((uint32_t)0x04000000), /*!< Channel 7 Half Transfer Complete flag */
DMA1_FLAG_TE7 = ((uint32_t)0x08000000), /*!< Channel 7 Transfer Error flag */
/* Only for APM32F091 devices */
DMA2_FLAG_AL1 = ((uint32_t)0x10000001), /*!< Channel 1 All flag */
DMA2_FLAG_TF1 = ((uint32_t)0X00000002), /*!< Channel 1 Transfer Complete flag */
DMA2_FLAG_HT1 = ((uint32_t)0X00000004), /*!< Channel 1 Half Transfer Complete flag */
DMA2_FLAG_TE1 = ((uint32_t)0X00000008), /*!< Channel 1 Transfer Error flag */
/* Only for APM32F091 devices */
DMA2_FLAG_AL2 = ((uint32_t)0x10000010), /*!< Channel 2 All flag */
DMA2_FLAG_TF2 = ((uint32_t)0x10000020), /*!< Channel 2 Transfer Complete flag */
DMA2_FLAG_HT2 = ((uint32_t)0x10000040), /*!< Channel 2 Half Transfer Complete flag */
DMA2_FLAG_TE2 = ((uint32_t)0x10000080), /*!< Channel 2 Transfer Error flag */
/* Only for APM32F091 devices */
DMA2_FLAG_AL3 = ((uint32_t)0x10000100), /*!< Channel 3 All flag */
DMA2_FLAG_TF3 = ((uint32_t)0x10000200), /*!< Channel 3 Transfer Complete flag */
DMA2_FLAG_HT3 = ((uint32_t)0x10000400), /*!< Channel 3 Half Transfer Complete flag */
DMA2_FLAG_TE3 = ((uint32_t)0x10000800), /*!< Channel 3 Transfer Error flag */
/* Only for APM32F091 devices */
DMA2_FLAG_AL4 = ((uint32_t)0x10001000), /*!< Channel 4 All flag */
DMA2_FLAG_TF4 = ((uint32_t)0x10002000), /*!< Channel 4 Transfer Complete flag */
DMA2_FLAG_HT4 = ((uint32_t)0x10004000), /*!< Channel 4 Half Transfer Complete flag */
DMA2_FLAG_TE4 = ((uint32_t)0x10008000), /*!< Channel 4 Transfer Error flag */
/* Only for APM32F091 devices */
DMA2_FLAG_AL5 = ((uint32_t)0x10010000), /*!< Channel 5 All flag */
DMA2_FLAG_TF5 = ((uint32_t)0x10020000), /*!< Channel 5 Transfer Complete flag */
DMA2_FLAG_HT5 = ((uint32_t)0x10040000), /*!< Channel 5 Half Transfer Complete flag */
DMA2_FLAG_TE5 = ((uint32_t)0x10080000), /*!< Channel 5 Transfer Error flag */
} DMA_FLAG_T;
/**
* @brief DMA interrupt flag definition
*/
typedef enum
{
DMA1_INT_FLAG_AL1 = ((uint32_t)0x00000001), /*!< Channel 1 All interrupt flag */
DMA1_INT_FLAG_TF1 = ((uint32_t)0x00000002), /*!< Channel 1 Transfer Complete interrupt flag */
DMA1_INT_FLAG_HT1 = ((uint32_t)0x00000004), /*!< Channel 1 Half Transfer Complete interrupt flag */
DMA1_INT_FLAG_TE1 = ((uint32_t)0x00000008), /*!< Channel 1 Transfer Error interrupt flag */
DMA1_INT_FLAG_AL2 = ((uint32_t)0x00000010), /*!< Channel 2 All interrupt flag */
DMA1_INT_FLAG_TF2 = ((uint32_t)0x00000020), /*!< Channel 2 Transfer Complete interrupt flag */
DMA1_INT_FLAG_HT2 = ((uint32_t)0x00000040), /*!< Channel 2 Half Transfer Complete interrupt flag */
DMA1_INT_FLAG_TE2 = ((uint32_t)0x00000080), /*!< Channel 2 Transfer Error interrupt flag */
DMA1_INT_FLAG_AL3 = ((uint32_t)0x00000100), /*!< Channel 3 All interrupt flag */
DMA1_INT_FLAG_TF3 = ((uint32_t)0x00000200), /*!< Channel 3 Transfer Complete interrupt flag */
DMA1_INT_FLAG_HT3 = ((uint32_t)0x00000400), /*!< Channel 3 Half Transfer Complete interrupt flag */
DMA1_INT_FLAG_TE3 = ((uint32_t)0x00000800), /*!< Channel 3 Transfer Error interrupt flag */
DMA1_INT_FLAG_AL4 = ((uint32_t)0x00001000), /*!< Channel 4 All interrupt flag */
DMA1_INT_FLAG_TF4 = ((uint32_t)0x00002000), /*!< Channel 4 Transfer Complete interrupt flag */
DMA1_INT_FLAG_HT4 = ((uint32_t)0x00004000), /*!< Channel 4 Half Transfer Complete interrupt flag */
DMA1_INT_FLAG_TE4 = ((uint32_t)0x00008000), /*!< Channel 4 Transfer Error interrupt flag */
DMA1_INT_FLAG_AL5 = ((uint32_t)0x00010000), /*!< Channel 5 All interrupt flag */
DMA1_INT_FLAG_TF5 = ((uint32_t)0x00020000), /*!< Channel 5 Transfer Complete interrupt flag */
DMA1_INT_FLAG_HT5 = ((uint32_t)0x00040000), /*!< Channel 5 Half Transfer Complete interrupt flag */
DMA1_INT_FLAG_TE5 = ((uint32_t)0x00080000), /*!< Channel 5 Transfer Error interrupt flag */
/* Only for APM32F072 and APM32F091 devices */
DMA1_INT_FLAG_AL6 = ((uint32_t)0x00100000), /*!< Channel 6 All interrupt flag */
DMA1_INT_FLAG_TF6 = ((uint32_t)0x00200000), /*!< Channel 6 Transfer Complete interrupt flag */
DMA1_INT_FLAG_HT6 = ((uint32_t)0x00400000), /*!< Channel 6 Half Transfer Complete interrupt flag */
DMA1_INT_FLAG_TE6 = ((uint32_t)0x00800000), /*!< Channel 6 Transfer Error interrupt flag */
/* Only for APM32F072 and APM32F091 devices */
DMA1_INT_FLAG_AL7 = ((uint32_t)0x01000000), /*!< Channel 7 All interrupt flag */
DMA1_INT_FLAG_TF7 = ((uint32_t)0x02000000), /*!< Channel 7 Transfer Complete interrupt flag */
DMA1_INT_FLAG_HT7 = ((uint32_t)0x04000000), /*!< Channel 7 Half Transfer Complete interrupt flag */
DMA1_INT_FLAG_TE7 = ((uint32_t)0x08000000), /*!< Channel 7 Transfer Error interrupt flag */
/* Only for APM32F091 devices */
DMA2_INT_FLAG_AL1 = ((uint32_t)0x10000001), /*!< Channel 1 All interrupt flag */
DMA2_INT_FLAG_TF1 = ((uint32_t)0x10000002), /*!< Channel 1 Transfer Complete interrupt flag */
DMA2_INT_FLAG_HT1 = ((uint32_t)0x10000004), /*!< Channel 1 Half Transfer Complete interrupt flag */
DMA2_INT_FLAG_TE1 = ((uint32_t)0x10000008), /*!< Channel 1 Transfer Error interrupt flag */
/* Only for APM32F091 devices */
DMA2_INT_FLAG_AL2 = ((uint32_t)0x10000010), /*!< Channel 2 All interrupt flag */
DMA2_INT_FLAG_TF2 = ((uint32_t)0x10000020), /*!< Channel 2 Transfer Complete interrupt flag */
DMA2_INT_FLAG_HT2 = ((uint32_t)0x10000040), /*!< Channel 2 Half Transfer Complete interrupt flag */
DMA2_INT_FLAG_TE2 = ((uint32_t)0x10000080), /*!< Channel 2 Transfer Error interrupt flag */
/* Only for APM32F091 devices */
DMA2_INT_FLAG_AL3 = ((uint32_t)0x10000100), /*!< Channel 3 All interrupt flag */
DMA2_INT_FLAG_TF3 = ((uint32_t)0x10000200), /*!< Channel 3 Transfer Complete interrupt flag */
DMA2_INT_FLAG_HT3 = ((uint32_t)0x10000400), /*!< Channel 3 Half Transfer Complete interrupt flag */
DMA2_INT_FLAG_TE3 = ((uint32_t)0x10000800), /*!< Channel 3 Transfer Error interrupt flag */
/* Only for APM32F091 devices */
DMA2_INT_FLAG_AL4 = ((uint32_t)0x10001000), /*!< Channel 4 All interrupt flag */
DMA2_INT_FLAG_TF4 = ((uint32_t)0x10002000), /*!< Channel 4 Transfer Complete interrupt flag */
DMA2_INT_FLAG_HT4 = ((uint32_t)0x10004000), /*!< Channel 4 Half Transfer Complete interrupt flag */
DMA2_INT_FLAG_TE4 = ((uint32_t)0x10008000), /*!< Channel 4 Transfer Error interrupt flag */
/* Only for APM32F091 devices */
DMA2_INT_FLAG_AL5 = ((uint32_t)0x10010000), /*!< Channel 5 All interrupt flag */
DMA2_INT_FLAG_TF5 = ((uint32_t)0x10020000), /*!< Channel 5 Transfer Complete interrupt flag */
DMA2_INT_FLAG_HT5 = ((uint32_t)0x10040000), /*!< Channel 5 Half Transfer Complete interrupt flag */
DMA2_INT_FLAG_TE5 = ((uint32_t)0x10080000), /*!< Channel 5 Transfer Error interrupt flag */
} DMA_INT_FLAG_T;
/**
* @brief DMA interrupt source
*/
typedef enum
{
DMA_INT_TFIE = BIT1, /*!< Transfer complete interrupt enable */
DMA_INT_HTIE = BIT2, /*!< Half Transfer interrupt enable */
DMA_INT_TEIE = BIT3, /*!< Transfer error interrupt enable */
} DMA_INT_T;
/**@} end of group DMA_Enumerations */
/** @defgroup DMA_Structures Structures
@{
*/
/**
* @brief DMA Config struct definition
*/
typedef struct
{
uint32_t memoryAddress; /*!< Specifies the DMA memory base address */
uint32_t peripheralAddress; /*!< Specifies the DMA peripheral base address */
DMA_DIR_T direction; /*!< Specifies the DMA data transfer direction */
uint32_t bufferSize; /*!< Specifies the DMA buffer size */
DMA_MEMORY_DATASIZE_T memoryDataSize; /*!< Specifies the DMA memory data size */
DMA_PERIPHERAL_DATASIZE_T peripheralDataSize; /*!< Specifies the DMA peripheral data size */
DMA_MEMORY_INC_T memoryInc; /*!< Specifies the DMA memory address increment */
DMA_PERIPHERAL_INC_T peripheralInc; /*!< Specifies the DMA peripheral address increment */
DMA_CIRCULAR_T circular; /*!< Specifies the DMA circular mode */
DMA_PRIORITY_LEVEL_T priority; /*!< Specifies the DMA software priority */
DMA_M2M_T memoryTomemory; /*!< Specifies the DMA memory-to-memory transfer */
} DMA_Config_T;
/**@} end of group DMA_Structures */
/** @defgroup DMA_Variables Variables
@{
*/
/**@} end of group DMA_Variables*/
/** @defgroup DMA_Functions Functions
@{
*/
/* Reset and configuration */
void DMA_Reset(DMA_CHANNEL_T* channel);
void DMA_Config(DMA_CHANNEL_T* channel, DMA_Config_T* dmaConfig);
void DMA_ConfigStructInit(DMA_Config_T* dmaConfig);
void DMA_Enable(DMA_CHANNEL_T* channel);
void DMA_Disable(DMA_CHANNEL_T* channel);
/* Data number */
void DMA_SetDataNumber(DMA_CHANNEL_T* channel, uint32_t dataNumber);
uint32_t DMA_ReadDataNumber(DMA_CHANNEL_T* channel);
/* Channel remap (Only for APM32F091 devices) */
void DMA_ConfigRemap(DMA_T* dma, DMA_CHANNEL_REMAP_T remap);
/* interrupt */
void DMA_EnableInterrupt(DMA_CHANNEL_T* channel, uint32_t interrupt);
void DMA_DisableInterrupt(DMA_CHANNEL_T* channel, uint32_t interrupt);
/* Flag */
uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag);
void DMA_ClearStatusFlag(uint32_t flag);
uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
void DMA_ClearIntFlag(uint32_t flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_DMA_H */
/**@} end of group DMA_Functions */
/**@} end of group DMA_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_eint.h
*
* @brief This file contains all the functions prototypes for the EINT firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_EINT_H
#define __APM32F0XX_EINT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup EINT_Driver
@{
*/
/** @defgroup EINT_Macros Macros
@{
*/
/* No interrupt selected */
#define EINT_LINENONE ((uint32_t)0x00000) /*!< clear EINT line config */
/* EINT register reset value */
#if defined (APM32F030) || defined (APM32F051)
#define EINT_INTMASK_RESET_VALUE ((uint32_t)(0x0F940000))
#elif defined (APM32F091) || defined (APM32F072) || defined (APM32F071) || defined (APM32F070)
#define EINT_INTMASK_RESET_VALUE ((uint32_t)(0x7F840000))
#endif
#define EINT_EVTMASK_RESET_VALUE ((uint32_t)(0x00000000)) /*!< EINT Event MASK register reset value */
#define EINT_RTSEL_RESET_VALUE ((uint32_t)(0x00000000)) /*!< EINT Rising Trigger enable register reset value */
#define EINT_FTSEL_RESET_VALUE ((uint32_t)(0x00000000)) /*!< EINT Falling Trigger enable register reset value */
#define EINT_PEND_RESET_VALUE ((uint32_t)(0x00000000)) /*!< EINT Interrupt Pending register reset value */
/**@} end of group EINT_Macros */
/** @defgroup EINT_Enumerations Enumerations
@{
*/
/*!
* @brief EINT mode
*/
typedef enum
{
EINT_MODE_INTERRUPT = ((uint8_t)0x00), /*!< EINT mode select interrupt */
EINT_MODE_EVENT = ((uint8_t)0x01), /*!< EINT mode select event */
} EINT_MODE_T;
/*!
* @brief EINT trigger mode
*/
typedef enum
{
EINT_TRIGGER_RISING = ((uint8_t)0x00), /*!< EINT trigger select rising edge */
EINT_TRIGGER_FALLING = ((uint8_t)0x01), /*!< EINT trigger select falling edge */
EINT_TRIGGER_ALL = ((uint8_t)0x02), /*!< EINT trigger select rising and falling edge */
} EINT_TRIGGER_T;
/*!
* @brief EINT line
*/
typedef enum
{
EINT_LINE0 = ((uint32_t)0x00000001), /*!< External interrupt line 0 */
EINT_LINE1 = ((uint32_t)0x00000002), /*!< External interrupt line 1 */
EINT_LINE2 = ((uint32_t)0x00000004), /*!< External interrupt line 2 */
EINT_LINE3 = ((uint32_t)0x00000008), /*!< External interrupt line 3 */
EINT_LINE4 = ((uint32_t)0x00000010), /*!< External interrupt line 4 */
EINT_LINE5 = ((uint32_t)0x00000020), /*!< External interrupt line 5 */
EINT_LINE6 = ((uint32_t)0x00000040), /*!< External interrupt line 6 */
EINT_LINE7 = ((uint32_t)0x00000080), /*!< External interrupt line 7 */
EINT_LINE8 = ((uint32_t)0x00000100), /*!< External interrupt line 8 */
EINT_LINE9 = ((uint32_t)0x00000200), /*!< External interrupt line 9 */
EINT_LINE10 = ((uint32_t)0x00000400), /*!< External interrupt line 10 */
EINT_LINE11 = ((uint32_t)0x00000800), /*!< External interrupt line 11 */
EINT_LINE12 = ((uint32_t)0x00001000), /*!< External interrupt line 12 */
EINT_LINE13 = ((uint32_t)0x00002000), /*!< External interrupt line 13 */
EINT_LINE14 = ((uint32_t)0x00004000), /*!< External interrupt line 14 */
EINT_LINE15 = ((uint32_t)0x00008000), /*!< External interrupt line 15 */
EINT_LINE16 = ((uint32_t)0x00010000), /*!< External interrupt line 16 Connected to the PVD Output, not applicable for 030 */
EINT_LINE17 = ((uint32_t)0x00020000), /*!< External interrupt line 17 Connected to the RTC Alarm event */
EINT_LINE18 = ((uint32_t)0x00040000), /*!< External interrupt line 18 Connected to the RTC Alarm event, only applicable for 072 devices */
EINT_LINE19 = ((uint32_t)0x00080000), /*!< External interrupt line 19 Connected to the RTC Tamper and TimeStamp events */
EINT_LINE20 = ((uint32_t)0x00100000), /*!< External interrupt line 20 Connected to the RTC wakeup event,only applicable for 072 and 091 */
EINT_LINE21 = ((uint32_t)0x00200000), /*!< External interrupt line 21 Connected to the Comparator 1 event,only applicable for 072 and 091 */
EINT_LINE22 = ((uint32_t)0x00400000), /*!< External interrupt line 22 Connected to the Comparator 2 event,only applicable for 072 and 091 */
EINT_LINE23 = ((uint32_t)0x00800000), /*!< External interrupt line 23 Connected to the I2C1 wakeup event,not applicable for 030 */
EINT_LINE25 = ((uint32_t)0x02000000), /*!< External interrupt line 25 Connected to the USART1 wakeup event,not applicable for 030 */
EINT_LINE26 = ((uint32_t)0x04000000), /*!< External interrupt line 26 Connected to the USART2 wakeup event,only applicable for 072 and 091 */
EINT_LINE27 = ((uint32_t)0x08000000), /*!< External interrupt line 27 Connected to the CEC wakeup event,only applicable for 072*/
EINT_LINE28 = ((uint32_t)0x10000000), /*!< External interrupt line 28 Connected to the USART3 wakeup event,only applicable for 091 */
EINT_LINE31 = ((int)0x80000000), /*!< External interrupt line 31 Connected to the VDD USB monitor,only applicable for 072 */
} EINT_LINE_T;
/**@} end of group EINT_Enumerations */
/** @defgroup EINT_Structures Structures
@{
*/
/*!
* @brief EINT Config struct definition
*/
typedef struct
{
uint32_t line; /*!< Specifies the new state of the selected EINT lines. */
EINT_MODE_T mode; /*!< Specifies the mode for the EINT lines. */
EINT_TRIGGER_T trigger; /*!< Specifies the trigger signal active edge for the EINT lines. */
uint8_t lineCmd; /*!< Specifies the EINT lines to be enabled or disabled. */
} EINT_Config_T;
/**@} end of group EINT_Structures */
/** @defgroup EINT_Variables Variables
@{
*/
/**@} end of group EINT_Variables */
/** @defgroup EINT_Functions Functions
@{
*/
/* Reset and configuration */
void EINT_Reset(void);
void EINT_Config(EINT_Config_T* eintConfig);
void EINT_ConfigStructInit(EINT_Config_T* eintConfig);
/* Interrupt */
void EINT_SelectSWInterrupt(uint32_t line);
/* Flag */
uint8_t EINT_ReadStatusFlag(uint32_t line);
void EINT_ClearStatusFlag(uint32_t line);
uint8_t EINT_ReadIntFlag(uint32_t line);
void EINT_ClearIntFlag(uint32_t line);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_EINT_H */
/**@} end of group EINT_Functions */
/**@} end of group EINT_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_fmc.h
*
* @brief This file contains all the functions prototypes for the FMC firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_FMC_H
#define __APM32F0XX_FMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup FMC_Driver
@{
*/
/** @defgroup FMC_Macros Macros
@{
*/
/* Macros description */
/* Flash Read protection key */
#define FMC_RP_KEY ((uint32_t)0XA5)
/* Flash key definition */
#define FMC_KEY_1 ((uint32_t)0x45670123)
#define FMC_KEY_2 ((uint32_t)0xCDEF89AB)
#define FMC_OB_KEY_1 ((uint32_t)0x45670123)
#define FMC_OB_KEY_2 ((uint32_t)0xCDEF89AB)
/* Delay definition */
#define FMC_DELAY_ERASE ((uint32_t)0x000B0000)
#define FMC_DELAY_PROGRAM ((uint32_t)0x00002000)
/* 32K and 64K Flash devices */
#if !defined (APM32F030xC) && !defined (APM32F070xB) && !defined (APM32F071xB) && !defined (APM32F072xB) && !defined (APM32F091)
/* Flash write protect page definition */
#define FLASH_WRP_PAGE_0_3 ((uint32_t)0x00000001) /*!< Write protection of page 0 to 3 */
#define FLASH_WRP_PAGE_4_7 ((uint32_t)0x00000002) /*!< Write protection of page 4 to 7 */
#define FLASH_WRP_PAGE_8_11 ((uint32_t)0x00000004) /*!< Write protection of page 8 to 11 */
#define FLASH_WRP_PAGE_12_15 ((uint32_t)0x00000008) /*!< Write protection of page 12 to 15 */
#define FLASH_WRP_PAGE_16_19 ((uint32_t)0x00000010) /*!< Write protection of page 16 to 19 */
#define FLASH_WRP_PAGE_20_23 ((uint32_t)0x00000020) /*!< Write protection of page 20 to 23 */
#define FLASH_WRP_PAGE_24_27 ((uint32_t)0x00000040) /*!< Write protection of page 24 to 27 */
#define FLASH_WRP_PAGE_28_31 ((uint32_t)0x00000080) /*!< Write protection of page 28 to 31 */
#define FLASH_WRP_PAGE_32_35 ((uint32_t)0x00000100) /*!< Write protection of page 32 to 35 */
#define FLASH_WRP_PAGE_36_39 ((uint32_t)0x00000200) /*!< Write protection of page 36 to 39 */
#define FLASH_WRP_PAGE_40_43 ((uint32_t)0x00000400) /*!< Write protection of page 40 to 43 */
#define FLASH_WRP_PAGE_44_47 ((uint32_t)0x00000800) /*!< Write protection of page 44 to 47 */
#define FLASH_WRP_PAGE_48_51 ((uint32_t)0x00001000) /*!< Write protection of page 48 to 51 */
#define FLASH_WRP_PAGE_52_55 ((uint32_t)0x00002000) /*!< Write protection of page 52 to 55 */
#define FLASH_WRP_PAGE_56_59 ((uint32_t)0x00004000) /*!< Write protection of page 56 to 59 */
#define FLASH_WRP_PAGE_60_63 ((uint32_t)0x00008000) /*!< Write protection of page 60 to 63 */
#define FLASH_WRP_PAGE_ALL ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
/* 128K and 256K Flash devices */
#else
/* Flash write protect page definition */
#define FMC_WRP_PAGE_0_1 ((uint32_t)0x00000001) /*!< Write protection of page 0 to 1 */
#define FMC_WRP_PAGE_2_3 ((uint32_t)0x00000002) /*!< Write protection of page 2 to 3 */
#define FMC_WRP_PAGE_4_5 ((uint32_t)0x00000004) /*!< Write protection of page 4 to 5 */
#define FMC_WRP_PAGE_6_7 ((uint32_t)0x00000008) /*!< Write protection of page 6 to 7 */
#define FMC_WRP_PAGE_8_9 ((uint32_t)0x00000010) /*!< Write protection of page 8 to 5 */
#define FMC_WRP_PAGE_10_11 ((uint32_t)0x00000020) /*!< Write protection of page 10 to 5 */
#define FMC_WRP_PAGE_12_13 ((uint32_t)0x00000040) /*!< Write protection of page 12 to 5 */
#define FMC_WRP_PAGE_14_15 ((uint32_t)0x00000080) /*!< Write protection of page 14 to 5 */
#define FMC_WRP_PAGE_16_17 ((uint32_t)0x00000100) /*!< Write protection of page 16 to 15 */
#define FMC_WRP_PAGE_18_19 ((uint32_t)0x00000200) /*!< Write protection of page 18 to 19 */
#define FMC_WRP_PAGE_20_21 ((uint32_t)0x00000400) /*!< Write protection of page 20 to 21 */
#define FMC_WRP_PAGE_22_23 ((uint32_t)0x00000800) /*!< Write protection of page 22 to 23 */
#define FMC_WRP_PAGE_24_25 ((uint32_t)0x00001000) /*!< Write protection of page 24 to 25 */
#define FMC_WRP_PAGE_26_27 ((uint32_t)0x00002000) /*!< Write protection of page 26 to 27 */
#define FMC_WRP_PAGE_28_29 ((uint32_t)0x00004000) /*!< Write protection of page 28 to 29 */
#define FMC_WRP_PAGE_30_31 ((uint32_t)0x00008000) /*!< Write protection of page 30 to 31 */
#define FMC_WRP_PAGE_32_33 ((uint32_t)0x00010000) /*!< Write protection of page 32 to 33 */
#define FMC_WRP_PAGE_34_35 ((uint32_t)0x00020000) /*!< Write protection of page 34 to 35 */
#define FMC_WRP_PAGE_36_37 ((uint32_t)0x00040000) /*!< Write protection of page 36 to 37 */
#define FMC_WRP_PAGE_38_39 ((uint32_t)0x00080000) /*!< Write protection of page 38 to 39 */
#define FMC_WRP_PAGE_40_41 ((uint32_t)0x00100000) /*!< Write protection of page 40 to 41 */
#define FMC_WRP_PAGE_42_43 ((uint32_t)0x00200000) /*!< Write protection of page 42 to 43 */
#define FMC_WRP_PAGE_44_45 ((uint32_t)0x00400000) /*!< Write protection of page 44 to 45 */
#define FMC_WRP_PAGE_46_47 ((uint32_t)0x00800000) /*!< Write protection of page 46 to 47 */
#define FMC_WRP_PAGE_48_49 ((uint32_t)0x01000000) /*!< Write protection of page 48 to 49 */
#define FMC_WRP_PAGE_50_51 ((uint32_t)0x02000000) /*!< Write protection of page 50 to 51 */
#define FMC_WRP_PAGE_52_53 ((uint32_t)0x04000000) /*!< Write protection of page 52 to 53 */
#define FMC_WRP_PAGE_54_55 ((uint32_t)0x08000000) /*!< Write protection of page 54 to 55 */
#define FMC_WRP_PAGE_56_57 ((uint32_t)0x10000000) /*!< Write protection of page 56 to 57 */
#define FMC_WRP_PAGE_58_59 ((uint32_t)0x20000000) /*!< Write protection of page 58 to 59 */
#define FMC_WRP_PAGE_60_61 ((uint32_t)0x40000000) /*!< Write protection of page 20 to 21 */
#define FMC_WRP_PAGE_ALL ((uint32_t)0xFFFFFFFF) /*!< Write protection of page all */
#endif
/**@} end of group FMC_Macros*/
/** @defgroup FMC_Enumerations Enumerations
@{
*/
/**
* @brief Flash Latency
*/
typedef enum
{
FMC_LATENCY_0, /*!< Flash zero latency cycle */
FMC_LATENCY_1 /*!< Flash one latency cycle */
} FMC_LATENCY_T;
/**
* @brief Flash definition
*/
typedef enum
{
FMC_FLAG_BUSY = ((uint8_t)0x01), /*!< Busy flag */
FMC_FLAG_PE = ((uint8_t)0x04), /*!< Program error flag */
FMC_FLAG_WPE = ((uint8_t)0x10), /*!< Write protection flag */
FMC_FLAG_OC = ((uint8_t)0x20), /*!< Operation complete flag */
} FMC_FLAG_T;
/**
* @brief Flash Status
*/
typedef enum
{
FMC_STATE_COMPLETE = ((uint8_t)0), /*!< Operation complete */
FMC_STATE_BUSY = ((uint8_t)1), /*!< Busy */
FMC_STATE_PG_ERR = ((uint8_t)2), /*!< Program error */
FMC_STATE_WRP_ERR = ((uint8_t)3), /*!< Write Protection error */
FMC_STATE_TIMEOUT = ((uint8_t)4), /*!< Time out */
} FMC_STATE_T;
/**
* @brief Interrupt source
*/
typedef enum
{
FMC_INT_ERROR = ((uint32_t)0x400), /*!< Error interrupt */
FMC_INT_COMPLETE = ((uint32_t)0x1000), /*!< Operation complete interrupt */
} FMC_INT_T;
/**
* @brief Protection Level
*/
typedef enum
{
FMC_RDP_LEVEL_0 = ((uint8_t)0xAA), /*!< Protection Level 0 */
FMC_RDP_LEVEL_1 = ((uint8_t)0xBB), /*!< Protection Level 1 */
} FMC_RDP_T;
/**
* @brief Option byte WDG mode activation
*/
typedef enum
{
FMC_OB_IWDT_HW = ((uint8_t)0X00), /*!< activated by hardware */
FMC_OB_IWDT_SW = ((uint8_t)0X01), /*!< activated by software */
} FMC_OB_IWDT_T;
/**
* @brief Option byte STOP mode activation
*/
typedef enum
{
FMC_OB_STOP_RESET = ((uint8_t)0X00), /*!< Reset generated when entering in STOP */
FMC_OB_STOP_NRST = ((uint8_t)0X02), /*!< No reset generated when entering in STOP */
} FMC_OB_STOP_T;
/**
* @brief Option byte STDBY mode activation
*/
typedef enum
{
FMC_OB_STDBY_RESET = ((uint8_t)0X00), /*!< Reset generated when entering in STDBY */
FMC_OB_STDBY_NRST = ((uint8_t)0X04), /*!< No reset generated when entering in STDBY */
} FMC_OB_STDBY_T;
/**
* @brief Flash Option Bytes BOOT0
*/
typedef enum
{
FMC_OB_BOOT0_RESET = ((uint8_t)0X00), /*!< BOOT0 Reset */
FMC_OB_BOOT0_SET = ((uint8_t)0X08), /*!< BOOT0 Set */
} FMC_OB_BOOT0_T;
/**
* @brief Flash Option Bytes BOOT1
*/
typedef enum
{
FMC_OB_BOOT1_RESET = ((uint8_t)0X00), /*!< BOOT1 Reset */
FMC_OB_BOOT1_SET = ((uint8_t)0X10), /*!< BOOT1 Set */
} FMC_OB_BOOT1_T;
/**
* @brief Flash Option Bytes VDDA Analog Monitoring
*/
typedef enum
{
FMC_OB_VDDA_ANALOG_OFF = ((uint8_t)0X00), /*!< Analog monitoring on VDDA Power source OFF */
FMC_OB_VDDA_ANALOG_ON = ((uint8_t)0X20), /*!< Analog monitoring on VDDA Power source ON */
} FMC_OB_VDDA_ANALOG_T;
/**
* @brief Flash Option Bytes SRAM Parity Enable
*/
typedef enum
{
FMC_OB_SRAM_PARITY_SET = ((uint8_t)0X00), /*!< SRAM parity enable Set */
FMC_OB_SRAM_PARITY_RESET = ((uint8_t)0X40), /*!< SRAM parity enable reset */
} FMC_OB_SRAM_PARITY_T;
/**
* @brief flash Option Bytes BOOT0SW
*/
typedef enum
{
FMC_OB_BOOT0_SW = ((uint8_t)0X00), /*!< BOOT0 pin disabled */
FMC_OB_BOOT0_HW = ((uint8_t)0X80), /*!< BOOT0 pin bonded with GPIO */
} FMC_OB_BOOT0SW_T;
/**@} end of group FMC_Enumerations*/
/** @defgroup FMC_Structures Structures
@{
*/
/**
* @brief User Option byte config struct definition
*/
typedef struct
{
FMC_OB_IWDT_T iwdtSw;
FMC_OB_STOP_T stopce;
FMC_OB_STDBY_T stdbyce;
} FMC_UserConfig_T;
/**@} end of group FMC_Structures*/
/** @defgroup FMC_Variables Variables
@{
*/
/**@} end of group FMC_Variables*/
/** @defgroup FMC_Functions Functions
@{
*/
/* Function description */
/* Latency */
void FMC_SetLatency(FMC_LATENCY_T latency);
/* Prefetch Buffer */
void FMC_EnablePrefetchBuffer(void);
void FMC_DisablePrefetchBuffer(void);
uint8_t FMC_ReadPrefetchBufferStatus(void);
/* Lock */
void FMC_Unlock(void);
void FMC_Lock(void);
/* Erase and Program */
FMC_STATE_T FMC_ErasePage(uint32_t pageAddr);
FMC_STATE_T FMC_EraseAllPages(void);
FMC_STATE_T FMC_ProgramWord(uint32_t addr, uint32_t data);
FMC_STATE_T FMC_ProgramHalfWord(uint32_t addr, uint16_t data);
/* FMC Option Bytes Programming functions */
void FMC_UnlockOptionByte(void);
void FMC_LockOptionByte(void);
void FMC_LaunchOptionByte(void);
FMC_STATE_T FMC_EraseOptionByte(void);
FMC_STATE_T FMC_EnableWriteProtection(uint32_t page);
FMC_STATE_T FMC_ConfigReadOutProtection(FMC_RDP_T rdp);
FMC_STATE_T FMC_ConfigOptionByteUser(FMC_UserConfig_T* userConfig);
FMC_STATE_T FMC_EnableOptionByteBOOT(void);
FMC_STATE_T FMC_DisableOptionByteBOOT(void);
FMC_STATE_T FMC_EnableOptionByteVDDA(void);
FMC_STATE_T FMC_DisableOptionByteVDDA(void);
FMC_STATE_T FMC_EnableOptionByteSRAMParity(void);
FMC_STATE_T FMC_DisableOptionByteSRAMParity(void);
FMC_STATE_T FMC_WriteOptionByteUser(uint8_t ob_user);
FMC_STATE_T FMC_ProgramOptionByteData(uint32_t addr, uint8_t data);
uint8_t FMC_ReadOptionByteUser(void);
uint32_t FMC_ReadOptionByteWriteProtection(void);
uint8_t FMC_GetReadProtectionStatus(void);
/* Interrupt and Flag */
void FMC_EnableInterrupt(uint32_t interrupt);
void FMC_DisableInterrupt(uint32_t interrupt);
uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag);
void FMC_ClearStatusFlag(uint8_t flag);
/* State management */
FMC_STATE_T FMC_ReadState(void);
FMC_STATE_T FMC_WaitForReady(uint32_t timeOut);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_FMC_H */
/**@} end of group FMC_Functions*/
/**@} end of group FMC_Driver*/
/**@} end of group APM32F0xx_StdPeriphDriver*/

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/*!
* @file apm32f0xx_gpio.h
*
* @brief This file contains all the functions prototypes for the GPIO firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_GPIO_H
#define __APM32F0XX_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup GPIO_Driver
@{
*/
/** @defgroup GPIO_Macros Macros
@{
*/
/**@} end of group GPIO_Macros */
/** @defgroup GPIO_Enumerations Enumerations
@{
*/
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{
GPIO_MODE_IN = 0x00, /*!< GPIO Input Mode */
GPIO_MODE_OUT = 0x01, /*!< GPIO Output Mode */
GPIO_MODE_AF = 0x02, /*!< GPIO Alternate function Mode */
GPIO_MODE_AN = 0x03, /*!< GPIO Analog In/Out Mode */
} GPIO_MODE_T;
/**
* @brief Output type enumeration
*/
typedef enum
{
GPIO_OUT_TYPE_PP = 0x00, /*!< General purpose output push-pull */
GPIO_OUT_TYPE_OD = 0x01, /*!< General purpose output Open-drain */
} GPIO_OUT_TYPE_T;
/**
* @brief GPIO Output Maximum frequency selection
*/
typedef enum
{
GPIO_SPEED_2MHz = 0x00, /*!< Output speed up to 2 MHz */
GPIO_SPEED_10MHz = 0x01, /*!< Output speed up to 10 MHz */
GPIO_SPEED_50MHz = 0x03, /*!< Output speed up to 50 MHz */
} GPIO_SPEED_T;
/**
* @brief Configuration Pull-Up Pull-Down enumeration
*/
typedef enum
{
GPIO_PUPD_NO = 0x00, /*!< GPIO no pull mode */
GPIO_PUPD_PU = 0x01, /*!< GPIO pull-up mode */
GPIO_PUPD_PD = 0x02, /*!< GPIO pull-down mode */
} GPIO_PUPD_T;
/**
* @brief Bit SET and Bit RESET enumeration
*/
typedef enum
{
Bit_RESET,
Bit_SET
} GPIO_BSRET_T;
/**
* @brief Definition of the GPIO pins
*/
typedef enum
{
GPIO_PIN_0 = ((uint16_t)BIT0), /*!< GPIO pin 0 selected */
GPIO_PIN_1 = ((uint16_t)BIT1), /*!< GPIO pin 1 selected */
GPIO_PIN_2 = ((uint16_t)BIT2), /*!< GPIO pin 2 selected */
GPIO_PIN_3 = ((uint16_t)BIT3), /*!< GPIO pin 3 selected */
GPIO_PIN_4 = ((uint16_t)BIT4), /*!< GPIO pin 4 selected */
GPIO_PIN_5 = ((uint16_t)BIT5), /*!< GPIO pin 5 selected */
GPIO_PIN_6 = ((uint16_t)BIT6), /*!< GPIO pin 6 selected */
GPIO_PIN_7 = ((uint16_t)BIT7), /*!< GPIO pin 7 selected */
GPIO_PIN_8 = ((uint16_t)BIT8), /*!< GPIO pin 8 selected */
GPIO_PIN_9 = ((uint16_t)BIT9), /*!< GPIO pin 9 selected */
GPIO_PIN_10 = ((uint16_t)BIT10), /*!< GPIO pin 10 selected */
GPIO_PIN_11 = ((uint16_t)BIT11), /*!< GPIO pin 11 selected */
GPIO_PIN_12 = ((uint16_t)BIT12), /*!< GPIO pin 12 selected */
GPIO_PIN_13 = ((uint16_t)BIT13), /*!< GPIO pin 13 selected */
GPIO_PIN_14 = ((uint16_t)BIT14), /*!< GPIO pin 14 selected */
GPIO_PIN_15 = ((uint16_t)BIT15), /*!< GPIO pin 15 selected */
GPIO_PIN_ALL = ((uint32_t)0XFFFF), /*!< GPIO all pins selected */
} GPIO_PIN_T;
/**
* @brief GPIO Pin sources
*/
typedef enum
{
GPIO_PIN_SOURCE_0 = ((uint8_t)0x00), /*!< GPIO pin source 0 */
GPIO_PIN_SOURCE_1 = ((uint8_t)0x01), /*!< GPIO pin source 1 */
GPIO_PIN_SOURCE_2 = ((uint8_t)0x02), /*!< GPIO pin source 2 */
GPIO_PIN_SOURCE_3 = ((uint8_t)0x03), /*!< GPIO pin source 3 */
GPIO_PIN_SOURCE_4 = ((uint8_t)0x04), /*!< GPIO pin source 4 */
GPIO_PIN_SOURCE_5 = ((uint8_t)0x05), /*!< GPIO pin source 5 */
GPIO_PIN_SOURCE_6 = ((uint8_t)0x06), /*!< GPIO pin source 6 */
GPIO_PIN_SOURCE_7 = ((uint8_t)0x07), /*!< GPIO pin source 7 */
GPIO_PIN_SOURCE_8 = ((uint8_t)0x08), /*!< GPIO pin source 8 */
GPIO_PIN_SOURCE_9 = ((uint8_t)0x09), /*!< GPIO pin source 9 */
GPIO_PIN_SOURCE_10 = ((uint8_t)0x0A), /*!< GPIO pin source 10 */
GPIO_PIN_SOURCE_11 = ((uint8_t)0x0B), /*!< GPIO pin source 11 */
GPIO_PIN_SOURCE_12 = ((uint8_t)0x0C), /*!< GPIO pin source 12 */
GPIO_PIN_SOURCE_13 = ((uint8_t)0x0D), /*!< GPIO pin source 13 */
GPIO_PIN_SOURCE_14 = ((uint8_t)0x0E), /*!< GPIO pin source 14 */
GPIO_PIN_SOURCE_15 = ((uint8_t)0x0F), /*!< GPIO pin source 15 */
} GPIO_PIN_SOURCE_T;
/**
* @brief gpio alternate function define
*/
typedef enum
{
GPIO_AF_PIN0 = ((uint8_t)0x00), /*!< GPIO alternate function pin 0 */
GPIO_AF_PIN1 = ((uint8_t)0x01), /*!< GPIO alternate function pin 1 */
GPIO_AF_PIN2 = ((uint8_t)0x02), /*!< GPIO alternate function pin 2 */
GPIO_AF_PIN3 = ((uint8_t)0x03), /*!< GPIO alternate function pin 3 */
GPIO_AF_PIN4 = ((uint8_t)0x04), /*!< GPIO alternate function pin 4 */
GPIO_AF_PIN5 = ((uint8_t)0x05), /*!< GPIO alternate function pin 5 */
GPIO_AF_PIN6 = ((uint8_t)0x06), /*!< GPIO alternate function pin 6 */
GPIO_AF_PIN7 = ((uint8_t)0x07), /*!< GPIO alternate function pin 7 */
} GPIO_AF_T;
/**@} end of group GPIO_Enumerations */
/** @defgroup GPIO_Structures Structures
@{
*/
/**
* @brief GPIO Config structure definition
*/
typedef struct
{
uint16_t pin; /*!< Specifies the GPIO pins to be configured */
GPIO_MODE_T mode; /*!< Specifies the operating mode for the selected pins */
GPIO_OUT_TYPE_T outtype; /*!< Specifies the speed for the selected pins */
GPIO_SPEED_T speed; /*!< Specifies the operating output type for the selected pins */
GPIO_PUPD_T pupd; /*!< Specifies the operating Pull-up/Pull down for the selected pins */
} GPIO_Config_T;
/**@} end of group GPIO_Structures */
/** @defgroup GPIO_Variables Variables
@{
*/
/**@} end of group GPIO_Variables*/
/** @defgroup GPIO_Functions Functions
@{
*/
/* Reset and common Configuration */
void GPIO_Reset(GPIO_T* port);
void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig);
void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig);
/* GPIO Lock functions */
void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin);
/* GPIO Read functions */
uint16_t GPIO_ReadOutputPort(GPIO_T* port);
uint16_t GPIO_ReadInputPort(GPIO_T* port);
uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin);
uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin);
/* GPIO Write functions */
void GPIO_SetBit(GPIO_T* port, uint16_t pin);
void GPIO_ClearBit(GPIO_T* port, uint16_t pin);
void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, GPIO_BSRET_T bitVal);
void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue);
/* GPIO Other functions */
void GPIO_ConfigPinAF(GPIO_T* port, GPIO_PIN_SOURCE_T pinSource, GPIO_AF_T afPin);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0xx_GPIO_H */
/**@} end of group GPIO_Functions */
/**@} end of group GPIO_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_i2c.h
*
* @brief This file contains all the functions prototypes for the I2C firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_I2C_H
#define __APM32F0XX_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup I2C_Driver
@{
*/
/** @defgroup I2C_Macros Macros
@{
*/
/* Slave address (master mode) */
#define I2C_CTRL2_SADD ((uint32_t)0x000003FF)
/* Number of bytes */
#define I2C_CTRL2_NUMBYT ((uint32_t)0x00FF0000)
/* ENDCFG,RELOADEN,STOP,START,TXDIR clear CTRL2 register Mask */
#define I2C_CTRL2_MASK ((uint32_t)0x03006400)
/* I2C Register reset value */
#define I2C_CTRL1_RESET_VALUE ((uint32_t)0x00)
#define I2C_CTRL2_RESET_VALUE ((uint32_t)0x00)
#define I2C_ADDR1_RESET_VALUE ((uint32_t)0x00)
#define I2C_ADDR2_RESET_VALUE ((uint32_t)0x00)
#define I2C_TIMING_RESET_VALUE ((uint32_t)0x00)
#define I2C_TIMEOUT_RESET_VALUE ((uint32_t)0x00)
#define I2C_STS_RESET_VALUE ((uint32_t)0x01)
#define I2C_INTFCLR_RESET_VALUE ((uint32_t)0x00)
#define I2C_PEC_RESET_VALUE ((uint32_t)0x00)
#define I2C_TXDATA_RESET_VALUE ((uint32_t)0x00)
#define I2C_RXDATA_RESET_VALUE ((uint32_t)0x00)
/* I2C_channels */
#define I2C_Channel_TempSensor ((uint32_t)I2C_CHANNEL_16)
#define I2C_Channel_Vrefint ((uint32_t)I2C_CHANNEL_17)
/**@} end of group I2C_Macros */
/** @defgroup I2C_Enumerations Enumerations
@{
*/
/**
* @brief I2C Analog noise filter
*/
typedef enum
{
I2C_ANALOG_FILTER_ENABLE = ((uint8_t)0), /*!< Analog noise filter enabled */
I2C_ANALOG_FILTER_DISABLE = ((uint8_t)1), /*!< Analog noise filter disabled */
} I2C_ANALOG_FILTER_T;
/**
* @brief I2C Digital noise filter
*/
typedef enum
{
I2C_DIGITAL_FILTER_0 = ((uint8_t)0x00), /*!< Digital filter disabled */
I2C_DIGITAL_FILTER_1 = ((uint8_t)0x01), /*!< Digital filter enabled and filtering capability is 1 T_i2cclk */
I2C_DIGITAL_FILTER_2 = ((uint8_t)0x02), /*!< Digital filter enabled and filtering capability is 3 T_i2cclk */
I2C_DIGITAL_FILTER_3 = ((uint8_t)0x03), /*!< Digital filter enabled and filtering capability is 3 T_i2cclk */
I2C_DIGITAL_FILTER_4 = ((uint8_t)0x04), /*!< Digital filter enabled and filtering capability is 4 T_i2cclk */
I2C_DIGITAL_FILTER_5 = ((uint8_t)0x05), /*!< Digital filter enabled and filtering capability is 5 T_i2cclk */
I2C_DIGITAL_FILTER_6 = ((uint8_t)0x06), /*!< Digital filter enabled and filtering capability is 6 T_i2cclk */
I2C_DIGITAL_FILTER_7 = ((uint8_t)0x07), /*!< Digital filter enabled and filtering capability is 7 T_i2cclk */
I2C_DIGITAL_FILTER_8 = ((uint8_t)0x08), /*!< Digital filter enabled and filtering capability is 8 T_i2cclk */
I2C_DIGITAL_FILTER_9 = ((uint8_t)0x09), /*!< Digital filter enabled and filtering capability is 9 T_i2cclk */
I2C_DIGITAL_FILTER_10 = ((uint8_t)0x0A), /*!< Digital filter enabled and filtering capability is 10 T_i2cclk */
I2C_DIGITAL_FILTER_11 = ((uint8_t)0x0B), /*!< Digital filter enabled and filtering capability is 11 T_i2cclk */
I2C_DIGITAL_FILTER_12 = ((uint8_t)0x0C), /*!< Digital filter enabled and filtering capability is 12 T_i2cclk */
I2C_DIGITAL_FILTER_13 = ((uint8_t)0x0D), /*!< Digital filter enabled and filtering capability is 13 T_i2cclk */
I2C_DIGITAL_FILTER_14 = ((uint8_t)0x0E), /*!< Digital filter enabled and filtering capability is 14 T_i2cclk */
I2C_DIGITAL_FILTER_15 = ((uint8_t)0x0F), /*!< Digital filter enabled and filtering capability is 15 T_i2cclk */
} I2C_DIGITAL_FILTER_T;
/**
* @brief I2C mode
*/
typedef enum
{
I2C_MODE_I2C = ((uint32_t)0x00000000), /*!< I2C mode */
I2C_MODE_SMBUSDEVICE = ((uint32_t)0x00100000), /*!< SMBus device mode */
I2C_MODE_SMBUSHOST = ((uint32_t)0x00200000), /*!< SMBus host mode */
} I2C_MODE_T;
/**
* @brief I2C acknowledge
*/
typedef enum
{
I2C_ACK_ENABLE = ((uint8_t)0), /*!< ACK generation (slave mode) */
I2C_ACK_DISABLE = ((uint8_t)1), /*!< NACK generation (slave mode) */
} I2C_ACK_T;
/**
* @brief I2C acknowledge address
*/
typedef enum
{
I2C_ACK_ADDRESS_7BIT = ((uint8_t)0), /*!< ACK generation (slave mode) */
I2C_ACK_ADDRESS_10BIT = ((uint8_t)1), /*!< NACK generation (slave mode) */
} I2C_ACK_ADDRESS_T;
/**
* @brief I2C transfer direction
*/
typedef enum
{
I2C_DIRECTION_TX = ((uint8_t)0), /*!< Transmission direction */
I2C_DIRECTION_RX = ((uint8_t)1), /*!< Reception direction */
} I2C_DIRECTION_T;
/**
* @brief I2C DMA requests
*/
typedef enum
{
I2C_DMA_REQ_TX = ((uint8_t)0), /*!< DMA transmission requests enable */
I2C_DMA_REQ_RX = ((uint8_t)1), /*!< DMA reception requests enable */
} I2C_DMA_REQ_T;
/**
* @brief I2C own address2 mask
*/
typedef enum
{
I2C_ADDR2MSK_NOMASK = ((uint8_t)0x00), /*!< No masked */
I2C_ADDR2MSK_MASK01 = ((uint8_t)0x01), /*!< Don't care masked ADDR2[1:0] */
I2C_ADDR2MSK_MASK02 = ((uint8_t)0x02), /*!< Don't care masked ADDR2[2:1] */
I2C_ADDR2MSK_MASK03 = ((uint8_t)0x03), /*!< Don't care masked ADDR2[3:1] */
I2C_ADDR2MSK_MASK04 = ((uint8_t)0x04), /*!< Don't care masked ADDR2[4:1] */
I2C_ADDR2MSK_MASK05 = ((uint8_t)0x05), /*!< Don't care masked ADDR2[5:1] */
I2C_ADDR2MSK_MASK06 = ((uint8_t)0x06), /*!< Don't care masked ADDR2[6:1] */
I2C_ADDR2MSK_MASK07 = ((uint8_t)0x07), /*!< Don't care masked ADDR2[7:1] */
} I2C_ADDR2MSK_T;
/**
* @brief I2C registers
*/
typedef enum
{
I2C_REGISTER_CTRL1 = ((uint8_t)0x00), /*!< CTRL1 register */
I2C_REGISTER_CTRL2 = ((uint8_t)0x04), /*!< CTRL2 register */
I2C_REGISTER_ADDR1 = ((uint8_t)0x08), /*!< ADDR1 register */
I2C_REGISTER_ADDR2 = ((uint8_t)0x0C), /*!< ADDR2 register */
I2C_REGISTER_TIMING = ((uint8_t)0x10), /*!< TIMING register */
I2C_REGISTER_TIMEOUT = ((uint8_t)0x14), /*!< TIMEOUT register */
I2C_REGISTER_STS = ((uint8_t)0x18), /*!< STS register */
I2C_REGISTER_INTFCLR = ((uint8_t)0x1C), /*!< INTFCLR register */
I2C_REGISTER_PEC = ((uint8_t)0x20), /*!< PEC register */
I2C_REGISTER_RXDATA = ((uint8_t)0x24), /*!< RXDATA register */
I2C_REGISTER_TXDATA = ((uint8_t)0x28), /*!< TXDATA register */
} I2C_REGISTER_T;
/**
* @brief I2C interrupts source
*/
typedef enum
{
I2C_INT_TXIE = ((uint8_t)0x02), /*!< TX Interrupt enable */
I2C_INT_RXIE = ((uint8_t)0x04), /*!< RX Interrupt enable */
I2C_INT_ADDRIE = ((uint8_t)0x08), /*!< Address match interrupt enable (slave only) */
I2C_INT_NACKIE = ((uint8_t)0x10), /*!< Not acknowledge received interrupt enable */
I2C_INT_STOPIE = ((uint8_t)0x20), /*!< STOP detection Interrupt enable */
I2C_INT_TXCIE = ((uint8_t)0x40), /*!< Transfer complete interrupt enable */
I2C_INT_ERRIE = ((uint8_t)0x80), /*!< Error interrupts enable */
} I2C_INT_T;
/**
* @brief I2C Flags
*/
typedef enum
{
/* STS1 register flag */
I2C_FLAG_TXBE = ((uint32_t)0x0001), /*!< Transmit buffer data register empty flag */
I2C_FLAG_TXINT = ((uint32_t)0x0002), /*!< Transmit interrupt flag */
I2C_FLAG_RXBNE = ((uint32_t)0x0004), /*!< Read buffer data register not empty flag */
I2C_FLAG_ADDR = ((uint32_t)0x0008), /*!< Address Sent/Matched (master/slave) flag */
I2C_FLAG_NACK = ((uint32_t)0x0010), /*!< Not acknowledge received flag */
I2C_FLAG_STOP = ((uint32_t)0x0020), /*!< Stop detected flag */
I2C_FLAG_TXCF = ((uint32_t)0x0040), /*!< Transfer complete flag */
I2C_FLAG_TCRF = ((uint32_t)0x0080), /*!< Transfer complete reload flag */
I2C_FLAG_BUSERR = ((uint32_t)0x0100), /*!< Bus error flag */
I2C_FLAG_ALF = ((uint32_t)0x0200), /*!< Arbitration Loss flag */
I2C_FLAG_OVR = ((uint32_t)0x0400), /*!< Overrun/Underrun flag */
I2C_FLAG_PECERR = ((uint32_t)0x0800), /*!< PEC error flag */
I2C_FLAG_TIMEOUT = ((uint32_t)0x1000), /*!< Timeout or t_low detection flag */
I2C_FLAG_ALERT = ((uint32_t)0x2000), /*!< SMBus alert flag */
I2C_FLAG_BUSY = ((uint32_t)0x8000), /*!< Bus Busy Flag */
} I2C_FLAG_T;
/**
* @brief I2C Interrupt flag
*/
typedef enum
{
I2C_INT_FLAG_TXINT = ((uint32_t)0x0002), /*!< Transmit interrupt flag */
I2C_INT_FLAG_RXBNE = ((uint32_t)0x0004), /*!< Read Buffer Data Register Not Empty interrupt flag */
I2C_INT_FLAG_ADDR = ((uint32_t)0x0008), /*!< Address Sent/Matched (master/slave) interrupt flag */
I2C_INT_FLAG_NACK = ((uint32_t)0x0010), /*!< Not acknowledge received interrupt flag */
I2C_INT_FLAG_STOP = ((uint32_t)0x0020), /*!< Stop detected interrupt flag */
I2C_INT_FLAG_TXCF = ((uint32_t)0x0040), /*!< Transfer complete interrupt flag */
I2C_INT_FLAG_TCRF = ((uint32_t)0x0080), /*!< Transfer Complete Reloadinterrupt flag */
I2C_INT_FLAG_BUSERR = ((uint32_t)0x0100), /*!< Bus error interrupt flag */
I2C_INT_FLAG_ALF = ((uint32_t)0x0200), /*!< Arbitration Loss interrupt flag */
I2C_INT_FLAG_OVR = ((uint32_t)0x0400), /*!< Overrun/Underrun interrupt flag */
I2C_INT_FLAG_PECERR = ((uint32_t)0x0800), /*!< PEC error interrupt flag */
I2C_INT_FLAG_TIMEOUT = ((uint32_t)0x1000), /*!< Timeout or t_low detection interrupt flag */
I2C_INT_FLAG_ALERT = ((uint32_t)0x2000), /*!< SMBus alert interrupt flag */
} I2C_INT_FLAG_T;
/**
* @brief I2C Reload End Mode
*/
typedef enum
{
I2C_RELOAD_MODE_RELOAD = ((uint32_t)0x01000000), /*!< Enable Reload mode */
I2C_RELOAD_MODE_AUTOEND = ((uint32_t)0x02000000), /*!< Enable Automatic end mode */
I2C_RELOAD_MODE_SOFTEND = ((uint32_t)0x00000000), /*!< Enable Software end mode */
} I2C_RELOAD_MODE_T;
/**
* @brief I2C Start/Stop Mode
*/
typedef enum
{
I2C_GENERATE_NO_STARTSTOP = ((uint32_t)0x00000000), /*!< Don't Generate stop and start condition */
I2C_GENERATE_START_WRITE = ((uint32_t)0x00002000), /*!< Generate Restart for write request */
I2C_GENERATE_STOP = ((uint32_t)0x00004000), /*!< Generate stop condition */
I2C_GENERATE_START_READ = ((uint32_t)0x00002400), /*!< Generate Restart for read request */
} I2C_GENERATE_T;
/**@} end of group I2C_Enumerations */
/** @defgroup I2C_Structures Structures
@{
*/
/**
* @brief I2C Config struct definition
*/
typedef struct
{
uint32_t timing; /*!< Specifies the I2C_TIMINGR_register value */
uint32_t address1; /*!< Specifies the device own address1 */
I2C_ACK_T ack; /*!< Enables or disables the acknowledgement */
I2C_MODE_T mode; /*!< Specifies the I2C mode*/
I2C_ACK_ADDRESS_T ackaddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged */
I2C_ANALOG_FILTER_T analogfilter; /*!< Enables or disables analog noise filter */
I2C_DIGITAL_FILTER_T digitalfilter; /*!< Configures the digital noise filter */
} I2C_Config_T;
/**@} end of group I2C_Structures */
/** @defgroup I2C_Variables Variables
@{
*/
/**@} end of group I2C_Variables*/
/** @defgroup I2C_Functions Functions
@{
*/
/* I2C reset and configuration */
void I2C_Reset(I2C_T* i2c);
void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig);
void I2C_ConfigStructInit(I2C_Config_T* i2cConfig);
void I2C_Enable(I2C_T* i2c);
void I2C_Disable(I2C_T* i2c);
void I2C_SoftwareReset(I2C_T* i2c);
void I2C_EnableAutoEnd(I2C_T* i2c);
void I2C_DisableAutoEnd(I2C_T* i2c);
void I2C_EnableReload(I2C_T* i2c);
void I2C_DisableReload(I2C_T* i2c);
void I2C_ConfigNumberOfBytes(I2C_T* i2c, uint8_t number);
void I2C_ConfigMasterRequest(I2C_T* i2c, I2C_DIRECTION_T direction);
void I2C_EnableGenerateStart(I2C_T* i2c);
void I2C_DisableGenerateStart(I2C_T* i2c);
void I2C_EnableGenerateStop(I2C_T* i2c);
void I2C_DisableGenerateStop(I2C_T* i2c);
void I2C_EnableAcknowledge(I2C_T* i2c);
void I2C_DisableAcknowledge(I2C_T* i2c);
uint8_t I2C_ReadAddressMatched(I2C_T* i2c);
uint16_t I2C_ReadTransferDirection(I2C_T* i2c);
void I2C_HandlingTransfer(I2C_T* i2c, uint16_t address, uint8_t number, I2C_RELOAD_MODE_T reloadend, I2C_GENERATE_T generates);
void I2C_ConfigTimeoutA(I2C_T* i2c, uint16_t timeout);
void I2C_ConfigTimeoutB(I2C_T* i2c, uint16_t timeout);
uint32_t I2C_ReadRegister(I2C_T* i2c, uint8_t registers);
/* Interrupt */
void I2C_EnableInterrupt(I2C_T* i2c, uint8_t interrupt);
void I2C_DisableInterrupt(I2C_T* i2c, uint8_t interrupt);
/* Clock Stretch */
void I2C_EnableStretchClock(I2C_T* i2c);
void I2C_DisableStretchClock(I2C_T* i2c);
/* Stop Mode */
void I2C_EnableStopMode(I2C_T* i2c); /*!< Not for APM32F030 devices */
void I2C_DisableStopMode(I2C_T* i2c); /*!< Not for APM32F030 devices */
/* Own address 2*/
void I2C_EnableOwnAddress2(I2C_T* i2c);
void I2C_DisableOwnAddress2(I2C_T* i2c);
void I2C_OwnAddress2Mask(I2C_T* i2c, uint16_t address, I2C_ADDR2MSK_T mask);
/* Broadcast */
void I2C_EnableBroadcastCall(I2C_T* i2c);
void I2C_DisableBroadcastCall(I2C_T* i2c);
/* slave */
void I2C_EnableSlaveByteControl(I2C_T* i2c);
void I2C_DisableSlaveByteControl(I2C_T* i2c);
void I2C_SlaveAddress(I2C_T* i2c, uint16_t address);
/* master */
void I2C_Enable10BitAddressingMode(I2C_T* i2c);
void I2C_Disable10BitAddressingMode(I2C_T* i2c);
void I2C_Enable10BitAddressHeader(I2C_T* i2c);
void I2C_Disable10BitAddressHeader(I2C_T* i2c);
/* Clock */
void I2C_EnableClockTimeout(I2C_T* i2c);
void I2C_DisableClockTimeout(I2C_T* i2c);
void I2C_EnableExtendClockTimeout(I2C_T* i2c);
void I2C_DisableExtendClockTimeout(I2C_T* i2c);
void I2C_EnableIdleClockTimeout(I2C_T* i2c);
void I2C_DisableIdleClockTimeout(I2C_T* i2c);
/* Transmit and receive */
void I2C_TxData(I2C_T* i2c, uint8_t data);
uint8_t I2C_RxData(I2C_T* i2c);
/* DMA request */
void I2C_EnableDMA(I2C_T* i2c, I2C_DMA_REQ_T request);
void I2C_DisableDMA(I2C_T* i2c, I2C_DMA_REQ_T request);
/* flag */
uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
void I2C_ClearStatusFlag(I2C_T* i2c, uint32_t flag);
uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag);
void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag);
/* SMBus */
void I2C_EnableSMBusAlert(I2C_T* i2c);
void I2C_DisableSMBusAlert(I2C_T* i2c);
void I2C_EnableSMBusHAEN(I2C_T* i2c);
void I2C_DisableSMBusHAEN(I2C_T* i2c);
void I2C_EnableSMBusDAEN(I2C_T* i2c);
void I2C_DisableSMBusDAEN(I2C_T* i2c);
void I2C_EnablePEC(I2C_T* i2c);
void I2C_DisablePEC(I2C_T* i2c);
void I2C_EnablePECRequest(I2C_T* i2c);
void I2C_DisablePECRequest(I2C_T* i2c);
uint8_t I2C_ReadPEC(I2C_T* i2c);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_I2C_H */
/**@} end of group I2C_Functions */
/**@} end of group I2C_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_iwdt.h
*
* @brief This file contains all the functions prototypes for the IWDT firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_IWDT_H
#define __APM32F0XX_IWDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup IWDT_Driver
@{
*/
/** @defgroup IWDT_Macros Macros
@{
*/
/**@} end of group IWDT_Macros*/
/** @defgroup IWDT_Enumerations Enumerations
@{
*/
/**@} end of group IWDT_Enumerations*/
/** @defgroup IWDT_Structures Structures
@{
*/
/**@} end of group IWDT_Structures*/
/** @defgroup IWDT_Variables Variables
@{
*/
/**@} end of group IWDT_Variables*/
/** @defgroup IWDT_Functions Functions
@{
*/
/**
* @brief IWDT key definition
*/
typedef enum
{
IWDT_KEY_REFRESH = ((uint16_t)0xAAAA), /*!< Value of Reload Register reoload to the counter to prevent the IWDT from resetting */
IWDT_KEY_ENABLE = ((uint16_t)0xCCCC), /*!< Enable the IWDT then the counter starts to count down from the reset value */
IWDT_KEY_ACCESS = ((uint16_t)0x5555), /*!< Rewrite the value of the Prescaler Register, Reload Register and Window Value Register */
} IWDT_KEY_T;
/**
* @brief IWDT divider
*/
typedef enum
{
IWDT_DIV_4 = ((uint8_t)0x00), /*!< Prescaler divider 4 */
IWDT_DIV_8 = ((uint8_t)0x01), /*!< Prescaler divider 8 */
IWDT_DIV_16 = ((uint8_t)0x02), /*!< Prescaler divider 16 */
IWDT_DIV_32 = ((uint8_t)0x03), /*!< Prescaler divider 32 */
IWDT_DIV_64 = ((uint8_t)0x04), /*!< Prescaler divider 64 */
IWDT_DIV_128 = ((uint8_t)0x05), /*!< Prescaler divider 128 */
IWDT_DIV_256 = ((uint8_t)0x06), /*!< Prescaler divider 256 */
} IWDT_DIV_T;
/**
* @brief IWDT flag definition
*/
typedef enum
{
IWDT_FLAG_DIVU = ((uint8_t)0X01), /*!< Watchdog prescaler value update */
IWDT_FLAG_CNTU = ((uint8_t)0X02), /*!< Watchdog counter reload value update */
IWDT_FLAG_WINU = ((uint8_t)0X04), /*!< Watchdog counter window value update */
} IWDT_FLAG_T;
/**@} end of group IWDT_Enumerations*/
/** @defgroup IWDT_Functions
@{
*/
/* Enable IWDT */
void IWDT_Enable(void);
/* Refresh IWDT */
void IWDT_Refresh(void);
/* Window Value */
void IWDT_ConfigWindowValue(uint16_t windowValue);
/* Set Counter reload */
void IWDT_ConfigReload(uint16_t reload);
/* Write Access */
void IWDT_EnableWriteAccess(void);
void IWDT_DisableWriteAccess(void);
/* divider */
void IWDT_ConfigDivider(IWDT_DIV_T div);
/* flag */
uint8_t IWDT_ReadStatusFlag(uint8_t flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_IWDT_H */
/**@} end of group IWDT_Functions*/
/**@} end of group IWDT_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver*/

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/*!
* @file apm32f0xx_misc.h
*
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_MISC_H
#define __APM32F0XX_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup MISC_Driver
@{
*/
/** @defgroup MISC_Macros Macros
@{
*/
/* MISC SysTick clock source */
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
/**@} end of group MISC_Macros */
/** @defgroup MISC_Enumerations Enumerations
@{
*/
/**
* @brief System low power mode
*/
typedef enum
{
NVIC_LOWPOER_SEVONPEND = 0x10, /*!< Wake up according to pending request */
NVIC_LOWPOER_SLEEPDEEP = 0x04, /*!< Enable sleep deep */
NVIC_LOWPOER_SLEEPONEXIT = 0x02 /*!< Sleep after exit ISR */
} NVIC_LOWPOER_T;
/**@} end of group MISC_Enumerations */
/** @defgroup MISC_Structures Structures
@{
*/
/**@} end of group MISC_Structures */
/** @defgroup MISC_Variables Variables
@{
*/
/**@} end of group MISC_Variables*/
/** @defgroup MISC_Functions Functions
@{
*/
/* NVIC */
void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t priority);
void NVIC_DisableIRQRequest(IRQn_Type irq);
/* Low Power */
void NVIC_EnableSystemLowPower(uint8_t lowPowerMode);
void NVIC_DisableSystemLowPower(uint8_t lowPowerMode);
/* SysTick */
void SysTick_ConfigCLKSource(uint32_t sysTickCLKSource);
/* PMU */
void PMU_EnterWaitMode(void);
void PMU_EnterHaltModeWFI(void);
void PMU_EnterHaltModeWFE(void);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_MISC_H */
/**@} end of group MISC_Functions */
/**@} end of group MISC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_ob.h
*
* @brief This file contains all the functions prototypes for the OB firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __APM32F0XX_OB_H
#define __APM32F0XX_OB_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes */
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup OB_Driver
@{
*/
/** @defgroup OB_Macros Macros
@{
*/
/**@} end of group OB_Macros*/
/** @defgroup OB_Enumerations Enumerations
@{
*/
/**
* @brief Read protection option byte
*/
typedef enum
{
OB_READ_PRO_LEVEL0 = 0xAA, /*!< No protection */
OB_READ_PRO_LEVEL1 = 0xBB, /*!< Read protection of the memory */
} OB_READ_PRO_T;
/**
* @brief Option Bytes Watchdog
*/
typedef enum
{
OB_WDG_HW = ((uint8_t)0), /*!< Hardware Watchdog */
OB_WDG_SW = ((uint8_t)1), /*!< Software Watchdog */
} OB_WDT_T;
/**
* @brief Option Bytes nRST STOP
*/
typedef enum
{
OB_STOP_RESET = ((uint8_t)0), /*!< Reset Stop mode */
OB_STOP_SET = ((uint8_t)1), /*!< Into Stop mode */
} OB_STOP_T;
/**
* @brief Option Bytes nRST Standby
*/
typedef enum
{
OB_STANDBY_RST = ((uint8_t)0), /*!< Reset STANDBY mode */
OB_STANDBY_SET = ((uint8_t)1), /*!< Into STANDBY mode */
} OB_STANDBY_T;
/**
* @brief Option Bytes nBOOT1
*/
typedef enum
{
OB_BOOT1_RST = ((uint8_t)0), /*!< Reset BOOT1 */
OB_BOOT1_SET = ((uint8_t)1), /*!< Into BOOT1 */
} OB_BOOT1_T;
/**
* @brief Option Bytes VDDA_Analog_Monitoring
*/
typedef enum
{
OB_VDDA_OFF = ((uint8_t)0), /*!< VDDA_Analog_Monitoring off */
OB_VDDA_ON = ((uint8_t)1), /*!< VDDA_Analog_Monitoring on */
} OB_VDDA_T;
/**
* @brief Option Bytes RAM PARITY CHECK
*/
typedef enum
{
OB_RAM_PARITY_CHECK_ENABLE = ((uint8_t)0), /*!< Enable Option Bytes RAM PARITY CHECK*/
OB_RAM_PARITY_CHECK_DISABLE = ((uint8_t)1), /*!< Disbale Option Bytes RAM PARITY CHECK */
} OB_RAM_PARITY_CHECK_T;
/**@} end of group OB_Enumerations*/
/** @defgroup OB_Structures Structures
@{
*/
/**
* @brief User Option byte config struct definition
*/
typedef struct
{
OB_READ_PRO_T readProtection; /*!< Read protection option byte */
OB_WDT_T wdt; /*!< Watch dog activation */
OB_STOP_T stop; /*!< Option Bytes nRST STOP */
OB_STANDBY_T stdby; /*!< Option Bytes nRST STDBY */
OB_BOOT1_T boot; /*!< Option Bytes nBOOT1 */
OB_VDDA_T vdda; /*!< Option Bytes nRST STOP */
OB_RAM_PARITY_CHECK_T ramParityCheck; /*!< Option Bytes RAM PARITY CHECK */
} OB_UserConfig_T;
/**@} end of group OB_Structures*/
/** @defgroup OB_Variables Variables
@{
*/
/**@} end of group OB_Variables*/
/** @defgroup OB_Functions Functions
@{
*/
/* Read protection option byte */
void OB_ReadProtectionOptionByte(OB_READ_PRO_T readProtection);
/* Option Bytes Watchdog */
void OB_OptionBytesWatchdog(OB_WDT_T wdt);
/* Option Bytes nRST STOP */
void OB_OptionBytesStop(OB_STOP_T stop);
/* Option Bytes nRST STDBY */
void OB_OptionBytesStandby(OB_STANDBY_T standby);
/* Option Bytes nBOOT1 */
void OB_OptionBytesBoot1(OB_BOOT1_T boot);
/* Option Bytes VDDA_Analog_Monitoring */
void OB_OptionBytesVddaAnalog(OB_VDDA_T vdda);
/* Option Bytes RAM PARITY CHECK */
void OB_OptionBytesRamParity(OB_RAM_PARITY_CHECK_T ramParityCheck);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_OB_H */
/**@} end of group OB_Functions*/
/**@} end of group OB_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver*/

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/*!
* @file apm32f0xx_pmu.h
*
* @brief This file contains all functions prototype and macros for the PMU peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F0XX_PMU_H
#define __APM32F0XX_PMU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup PMU_Driver PMU Driver
@{
*/
/** @defgroup PMU_Macros Macros
@{
*/
/**@} end of group PMU_Macros */
/** @defgroup PMU_Enumerations Enumerations
@{
*/
/**
* @brief PVD detection level (Not for APM32F030 devices)
*/
typedef enum
{
PMU_PVDLEVEL_0 = ((uint8_t)0x00), /*!< PVD detection level set to 2.2V */
PMU_PVDLEVEL_1 = ((uint8_t)0x01), /*!< PVD detection level set to 2.3V */
PMU_PVDLEVEL_2 = ((uint8_t)0x02), /*!< PVD detection level set to 2.4V */
PMU_PVDLEVEL_3 = ((uint8_t)0x03), /*!< PVD detection level set to 2.5V */
PMU_PVDLEVEL_4 = ((uint8_t)0x04), /*!< PVD detection level set to 2.6V */
PMU_PVDLEVEL_5 = ((uint8_t)0x05), /*!< PVD detection level set to 2.7V */
PMU_PVDLEVEL_6 = ((uint8_t)0x06), /*!< PVD detection level set to 2.8V */
PMU_PVDLEVEL_7 = ((uint8_t)0x07), /*!< PVD detection level set to 2.9V */
} PMU_PVDLEVEL_T;
/**
* @brief Wake Up PIN
*/
typedef enum
{
PMU_WAKEUPPIN_1 = ((uint16_t)0x0100), /*!< PIN_1 wakeup mcu */
PMU_WAKEUPPIN_2 = ((uint16_t)0x0200), /*!< PIN_2 wakeup mcu */
PMU_WAKEUPPIN_3 = ((uint16_t)0x0400), /*!< PIN_3 wakeup mcu, only for APM32F072/091 devices */
PMU_WAKEUPPIN_4 = ((uint16_t)0x0800), /*!< PIN_4 wakeup mcu, only for APM32F072/091 devices */
PMU_WAKEUPPIN_5 = ((uint16_t)0x1000), /*!< PIN_5 wakeup mcu , only for APM32F072/091 devices */
PMU_WAKEUPPIN_6 = ((uint16_t)0x2000), /*!< PIN_6, only for APM32F072/091 devices */
PMU_WAKEUPPIN_7 = ((uint16_t)0x4000), /*!< PIN_7, only for APM32F072/091 devices */
PMU_WAKEUPPIN_8 = ((uint16_t)0x8000), /*!< PIN_8, only for APM32F072/091 devices */
} PMU_WAKEUPPIN_T;
/**
* @brief Sleep mode entry
*/
typedef enum
{
PMU_SLEEPENTRY_WFI = 0x00, /*!< enter SLEEP mode with WFI instruction */
PMU_SLEEPENTRY_WFE = 0x01, /*!< enter SLEEP mode with WFE instruction */
} PMU_SLEEPENTRY_T;
/**
* @brief Regulator state is Sleep/Stop mode
*/
typedef enum
{
PMU_REGULATOR_ON = 0x00, /*!< STOP mode with regulator ON */
PMU_REGULATOR_LowPower = 0x01, /*!< STOP mode with regulator in low power mode */
} PMU_REGULATOR_T;
/**
* @brief Stop mode entry
*/
typedef enum
{
PMU_STOPENTRY_WFI = 0x00, /*!< Enter STOP mode with WFI instruction */
PMU_STOPENTRY_WFE = 0x01, /*!< Enter STOP mode with WFE instruction */
PMU_STOPENTRY_SLEEPONEXIT = 0x02, /*!< Enter STOP mode with SLEEPONEXIT instruction */
} PMU_STOPENTRY_T;
/**
* @brief Flag
*/
typedef enum
{
PMU_FLAG_WUPF = 0x01, /*!< Wake Up flag */
PMU_FLAG_STDBYF = 0x02, /*!< StandBy flag */
PMU_FLAG_PVDOF = 0x04, /*!< Not for APM32F030 devices */
PMU_FLAG_VREFINTF = 0x08, /*!<VREFINT flag */
} PMU_FLAG_T;
/**@} end of group PMU_Enumerations*/
/** @defgroup PMU_Structures Structures
@{
*/
/**@} end of group PMU_Structures */
/** @defgroup PMU_Variables Variables
@{
*/
/**@} end of group PMU_Variables */
/** @defgroup PMU_Fuctions Fuctions
@{
*/
/** Function used to set the PMU configuration to the default reset state */
void PMU_Reset(void);
/** Backup Domain Access function */
void PMU_EnableBackupAccess(void);
void PMU_DisableBackupAccess(void);
/** PVD configuration functions */
void PMU_ConfigPVDLevel(PMU_PVDLEVEL_T level); /*!< Not for APM32F030 devices */
void PMU_EnablePVD(void); /*!< Not for APM32F030 devices */
void PMU_DisablePVD(void); /*!< Not for APM32F030 devices */
/** WakeUp pins configuration functions */
void PMU_EnableWakeUpPin(PMU_WAKEUPPIN_T pin);
void PMU_DisableWakeUpPin(PMU_WAKEUPPIN_T pin);
/** Low Power modes configuration functions */
void PMU_EnterSleepMode(PMU_SLEEPENTRY_T entry);
void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOPENTRY_T entry);
void PMU_EnterSTANDBYMode(void);
/** Flags management functions */
uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag);
void PMU_ClearStatusFlag(uint8_t flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_PMU_H */
/**@} end of group PMU_Functions */
/**@} end of group PMU_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_rcm.h
*
* @brief This file contains all the functions prototypes for the RCM firmware library
*
* @version V1.0.2
*
* @date 2022-02-21
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F0XX_RCM_H
#define __APM32F0XX_RCM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup RCM_Driver RCM Driver
@{
*/
/** @defgroup RCM_Macros Macros
@{
*/
/**@} end of group RCM_Macros*/
/** @defgroup RCM_Enumerations Enumerations
@{
*/
/**
* @brief HSE enum
*/
typedef enum
{
RCM_HSE_CLOSE = 0x00, /*!< turn OFF the HSE oscillator */
RCM_HSE_OPEN = 0x01, /*!< turn ON the HSE oscillator */
RCM_HSE_BYPASS = 0x05, /*!< HSE oscillator bypassed with external clock */
} RCM_HSE_T;
/**
* @brief LSE enum
*/
typedef enum
{
RCM_LSE_CLOSE = 0x00, /*!< turn OFF the LSE oscillator */
RCM_LSE_OPEN = 0x01, /*!< turn ON the LSE oscillator */
RCM_LSE_BYPASS = 0x05, /*!< LSE oscillator bypassed with external clock */
} RCM_LSE_T;
/**
* @brief LSE_Drive enum
*/
typedef enum
{
RCM_LSE_DRIVE_Low = 0x00, /*!< LSE oscillator low drive capability */
RCM_LSE_DRIVE_MediumLow, /*!< LSE oscillator medium low drive capability */
RCM_LSE_DRIVE_MediumHigh, /*!< LSE oscillator medium high drive capability */
RCM_LSE_DRIVE_High, /*!< LSE oscillator high drive capability */
} RCM_LSE_DRIVE_T;
/**
* @brief System clock select
*/
typedef enum
{
RCM_PLL_SEL_HSI_DIV2, /*!< HSI clock divided by 2 selected as PLL clock source */
RCM_PLL_SEL_HSI, /*!< HSI clock selected as PLL clock entry, only for APM32F072 and APM32F091 devices */
RCM_PLL_SEL_HSE, /*!< HSE/CLKDIV1 selected as PLL clock entry */
RCM_PLL_SEL_HSI48 /*!< HSI48 oscillator clock selected as PLL clock source, only for APM32F072 and APM32F091 devices */
} RCM_PLL_SEL_T;
/**
* @brief PLL multiplication factor
*/
typedef enum
{
RCM_PLLMF_2, /*!< specifies the PLLMULCFG clock multiple factor as 2 */
RCM_PLLMF_3, /*!< specifies the PLLMULCFG clock multiple factor as 3 */
RCM_PLLMF_4, /*!< specifies the PLLMULCFG clock multiple factor as 4 */
RCM_PLLMF_5, /*!< specifies the PLLMULCFG clock multiple factor as 5 */
RCM_PLLMF_6, /*!< specifies the PLLMULCFG clock multiple factor as 6 */
RCM_PLLMF_7, /*!< specifies the PLLMULCFG clock multiple factor as 7 */
RCM_PLLMF_8, /*!< specifies the PLLMULCFG clock multiple factor as 8 */
RCM_PLLMF_9, /*!< specifies the PLLMULCFG clock multiple factor as 9 */
RCM_PLLMF_10, /*!< specifies the PLLMULCFG clock multiple factor as 10 */
RCM_PLLMF_11, /*!< specifies the PLLMULCFG clock multiple factor as 11 */
RCM_PLLMF_12, /*!< specifies the PLLMULCFG clock multiple factor as 12 */
RCM_PLLMF_13, /*!< specifies the PLLMULCFG clock multiple factor as 13 */
RCM_PLLMF_14, /*!< specifies the PLLMULCFG clock multiple factor as 14 */
RCM_PLLMF_15, /*!< specifies the PLLMULCFG clock multiple factor as 15 */
RCM_PLLMF_16, /*!< specifies the PLLMULCFG clock multiple factor as 16 */
} RCM_PLLMF_T;
/**
* @brief RCM clock division
*/
typedef enum
{
RCM_CLK_DIV_1, /*!< specifies the PLLDIVCFG clock division factor as 1 */
RCM_CLK_DIV_2, /*!< specifies the PLLDIVCFG clock division factor as 2 */
RCM_CLK_DIV_3, /*!< specifies the PLLDIVCFG clock division factor as 3 */
RCM_CLK_DIV_4, /*!< specifies the PLLDIVCFG clock division factor as 4 */
RCM_CLK_DIV_5, /*!< specifies the PLLDIVCFG clock division factor as 5 */
RCM_CLK_DIV_6, /*!< specifies the PLLDIVCFG clock division factor as 6 */
RCM_CLK_DIV_7, /*!< specifies the PLLDIVCFG clock division factor as 7 */
RCM_CLK_DIV_8, /*!< specifies the PLLDIVCFG clock division factor as 8 */
RCM_CLK_DIV_9, /*!< specifies the PLLDIVCFG clock division factor as 9 */
RCM_CLK_DIV_10, /*!< specifies the PLLDIVCFG clock division factor as 10 */
RCM_CLK_DIV_11, /*!< specifies the PLLDIVCFG clock division factor as 11 */
RCM_CLK_DIV_12, /*!< specifies the PLLDIVCFG clock division factor as 12 */
RCM_CLK_DIV_13, /*!< specifies the PLLDIVCFG clock division factor as 13 */
RCM_CLK_DIV_14, /*!< specifies the PLLDIVCFG clock division factor as 14 */
RCM_CLK_DIV_15, /*!< specifies the PLLDIVCFG clock division factor as 15 */
RCM_CLK_DIV_16, /*!< specifies the PLLDIVCFG clock division factor as 16 */
} RCM_CLK_DIV_T;
/**
* @brief Clock output control
*/
typedef enum
{
RCM_COC_NO_CLOCK, /*!< No clock selected */
RCM_COC_HSI14, /*!< HSI14 oscillator clock selected */
RCM_COC_LSI, /*!< LSI oscillator clock selected */
RCM_COC_LSE, /*!< LSE oscillator clock selected */
RCM_COC_SYSCLK, /*!< System clock selected */
RCM_COC_HSI, /*!< HSI oscillator clock selected */
RCM_COC_HSE, /*!< HSE oscillator clock selected */
RCM_COC_PLLCLK_DIV_2, /*!< PLL clock divided by 2 selected */
RCM_COC_HSI48, /*!< HSI48 oscillator clock selected, only for APM32F072 and APM32F091 devices */
RCM_COC_PLLCLK /*!< PLL clock selected */
} RCM_COCCLK_T;
/**
* @brief Clock output division
*/
typedef enum
{
RCM_COC_DIV_1, /*!< MCOSEL clock is divided by 1 */
RCM_COC_DIV_2, /*!< MCOSEL clock is divided by 2 */
RCM_COC_DIV_4, /*!< MCOSEL clock is divided by 4 */
RCM_COC_DIV_8, /*!< MCOSEL clock is divided by 8 */
RCM_COC_DIV_16, /*!< MCOSEL clock is divided by 16 */
RCM_COC_DIV_32, /*!< MCOSEL clock is divided by 32 */
RCM_COC_DIV_64, /*!< MCOSEL clock is divided by 64 */
RCM_COC_DIV_128, /*!< MCOSEL clock is divided by 128 */
} RCM_COCPRE_T;
/**
* @brief System clock select
*/
typedef enum
{
RCM_SYSCLK_SEL_HSI, /*!< HSI selected as system clock source */
RCM_SYSCLK_SEL_HSE, /*!< HSE selected as system clock source */
RCM_SYSCLK_SEL_PLL, /*!< PLL selected as system clock source */
RCM_SYSCLK_SEL_HSI48, /*!< HSI48 selected as system clock source, only for APM32F072 and APM32F091 devices */
} RCM_SYSCLK_SEL_T;
/**
* @brief AHB divider Number
*/
typedef enum
{
RCM_SYSCLK_DIV_1 = 7, /*!< AHB clock = SYSCLK */
RCM_SYSCLK_DIV_2, /*!< AHB clock = SYSCLK/2 */
RCM_SYSCLK_DIV_4, /*!< AHB clock = SYSCLK/4 */
RCM_SYSCLK_DIV_8, /*!< AHB clock = SYSCLK/8 */
RCM_SYSCLK_DIV_16, /*!< AHB clock = SYSCLK/16 */
RCM_SYSCLK_DIV_64, /*!< AHB clock = SYSCLK/64 */
RCM_SYSCLK_DIV_128, /*!< AHB clock = SYSCLK/128 */
RCM_SYSCLK_DIV_256, /*!< AHB clock = SYSCLK/256 */
RCM_SYSCLK_DIV_512, /*!< AHB clock = SYSCLK/512 */
} RCM_AHBDIV_T;
/**
* @brief APB divider Number
*/
typedef enum
{
RCM_HCLK_DIV_1 = 3, /*!< APB clock = HCLK */
RCM_HCLK_DIV_2, /*!< APB clock = HCLK/2 */
RCM_HCLK_DIV_4, /*!< APB clock = HCLK/4 */
RCM_HCLK_DIV_8, /*!< APB clock = HCLK/8 */
RCM_HCLK_DIV_16 /*!< APB clock = HCLK/16 */
} RCM_APBDIV_T;
/**
* @brief CEC divider Number
*/
typedef enum
{
RCM_CECCLK_HSI_DIV_224, /*!< CEC clock = HSI/244 (32768Hz) */
RCM_CECCLK_LSI_DIV, /*!< CEC clock = LSI */
} RCM_CECCLK_T;
/**
* @brief I2C clock source selectio
*/
typedef enum
{
RCM_I2C1CLK_HSI, /*!< I2C1 clock = HSI */
RCM_I2C1CLK_SYSCLK, /*!< I2C1 clock = System Clock */
} RCM_I2CCLK_T;
/**
* @brief USART clock source selectio
*/
typedef enum
{
RCM_USART1CLK_PCLK = ((uint32_t)0x00010000), /*!< USART1 clock = APB Clock (PCLK) */
RCM_USART1CLK_SYSCLK = ((uint32_t)0x00010001), /*!< USART1 clock = System Clock */
RCM_USART1CLK_LSE = ((uint32_t)0x00010002), /*!< USART1 clock = LSE Clock */
RCM_USART1CLK_HSI = ((uint32_t)0x00010003), /*!< USART1 clock = HSI Clock */
RCM_USART2CLK_PCLK = ((uint32_t)0x00020000), /*!< USART2 clock = APB Clock (PCLK), only for APM32F072 and APM32F091 devices */
RCM_USART2CLK_SYSCLK = ((uint32_t)0x00020001), /*!< USART2 clock = System Clock, only for APM32F072 and APM32F091 devices */
RCM_USART2CLK_LSE = ((uint32_t)0x00020002), /*!< USART2 clock = LSE Clock, only for APM32F072 and APM32F091 devices */
RCM_USART2CLK_HSI = ((uint32_t)0x00020003), /*!< USART2 clock = HSI Clock, only for APM32F072 and APM32F091 devices */
RCM_USART3CLK_PCLK = ((uint32_t)0x00040000), /*!< USART3 clock = APB Clock (PCLK), only for APM32F091 devices */
RCM_USART3CLK_SYSCLK = ((uint32_t)0x00040001), /*!< USART3 clock = System Clock, only for APM32F091 devices */
RCM_USART3CLK_LSE = ((uint32_t)0x00040002), /*!< USART3 clock = LSE Clock, only for APM32F091 devices */
RCM_USART3CLK_HSI = ((uint32_t)0x00040003), /*!< USART3 clock = HSI Clock, only for APM32F091 devices */
} RCM_USARTCLK_T;
/**
* @brief USB clock source selection
*/
typedef enum
{
RCM_USBCLK_HSI48, /*!<hsi48 selected as USB clock, only for APM32F072 devices */
RCM_USBCLK_PLLCLK, /*!<PLL clock selected as USB clock, only for APM32F072 devices */
} RCM_USBCLK_T;
/**
* @brief RTC clock select
*/
typedef enum
{
RCM_RTCCLK_LSE = 0X01, /*!< LSE selected as RTC clock */
RCM_RTCCLK_LSI, /*!< LSI selected as RTC clock */
RCM_RTCCLK_HSE_DIV_32 /*!< HSE divided by 32 selected as RTC clock */
} RCM_RTCCLK_T;
/**
* @brief AHB peripheral
*/
typedef enum
{
RCM_AHB_PERIPH_DMA1 = BIT0, /*!< DMA1 peripheral clock */
RCM_AHB_PERIPH_DMA2 = BIT1, /*!< DMA2 peripheral clock */
RCM_AHB_PERIPH_SRAM = BIT2, /*!< SRAM peripheral clock */
RCM_AHB_PERIPH_FPU = BIT4, /*!< FMC peripheral clock */
RCM_AHB_PERIPH_CRC = BIT6, /*!< CRC peripheral clock */
RCM_AHB_PERIPH_GPIOA = BIT17, /*!< GPIOA peripheral clock */
RCM_AHB_PERIPH_GPIOB = BIT18, /*!< GPIOB peripheral clock */
RCM_AHB_PERIPH_GPIOC = BIT19, /*!< GPIOC peripheral clock */
RCM_AHB_PERIPH_GPIOD = BIT20, /*!< GPIOD peripheral clock */
RCM_AHB_PERIPH_GPIOE = BIT21, /*!< GPIOE peripheral clock, only for APM32F072 and APM32F091 devices */
RCM_AHB_PERIPH_GPIOF = BIT22, /*!< GPIOF peripheral clock */
RCM_AHB_PERIPH_TSC = BIT24, /*!< TSC peripheral clock */
} RCM_AHB_PERIPH_T;
/**
* @brief AHB2 peripheral
*/
typedef enum
{
RCM_APB2_PERIPH_SYSCFG = BIT0, /*!< SYSCFG peripheral clock */
RCM_APB2_PERIPH_USART6 = BIT5, /*!< USART6 peripheral clock */
RCM_APB2_PERIPH_USART7 = BIT6, /*!< USART7 peripheral clock */
RCM_APB2_PERIPH_USART8 = BIT7, /*!< USART8 peripheral clock */
RCM_APB2_PERIPH_ADC1 = BIT9, /*!< ADC1 peripheral clock */
RCM_APB2_PERIPH_TMR1 = BIT11, /*!< TMR1 peripheral clock */
RCM_APB2_PERIPH_SPI1 = BIT12, /*!< SPI1 peripheral clock */
RCM_APB2_PERIPH_USART1 = BIT14, /*!< USART1 peripheral clock */
RCM_APB2_PERIPH_TMR15 = BIT16, /*!< TMR15 peripheral clock */
RCM_APB2_PERIPH_TMR16 = BIT17, /*!< TMR16 peripheral clock */
RCM_APB2_PERIPH_TMR17 = BIT18, /*!< TMR17 peripheral clock */
RCM_APB2_PERIPH_DBGMCU = BIT22, /*!< DBGMCU peripheral clock */
} RCM_APB2_PERIPH_T;
/**
* @brief AHB1 peripheral
*/
typedef enum
{
RCM_APB1_PERIPH_TMR2 = BIT0, /*!< TMR2 peripheral clock, only for APM32F072 and APM32F091 devices */
RCM_APB1_PERIPH_TMR3 = BIT1, /*!< TMR3 peripheral clock */
RCM_APB1_PERIPH_TMR6 = BIT4, /*!< TMR6 peripheral clock */
RCM_APB1_PERIPH_TMR7 = BIT5, /*!< TMR7 peripheral clock, only for APM32F072 and APM32F091 devices */
RCM_APB1_PERIPH_TMR14 = BIT8, /*!< TMR14 peripheral clock */
RCM_APB1_PERIPH_WWDT = BIT11, /*!< WWDT peripheral clock */
RCM_APB1_PERIPH_SPI2 = BIT14, /*!< SPI2 peripheral clock */
RCM_APB1_PERIPH_USART2 = BIT17, /*!< USART2 peripheral clock */
RCM_APB1_PERIPH_USART3 = BIT18, /*!< USART3 peripheral clock, only for APM32F072 and APM32F091 devices */
RCM_APB1_PERIPH_USART4 = BIT19, /*!< USART4 peripheral clock, only for APM32F072 and APM32F091 devices */
RCM_APB1_PERIPH_USART5 = BIT20, /*!< USART5 peripheral clock, only for APM32F091 devices */
RCM_APB1_PERIPH_I2C1 = BIT21, /*!< I2C1 peripheral clock */
RCM_APB1_PERIPH_I2C2 = BIT22, /*!< I2C2 peripheral clock */
RCM_APB1_PERIPH_USB = BIT23, /*!< USB peripheral clock only for APM32F072 devices */
RCM_APB1_PERIPH_CAN = BIT25, /*!< CAN peripheral clock, only for APM32F072 and APM32F091 devices */
RCM_APB1_PERIPH_CRS = BIT27, /*!< CRS peripheral clock, only for APM32F072 and APM32F091 devices */
RCM_APB1_PERIPH_PMU = BIT28, /*!< PMU peripheral clock */
RCM_APB1_PERIPH_DAC = BIT29, /*!< DAC peripheral clock, only for APM32F072 and APM32F091 devices */
RCM_APB1_PERIPH_CEC = BIT30, /*!< CEC peripheral clock, only for APM32F072 and APM32F091 devices */
} RCM_APB1_PERIPH_T;
/**
* @brief RCM Interrupt Source
*/
typedef enum
{
RCM_INT_LSIRDY = BIT0, /*!< LSI ready interrupt */
RCM_INT_LSERDY = BIT1, /*!< LSE ready interrupt */
RCM_INT_HSIRDY = BIT2, /*!< HSI ready interrupt */
RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */
RCM_INT_PLLRDY = BIT4, /*!< PLL ready interrupt */
RCM_INT_HSI14RDY = BIT5, /*!< HSI14 ready interrupt */
RCM_INT_HSI48RDY = BIT6, /*!< HSI48 ready interrupt (Only for APM32F072 and APM32F091 devices) */
RCM_INT_CSS = BIT7 /*!< Clock security system interrupt */
} RCM_INT_T;
/**
* @brief RCM FLAG define
*/
typedef enum
{
RCM_FLAG_HSIRDY = 0x001, /*!< HSI Ready Flag */
RCM_FLAG_HSERDY = 0x011, /*!< HSE Ready Flag */
RCM_FLAG_PLLRDY = 0x019, /*!< PLL Ready Flag */
RCM_FLAG_LSERDY = 0x101, /*!< LSE Ready Flag */
RCM_FLAG_LSIRDY = 0x201, /*!< LSI Ready Flag */
RCM_FLAG_V18PRRST = 0x217, /*!< Software reset flag */
RCM_FLAG_OBRST = 0x219, /*!< Option byte loader reset flag */
RCM_FLAG_PINRST = 0x21A, /*!< PIN reset flag */
RCM_FLAG_PWRRST = 0x21B, /*!< POR/PDR reset flag */
RCM_FLAG_SWRST = 0x21C, /*!< Software reset flag */
RCM_FLAG_IWDTRST = 0x21D, /*!< Independent watchdog reset flag */
RCM_FLAG_WWDTRST = 0x21E, /*!< Window watchdog reset flag */
RCM_FLAG_LPRRST = 0x21F, /*!< Low-power reset flag */
RCM_FLAG_HSI14RDY = 0x301, /*!< HSI14 Ready Flag */
RCM_FLAG_HSI48RDY = 0x311, /*!< HSI48 Ready Flag (Only for APM32F072 devices and APM32F091 devices) */
} RCM_FLAG_T;
/**@} end of group RCM_Enumerations*/
/** @defgroup RCM_Structures Structures
@{
*/
/**@} end of group RCM_Structures*/
/** @defgroup RCM_Variables Variables
@{
*/
/**@} end of group RCM_Variables*/
/** @defgroup RCM_Fuctions Fuctions
@{
*/
/** Function description */
void RCM_Reset(void);
void RCM_ConfigHSE(RCM_HSE_T state);
uint8_t RCM_WaitHSEReady(void);
void RCM_SetHSITrim(uint8_t HSITrim);
void RCM_EnableHSI(void);
void RCM_DisableHSI(void);
void RCM_SetHSI14Trim(uint8_t HSI14Trim);
void RCM_EnableHSI14(void);
void RCM_DisableHSI14(void);
void RCM_EnableHSI14ADC(void);
void RCM_DisableHSI14ADC(void);
void RCM_ConfigLSE(RCM_LSE_T state);
void RCM_ConfigDriveLSE(RCM_LSE_DRIVE_T state);
void RCM_EnableLSI(void);
void RCM_DisableLSI(void);
void RCM_ConfigPLL(RCM_PLL_SEL_T pllSelect, RCM_PLLMF_T pllMf);
void RCM_EnablePLL(void);
void RCM_DisablePLL(void);
void RCM_EnableHSI48(void); /*!< Only for APM32F072 and APM32F091 devices */
void RCM_DisableHSI48(void); /*!< Only for APM32F072 and APM32F091 devices */
uint32_t RCM_ReadHSI48CalibrationValue(void); /*!< Only for APM32F072 and APM32F091 devices */
void RCM_ConfigCLKDIV(RCM_CLK_DIV_T state);
void RCM_EnableCCS(void);
void RCM_DisableCCS(void);
#if defined (APM32F030) || defined (APM32F051)
void RCM_ConfigCOC(RCM_COCCLK_T cocClock);
#else
void RCM_ConfigCOC(RCM_COCCLK_T cocClock, RCM_COCPRE_T divided);
#endif
void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect);
RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void);
void RCM_ConfigAHB(RCM_AHBDIV_T AHBDiv);
void RCM_ConfigAPB(RCM_APBDIV_T APBDiv);
void RCM_ConfigCECCLK(RCM_CECCLK_T CECClk);
void RCM_ConfigI2CCLK(RCM_I2CCLK_T I2CCLk);
void RCM_ConfigUSARTCLK(RCM_USARTCLK_T USARTClk);
void RCM_ConfigUSBCLK(RCM_USBCLK_T USBClk); /*!< Only for APM32F072 devices */
uint32_t RCM_ReadSYSCLKFreq(void);
uint32_t RCM_ReadHCLKFreq(void);
uint32_t RCM_ReadPCLKFreq(void);
uint32_t RCM_ReadADCCLKFreq(void);
uint32_t RCM_ReadCECCLKFreq(void);
uint32_t RCM_ReadI2C1CLKFreq(void);
uint32_t RCM_ReadUSART1CLKFreq(void);
uint32_t RCM_ReadUSART2CLKFreq(void);
uint32_t RCM_ReadUSBCLKFreq(void);
void RCM_ConfigRTCCLK(RCM_RTCCLK_T RTCClk);
void RCM_EnableRTCCLK(void);
void RCM_DisableRTCCLK(void);
void RCM_EnableBackupReset(void);
void RCM_DisableBackupReset(void);
void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph);
void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph);
void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph);
void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph);
void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph);
void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph);
void RCM_EnableAHBPeriphReset(uint32_t AHBPeriph);
void RCM_DisableAHBPeriphReset(uint32_t AHBPeriph);
void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph);
void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph);
void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph);
void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph);
void RCM_EnableInterrupt(uint8_t interrupt);
void RCM_DisableInterrupt(uint8_t interrupt);
uint16_t RCM_ReadStatusFlag(RCM_FLAG_T flag);
void RCM_ClearStatusFlag(void);
uint8_t RCM_ReadIntFlag(RCM_INT_T flag);
void RCM_ClearIntFlag(uint8_t flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_RCM_H */
/**@} end of group RCM_Functions*/
/**@} end of group RCM_Driver*/
/**@} end of group APM32F0xx_StdPeriphDriver*/

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/*!
* @file apm32f0xx_rtc.h
*
* @brief This file contains all the functions prototypes for the RTC firmware library.
*
* @version V1.0.2
*
* @date 2022-02-21
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F0XX_RTC_H
#define __APM32F0XX_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup RTC_Driver RTC Driver
@{
*/
/** @defgroup RTC_Macros Macros
@{
*/
/**@} end of group RTC_Macros */
/** @defgroup RTC_Enumerations Enumerations
@{
*/
/**
* @brief RTC Hour Formats
*/
typedef enum
{
RTC_HourFormat_24, /*!< 24 hour/day format */
RTC_HourFormat_12 /*!< AM/PM hour format */
} RTC_HOUR_FORMAT_T;
/**
* @brief RTC Input parameter format
*/
typedef enum
{
RTC_FORMAT_BIN, /*!< Format in BIN */
RTC_FORMAT_BCD /*!< Format in BCD */
} RTC_FORMAT_T;
/**
* @brief RTC_AM_PM
*/
typedef enum
{
RTC_H12_AM, /*!< Set RTC time to AM */
RTC_H12_PM /*!< Set RTC time to PM */
} RTC_H12_T;
/**
* @brief RTC DayLightSaving
*/
typedef enum
{
RTC_DLS_SUB1H, /*!< Winter time change */
RTC_DLS_ADD1H /*!< Summer time change */
} RTC_DAYLIGHT_SAVING_T;
/**
* @brief RTC DayLightSaving
*/
typedef enum
{
RTC_SO_RESET = BIT_RESET, /*!< Reset backup value */
RTC_SO_SET = BIT_SET, /*!< Set backup value */
} RTC_STORE_OPERATION_T;
/**
* @brief RTC Output selection
*/
typedef enum
{
RTC_OPSEL_DISABLE = 0x00, /*!< output disable */
RTC_OPSEL_ALARMA = 0x01, /*!< alarma output enable */
RTC_OPSEL_WAKEUP = 0x03, /*!< Only for APM32F072 and APM32F091 devices */
} RTC_OPSEL_T;
/**
* @brief RTC Output Polarity
*/
typedef enum
{
RTC_OPP_HIGH, /*!< output polarity is high */
RTC_OPP_LOW /*!< output polarity is low */
} RTC_OPP_T;
/**
* @brief RTC Calib Output selection
*/
typedef enum
{
RTC_CALIBOUTPUT_512Hz, /*!< calib output is 512Hz */
RTC_CALIBOUTPUT_1Hz /*!< calib output is 1Hz */
} RTC_CALIB_OUTPUT_T;
/**
* @brief RTC Smooth calib period
*/
typedef enum
{
RTC_SCP_16SEC, /*!<The smooth calibration periode is 16 */
RTC_SCP_8SEC /*!<The smooth calibration periode is 8 */
} RTC_SCP_T;
/**
* @brief RTC Smooth calib period
*/
typedef enum
{
RTC_SCPP_RESET, /*!< Add one RTCCLK puls every 2**11 pulses */
RTC_SCPP_SET /*!< No RTCCLK pulses are added */
} RTC_SCPP_T;
/**
* @brief RTC Time Stamp Edges
*/
typedef enum
{
RTC_TIME_STAMPEDGE_RISING, /*!< event occurs on the rising edge */
RTC_TIME_STAMPEDGE_FALLING /*!< event occurs on the falling edge */
} RTC_TIMESTAMP_EDGE_T;
/**
* @brief RTC Tamper Trigger
*/
typedef enum
{
RTC_TAMPER_TRIGGER_RISINGEDGE = 0x00, /*!< Rising Edge of the tamper pin causes tamper event */
RTC_TAMPER_TRIGGER_FALLINGEDGE = 0x01, /*!< Falling Edge of the tamper pin causes tamper event */
RTC_TAMPER_TRIGGER_LOWLEVEL = 0x00, /*!< Low Level of the tamper pin causes tamper event */
RTC_TAMPER_TRIGGER_HIGHLEVEL = 0x01 /*!< High Level of the tamper pin causes tamper event */
} RTC_TAMPER_TRIGGER_T;
/**
* @brief RTC Tamper Pins
*/
typedef enum
{
RTC_TAMPER_1, /*!< Select Tamper 1 */
RTC_TAMPER_2, /*!< Select Tamper 1 */
RTC_TAMPER_3 /*!< Only for APM32F072 and APM32F091 devices */
} RTC_TAMPER_T;
/**
* @brief Tampers Sampling Frequency
*/
typedef enum
{
RTC_TAMPER_FILTER_DISABLE, /*!< Tamper filter is disabled */
RTC_TAMPER_FILTER_2SAMPLE, /*!< Tamper is activated after 2 consecutive samples at the active level */
RTC_TAMPER_FILTER_4SAMPLE, /*!< Tamper is activated after 4 consecutive samples at the active level */
RTC_TAMPER_FILTER_8SAMPLE /*!< Tamper is activated after 8 consecutive samples at the active level */
} RTC_TAMPER_FILTER_T;
/**
* @brief Tampers Sampling Frequency
*/
typedef enum
{
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768, /*!< Tampers Sampling Frequency = RTC_CLK / 32768 */
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384, /*!< Tampers Sampling Frequency = RTC_CLK / 16384 */
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192, /*!< Tampers Sampling Frequency = RTC_CLK / 8192 */
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096, /*!< Tampers Sampling Frequency = RTC_CLK / 4096 */
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048, /*!< Tampers Sampling Frequency = RTC_CLK / 2048 */
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024, /*!< Tampers Sampling Frequency = RTC_CLK / 1024 */
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512, /*!< Tampers Sampling Frequency = RTC_CLK / 512 */
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 /*!< Tampers Sampling Frequency = RTC_CLK / 256 */
} RTC_TAMPER_SAMPLING_FREQ_T;
/**
* @brief Precharge Duration
*/
typedef enum
{
RTC_PRECHARGEDURATION_1RTCCLK, /*!< Duration is 1 RTCCLK cycle */
RTC_PRECHARGEDURATION_2RTCCLK, /*!< Duration is 2 RTCCLK cycle */
RTC_PRECHARGEDURATION_4RTCCLK, /*!< Duration is 4 RTCCLK cycle */
RTC_PRECHARGEDURATION_8RTCCLK /*!< Duration is 8 RTCCLK cycle */
} RTC_PRECHARGE_DURATION_T;
/**
* @brief RTC Add 1 Second Parameter
*/
typedef enum
{
RTC_SHIFTADD1S_RESET, /*!< No effect */
RTC_SHIFTADD1S_SET /*!< Add one second to the clock calendar */
} RTC_SHIFT_ADD1S_T;
/**
* @brief
*/
typedef enum
{
RTC_OPENDRAIN, /*!< RTC Output is configured in Open Drain mode */
RTC_PUSHPULL /*!< RTC Output is configured in Push Pull mode */
} RTC_OUTPUT_T;
/**
* @brief RTC AlarmDateWeekDay
*/
typedef enum
{
RTC_WEEKDAY_SEL_DATE, /*!< Select DAYU to represent the date */
RTC_WEEKDAY_SEL_WEEKDAY /*!< Select DAYU to represent the weekday */
} RTC_WEEKDAY_SEL_T;
/**
* @brief RTC Interrupts Soure
*/
typedef enum
{
RTC_INT_ALR = 0x00001000, /*!< ALRMA A interrupt mask */
RTC_INT_WT = 0x00004000, /*!< WakeUp Timer interrupt mask (It's only for APM32F091 devices) */
RTC_INT_TS = 0x00008000, /*!< Time Stamp interrupt mask */
RTC_INT_TAMP = 0x00000004, /*!< Tamper event interrupt mask */
} RTC_INT_T;
/**
* @brief RTC Interrupts Flag
*/
typedef enum
{
RTC_INT_FLAG_ALR = 0x00001000, /*!< ALRMA interrupt */
RTC_INT_FLAG_WT = 0x00004000, /*!< WakeUp Timer (It's only for APM32F072 and APM32F091 devices) */
RTC_INT_FLAG_TS = 0x00008000, /*!< Time Stamp interrupt mask */
RTC_INT_FLAG_TAMP1 = 0x00020004, /*!< Tamper1 event interrupt mask */
RTC_INT_FLAG_TAMP2 = 0x00040004, /*!< Tamper2 event interrupt mask */
RTC_INT_FLAG_TAMP3 = 0x00080004, /*!< Tamper3 event interrupt mask, only for APM32F072 and APM32F091 device */
} RTC_INT_FLAG_T;
/**
* @brief RTC flag
*/
typedef enum
{
RTC_FLAG_AWF = BIT0, /*!< Alarm Write Flag */
RTC_FLAG_WTWF = BIT2, /*!< Wakeup Timer Write Flag, Only for APM32F072 and APM32F091 devices */
RTC_FLAG_SOPF = BIT3, /*!< Shift Operation Pending Flag */
RTC_FLAG_ISF = BIT4, /*!< Initialization State Flag */
RTC_FLAG_RSF = BIT5, /*!< Registers Synchronization Flag */
RTC_FLAG_INTF = BIT6, /*!< Register Initialization Flag */
RTC_FLAG_ALRF = BIT8, /*!< Alarm Match Flag */
RTC_FLAG_WTF = BIT10, /*!< Wakeup Timer Flag, only for APM32F072 and APM32F091 devices */
RTC_FLAG_TSF = BIT11, /*!< Time Stamp Flag */
RTC_FLAG_TSOF = BIT12, /*!< Time Stamp Overflow Flag */
RTC_FLAG_TP1F = BIT13, /*!< Tamper 1 event Detection Flag */
RTC_FLAG_TP2F = BIT14, /*!< Tamper 2 event Detection Flag */
RTC_FLAG_TP3F = BIT15, /*!< Tamper 3 event Detection Flag, only for APM32F072 and APM32F091 devices */
RTC_FLAG_RPF = BIT16, /*!< Recalibration Pending Flag */
} RTC_FLAG_T;
/**
* @brief RTC_Backup
*/
typedef enum
{
RTC_BAKP_DATA0, /*!< set Backup data0 */
RTC_BAKP_DATA1, /*!< set Backup data1 */
RTC_BAKP_DATA2, /*!< set Backup data2 */
RTC_BAKP_DATA3, /*!< set Backup data3 */
RTC_BAKP_DATA4 /*!< set Backup data4 */
} RTC_BAKP_DATA_T;
/**
* @brief RTC_AlarmMask
*/
typedef enum
{
RTC_MASK_NONE = 0x00000000, /*!< No mask */
RTC_MASK_DATEWEEK = (int)0x80000000, /*!< Dateweek mask */
RTC_MASK_HOURS = 0x00800000, /*!< Hours mask */
RTC_MASK_MINUTES = 0x00008000, /*!< Minutes mask */
RTC_MASK_SECONDS = 0x00000080, /*!< Seconds mask */
RTC_MASK_ALL = (int)0x80808080, /*!< ALL mask */
} RTC_MASK_T;
/**
* @brief RTC Wakeup clock select (only APM32F072 and APM32F091 devices)
*/
typedef enum
{
RTC_WAKEUP_CLOCK_RTCDIV16 = 0x00, /*!< Wakeup Clock select to RTC/16 */
RTC_WAKEUP_CLOCK_RTCDIV8, /*!< Wakeup Clock select to RTC/8 */
RTC_WAKEUP_CLOCK_RTCDIV4, /*!< Wakeup Clock select to RTC/4 */
RTC_WAKEUP_CLOCK_RTCDIV2, /*!< Wakeup Clock select to RTC/2 */
RTC_WAKEUP_CLOCK_CK_SPRE_16B, /*!< Wakeup Clock select to clk_spre */
RTC_WAKEUP_CLOCK_CK_SPRE_17B, /*!< Wakeup Clock select to clk_spre */
} RTC_WAKEUP_CLOCK_T;
/**@} end of group RTC_Enumerations*/
/** @addtogroup RTC_Macros Macros
@{
*/
/** Macros description */
#define RTC_INITMODE_TIMEOUT ((uint32_t) 0x00004000)
#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)
#define RTC_RECALPF_TIMEOUT ((uint32_t) 0x00001000)
#define RTC_SHPF_TIMEOUT ((uint32_t) 0x00001000)
#define RTC_CTRL_INT ((uint32_t) 0x0000D000)
#define RTC_TAFCFG_INT ((uint32_t) 0x00000004)
#define RTC_CTRL_INT ((uint32_t) 0x0000D000)
#define RTC_TAFCFG_INT ((uint32_t) 0x00000004)
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
#define RTC_MONTH_APRIL ((uint8_t)0x04)
#define RTC_MONTH_MAY ((uint8_t)0x05)
#define RTC_MONTH_JUNE ((uint8_t)0x06)
#define RTC_MONTH_JULY ((uint8_t)0x07)
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define RTC_MONTH_OCTOBER ((uint8_t)0x0A)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x0B)
#define RTC_MONTH_DECEMBER ((uint8_t)0x0C)
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
/**@} end of group RTC_Macros*/
/** @defgroup RTC_Enumerations Enumerations
@{
*/
/**@} end of group RTC_Enumerations */
/** @defgroup RTC_Structures Structures
@{
*/
/**
* @brief RTC Init structures definition
*/
typedef struct
{
RTC_HOUR_FORMAT_T format; /*!< RTC hour formats selection */
uint32_t AsynchPrediv; /*!< Asynchronous prescaler coefficient setting */
uint32_t SynchPrediv; /*!< Synchronous prescaler coefficient setting */
} RTC_Config_T;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t hours; /*!< Set hours of RTC time */
uint8_t minutes; /*!< Set minutes of RTC time */
uint8_t seconds; /*!< Set seconds of RTC time */
uint8_t H12; /*!< Set RTC time to AM or PM */
} RTC_TIME_T;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t weekday; /*!< Set weekday of RTC date */
uint8_t month; /*!< Set month of RTC date */
uint8_t date; /*!< Set data of RTC date */
uint8_t year; /*!< Set year of RTC date */
} RTC_DATE_T;
/**
* @brief RTC ALRMA structure definition
*/
typedef struct
{
RTC_TIME_T time; /*!< Set RTC time */
uint32_t AlarmMask; /*!< Set alarm mask */
RTC_WEEKDAY_SEL_T AlarmDateWeekDaySel; /*!< Set weekday's DAYU of alarm date */
uint8_t AlarmDateWeekDay; /*!< Set weekday of alarm date */
} RTC_ALARM_T;
/**@} end of group RTC_Structures*/
/** @defgroup RTC_Variables Variables
@{
*/
/**@} end of group RTC_Variables */
/** @defgroup RTC_Fuctions Fuctions
@{
*/
/** Initialization and Configuration functions */
uint8_t RTC_Reset(void);
uint8_t RTC_Config(RTC_Config_T* Struct);
void RTC_ConfigStructInit(RTC_Config_T* Struct);
void RTC_EnableWriteProtection(void);
void RTC_DisableWriteProtection(void);
uint8_t RTC_EnableInit(void);
void RTC_DisableInit(void);
uint8_t RTC_WaitForSynchro(void);
uint8_t RTC_EnableRefClock(void);
uint8_t RTC_DisableRefClock(void);
void RTC_EnableBypassShadow(void);
void RTC_DisableBypassShadow(void);
/** Time and Date configuration functions */
uint8_t RTC_ConfigTime(RTC_FORMAT_T format, RTC_TIME_T* timeStruct);
void RTC_ConfigTimeStructInit(RTC_TIME_T* timeStruct);
void RTC_ReadTime(RTC_FORMAT_T format, RTC_TIME_T* timeStruct);
uint32_t RTC_ReadSubSecond(void);
uint8_t RTC_ConfigDate(RTC_FORMAT_T format, RTC_DATE_T* dateStruct);
void RTC_ConfigDateStructInit(RTC_DATE_T* dateStruct);
void RTC_ReadDate(RTC_FORMAT_T format, RTC_DATE_T* dateStruct);
/** Alarms (ALRMA A) configuration functions */
void RTC_ConfigAlarm(RTC_FORMAT_T format, RTC_ALARM_T* alarmStruct);
void RTC_ConfigAlarmStructInit(RTC_ALARM_T* alarmStruct);
void RTC_ReadAlarm(RTC_FORMAT_T format, RTC_ALARM_T* alarmStruct);
void RTC_EnableAlarm(void);
uint8_t RTC_DisableAlarm(void);
void RTC_ConfigAlarmSubSecond(uint32_t val, uint8_t mask);
uint32_t RTC_ReadAlarmSubSecond(void);
/** WakeUp Timer configuration functions */
void RTC_ConfigWakeUpClock(RTC_WAKEUP_CLOCK_T wakeUpClock); //!< Only for APM32F072 and APM32F091 devices
void RTC_SetWakeUpValue(uint32_t wakeUpValue); //!< Only for APM32F072 and APM32F091 devices
uint32_t RTC_ReadWakeUpValue(void); //!< Only for APM32F072 and APM32F091 devices
void RTC_EnableWakeUp(void); //!< Only for APM32F072 and APM32F091 devices
uint8_t RTC_DisableWakeUp(void); //!< Only for APM32F072 and APM32F091 devices
/** Daylight Saving configuration functions */
void RTC_ConfigDayLightSaving(RTC_DAYLIGHT_SAVING_T sav, RTC_STORE_OPERATION_T bit);
uint32_t RTC_ReadStoreOperation(void);
/** Output pin Configuration function */
void RTC_ConfigOutput(RTC_OPSEL_T opsel, RTC_OPP_T opp);
/** Digital Calibration configuration functions */
void RTC_EnableCalibOutput(void);
void RTC_DisableCalibOutput(void);
void RTC_ConfigCalibOutput(RTC_CALIB_OUTPUT_T calib);
uint8_t RTC_ConfigSmoothCalib(RTC_SCP_T period, RTC_SCPP_T bit, uint32_t value);
/** TimeStamp configuration functions */
void RTC_EnableTimeStamp(RTC_TIMESTAMP_EDGE_T edge);
void RTC_DisableTimeStamp(RTC_TIMESTAMP_EDGE_T edge);
void RTC_ReadTimeDate(RTC_FORMAT_T format, RTC_TIME_T* timeStruct,
RTC_DATE_T* dateStruct);
uint32_t RTC_ReadTimeStampSubSecond(void);
/** Tampers configuration functions */
void RTC_ConfigTamperTrigger(RTC_TAMPER_T tamper, RTC_TAMPER_TRIGGER_T trigger);
void RTC_EnableTamper(RTC_TAMPER_T tamper);
void RTC_DisableTamper(RTC_TAMPER_T tamper);
void RTC_ConfigFilter(RTC_TAMPER_FILTER_T filter);
void RTC_ConfigSamplingFreq(RTC_TAMPER_SAMPLING_FREQ_T freq);
void RTC_PinsPrechargeDuration(RTC_PRECHARGE_DURATION_T duration);
void RTC_EnableTDE(void);
void RTC_DisableTDE(void);
void RTC_EnablePullUp(void);
void RTC_DisablePullUp(void);
/** Backup Data Registers configuration functions */
void RTC_WriteBackup(RTC_BAKP_DATA_T backup, uint32_t data);
uint32_t RTC_ReadBackup(RTC_BAKP_DATA_T backup);
/** Output Type Config configuration functions */
void RTC_ConfigOutputType(RTC_OUTPUT_T output);
/** RTC Shift control synchonisation functions */
uint8_t RTC_ConfigSynchroShift(RTC_SHIFT_ADD1S_T add1S, uint32_t subFS);
/** Interrupts and flags management functions */
void RTC_EnableInterrupt(uint32_t interrupt);
void RTC_DisableInterrupt(uint32_t interrupt);
uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag);
void RTC_ClearStatusFlag(uint32_t flag);
uint8_t RTC_ReadIntFlag(RTC_INT_FLAG_T flag);
void RTC_ClearIntFlag(uint32_t flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_RTC_H */
/**@} end of group RTC_Functions */
/**@} end of group RTC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_spi.h
*
* @brief This file contains all the functions prototypes for the SPI firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F0XX_SPI_H
#define __APM32F0XX_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup SPI_Driver SPI Driver
@{
*/
/** @defgroup SPI_Macros Macros
@{
*/
/**@} end of group SPI_Macros */
/** @defgroup SPI_Enumerations Enumerations
@{
*/
/**
* @brief SPI data direction mode
*/
typedef enum
{
SPI_DIRECTION_2LINES_FULLDUPLEX = ((uint16_t)0x0000), /*!< Full duplex mode,in 2-line unidirectional data mode */
SPI_DIRECTION_2LINES_RXONLY = ((uint16_t)0x0400), /*!< Receiver only, in 2-line unidirectional data mode */
SPI_DIRECTION_1LINE_RX = ((uint16_t)0x8000), /*!< Receiver mode, in 1 line bidirectional data mode */
SPI_DIRECTION_1LINE_TX = ((uint16_t)0xC000), /*!< Transmit mode, in 1 line bidirectional data mode */
} SPI_DIRECTION_T;
/**
* @brief SPI mode
*/
typedef enum
{
SPI_MODE_SLAVE = ((uint8_t)0), /*!< Slave mode */
SPI_MODE_MASTER = ((uint8_t)1), /*!< Master mode */
} SPI_MODE_T;
/**
* @brief SPI data length
*/
typedef enum
{
SPI_DATA_LENGTH_4B = ((uint8_t)0x03), /*!< Set data length to 4 bits */
SPI_DATA_LENGTH_5B = ((uint8_t)0x04), /*!< Set data length to 5 bits */
SPI_DATA_LENGTH_6B = ((uint8_t)0x05), /*!< Set data length to 6 bits */
SPI_DATA_LENGTH_7B = ((uint8_t)0x06), /*!< Set data length to 7 bits */
SPI_DATA_LENGTH_8B = ((uint8_t)0x07), /*!< Set data length to 8 bits */
SPI_DATA_LENGTH_9B = ((uint8_t)0x08), /*!< Set data length to 9 bits */
SPI_DATA_LENGTH_10B = ((uint8_t)0x09), /*!< Set data length to 10 bits */
SPI_DATA_LENGTH_11B = ((uint8_t)0x0A), /*!< Set data length to 11 bits */
SPI_DATA_LENGTH_12B = ((uint8_t)0x0B), /*!< Set data length to 12 bits */
SPI_DATA_LENGTH_13B = ((uint8_t)0x0C), /*!< Set data length to 13 bits */
SPI_DATA_LENGTH_14B = ((uint8_t)0x0D), /*!< Set data length to 14 bits */
SPI_DATA_LENGTH_15B = ((uint8_t)0x0E), /*!< Set data length to 15 bits */
SPI_DATA_LENGTH_16B = ((uint8_t)0x0F), /*!< Set data length to 16 bits */
} SPI_DATA_LENGTH_T;
/**
* @brief SPI CRC length
*/
typedef enum
{
SPI_CRC_LENGTH_8B = ((uint8_t)0), /*!< 8-bit CRC length */
SPI_CRC_LENGTH_16B = ((uint8_t)1), /*!< 16-bit CRC length */
} SPI_CRC_LENGTH_T;
/**
* @brief SPI Clock Polarity
*/
typedef enum
{
SPI_CLKPOL_LOW = ((uint8_t)0), /*!< Clock Polarity low */
SPI_CLKPOL_HIGH = ((uint8_t)1), /*!< Clock Polarity high */
} SPI_CLKPOL_T;
/**
* @brief SPI Clock Phase
*/
typedef enum
{
SPI_CLKPHA_1EDGE = ((uint8_t)0), /*!< 1 edge clock phase */
SPI_CLKPHA_2EDGE = ((uint8_t)1), /*!< 2 edge clock phase */
} SPI_CLKPHA_T;
/**
* @brief Software slave control
*/
typedef enum
{
SPI_SSC_DISABLE = ((uint8_t)0), //!< Disable software select slave */
SPI_SSC_ENABLE = ((uint8_t)1), //!< Enable software select slave */
} SPI_SSC_T;
/**
* @brief SPI BaudRate divider
*/
typedef enum
{
SPI_BAUDRATE_DIV_2 = ((uint8_t)0), //!< Baud rate divider is 2 */
SPI_BAUDRATE_DIV_4 = ((uint8_t)1), //!< Baud rate divider is 4 */
SPI_BAUDRATE_DIV_8 = ((uint8_t)2), //!< Baud rate divider is 8 */
SPI_BAUDRATE_DIV_16 = ((uint8_t)3), //!< Baud rate divider is 16 */
SPI_BAUDRATE_DIV_32 = ((uint8_t)4), //!< Baud rate divider is 32 */
SPI_BAUDRATE_DIV_64 = ((uint8_t)5), //!< Baud rate divider is 64 */
SPI_BAUDRATE_DIV_128 = ((uint8_t)6), //!< Baud rate divider is 128 */
SPI_BAUDRATE_DIV_256 = ((uint8_t)7), //!< Baud rate divider is 256 */
} SPI_BAUDRATE_DIV_T;
/**
* @brief MSB or LSB is transmitted/received first
*/
typedef enum
{
SPI_FIRST_BIT_MSB = ((uint8_t)0), //!< First bit is MSB */
SPI_FIRST_BIT_LSB = ((uint8_t)1), //!< First bit is LSB */
} SPI_FIRST_BIT_T;
/**
* @brief SPI FIFO reception threshold
*/
typedef enum
{
SPI_RXFIFO_HALF = ((uint8_t)0), //!< FIFO level is greater than or equal to 1/2 (16-bit) */
SPI_RXFIFO_QUARTER = ((uint8_t)1), //!< FIFO level is greater than or equal to 1/4 (8-bit) */
} SPI_RXFIFO_T;
/**
* @brief SPI last DMA transfers and reception
*/
typedef enum
{
SPI_LAST_DMA_TXRXEVEN = ((uint16_t)0x0000), //!< transmission Even reception Even */
SPI_LAST_DMA_TXEVENRXODD = ((uint16_t)0x2000), //!< transmission Even reception Odd */
SPI_LAST_DMA_TXODDRXEVEN = ((uint16_t)0x4000), //!< transmission Odd reception Even */
SPI_LAST_DMA_TXRXODD = ((uint16_t)0x6000), //!< transmission Odd reception Odd */
} SPI_LAST_DMA_T;
/**
* @brief SPI transmission fifo level
*/
typedef enum
{
SPI_TXFIFO_LEVEL_EMPTY = ((uint8_t)0x00), //!< Transmission FIFO filled level is empty */
SPI_TXFIFO_LEVEL_QUARTER = ((uint8_t)0x01), //!< Transmission FIFO filled level is more than quarter */
SPI_TXFIFO_LEVEL_HALF = ((uint8_t)0x02), //!< Transmission FIFO filled level is more than half */
SPI_TXFIFO_LEVEL_FULL = ((uint8_t)0x03), //!< Transmission FIFO filled level is full */
} SPI_TXFIFO_LEVEL_T;
/**
* @brief SPI reception fifo level
*/
typedef enum
{
SPI_RXFIFO_LEVEL_EMPTY = ((uint8_t)0x00), //!< Reception FIFO filled level is empty */
SPI_RXFIFO_LEVEL_QUARTER = ((uint8_t)0x01), //!< Reception FIFO filled level is more than quarter */
SPI_RXFIFO_LEVEL_HALF = ((uint8_t)0x02), //!< Reception FIFO filled level is more than half */
SPI_RXFIFO_LEVEL_FULL = ((uint8_t)0x03), //!< Reception FIFO filled level is full */
} SPI_RXFIFO_LEVEL_T;
/**
* @brief SPI flags definition
*/
typedef enum
{
SPI_FLAG_RXBNE = ((uint16_t)0x0001), //!< Receive buffer not empty flag */
SPI_FLAG_TXBE = ((uint16_t)0x0002), //!< Transmit buffer empty flag */
I2S_FLAG_CHDIR = ((uint16_t)0x0004), //!< Channel direction flag */
I2S_FLAG_UDR = ((uint16_t)0x0008), //!< Underrun flag */
SPI_FLAG_CRCE = ((uint16_t)0x0010), //!< CRC error flag */
SPI_FLAG_MME = ((uint16_t)0x0020), //!< Master mode error flag */
SPI_FLAG_OVR = ((uint16_t)0x0040), //!< Receive Overrun flag */
SPI_FLAG_BUSY = ((uint16_t)0x0080), //!< Busy flag */
SPI_FLAG_FFE = ((uint16_t)0x0100), //!< Frame format error flag */
} SPI_FLAG_T;
/**
* @brief SPI interrupt source
*/
typedef enum
{
SPI_INT_ERRIE = ((uint8_t)0x20), //!< Error interrupt */
SPI_INT_RXBNEIE = ((uint8_t)0x40), //!< Receive buffer not empty interrupt */
SPI_INT_TXBEIE = ((uint8_t)0x80), //!< Transmit buffer empty interrupt */
} SPI_INT_T;
/**
* @brief SPI interrupt flag
*/
typedef enum
{
SPI_INT_FLAG_RXBNE = ((uint32_t)0x400001), //!< Receive buffer not empty interrupt flag */
SPI_INT_FLAG_TXBE = ((uint32_t)0x800002), //!< Transmit buffer empty interrupt flag */
SPI_INT_FLAG_UDR = ((uint32_t)0x200008), //!< Underrun flag interrupt flag */
SPI_INT_FLAG_MME = ((uint32_t)0x200020), //!< Master mode error interrupt flag */
SPI_INT_FLAG_OVR = ((uint32_t)0x200040), //!< Receive Overrun interrupt flag */
SPI_INT_FLAG_FFE = ((uint32_t)0x200100), //!< Frame format error interrupt flag */
} SPI_INT_FLAG_T;
/**
* @brief I2S mode
*/
typedef enum
{
I2S_MODE_SLAVER_TX = ((uint8_t)0), //!< Slave TX mode */
I2S_MODE_SLAVER_RX = ((uint8_t)1), //!< Slave RX mode */
I2S_MODE_MASTER_TX = ((uint8_t)2), //!< Master TX mode */
I2S_MODE_MASTER_RX = ((uint8_t)3), //!< Master RX mode */
} I2S_MODE_T;
/**
* @brief I2S Standard
*/
typedef enum
{
I2S_STANDARD_PHILIPS = ((uint16_t)0x0000), //!< I2S Philips standard. */
I2S_STANDARD_MSB = ((uint16_t)0x0010), //!< MSB justified standard (left justified) */
I2S_STANDARD_LSB = ((uint16_t)0x0020), //!< LSB justified standard (right justified) */
I2S_STANDARD_PCM_SHORT = ((uint16_t)0x0030), //!< PCM short standard */
I2S_STANDARD_PCM_LONG = ((uint16_t)0x00B0), //!< PCM long standard */
} I2S_STANDARD_T;
/**
* @brief I2S data length
*/
typedef enum
{
I2S_DATA_LENGTH_16B = ((uint8_t)0x00), //!< Set data length to 16 bits */
I2S_DATA_LENGTH_16BEX = ((uint8_t)0x01), //!< Set data length to 16 bits */
I2S_DATA_LENGTH_24B = ((uint8_t)0x03), //!< Set data length to 24 bits */
I2S_DATA_LENGTH_32B = ((uint8_t)0x05), //!< Set data length to 32 bits */
} I2S_DATA_LENGTH_T;
/**
* @brief I2S MCLK Output
*/
typedef enum
{
I2S_MCLK_OUTPUT_DISABLE = ((uint8_t)0x00), //!< Set I2S MCLK Output disable */
I2S_MCLK_OUTPUT_ENABLE = ((uint8_t)0x01), //!< Set I2S MCLK Output enable */
} I2S_MCLK_OUTPUT_T;
/**
* @brief I2S Audio divider
*/
typedef enum
{
I2S_AUDIO_DIV_192K = ((uint32_t)192000), /*!< specifie the AUDIO divider division factor as 192K */
I2S_AUDIO_DIV_96K = ((uint32_t)96000), /*!< specifie the AUDIO divider division factor as 96K */
I2S_AUDIO_DIV_48K = ((uint32_t)48000), /*!< specifie the AUDIO divider division factor as 48K */
I2S_AUDIO_DIV_44K = ((uint32_t)44100), /*!< specifie the AUDIO divider division factor as 44K */
I2S_AUDIO_DIV_32K = ((uint32_t)32000), /*!< specifie the AUDIO divider division factor as 32K */
I2S_AUDIO_DIV_22K = ((uint32_t)22050), /*!< specifie the AUDIO divider division factor as 22K */
I2S_AUDIO_DIV_16K = ((uint32_t)16000), /*!< specifie the AUDIO divider division factor as 16K */
I2S_AUDIO_DIV_11K = ((uint32_t)11025), /*!< specifie the AUDIO divider division factor as 11K */
I2S_AUDIO_DIV_8K = ((uint32_t)8000), /*!< specifie the AUDIO divider division factor as 8K */
I2S_AUDIO_DIV_DEFAULT = ((uint32_t)2), /*!< specifie the AUDIO divider division factor as DEFAULT value */
} I2S_AUDIO_DIV_T;
/**
* @brief I2S Clock Polarity
*/
typedef enum
{
I2S_CLKPOL_LOW = ((uint8_t)0), //!< Clock Polarity low */
I2S_CLKPOL_HIGH = ((uint8_t)1), //!< Clock Polarity high */
} I2S_CLKPOL_T;
/**@} end of group SPI_Enumerations*/
/** @defgroup SPI_Structures Structures
@{
*/
/**
* @brief SPI Config struct definition
*/
typedef struct
{
SPI_MODE_T mode; /*!< Specifies the SPI mode */
SPI_DATA_LENGTH_T length; /*!< Specifies the SPI data length */
SPI_CLKPHA_T phase; /*!< Specifies the Clock phase */
SPI_CLKPOL_T polarity; /*!< Specifies the Clock polarity */
SPI_SSC_T slaveSelect; /*!< Specifies the slave select mode */
SPI_FIRST_BIT_T firstBit; /*!< Specifies the Frame format */
SPI_DIRECTION_T direction; /*!< Specifies the data direction mode */
SPI_BAUDRATE_DIV_T baudrateDiv; /*!< Specifies the baud rate divider */
uint8_t crcPolynomial; /*!< Specifies the CRC polynomial */
} SPI_Config_T;
/**
* @brief I2S Config struct definition
*/
typedef struct
{
I2S_MODE_T mode; /*!< Specifies the I2S mode */
I2S_STANDARD_T standard; /*!< Specifies the I2S standard */
I2S_DATA_LENGTH_T length; /*!< Specifies the I2S data length */
I2S_MCLK_OUTPUT_T MCLKOutput; /*!< Specifies the I2S MCLK Output */
I2S_AUDIO_DIV_T audioDiv; /*!< Specifies the I2S Audio Diver */
I2S_CLKPOL_T polarity; /*!< Specifies the Clock polarity */
} I2S_Config_T;
/**@} end of group SPI_Structures*/
/** @defgroup SPI_Variables Variables
@{
*/
/**@} end of group SPI_Variables */
/** @defgroup SPI_Functions Functions
@{
*/
/** SPI reset and configuration */
void SPI_Reset(SPI_T* spi);
void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig);
void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig); /*!< Not for APM32F030 devices */
void SPI_ConfigStructInit(SPI_Config_T* spiConfig);
void I2S_ConfigStructInit(I2S_Config_T* i2sConfig); /*!< Not for APM32F030 devices */
void SPI_Enable(SPI_T* spi);
void SPI_Disable(SPI_T* spi);
void I2S_Enable(SPI_T* spi); /*!< Not for APM32F030 devices */
void I2S_Disable(SPI_T* spi); /*!< Not for APM32F030 devices */
void SPI_EnableFrameFormatMode(SPI_T* spi);
void SPI_DisableFrameFormatMode(SPI_T* spi);
void SPI_ConfigDatalength(SPI_T* spi, uint8_t length);
void SPI_EnableOutputDirection(SPI_T* spi);
void SPI_DisableOutputDirection(SPI_T* spi);
void SPI_EnableInternalSlave(SPI_T* spi);
void SPI_DisableInternalSlave(SPI_T* spi);
void SPI_EnableSSoutput(SPI_T* spi);
void SPI_DisableSSoutput(SPI_T* spi);
void SPI_EnableNSSPulse(SPI_T* spi);
void SPI_DisableNSSPulse(SPI_T* spi);
/** CRC */
void SPI_CRCLength(SPI_T* spi, SPI_CRC_LENGTH_T crcLength);
void SPI_EnableCRC(SPI_T* spi);
void SPI_DisableCRC(SPI_T* spi);
void SPI_TxCRC(SPI_T* spi);
uint16_t SPI_ReadRxCRC(SPI_T* spi);
uint16_t SPI_ReadTxCRC(SPI_T* spi);
uint16_t SPI_ReadCRCPolynomial(SPI_T* spi);
/** DMA */
void SPI_EnableDMARxBuffer(SPI_T* spi);
void SPI_DisableDMARxBuffer(SPI_T* spi);
void SPI_EnableDMATxBuffer(SPI_T* spi);
void SPI_DisableDMATxBuffer(SPI_T* spi);
void SPI_LastDMATransfer(SPI_T* spi, SPI_LAST_DMA_T lastDMA);
/** FIFO */
void SPI_ConfigFIFOThreshold(SPI_T* spi, SPI_RXFIFO_T threshold);
uint8_t SPI_ReadTransmissionFIFOLeve(SPI_T* spi);
uint8_t SPI_ReadReceptionFIFOLeve(SPI_T* spi);
/** Interrupt */
void SPI_EnableInterrupt(SPI_T* spi, uint8_t interrupt);
void SPI_DisableInterrupt(SPI_T* spi, uint8_t interrupt);
/** Transmit and receive */
void SPI_TxData8(SPI_T* spi, uint8_t data);
void SPI_I2S_TxData16(SPI_T* spi, uint16_t data);
uint8_t SPI_RxData8(SPI_T* spi);
uint16_t SPI_I2S_RxData16(SPI_T* spi);
/** flag */
uint8_t SPI_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
void SPI_ClearStatusFlag(SPI_T* spi, uint8_t flag);
uint8_t SPI_ReadIntFlag(SPI_T* spi, SPI_INT_FLAG_T flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_SPI_H */
/**@} end of group SPI_Functions */
/**@} end of group SPI_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_syscfg.h
*
* @brief This file contains all the functions prototypes for the SYSCFG firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F0XX_SYSCFG_H
#define __APM32F0XX_SYSCFG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup SYSCFG_Driver SYSCFG Driver
@{
*/
/** @defgroup SYSCFG_Macros Macros
@{
*/
/** Macros description */
#define SYSCFG_CFG1_MEMMODE ((uint32_t)0x00000003); /*!< SYSCFG_Memory Remap Config */
/**@} end of group SYSCFG_Macros*/
/** @defgroup SYSCFG_Enumerations Enumerations
@{
*/
/**
* @brief SYSCFG EINT Port Sources
*/
typedef enum
{
SYSCFG_PORT_GPIOA = ((uint8_t)0x00), /*!< Port Source GPIOA */
SYSCFG_PORT_GPIOB = ((uint8_t)0x01), /*!< Port Source GPIOB */
SYSCFG_PORT_GPIOC = ((uint8_t)0x02), /*!< Port Source GPIOC */
SYSCFG_PORT_GPIOD = ((uint8_t)0x03), /*!< Port Source GPIOD */
SYSCFG_PORT_GPIOE = ((uint8_t)0x04), /*!< Port Source GPIOE (only for APM32F072 and APM32F091 devices) */
SYSCFG_PORT_GPIOF = ((uint8_t)0x05), /*!< Port Source GPIOF */
} SYSCFG_PORT_T;
/**
* @brief SYSCFG EINT Pin Sources
*/
typedef enum
{
SYSCFG_PIN_0 = ((uint8_t)0x00), /*!< Pin Source 0 */
SYSCFG_PIN_1 = ((uint8_t)0x01), /*!< Pin Source 1 */
SYSCFG_PIN_2 = ((uint8_t)0x02), /*!< Pin Source 2 */
SYSCFG_PIN_3 = ((uint8_t)0x03), /*!< Pin Source 3 */
SYSCFG_PIN_4 = ((uint8_t)0x04), /*!< Pin Source 4 */
SYSCFG_PIN_5 = ((uint8_t)0x05), /*!< Pin Source 5 */
SYSCFG_PIN_6 = ((uint8_t)0x06), /*!< Pin Source 6 */
SYSCFG_PIN_7 = ((uint8_t)0x07), /*!< Pin Source 7 */
SYSCFG_PIN_8 = ((uint8_t)0x08), /*!< Pin Source 8 */
SYSCFG_PIN_9 = ((uint8_t)0x09), /*!< Pin Source 9 */
SYSCFG_PIN_10 = ((uint8_t)0x0A), /*!< Pin Source 10 */
SYSCFG_PIN_11 = ((uint8_t)0x0B), /*!< Pin Source 11 */
SYSCFG_PIN_12 = ((uint8_t)0x0C), /*!< Pin Source 12 */
SYSCFG_PIN_13 = ((uint8_t)0x0D), /*!< Pin Source 13 */
SYSCFG_PIN_14 = ((uint8_t)0x0E), /*!< Pin Source 14 */
SYSCFG_PIN_15 = ((uint8_t)0x0F), /*!< Pin Source 15 */
} SYSCFG_PIN_T;
/**
* @brief SYSCFG Memory Remap Config
*/
typedef enum
{
SYSCFG_MEMORY_REMAP_FMC = ((uint8_t)0x00), /*!< SYSCFG MemoryRemap Flash */
SYSCFG_MEMORY_REMAP_SYSTEM = ((uint8_t)0x01), /*!< SYSCFG MemoryRemap SystemMemory */
SYSCFG_MEMORY_REMAP_SRAM = ((uint8_t)0x03), /*!< SYSCFG MemoryRemap SRAM */
} SYSCFG_MEMORY_REMAP_T;
/**
* @brief SYSCFG DMA Remap Config
*/
typedef enum
{
SYSCFG_DAM_REMAP_ADC = ((uint32_t)0x00000100), /*!< ADC DMA remap */
SYSCFG_DAM_REMAP_USART1TX = ((uint32_t)0x00000200), /*!< USART1 TX DMA remap */
SYSCFG_DAM_REMAP_USART1RX = ((uint32_t)0x00000400), /*!< USART1 RX DMA remap */
SYSCFG_DAM_REMAP_TMR16 = ((uint32_t)0x00000800), /*!< Timer 16 DMA remap */
SYSCFG_DAM_REMAP_TMR17 = ((uint32_t)0x00001000), /*!< Timer 17 DMA remap */
SYSCFG_DAM_REMAP_TMR16_2 = ((uint32_t)0x00002000), /*!< Timer 16 DMA remap2(only for APM32F072) */
SYSCFG_DAM_REMAP_TMR17_2 = ((uint32_t)0x00004000), /*!< Timer 17 DMA remap2(only for APM32F072) */
SYSCFG_DAM_REMAP_SPI2 = ((uint32_t)0x01000000), /*!< SPI2 DMA remap(only for APM32F072) */
SYSCFG_DAM_REMAP_USART2 = ((uint32_t)0x02000000), /*!< USART2 DMA remap(only for APM32F072) */
SYSCFG_DAM_REMAP_USART3 = ((uint32_t)0x04000000), /*!< USART3 DMA remap(only for APM32F072) */
SYSCFG_DAM_REMAP_I2C1 = ((uint32_t)0x08000000), /*!< I2C1 DMA remap(only for APM32F072) */
SYSCFG_DAM_REMAP_TMR1 = ((uint32_t)0x10000000), /*!< TMR1 DMA remap(only for APM32F072) */
SYSCFG_DAM_REMAP_TMR2 = ((uint32_t)0x20000000), /*!< TMR2 DMA remap(only for APM32F072) */
SYSCFG_DAM_REMAP_TMR3 = ((uint32_t)0x40000000), /*!< TMR3 DMA remap(only for APM32F072) */
} SYSCFG_DAM_REMAP_T;
/**
* @brief SYSCFG I2C FastModePlus Config
*/
typedef enum
{
SYSCFG_I2C_FMP_PB6 = ((uint32_t)0x00010000), /*!< I2C PB6 Fast mode plus */
SYSCFG_I2C_FMP_PB7 = ((uint32_t)0x00020000), /*!< I2C PB7 Fast mode plus */
SYSCFG_I2C_FMP_PB8 = ((uint32_t)0x00040000), /*!< I2C PB8 Fast mode plus */
SYSCFG_I2C_FMP_PB9 = ((uint32_t)0x00080000), /*!< I2C PB9 Fast mode plus */
SYSCFG_I2C_FMP_I2C1 = ((uint32_t)0x00100000), /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for APM32F030) */
SYSCFG_I2C_FMP_I2C2 = ((uint32_t)0x00200000), /*!< Enable Fast Mode Plus on I2C2 pins(only for APM32F072 and APM32F091) */
SYSCFG_I2C_FMP_PA9 = ((uint32_t)0x00400000), /*!< I2C PA9 Fast mode plus(only for APM32F030 and APM32F091) */
SYSCFG_I2C_FMP_PA10 = ((uint32_t)0x00800000), /*!< I2C PA10 Fast mode plus(only for APM32F030 and APM32F091) */
} SYSCFG_I2C_FMP_T;
/**
* @brief SYSCFG Lock Config
*/
typedef enum
{
SYSCFG_LOCK_LOCKUP = ((uint32_t)0x00000001), /*!< Cortex-M0 LOCKUP bit enable */
SYSCFG_LOCK_SRAM = ((uint32_t)0x00000002), /*!< SRAM parity lock bit */
SYSCFG_LOCK_PVD = ((uint32_t)0x00000004), /*!< PVD lock enable bit, not available for APM32F030 devices */
} SYSCFG_LOCK_T;
/**
* @brief IRDA ENV SOURCE
*/
typedef enum
{
SYSCFG_IRDA_ENV_TMR16 = ((uint32_t)0x000000C0), /*!< Timer16 as IRDA Modulation envelope source */
SYSCFG_IRDA_ENV_USART1 = ((uint32_t)0x00000040), /*!< USART1 as IRDA Modulation envelope source */
SYSCFG_IRDA_ENV_USART4 = ((uint32_t)0x00000080), /*!< USART4 as IRDA Modulation envelope source */
} SYSCFG_IRDA_ENV_T;
/**
* @brief SYSCFG flag
*/
typedef enum
{
SYSCFG_CFG2_SRAMPEF = ((uint32_t)0x00000100), /*!< SRAM Parity error flag */
} SYSCFG_FLAG_T;
/**@} end of group SYSCFG_Enumerations*/
/** @defgroup SYSCFG_Structures Structures
@{
*/
/**@} end of group SYSCFG_Structures */
/** @defgroup SYSCFG_Variables Variables
@{
*/
/**@} end of group SYSCFG_Variables */
/** @defgroup SYSCFG_Functions Functions
@{
*/
/* Reset */
void SYSCFG_Reset(void);
/* Memory Remap selects */
void SYSCFG_MemoryRemapSelect(uint8_t memory);
/* DMA Channel Remap */
void SYSCFG_EnableDMAChannelRemap(uint32_t channel);
void SYSCFG_DisableDMAChannelRemap(uint32_t channel);
/* I2C Fast Mode Plus */
void SYSCFG_EnableI2CFastModePlus(uint32_t pin);
void SYSCFG_DisableI2CFastModePlus(uint32_t pin);
/* IRDA Envelope */
void SYSCFG_SelectIRDAEnv(SYSCFG_IRDA_ENV_T IRDAEnv);
/* Eint Line */
void SYSCFG_EINTLine(SYSCFG_PORT_T port, SYSCFG_PIN_T pin);
/* Break lock */
void SYSCFG_BreakLock(uint32_t lock);
/* Flag */
uint8_t SYSCFG_ReadStatusFlag(uint32_t flag);
void SYSCFG_ClearStatusFlag(uint8_t flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_SYSCFG_H */
/**@} end of group SYSCFG_Functions */
/**@} end of group SYSCFG_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_tmr.h
*
* @brief This file contains all functions prototype and macros for the TMR peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F0XX_TMR_H
#define __APM32F0XX_TMR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup TMR_Driver TMR Driver
@{
*/
/** @defgroup TMR_Marcos Marcos
@{
*/
/**@} end of group TMR_Marcos */
/** @defgroup TMR_Enumerations Enumerations
@{
*/
/**
* @brief Counter_Mode
*/
typedef enum
{
TMR_COUNTER_MODE_UP = 0, /*!< Timer Up Counting Mode */
TMR_COUNTER_MODE_DOWN = 1, /*!< Timer Down Counting Mode */
TMR_COUNTER_MODE_CENTERALIGNED1 = 2, /*!< Timer Center Aligned Mode1 */
TMR_COUNTER_MODE_CENTERALIGNED2 = 4, /*!< Timer Center Aligned Mode2 */
TMR_COUNTER_MODE_CENTERALIGNED3 = 6 /*!< Timer Center Aligned Mode3 */
} TMR_COUNTER_MODE_T;
/**
* @brief Clock_Division_CKD
*/
typedef enum
{
TMR_CKD_DIV1 = 0, /*!< TDTS = Tck_tim */
TMR_CKD_DIV2 = 1, /*!< TDTS = 2 * Tck_tim */
TMR_CKD_DIV4 = 2 /*!< TDTS = 4 * Tck_tim */
} TMR_CKD_T;
/**
* @brief Prescaler_Reload_Mode
*/
typedef enum
{
TMR_PRESCALER_RELOAD_UPDATA = 0, /*!< The Prescaler reload at the update event */
TMR_PRESCALER_RELOAD_IMMEDIATE = 1 /*!< The Prescaler reload immediately */
} TMR_PRESCALER_RELOAD_T;
/**
* @brief TMR UpdateSource
*/
typedef enum
{
TMR_UPDATE_SOURCE_GLOBAL = 0, /*!< Source of update is Counter overflow/underflow.
- UEG bit of Control event generation register(CEG) is set.
- Update generation through the slave mode controller. */
TMR_UPDATE_SOURCE_REGULAR = 1 /*!< Source of update is Counter overflow/underflow */
} TMR_UPDATE_SOURCE_T;
/**
* @brief TMR OPMode
*/
typedef enum
{
TMR_OPMODE_REPETITIVE = 0, /*!< Enable repetitive pulse mode */
TMR_OPMODE_SINGLE = 1 /*!< Enable single pulse mode */
} TMR_OPMODE_T;
/**
* @brief TMR Specifies the Off-State selection used in Run mode
*/
typedef enum
{
TMR_RMOS_STATE_DISABLE = 0, /*!< Disable run mode off-state */
TMR_RMOS_STATE_ENABLE = 1 /*!< Enable run mode off-state */
} TMR_RMOS_STATE_T;
/**
* @brief TMR Closed state configuration in idle mode
*/
typedef enum
{
TMR_IMOS_STATE_DISABLE = 0, /*!< Disable idle mode off-state */
TMR_IMOS_STATE_ENABLE = 1 /*!< Enable idle mode off-state */
} TMR_IMOS_STATE_T;
/**
* @brief TMR Protect mode configuration values
*/
typedef enum
{
TMR_LOCK_LEVEL_OFF = 0, /*!< No lock write protection */
TMR_LOCK_LEVEL_1 = 1, /*!< Lock write protection level 1 */
TMR_LOCK_LEVEL_2 = 2, /*!< Lock write protection level 2 */
TMR_LOCK_LEVEL_3 = 3 /*!< Lock write protection level 3 */
} TMR_LOCK_LEVEL_T;
/**
* @brief TMR break state
*/
typedef enum
{
TMR_BREAK_STATE_DISABLE, /*!< Disable brake function */
TMR_BREAK_STATE_ENABLE /*!< Enable brake function */
} TMR_BREAK_STATE_T;
/**
* @brief TMR Specifies the Break Input pin polarity.
*/
typedef enum
{
TMR_BREAK_POLARITY_LOW, /*!< BREAK low level valid */
TMR_BREAK_POLARITY_HIGH /*!< BREAK high level valid */
} TMR_BREAK_POLARITY_T;
/**
* @brief TMR Automatic Output feature is enable or disable
*/
typedef enum
{
TMR_AUTOMATIC_OUTPUT_DISABLE, /*!< Disable automatic output */
TMR_AUTOMATIC_OUTPUT_ENABLE /*!< Enable automatic output */
} TMR_AUTOMATIC_OUTPUT_T;
/**
* @brief TMR_Output_Compare_and_PWM_modes
*/
typedef enum
{
TMR_OC_MODE_TMRING = 0x00, /*!< Frozen TMR output compare mode */
TMR_OC_MODE_ACTIVE = 0x01, /*!< Set output to high when matching */
TMR_OC_MODE_INACTIVE = 0x02, /*!< Set output to low when matching */
TMR_OC_MODE_TOGGEL = 0x03, /*!< Toggle output when matching */
TMR_OC_MODE_LOWLEVEL = 0x04, /*!< Force output to be low */
TMR_OC_MODE_HIGHLEVEL = 0x05, /*!< Force output to be high */
TMR_OC_MODE_PWM1 = 0x06, /*!< PWM1 mode */
TMR_OC_MODE_PWM2 = 0x07 /*!< PWM2 mode */
} TMR_OC_MODE_T;
/**
* @brief TMR_Output_Compare_state
*/
typedef enum
{
TMR_OUTPUT_STATE_DISABLE, /*!< Disable output compare */
TMR_OUTPUT_STATE_ENABLE /*!< Enable output compare */
} TMR_OC_OUTPUT_STATE_T;
/**
* @brief TMR_Output_Compare_N_state
*/
typedef enum
{
TMR_OUTPUT_NSTATE_DISABLE, /*!< Disable complementary output */
TMR_OUTPUT_NSTATE_ENABLE /*!< Enable complementary output */
} TMR_OC_OUTPUT_NSTATE_T;
/**
* @brief TMR_Output_Compare_Polarity
*/
typedef enum
{
TMR_OC_POLARITY_HIGH, /*!< Output Compare active high */
TMR_OC_POLARITY_LOW /*!< Output Compare active low */
} TMR_OC_POLARITY_T;
/**
* @brief TMR_Output_Compare_N_Polarity
*/
typedef enum
{
TMR_OC_NPOLARITY_HIGH, /*!< Output Compare active high */
TMR_OC_NPOLARITY_LOW /*!< Output Compare active low */
} TMR_OC_NPOLARITY_T;
/**
* @brief TMR_Output_Compare_Idle_State
*/
typedef enum
{
TMR_OCIDLESTATE_RESET, /*!< Reset output compare idle state */
TMR_OCIDLESTATE_SET /*!< Set output compare idle state */
} TMR_OC_IDLE_STATE_T;
/**
* @brief TMR_Output_Compare_N_Idle_State
*/
typedef enum
{
TMR_OCNIDLESTATE_RESET, /*!< Reset output complementary idle state */
TMR_OCNIDLESTATE_SET /*!< Set output complementary idle state */
} TMR_OC_NIDLE_STATE_T;
/**
* @brief TMR Input Capture Init structure definition
*/
typedef enum
{
TMR_CHANNEL_1 = 0x0000, /*!< Timer Channel 1 */
TMR_CHANNEL_2 = 0x0004, /*!< Timer Channel 2 */
TMR_CHANNEL_3 = 0x0008, /*!< Timer Channel 3 */
TMR_CHANNEL_4 = 0x000C /*!< Timer Channel 4 */
} TMR_CHANNEL_T;
/**
* @brief TMR ForcedAction
*/
typedef enum
{
TMR_FORCEDACTION_INACTIVE = 0x04, /*!< Force inactive level on OC1REF */
TMR_FORCEDACTION_ACTIVE = 0x05 /*!< Force active level on OC1REF */
} TMR_FORCED_ACTION_T;
/**
* @brief TMR Output_Compare_Preload_State
*/
typedef enum
{
TMR_OC_PRELOAD_DISABLE, /*!< Disable preload */
TMR_OC_PRELOAD_ENABLE /*!< Enable preload */
} TMR_OC_PRELOAD_T;
/**
* @brief TMR Output_Compare_Fast_State
*/
typedef enum
{
TMR_OCFAST_DISABLE, /*!< Disable fast output compare */
TMR_OCFAST_ENABLE /*!< Enable fast output compare */
} TMR_OCFAST_T;
/**
* @brief TMR Output_Compare_Clear_State
*/
typedef enum
{
TMR_OCCLER_DISABLE, /*!< Disable output compare clear */
TMR_OCCLER_ENABLE /*!< Enable output compare clear */
} TMR_OCCLER_T;
/**
* @brief TMR_OCReferenceClear Clear source
*/
typedef enum
{
TMR_OCCS_ETRF, /*!< Select ETRF as clear source */
TMR_OCCS_OCREFCLR /*!< Select OCREFCLR as clear source */
} TMR_OCCSEL_T;
/**
* @brief TMR Input_Capture_Polarity
*/
typedef enum
{
TMR_IC_POLARITY_RISING = 0x00, /*!< Rising edge */
TMR_IC_POLARITY_FALLING = 0x02, /*!< Falling edge */
TMR_IC_POLARITY_BOTHEDGE = 0x0A /*!< Both rising and falling edge */
} TMR_IC_POLARITY_T;
/**
* @brief TMR Input_Capture_Selection
*/
typedef enum
{
TMR_IC_SELECTION_DIRECT_TI = 0x01, /*!< Input capture mapping in TI1 */
TMR_IC_SELECTION_INDIRECT_TI = 0x02, /*!< Input capture mapping in TI2 */
TMR_IC_SELECTION_TRC = 0x03 /*!< Input capture mapping in TRC */
} TMR_IC_SELECTION_T;
/**
* @brief TMR_Input_Capture_Prescaler
*/
typedef enum
{
TMR_ICPSC_DIV1 = 0x00, /*!< No prescaler */
TMR_ICPSC_DIV2 = 0x01, /*!< Capture is done once every 2 events */
TMR_ICPSC_DIV4 = 0x02, /*!< capture is done once every 4 events */
TMR_ICPSC_DIV8 = 0x03 /*!< capture is done once every 8 events */
} TMR_IC_PRESCALER_T;
/**
* @brief TMR_interrupt_sources
*/
typedef enum
{
TMR_INT_UPDATE = 0x0001, /*!< Timer update Interrupt source */
TMR_INT_CH1 = 0x0002, /*!< Timer Capture Compare 1 Interrupt source */
TMR_INT_CH2 = 0x0004, /*!< Timer Capture Compare 2 Interrupt source */
TMR_INT_CH3 = 0x0008, /*!< Timer Capture Compare 3 Interrupt source */
TMR_INT_CH4 = 0x0010, /*!< Timer Capture Compare 4 Interrupt source */
TMR_INT_CCU = 0x0020, /*!< Timer Commutation Interrupt */
TMR_INT_TRG = 0x0040, /*!< Timer Trigger Interrupt source */
TMR_INT_BRK = 0x0080 /*!< Timer Break Interrupt source */
} TMR_INT_T;
/**
* @brief TMR_event_sources
*/
typedef enum
{
TMR_EVENT_UPDATE = 0x0001, /*!< Timer update Interrupt source */
TMR_EVENT_CH1 = 0x0002, /*!< Timer Capture Compare 1 Event source */
TMR_EVENT_CH2 = 0x0004, /*!< Timer Capture Compare 2 Event source */
TMR_EVENT_CH3 = 0x0008, /*!< Timer Capture Compare 3 Event source */
TMR_EVENT_CH4 = 0x0010, /*!< Timer Capture Compare 4 Event source */
TMR_EVENT_CCU = 0x0020, /*!< Timer Commutation Event source */
TMR_EVENT_TRG = 0x0040, /*!< Timer Trigger Event source */
TMR_EVENT_BRK = 0x0080 /*!< Timer Break Event source */
} TMR_EVENT_T;
/**
* @brief TMR_interrupt_flag
*/
typedef enum
{
TMR_INT_FLAG_UPDATE = 0x0001, /*!< Timer update Interrupt source */
TMR_INT_FLAG_CH1 = 0x0002, /*!< Timer Capture Compare 1 Interrupt source */
TMR_INT_FLAG_CH2 = 0x0004, /*!< Timer Capture Compare 2 Interrupt source */
TMR_INT_FLAG_CH3 = 0x0008, /*!< Timer Capture Compare 3 Interrupt source */
TMR_INT_FLAG_CH4 = 0x0010, /*!< Timer Capture Compare 4 Interrupt source */
TMR_INT_FLAG_CCU = 0x0020, /*!< Timer Commutation Interrupt source */
TMR_INT_FLAG_TRG = 0x0040, /*!< Timer Trigger Interrupt source */
TMR_INT_FLAG_BRK = 0x0080 /*!< Timer Break Interrupt source */
} TMR_INT_FLAG_T;
/**
* @brief TMR Flag
*/
typedef enum
{
TMR_FLAG_UPDATE = 0x0001, /*!< Timer update Flag */
TMR_FLAG_CH1 = 0x0002, /*!< Timer Capture Compare 1 Flag */
TMR_FLAG_CH2 = 0x0004, /*!< Timer Capture Compare 2 Flag */
TMR_FLAG_CH3 = 0x0008, /*!< Timer Capture Compare 3 Flag */
TMR_FLAG_CH4 = 0x0010, /*!< Timer Capture Compare 4 Flag */
TMR_FLAG_CCU = 0x0020, /*!< Timer Commutation Flag */
TMR_FLAG_TRG = 0x0040, /*!< Timer Trigger Flag */
TMR_FLAG_BRK = 0x0080, /*!< Timer Break Flag (Only for TMR1 and TMR8) */
TMR_FLAG_CH1OC = 0x0200, /*!< Timer Capture Compare 1 Repetition Flag */
TMR_FLAG_CH2OC = 0x0400, /*!< Timer Capture Compare 2 Repetition Flag */
TMR_FLAG_CH3OC = 0x0800, /*!< Timer Capture Compare 3 Repetition Flag */
TMR_FLAG_CH4OC = 0x1000 /*!< Timer Capture Compare 4 Repetition Flag */
} TMR_FLAG_T;
/**
* @brief TMR DMA Base Address
*/
typedef enum
{
TMR_DMABASE_CTRL1 = 0x0000, /*!< TMR CTRL1 DMA base address setup */
TMR_DMABASE_CTRL2 = 0x0001, /*!< TMR CTRL2 DMA base address setup */
TMR_DMABASE_SMCTRL = 0x0002, /*!< TMR SMCTRL DMA base address setup */
TMR_DMABASE_DIEN = 0x0003, /*!< TMR DIEN DMA base address setup */
TMR_DMABASE_STS = 0x0004, /*!< TMR STS DMA base address setup */
TMR_DMABASE_CEG = 0x0005, /*!< TMR CEG DMA base address setup */
TMR_DMABASE_CCM1 = 0x0006, /*!< TMR CCM1 DMA base address setup */
TMR_DMABASE_CCM2 = 0x0007, /*!< TMR CCM2 DMA base address setup */
TMR_DMABASE_CHCTRL = 0x0008, /*!< TMR CHCTRL DMA base address setup */
TMR_DMABASE_CNT = 0x0009, /*!< TMR CNT DMA base address setup */
TMR_DMABASE_DIV = 0x000A, /*!< TMR DIV DMA base address setup */
TMR_DMABASE_AUTORLD = 0x000B, /*!< TMR AUTORLD DMA base address setup */
TMR_DMABASE_REPCNT = 0x000C, /*!< TMR REPCNT DMA base address setup */
TMR_DMABASE_CH1CC = 0x000D, /*!< TMR CH1CC DMA base address setup */
TMR_DMABASE_CH2CC = 0x000E, /*!< TMR CH2CC DMA base address setup */
TMR_DMABASE_CH3CC = 0x000F, /*!< TMR CH3CC DMA base address setup */
TMR_DMABASE_CH4CC = 0x0010, /*!< TMR CH4CC DMA base address setup */
TMR_DMABASE_BDT = 0x0011, /*!< TMR BDT DMA base address setup */
TMR_DMABASE_DMAB = 0x0012 /*!< TMR DMAB DMA base address setup */
} TMR_DMA_BASE_ADDERSS_T;
/**
* @brief TMR DMA Burst Lenght
*/
typedef enum
{
TMR_DMA_BURSTLENGHT_1TRANSFER = 0x0000, /*!< Select TMR DMA burst Length 1 */
TMR_DMA_BURSTLENGHT_2TRANSFERS = 0x0100, /*!< Select TMR DMA burst Length 2 */
TMR_DMA_BURSTLENGHT_3TRANSFERS = 0x0200, /*!< Select TMR DMA burst Length 3 */
TMR_DMA_BURSTLENGHT_4TRANSFERS = 0x0300, /*!< Select TMR DMA burst Length 4 */
TMR_DMA_BURSTLENGHT_5TRANSFERS = 0x0400, /*!< Select TMR DMA burst Length 5 */
TMR_DMA_BURSTLENGHT_6TRANSFERS = 0x0500, /*!< Select TMR DMA burst Length 6 */
TMR_DMA_BURSTLENGHT_7TRANSFERS = 0x0600, /*!< Select TMR DMA burst Length 7 */
TMR_DMA_BURSTLENGHT_8TRANSFERS = 0x0700, /*!< Select TMR DMA burst Length 8 */
TMR_DMA_BURSTLENGHT_9TRANSFERS = 0x0800, /*!< Select TMR DMA burst Length 9 */
TMR_DMA_BURSTLENGHT_10TRANSFERS = 0x0900, /*!< Select TMR DMA burst Length 10 */
TMR_DMA_BURSTLENGHT_11TRANSFERS = 0x0A00, /*!< Select TMR DMA burst Length 11 */
TMR_DMA_BURSTLENGHT_12TRANSFERS = 0x0B00, /*!< Select TMR DMA burst Length 12 */
TMR_DMA_BURSTLENGHT_13TRANSFERS = 0x0C00, /*!< Select TMR DMA burst Length 13 */
TMR_DMA_BURSTLENGHT_14TRANSFERS = 0x0D00, /*!< Select TMR DMA burst Length 14 */
TMR_DMA_BURSTLENGHT_15TRANSFERS = 0x0E00, /*!< Select TMR DMA burst Length 15 */
TMR_DMA_BURSTLENGHT_16TRANSFERS = 0x0F00, /*!< Select TMR DMA burst Length 16 */
TMR_DMA_BURSTLENGHT_17TRANSFERS = 0x1000, /*!< Select TMR DMA burst Length 17 */
TMR_DMA_BURSTLENGHT_18TRANSFERS = 0x1100, /*!< Select TMR DMA burst Length 18 */
} TMR_DMA_BURST_LENGHT_T;
/**
* @brief TMR DMA Soueces
*/
typedef enum
{
TMR_DMA_UPDATE = 0x0100, /*!< TMR update DMA souces */
TMR_DMA_CH1 = 0x0200, /*!< TMR Capture Compare 1 DMA souces */
TMR_DMA_CH2 = 0x0400, /*!< TMR Capture Compare 2 DMA souces */
TMR_DMA_CH3 = 0x0800, /*!< TMR Capture Compare 3 DMA souces */
TMR_DMA_CH4 = 0x1000, /*!< TMR Capture Compare 4 DMA souces */
TMR_DMA_CCU = 0x2000, /*!< TMR Commutation DMA souces */
TMR_DMA_TRG = 0x4000 /*!< TMR Trigger DMA souces */
} TMR_DMA_SOUCES_T;
/**
* @brief TMR Internal_Trigger_Selection
*/
typedef enum
{
TMR_TS_ITR0 = 0x00, /*!< Internal Trigger 0 */
TMR_TS_ITR1 = 0x01, /*!< Internal Trigger 1 */
TMR_TS_ITR2 = 0x02, /*!< Internal Trigger 2 */
TMR_TS_ITR3 = 0x03, /*!< Internal Trigger 3 */
TMR_TS_TI1F_ED = 0x04, /*!< TI1 Edge Detector */
TMR_TS_TI1FP1 = 0x05, /*!< Filtered Timer Input 1 */
TMR_TS_TI2FP2 = 0x06, /*!< Filtered Timer Input 2 */
TMR_TS_ETRF = 0x07 /*!< External Trigger input */
} TMR_INPUT_TRIGGER_SOURCE_T;
/**
* @brief TMR The external Trigger Prescaler.
*/
typedef enum
{
TMR_ExtTRGPSC_OFF = 0x00, /*!< ETRP Prescaler OFF */
TMR_EXTTRGPSC_DIV2 = 0x01, /*!< ETRP frequency divided by 2 */
TMR_EXTTRGPSC_DIV4 = 0x02, /*!< ETRP frequency divided by 4 */
TMR_EXTTRGPSC_DIV8 = 0x03 /*!< ETRP frequency divided by 8 */
} TMR_EXTTRG_PRESCALER_T;
/**
* @brief TMR External_Trigger_Polarity
*/
typedef enum
{
TMR_EXTTRGPOLARITY_INVERTED = 0x01, /*!< Active low or falling edge active */
TMR_EXTTGRPOLARITY_NONINVERTED = 0x00 /*!< Active high or rising edge active */
} TMR_EXTTRG_POLARITY_T;
/**
* @brief TMR OPMode
*/
typedef enum
{
TMR_TRGOSOURCE_RESET, /*!< Select reset signal as TRGO source */
TMR_TRGOSOURCE_ENABLE, /*!< Select enable signal as TRGO source */
TMR_TRGOSOURCE_UPDATE, /*!< Select update signal as TRGO source */
TMR_TRGOSOURCE_OC1, /*!< Select OC1 signal as TRGO source */
TMR_TRGOSOURCE_OC1REF, /*!< Select OC1REF signal as TRGO source */
TMR_TRGOSOURCE_OC2REF, /*!< Select OC2REF signal as TRGO source */
TMR_TRGOSOURCE_OC3REF, /*!< Select OC3REF signal as TRGO source */
TMR_TRGOSOURCE_OC4REF /*!< Select OC4REF signal as TRGO source */
} TMR_TRGOSOURCE_T;
/**
* @brief TMR OPMode
*/
typedef enum
{
TMR_SLAVEMODE_RESET = 0x04, /*!< Reset mode */
TMR_SLAVEMODE_GATED = 0x05, /*!< Gated mode */
TMR_SLAVEMODE_TRIGGER = 0x06, /*!< Trigger mode */
TMR_SLAVEMODE_EXTERNALL = 0x07 /*!< External 1 mode */
} TMR_SLAVEMODE_T;
/**
* @brief TMR Encoder_Mode
*/
typedef enum
{
TMR_ENCODER_MODE_TI1 = 0x01, /*!< Encoder mode 1 */
TMR_ENCODER_MODE_TI2 = 0x02, /*!< Encoder mode 2 */
TMR_ENCODER_MODE_TI12 = 0x03 /*!< Encoder mode 3 */
} TMR_ENCODER_MODE_T;
/**
* @brief TMR Remap Select
*/
typedef enum
{
TMR_REMAP_GPIO = 0x00, /*!< TMR input is connected to GPIO */
TMR_REMAP_RTC_CLK = 0x01, /*!< TMR input is connected to RTC clock */
TMR_REMAP_HSEDiv32 = 0x02, /*!< TMR input is connected to HSE clock/32 */
TMR_REMAP_MCO = 0x03 /*!< TMR input is connected to MCO */
} TMR_REMAP_T;
/**@} end of group TMR_Enumerations*/
/** @defgroup TMR_Structures Stuctures
@{
*/
/**
* @brief TMR Time Base Init structure definition
* @note This sturcture is used with all TMRx.
*/
typedef struct
{
uint16_t div; /*!< This must between 0x0000 and 0xFFFF */
TMR_COUNTER_MODE_T counterMode; /*!< TMR counter mode selection */
uint32_t period; /*!< This must between 0x0000 and 0xFFFF */
TMR_CKD_T clockDivision; /*!< TMR clock division selection */
uint8_t repetitionCounter; /*!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. */
} TMR_TimeBase_T;
/**
* @brief TMR BDT structure definition
*/
typedef struct
{
TMR_RMOS_STATE_T RMOS_State; /*!< TMR Specifies the Off-State selection used in Run mode selection */
TMR_IMOS_STATE_T IMOS_State; /*!< TMR Closed state configuration in idle mode selection */
TMR_LOCK_LEVEL_T lockLevel; /*!< TMR Protect mode configuration values selection */
uint8_t deadTime; /*!< Setup dead time */
TMR_BREAK_STATE_T breakState; /*!< Setup TMR BRK state */
TMR_BREAK_POLARITY_T breakPolarity; /*!< Setup TMR BRK polarity */
TMR_AUTOMATIC_OUTPUT_T automaticOutput; /*!< Setup break input pin polarity */
} TMR_BDTInit_T;
/**
* @brief TMR Config struct definition
*/
typedef struct
{
TMR_OC_MODE_T OC_Mode; /*!< Specifies the TMR mode. */
TMR_OC_OUTPUT_STATE_T OC_OutputState; /*!< Specifies the TMR Output Compare state. */
TMR_OC_OUTPUT_NSTATE_T OC_OutputNState; /*!< Specifies the TMR complementary Output Compare state. @note This parameter is valid only for TMR1 and TMR8. */
TMR_OC_POLARITY_T OC_Polarity; /*!< Specifies the output polarity. */
TMR_OC_NPOLARITY_T OC_NPolarity; /*!< Specifies the complementary output polarity. @note This parameter is valid only for TMR1 and TMR8. */
TMR_OC_IDLE_STATE_T OC_Idlestate; /*!< Specifies the TMR Output Compare pin state during Idle state. @note This parameter is valid only for TMR1 and TMR8. */
TMR_OC_NIDLE_STATE_T OC_NIdlestate; /*!< Specifies the TMR Output Compare pin state during Idle state. @note This parameter is valid only for TMR1 and TMR8. */
uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. */
} TMR_OCConfig_T;
/**
* @brief TMR Input Capture Config struct definition
*/
typedef struct
{
TMR_CHANNEL_T channel; /*!< Specifies the TMR channel. */
TMR_IC_POLARITY_T ICpolarity; /*!< Specifies the active edge of the input signal. */
TMR_IC_SELECTION_T ICselection; /*!< Specifies the input. */
TMR_IC_PRESCALER_T ICprescaler; /*!< Specifies the Input Capture Prescaler. */
uint16_t ICfilter; /*!< Specifies the input capture filter. */
} TMR_ICConfig_T;
/**@} end of group TMR_Structures*/
/** @defgroup TMR_Variables Variables
@{
*/
/**@} end of group TMR_Variables */
/** @defgroup TMR_Functions Functions
@{
*/
/* TimeBase management */
void TMR_Reset(TMR_T* TMRx);
void TMR_ConfigTimeBase(TMR_T* TMRx, TMR_TimeBase_T* timeBaseConfig);
void TMR_ConfigTimeBaseStruct(TMR_TimeBase_T* timeBaseConfig);
void TMR_ConfigDIV(TMR_T* TMRx, uint16_t div, TMR_PRESCALER_RELOAD_T mode);
void TMR_ConfigCounterMode(TMR_T* TMRx, TMR_COUNTER_MODE_T mode);
void TMR_SetCounter(TMR_T* TMRx, uint32_t counter);
void TMR_SetAutoReload(TMR_T* TMRx, uint32_t autoReload);
uint32_t TMR_ReadCounter(TMR_T* TMRx);
uint32_t TMR_ReadDiv(TMR_T* TMRx);
void TMR_EnableNGUpdate(TMR_T* TMRx);
void TMR_DisableNGUpdate(TMR_T* TMRx);
void TMR_ConfigUPdateRequest(TMR_T* TMRx, TMR_UPDATE_SOURCE_T source);
void TMR_EnableAUTOReload(TMR_T* TMRx);
void TMR_DisableAUTOReload(TMR_T* TMRx);
void TMR_SetClockDivision(TMR_T* TMRx, TMR_CKD_T clockDivision);
void TMR_Enable(TMR_T* TMRx);
void TMR_Disable(TMR_T* TMRx);
void TMR_ConfigBDT(TMR_T* TMRx, TMR_BDTInit_T* structure);
void TMR_ConfigBDTStructInit(TMR_BDTInit_T* structure);
void TMR_EnablePWMOutputs(TMR_T* TMRx);
void TMR_DisablePWMOutputs(TMR_T* TMRx);
void TMR_OC1Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct);
void TMR_OC2Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct);
void TMR_OC3Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct);
void TMR_OC4Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct);
void TMR_OCConfigStructInit(TMR_OCConfig_T* OCcongigStruct);
void TMR_SelectOCxMode(TMR_T* TMRx, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode);
void TMR_SelectSlaveMode(TMR_T* TMRx, TMR_SLAVEMODE_T mode);
void TMR_SelectOnePulseMode(TMR_T* TMRx, TMR_OPMODE_T OPMode);
void TMR_SetCompare1(TMR_T* TMRx, uint32_t compare);
void TMR_SetCompare2(TMR_T* TMRx, uint32_t compare);
void TMR_SetCompare3(TMR_T* TMRx, uint32_t compare);
void TMR_SetCompare4(TMR_T* TMRx, uint32_t compare);
void TMR_ForcedOC1Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action);
void TMR_ForcedOC2Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action);
void TMR_ForcedOC3Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action);
void TMR_ForcedOC4Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action);
void TMR_EnableCCPreload(TMR_T* TMRx);
void TMR_DisableCCPreload(TMR_T* TMRx);
void TMR_OC1PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload);
void TMR_OC2PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload);
void TMR_OC3PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload);
void TMR_OC4PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload);
void TMR_OC1FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast);
void TMR_OC2FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast);
void TMR_OC3FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast);
void TMR_OC4FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast);
void TMR_OC1PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity);
void TMR_OC1NPolarityConfig(TMR_T* TMRx, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_OC2PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity);
void TMR_OC2NPolarityConfig(TMR_T* TMRx, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_OC3PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity);
void TMR_OC3NPolarityConfig(TMR_T* TMRx, TMR_OC_NPOLARITY_T OCNPolarity);
void TMR_OC4PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity);
void TMR_SelectOCREFClear(TMR_T* TMRx, TMR_OCCSEL_T OCReferenceClear);
void TMR_EnableCCxChannel(TMR_T* TMRx, TMR_CHANNEL_T channel);
void TMR_DisableCCxChannel(TMR_T* TMRx, TMR_CHANNEL_T channel);
void TMR_EnableCCxNChannel(TMR_T* TMRx, TMR_CHANNEL_T channel);
void TMR_DisableCCxNChannel(TMR_T* TMRx, TMR_CHANNEL_T channel);
void TMR_EnableAUTOReload(TMR_T* TMRx);
void TMR_DisableAUTOReload(TMR_T* TMRx);
void TMR_EnableSelectCOM(TMR_T* TMRx);
void TMR_DisableSelectCOM(TMR_T* TMRx);
void TMR_ICConfig(TMR_T* TMRx, TMR_ICConfig_T* ICconfigstruct);
void TMR_ICConfigStructInit(TMR_ICConfig_T* ICconfigstruct);
void TMR_PWMConfig(TMR_T* TMRx, TMR_ICConfig_T* ICconfigstruct);
uint16_t TMR_ReadCaputer1(TMR_T* TMRx);
uint16_t TMR_ReadCaputer2(TMR_T* TMRx);
uint16_t TMR_ReadCaputer3(TMR_T* TMRx);
uint16_t TMR_ReadCaputer4(TMR_T* TMRx);
void TMR_SetIC1Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler);
void TMR_SetIC2Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler);
void TMR_SetIC3Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler);
void TMR_SetIC4Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler);
/* Interrupts and Event management functions */
void TMR_EnableInterrupt(TMR_T* TMRx, uint16_t interrupt);
void TMR_DisableInterrupt(TMR_T* TMRx, uint16_t interrupt);
void TMR_GenerateEvent(TMR_T* TMRx, uint16_t event);
uint16_t TMR_ReadStatusFlag(TMR_T* TMRx, TMR_FLAG_T flag);
void TMR_ClearStatusFlag(TMR_T* TMRx, uint16_t flag);
uint16_t TMR_ReadIntFlag(TMR_T* TMRx, TMR_INT_FLAG_T flag);
void TMR_ClearIntFlag(TMR_T* TMRx, uint16_t flag);
void TMR_ConfigDMA(TMR_T* TMRx, TMR_DMA_BASE_ADDERSS_T address, TMR_DMA_BURST_LENGHT_T lenght);
void TMR_EnableDMASoure(TMR_T* TMRx, uint16_t souces);
void TMR_DisableDMASoure(TMR_T* TMRx, uint16_t souces);
void TMR_EnableCCDMA(TMR_T* TMRx);
void TMR_DisableCCDMA(TMR_T* TMRx);
/* Clocks management */
void TMR_ConfigInternalClock(TMR_T* TMRx);
void TMR_ConfigITRxExternalClock(TMR_T* TMRx, TMR_INPUT_TRIGGER_SOURCE_T input);
void TMR_ConfigTIxExternalClock(TMR_T* TMRx, TMR_INPUT_TRIGGER_SOURCE_T input,
TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
void TMR_ConfigExternalClockMode1(TMR_T* TMRx, TMR_EXTTRG_PRESCALER_T prescaler,
TMR_EXTTRG_POLARITY_T polarity, uint16_t filter);
void TMR_ConfigExternalClockMode2(TMR_T* TMRx, TMR_EXTTRG_PRESCALER_T prescaler,
TMR_EXTTRG_POLARITY_T polarity, uint16_t filter);
/* Synchronization management */
void TMR_SelectInputTrigger(TMR_T* TMRx, TMR_INPUT_TRIGGER_SOURCE_T input);
void TMR_SelectOutputTrigger(TMR_T* TMRx, TMR_TRGOSOURCE_T source);
void TMR_EnableMasterSlaveMode(TMR_T* TMRx);
void TMR_DisableMasterSlaveMode(TMR_T* TMRx);
void TMR_ConfigExternalTrigger(TMR_T* TMRx, TMR_EXTTRG_PRESCALER_T prescaler,
TMR_EXTTRG_POLARITY_T polarity, uint16_t filter);
/* Specific interface management */
void TMR_ConfigEncodeInterface(TMR_T* TMRx, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
TMR_IC_POLARITY_T IC2Polarity);
void TMR_EnableHallSensor(TMR_T* TMRx);
void TMR_DisableHallSensor(TMR_T* TMRx);
/* Specific remapping management */
void TMR_ConfigRemap(TMR_T* TMRx, TMR_REMAP_T remap);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_TMR_H */
/**@} end of group TMR_Functions */
/**@} end of group TMR_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_usart.h
*
* @brief This file contains all the functions prototypes for the USART firmware library
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F0XX_USART_H
#define __APM32F0XX_USART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup USART_Driver USART Driver
@{
*/
/** @defgroup USART_Macros Macros
@{
*/
/** Macros description */
#define USART_MACROS 1
/**@} end of group USART_Macros*/
/** @defgroup USART_Enumerations Enumerations
@{
*/
/**
* @brief USART Word Length define
*/
typedef enum
{
USART_WORD_LEN_8B = 0, /*!< 8-bit data length */
USART_WORD_LEN_9B = BIT12, /*!< 9-bit data length */
USART_WORD_LEN_7B = BIT12 | BIT28 /*!< only available for APM32F072 and APM32F030 devices */
} USART_WORD_LEN_T;
/**
* @brief USART Stop bits define
*/
typedef enum
{
USART_STOP_BIT_1 = 0, /*!< 1-bit stop bit */
USART_STOP_BIT_2 = BIT13, /*!< 2-bit stop bit */
USART_STOP_BIT_1_5 = BIT12 | BIT13 /*!< 1.5-bit stop bit */
} USART_STOP_BITS_T;
/**
* @brief USART Parity define
*/
typedef enum
{
USART_PARITY_NONE = 0, /*!< Disable parity control */
USART_PARITY_EVEN = BIT10, /*!< Enable even parity control */
USART_PARITY_ODD = BIT10 | BIT9 /*!< Enable odd parity control*/
} USART_PARITY_T;
/**
* @brief USART mode define
*/
typedef enum
{
USART_MODE_RX = BIT2, /*!< Enable USART Receive mode */
USART_MODE_TX = BIT3, /*!< Enable USART transmit mode */
USART_MODE_TX_RX = BIT2 | BIT3 /*!< Enable USART receive and transmit mode */
} USART_MODE_T;
/**
* @brief USART hardware flow control define
*/
typedef enum
{
USART_FLOW_CTRL_NONE = 0, /*!< Disable hardware flow control */
USART_FLOW_CTRL_RTS = BIT8, /*!< Enable RTS hardware flow control */
USART_FLOW_CTRL_CTS = BIT9, /*!< Enable CTS hardware flow control */
USART_FLOW_CTRL_RTS_CTS = BIT8 | BIT9 /*!< Enable RTS and CTS hardware flow control */
} USART_HARDWARE_FLOW_CTRL_T;
/**
* @brief USART synchronization clock enable/disable
*/
typedef enum
{
USART_CLKEN_DISABLE = ((uint8_t)0), /*!< Disable usart clock */
USART_CLKEN_ENABLE = ((uint8_t)1) /*!< Enable usart clock */
} USART_CLKEN_T;
/**
* @brief USART Clock polarity define
*/
typedef enum
{
USART_CLKPOL_LOW = ((uint8_t)0), /*!< Set clock polarity to low */
USART_CLKPOL_HIGH = ((uint8_t)1) /*!< Set clock polarity to high */
} USART_CLKPOL_T;
/**
* @brief USART Clock phase define
*/
typedef enum
{
USART_CLKPHA_1EDGE = ((uint8_t)0), /*!< Set usart to sample at the edge of the first clock */
USART_CLKPHA_2EDGE = ((uint8_t)1) /*!< Set usart to sample at the edge of the second clock */
} USART_CLKPHA_T;
/**
* @brief USART Last bit clock pulse enable
*/
typedef enum
{
USART_LBCP_DISABLE = ((uint8_t)0), /*!< Disable output last bit clock pulse */
USART_LBCP_ENABLE = ((uint8_t)1) /*!< Enable output last bit clock pulse */
} USART_LBCP_T;
/**
* @brief USART DMA requests
*/
typedef enum
{
USART_DMA_REQUEST_RX = BIT6, /*!< USART DMA receive request */
USART_DMA_REQUEST_TX = BIT7 /*!< USART DMA transmit request */
} USART_DMA_REQUEST_T;
/**
* @brief USART DMA reception error
*/
typedef enum
{
USART_DMA_RXERR_ENABLE = ((uint8_t)0), /*!< USART DMA reception error enable */
USART_DMA_RXERR_DISABLE = ((uint8_t)1) /*!< USART DMA reception error disable */
} USART_DMA_RXERR_T;
/**
* @brief USART wakeup method
*/
typedef enum
{
USART_WAKEUP_IDLE_LINE = ((uint8_t)0), /*!< WakeUp by an idle line detection */
USART_WAKEUP_ADDRESS_MARK = ((uint8_t)1) /*!< WakeUp by an address mark */
} USART_WAKEUP_T;
/**
* @brief USART LIN break detection length
*/
typedef enum
{
USART_BREAK_LENGTH_10B = ((uint8_t)0), /*!< 10-bit break detection */
USART_BREAK_LENGTH_11B = ((uint8_t)1) /*!< 11-bit break detection */
} USART_BREAK_LENGTH_T;
/**
* @brief USART address mode
*/
typedef enum
{
USART_ADDRESS_MODE_4B = ((uint8_t)0), /*!< 4-bit address detection */
USART_ADDRESS_MODE_7B = ((uint8_t)1) /*!< 7-bit address detection */
} USART_ADDRESS_MODE_T;
/**
* @brief USART address mode, only available for APM32F072 devices
*/
typedef enum
{
USART_WAKEUP_SOURCE_ADDRESS = ((uint8_t)0), /*!< usart wakeup by address */
USART_WAKEUP_SOURCE_START = ((uint8_t)2), /*!< usart wakeup by start bit */
USART_WAKEUP_SOURCE_RXNE = ((uint8_t)3) /*!< usart wakeup by RXNE */
} USART_WAKEUP_SOURCE_T;
/**
* @brief USART driver enable polarity select
*/
typedef enum
{
USART_DE_POL_HIGH = ((uint8_t)0), /*!< driver enable polarity is high */
USART_DE_POL_LOW = ((uint8_t)1) /*!< driver enable polarity is low */
} USART_DE_POL_T;
/**
* @brief USART inversion Pins
*/
typedef enum
{
USART_INVERSION_RX = BIT16, /*!< usart RX Pins active level inversion */
USART_INVERSION_TX = BIT17, /*!< usart TX Pins active level inversion */
USART_INVERSION_TX_RX = BIT16 | BIT17 /*!< usart RX TX Pins active level inversion */
} USART_INVERSION_T;
/**
* @brief USART IrDA Low Power
*/
typedef enum
{
USART_IRDA_MODE_NORMAL = ((uint8_t)0), /*!< usart irda works in normal mode */
USART_IRDA_MODE_LOWPOWER = ((uint8_t)1) /*!< usart irda works in low-power mode */
} USART_IRDA_MODE_T;
/**
* @brief USART auto baud rate mode
*/
typedef enum
{
USART_AUTO_BAUD_RATE_STARTBIT = ((uint8_t)0x00), /*!< auto-baud measure start bit */
USART_AUTO_BAUD_RATE_FALLINGEDGE = ((uint8_t)0x01) /*!< auto-baud measure falling edge */
} USART_AUTO_BAUD_RATE_T;
/**
* @brief USART over detection disable
*/
typedef enum
{
USART_OVER_DETECTION_ENABLE = ((uint8_t)0), /*!< enable overrun detection */
USART_OVER_DETECTION_DISABLE = ((uint8_t)1) /*!< disable overrun detection */
} USART_OVER_DETECTION_T;
/**
* @brief USART request
*/
typedef enum
{
USART_REQUEST_ABRQ = ((uint8_t)0x01), /*!< Auto Baud Rate Request */
USART_REQUEST_SBQ = ((uint8_t)0x02), /*!< Send Break Request */
USART_REQUEST_MMQ = ((uint8_t)0x04), /*!< Mute Mode Request */
USART_REQUEST_RDFQ = ((uint8_t)0x08), /*!< Receive data flush Request */
USART_REQUEST_TDFQ = ((uint8_t)0x10) /*!< Transmit data flush Request */
} USART_REQUEST_T;
/**
* @brief USART flag definition
*/
typedef enum
{
USART_FLAG_RXENACKF = ((uint32_t)0x00400000), /*!< Receive Enable Acknowledge Flag */
USART_FLAG_TXENACKF = ((uint32_t)0x00200000), /*!< Transmit Enable Acknowledge Flag */
USART_FLAG_WAKEUP = ((uint32_t)0x00100000), /*!< Wake Up from stop mode Flag (Not for APM32F030 devices) */
USART_FLAG_RWF = ((uint32_t)0x00080000), /*!< Send Break flag (Not for APM32F030 devices) */
USART_FLAG_SBF = ((uint32_t)0x00040000), /*!< Send Break flag */
USART_FLAG_CMF = ((uint32_t)0X00020000), /*!< Character match flag */
USART_FLAG_BUSY = ((uint32_t)0X00010000), /*!< Busy flag */
USART_FLAG_ABRTF = ((uint32_t)0X00008000), /*!< Auto baud rate flag */
USART_FLAG_ABRTE = ((uint32_t)0X00004000), /*!< Auto baud rate error flag */
USART_FLAG_EOBF = ((uint32_t)0X00001000), /*!< End of block flag (Not for APM32F030 devices) */
USART_FLAG_RXTOF = ((uint32_t)0X00000800), /*!< Receive time out flag */
USART_FLAG_CTSF = ((uint32_t)0X00000400), /*!< CTS Change flag */
USART_FLAG_CTSIF = ((uint32_t)0X00000200), /*!< CTS interrupt flag */
USART_FLAG_LBDF = ((uint32_t)0x00000100), /*!< LIN Break Detection Flag (Not for APM32F030 devices) */
USART_FLAG_TXBE = ((uint32_t)0X00000080), /*!< Transmit data register empty flag */
USART_FLAG_TXC = ((uint32_t)0X00000040), /*!< Transmission Complete flag */
USART_FLAG_RXBNE = ((uint32_t)0X00000020), /*!< Receive data buffer not empty flag */
USART_FLAG_IDLEF = ((uint32_t)0X00000010), /*!< Idle Line detection flag */
USART_FLAG_OVRE = ((uint32_t)0X00000008), /*!< OverRun Error flag */
USART_FLAG_NEF = ((uint32_t)0X00000004), /*!< Noise Error flag */
USART_FLAG_FEF = ((uint32_t)0X00000002), /*!< Framing Error flag */
USART_FLAG_PEF = ((uint32_t)0X00000001), /*!< Parity Error flag */
} USART_FLAG_T;
/**
* @brief USART interrupts source
*/
typedef enum
{
USART_INT_WAKEUP = ((uint32_t)0x00400000), /*!< Wake up interrupt (Not for APM32F030 devices) */
USART_INT_CMIE = ((uint32_t)0x00004000), /*!< Character match interrupt */
USART_INT_EOBIE = ((uint32_t)0x08000000), /*!< End of Block interrupt (Not for APM32F030 devices) */
USART_INT_RXTOIE = ((uint32_t)0x04000000), /*!< Receive time out interrupt */
USART_INT_CTSIE = ((uint32_t)0x00000400), /*!< CTS change interrupt */
USART_INT_LBDIE = ((uint32_t)0X00000040), /*!< LIN Break detection interrupt (Not for APM32F030 devices) */
USART_INT_TXBEIE = ((uint32_t)0x00000080), /*!< Tansmit Data Register empty interrupt */
USART_INT_TXCIE = ((uint32_t)0x40000040), /*!< Transmission complete interrupt */
USART_INT_RXBNEIE = ((uint32_t)0x00000020), /*!< Receive Data buffer not empty interrupt */
USART_INT_IDLEIE = ((uint32_t)0x00000010), /*!< Idle line detection interrupt */
USART_INT_PEIE = ((uint32_t)0x00000100), /*!< Parity Error interrupt */
USART_INT_ERRIE = ((uint32_t)0x00000001), /*!< Error interrupt */
} USART_INT_T;
/**
* @brief USART Interrupt flag definition
*/
typedef enum
{
USART_INT_FLAG_WAKEUP = ((uint32_t)0X00100000), /*!< Wake up flag (Not for APM32F030 devices) */
USART_INT_FLAG_CMF = ((uint32_t)0X00020000), /*!< Character match flag */
USART_INT_FLAG_EOBF = ((uint32_t)0X00001000), /*!< End of block flag (Not for APM32F030 devices) */
USART_INT_FLAG_RXTOF = ((uint32_t)0X00000800), /*!< Receive time out flag */
USART_INT_FLAG_CTSIF = ((uint32_t)0X00000200), /*!< CTS interrupt flag */
USART_INT_FLAG_LBDF = ((uint32_t)0X00000100), /*!< LIN Break detection flag (Not for APM32F030 devices) */
USART_INT_FLAG_TXBE = ((uint32_t)0X00000080), /*!< Transmit data register empty flag */
USART_INT_FLAG_TXC = ((uint32_t)0X00000040), /*!< Transmission Complete flag */
USART_INT_FLAG_RXBNE = ((uint32_t)0X00000020), /*!< Receive data buffer not empty flag */
USART_INT_FLAG_IDLE = ((uint32_t)0X00000010), /*!< Idle Line detection flag */
USART_INT_FLAG_OVRE = ((uint32_t)0X00000008), /*!< OverRun Error flag */
USART_INT_FLAG_NE = ((uint32_t)0X00000004), /*!< Noise Error flag */
USART_INT_FLAG_FE = ((uint32_t)0X00000002), /*!< Framing Error flag */
USART_INT_FLAG_PE = ((uint32_t)0X00000001), /*!< Parity Error flag */
} USART_INT_FLAG_T;
/**@} end of group USART_Enumerations*/
/** @defgroup USART_Structures Structures
@{
*/
/**
* @brief USART Config struct definition
*/
typedef struct
{
uint32_t baudRate; /*!< Specifies the baud rate */
USART_WORD_LEN_T wordLength; /*!< Specifies the word length */
USART_STOP_BITS_T stopBits; /*!< Specifies the stop bits */
USART_PARITY_T parity; /*!< Specifies the parity */
USART_MODE_T mode; /*!< Specifies the mode */
USART_HARDWARE_FLOW_CTRL_T hardwareFlowCtrl;
} USART_Config_T;
/**
* @brief USART synchronous communication clock config struct definition
*/
typedef struct
{
USART_CLKEN_T enable; /*!< Enable or Disable Clock */
USART_CLKPOL_T polarity; /*!< Specifies the clock polarity */
USART_CLKPHA_T phase; /*!< Specifies the clock phase */
USART_LBCP_T lastBitClock; /*!< Enable or Disable last bit clock */
} USART_SyncClockConfig_T;
/**@} end of group USART_Structures*/
/** @defgroup USART_Variables Variables
@{
*/
/**@} end of group USART_Variables */
/** @addtogroup USART_Functions Functions
@{
*/
/* USART peripheral Reset and Configuration */
void USART_Reset(USART_T* usart);
void USART_Config(USART_T* uart, USART_Config_T* configStruct);
void USART_ConfigStructInit(USART_Config_T* configStruct);
void USART_ConfigSyncClock(USART_T* usart, USART_SyncClockConfig_T* SyncClockConfig);
void USART_ConfigSyncClockStructInit(USART_SyncClockConfig_T* SyncClockConfig);
void USART_Enable(USART_T* usart);
void USART_Disable(USART_T* usart);
void USART_EnableDirectionMode(USART_T* usart, USART_MODE_T mode);
void USART_DisableDirectionMode(USART_T* usart, USART_MODE_T mode);
void USART_ConfigDivider(USART_T* usart, uint8_t divider); /*!< Not for APM32F030 devices */
void USART_EnableOverSampling8(USART_T* usart);
void USART_DisableOverSampling8(USART_T* usart);
void USART_EnableMSBFirst(USART_T* usart);
void USART_DisableMSBFirst(USART_T* usart);
void USART_EnableOneBitMethod(USART_T* usart);
void USART_DisableOneBitMethod(USART_T* usart);
void USART_EnableDataInv(USART_T* usart);
void USART_DisableDataInv(USART_T* usart);
void USART_EnableInvPin(USART_T* usart, USART_INVERSION_T invPin);
void USART_DisableInvPin(USART_T* usart, USART_INVERSION_T invPin);
void USART_EnableSWAPPin(USART_T* usart);
void USART_DisableSWAPPin(USART_T* usart);
void USART_EnableReceiverTimeOut(USART_T* usart);
void USART_DisableReceiverTimeOut(USART_T* usart);
void USART_ReceiverTimeOutValue(USART_T* usart, uint32_t timeOut);
void USART_EnableAutoBaudRate(USART_T* usart);
void USART_DisableAutoBaudRate(USART_T* usart);
void USART_ConfigAutoBaudRate(USART_T* usart, USART_AUTO_BAUD_RATE_T mode);
void USART_ConfigOverrunDetection(USART_T* usart, USART_OVER_DETECTION_T overDetection);
/* Stop mode */
void USART_EnableStopMode(USART_T* usart);
void USART_DisableStopMode(USART_T* usart);
void USART_ConfigStopModeWakeUpSource(USART_T* usart, USART_WAKEUP_SOURCE_T source); /*!< Not for APM32F030 devices */
/* Address */
void USART_Address(USART_T* usart, uint8_t address);
void USART_ConfigAddressDetection(USART_T* usart, USART_ADDRESS_MODE_T address);
/* Transmit and receive */
void USART_TxData(USART_T* usart, uint16_t data);
uint16_t USART_RxData(USART_T* usart);
/* Mute mode */
void USART_EnableMuteMode(USART_T* usart);
void USART_DisableMuteMode(USART_T* usart);
void USART_ConfigMuteModeWakeUp(USART_T* usart, USART_WAKEUP_T wakeup);
/* LIN mode */
void USART_EnableLINmode(USART_T* usart); /*!< Not for APM32F030 devices */
void USART_DisableLINmode(USART_T* usart); /*!< Not for APM32F030 devices */
void USART_ConfigLINbreakDetectLength(USART_T* usart, USART_BREAK_LENGTH_T length); /*!< Not for APM32F030 devices */
/* Half-duplex mode */
void USART_EnableHalfDuplex(USART_T* usart);
void USART_DisableHalfDuplex(USART_T* usart);
/* Smartcard mode */
void USART_EnableSmartCard(USART_T* usart); /*!< Not for APM32F030 devices */
void USART_DisableSmartCard(USART_T* usart); /*!< Not for APM32F030 devices */
void USART_EnableSmartCardNACK(USART_T* usart); /*!< Not for APM32F030 devices */
void USART_DisableSmartCardNACK(USART_T* usart); /*!< Not for APM32F030 devices */
void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime); /*!< Not for APM32F030 devices */
void USART_ConfigAutoCount(USART_T* usart, uint8_t autoCount); /*!< Not for APM32F030 devices */
void USART_ConfigBlockSize(USART_T* usart, uint8_t blockSize); /*!< Not for APM32F030 devices */
/* IrDA mode */
void USART_EnableIrDA(USART_T* usart); /*!< Not for APM32F030 devices */
void USART_DisableIrDA(USART_T* usart); /*!< Not for APM32F030 devices */
void USART_ConfigIrDAMode(USART_T* usart, USART_IRDA_MODE_T IrDAMode); /*!< Not for APM32F030 devices */
/* Driver enable Configuration */
void USART_EnableDE(USART_T* usart);
void USART_DisableDE(USART_T* usart);
void USART_ConfigDEPolarity(USART_T* usart, USART_DE_POL_T polarity);
void USART_DEAssertionTimeValue(USART_T* usart, uint8_t value);
void USART_DEDeassertionTimeValue(USART_T* usart, uint8_t value);
/* DMA */
void USART_EnableDMA(USART_T* usart, uint32_t dmaReq);
void USART_DisableDMA(USART_T* usart, uint32_t dmaReq);
void USART_ConfigDMAReceptionError(USART_T* usart, USART_DMA_RXERR_T error);
/* Request */
void USART_EnableRequest(USART_T* usart, USART_REQUEST_T request);
void USART_DisableRequest(USART_T* usart, USART_REQUEST_T request);
/* Interrupt */
void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt);
void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt);
uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_FLAG_T flag);
void USART_ClearIntFlag(USART_T* usart, uint32_t flag);
/* Flag */
uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag);
void USART_ClearStatusFlag(USART_T* usart, uint32_t flag);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_USART_H */
/**@} end of group USART_Functions */
/**@} end of group USART_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_wwdt.h
*
* @brief This file contains all the functions prototypes for the WWDG firmware library
*
* @version V1.0.2
*
* @date 2022-02-21
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#ifndef __APM32F0XX_WWDT_H
#define __APM32F0XX_WWDT_H
#ifdef __cplusplus
extern "C" {
#endif
#include "apm32f0xx.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup WWDT_Driver WWDT Driver
@{
*/
/** @defgroup WWDT_Macros Macros
@{
*/
/**@} end of group WWDT_Macros */
/** @defgroup WWDT_Enumerations Enumerations
@{
*/
/**
* @brief WWDT Timebase(Prescaler) define
*/
typedef enum
{
WWDT_DIV_1 = ((uint8_t)0x00),
WWDT_DIV_2 = ((uint8_t)0x01),
WWDT_DIV_4 = ((uint8_t)0x02),
WWDT_DIV_8 = ((uint8_t)0x03)
} WWDT_DIV_T;
/**@} end of group WWDT_Enumerations*/
/** @defgroup WWDT_Structures Structures
@{
*/
/**@} end of group WWDT_Structures */
/** @defgroup WWDT_Variables Variables
@{
*/
/**@} end of group WWDT_Variables */
/** @defgroup WWDT_Functions Functions
@{
*/
/* WWDT reset */
void WWDT_Reset(void);
/* Set WWDT Timebase */
void WWDT_SetTimebase(uint32_t div);
/* Set Window Data */
void WWDT_ConfigWindowValue(uint16_t windowValue);
/* Set Couter */
void WWDT_ConfigCounter(uint8_t couter);
/* Enable WWDT and Early Wakeup interrupt */
void WWDT_EnableEWI(void);
void WWDT_Enable(uint8_t count);
/* Read Flag and Clear Flag */
uint8_t WWDT_ReadStatusFlag(void);
void WWDT_ClearStatusFlag(void);
#ifdef __cplusplus
}
#endif
#endif /* __APM32F0XX_WWDT_H */
/**@} end of group WWDT_Functions */
/**@} end of group WWDT_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_adc.c
*
* @brief This file contains all the functions for the ADC peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_adc.h"
#include "apm32f0xx_rcm.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup ADC_Driver
@{
*/
/** @defgroup ADC_Macros Macros
@{
*/
/**@} end of group ADC_Macros */
/** @defgroup ADC_Enumerations Enumerations
@{
*/
/**@} end of group ADC_Enumerations */
/** @defgroup ADC_Structures Structures
@{
*/
/**@} end of group ADC_Structures */
/** @defgroup ADC_Variables Variables
@{
*/
/**@} end of group ADC_Variables */
/** @defgroup ADC_Functions Functions
@{
*/
/*!
* @brief Set the ADC peripheral registers to their default reset values
*
* @param None
*
* @retval None
*/
void ADC_Reset(void)
{
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1);
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1);
}
/*!
* @brief Config the ADC peripheral according to the specified parameters in the adcConfig
*
* @param adcConfig: Pointer to a ADC_Config_T structure that
* contains the configuration information for the ADC peripheral
*
* @retval None
*/
void ADC_Config(ADC_Config_T* adcConfig)
{
ADC->CFG1_B.DATARESCFG = adcConfig->resolution;
ADC->CFG1_B.DALIGCFG = adcConfig->dataAlign;
ADC->CFG1_B.SCANSEQDIR = adcConfig->scanDir;
ADC->CFG1_B.CMODESEL = adcConfig->convMode;
ADC->CFG1_B.EXTPOLSEL = adcConfig->extTrigEdge;
ADC->CFG1_B.EXTTRGSEL = adcConfig->extTrigConv;
}
/*!
* @brief Fills each adcConfig member with its default value
*
* @param adcConfig: Pointer to a ADC_Config_T structure which will be initialized
*
* @retval None
*/
void ADC_ConfigStructInit(ADC_Config_T* adcConfig)
{
adcConfig->resolution = ADC_RESOLUTION_12B;
adcConfig->dataAlign = ADC_DATA_ALIGN_RIGHT;
adcConfig->scanDir = ADC_SCAN_DIR_UPWARD;
adcConfig->convMode = ADC_CONVERSION_SINGLE;
adcConfig->extTrigConv = ADC_EXT_TRIG_CONV_TRG0;
adcConfig->extTrigEdge = ADC_EXT_TRIG_EDGE_NONE;
}
/*!
* @brief Enable the ADC peripheral
*
* @param None
*
* @retval None
*/
void ADC_Enable(void)
{
ADC->CTRL_B.ADCEN = BIT_SET;
}
/*!
* @brief Disable the ADC peripheral
*
* @param None
*
* @retval None
*/
void ADC_Disable(void)
{
ADC->CTRL_B.ADCD = BIT_SET;
}
/*!
* @brief Configure the ADC to either be clocked by the asynchronous clock
*
* @param clockmode: selects the ADC clock mode.
* The parameter can be one of following values:
* @arg ADC_CLOCK_MODE_ASYNCLK: ADC Asynchronous clock mode
* @arg ADC_CLOCK_MODE_SYNCLKDIV2: Synchronous clock mode divided by 2
* @arg ADC_CLOCK_MODE_SYNCLKDIV4: Synchronous clock mode divided by 4
*
* @retval None
*/
void ADC_ClockMode(ADC_CLOCK_MODE_T clockMode)
{
ADC->CFG2_B.CLKCFG = (uint32_t)clockMode;
}
/*!
* @brief Enables the jitter when the ADC is clocked by PCLK div2 or div4
*
* @param jitter: They are replaced by PCLK div2 or div4
* The parameter can be one of following values:
* @arg ADC_JITTER_PCLKDIV2: ADC clocked by PCLK div2
* @arg ADC_JITTER_PCLKDIV4: ADC clocked by PCLK div4
*
* @retval None
*/
void ADC_EnableJitter(ADC_JITTER_T jitter)
{
ADC->CFG2_B.CLKCFG |= (uint32_t)jitter;
}
/*!
* @brief Disables the jitter when the ADC is clocked by PCLK div2 or div4
*
* @param jitter: They are replaced by PCLK div2 or div4
* The parameter can be one of following values:
* @arg ADC_JITTER_PCLKDIV2: ADC clocked by PCLK div2
* @arg ADC_JITTER_PCLKDIV4: ADC clocked by PCLK div4
* @retval None
*/
void ADC_DisableJitter(ADC_JITTER_T jitter)
{
ADC->CFG2_B.CLKCFG &= (uint32_t)~jitter;
}
/*!
* @brief Enables the Auto Power Off mode
*
* @param None
*
* @retval None
*/
void ADC_EnableAutoPowerOff(void)
{
ADC->CFG1_B.AOEN = BIT_SET;
}
/*!
* @brief Disables the Auto Power Off mode
*
* @param None
*
* @retval None
*/
void ADC_DisableAutoPowerOff(void)
{
ADC->CFG1_B.AOEN = BIT_RESET;
}
/*!
* @brief Enables the Auto-delayed conversion mode
*
* @param None
*
* @retval None
*/
void ADC_EnableWaitMode(void)
{
ADC->CFG1_B.WAITCEN = BIT_SET;
}
/*!
* @brief Disables the Auto-delayed conversion mode
*
* @param None
*
* @retval None
*/
void ADC_DisableWaitMode(void)
{
ADC->CFG1_B.WAITCEN = BIT_RESET;
}
/*!
* @brief Enables the analog watchdog
*
* @param None
*
* @retval None
*/
void ADC_EnableAnalogWatchdog(void)
{
ADC->CFG1_B.AWDEN = BIT_SET;
}
/*!
* @brief Disables the analog watchdog
*
* @param None
*
* @retval None
*/
void ADC_DisableAnalogWatchdog(void)
{
ADC->CFG1_B.AWDEN = BIT_RESET;
}
/*!
* @brief The analog watchdog low threshold
*
* @param None
*
* @retval None
*/
void ADC_AnalogWatchdogLowThreshold(uint16_t lowThreshold)
{
ADC->AWDT_B.AWDLT = (uint16_t)lowThreshold;
}
/*!
* @brief The analog watchdog High threshold
*
* @param None
*
* @retval None
*/
void ADC_AnalogWatchdogHighThreshold(uint16_t highThreshold)
{
ADC->AWDT_B.AWDHT = (uint16_t)highThreshold;
}
/*!
* @brief Configures the analog watchdog guarded single channel
*
* @param channel: ADC analog watchdog channel selection
* The parameter can be one of following values:
* @arg ADC_ANALG_WDT_CHANNEL_0: AWD Channel 0
* @arg ADC_ANALG_WDT_CHANNEL_1: AWD Channel 1
* @arg ADC_ANALG_WDT_CHANNEL_2: AWD Channel 2
* @arg ADC_ANALG_WDT_CHANNEL_3: AWD Channel 3
* @arg ADC_ANALG_WDT_CHANNEL_4: AWD Channel 4
* @arg ADC_ANALG_WDT_CHANNEL_5: AWD Channel 5
* @arg ADC_ANALG_WDT_CHANNEL_6: AWD Channel 6
* @arg ADC_ANALG_WDT_CHANNEL_7: AWD Channel 7
* @arg ADC_ANALG_WDT_CHANNEL_8: AWD Channel 8
* @arg ADC_ANALG_WDT_CHANNEL_9: AWD Channel 9
* @arg ADC_ANALG_WDT_CHANNEL_10: AWD Channel 10
* @arg ADC_ANALG_WDT_CHANNEL_11: AWD Channel 11
* @arg ADC_ANALG_WDT_CHANNEL_12: AWD Channel 12
* @arg ADC_ANALG_WDT_CHANNEL_13: AWD Channel 13
* @arg ADC_ANALG_WDT_CHANNEL_14: AWD Channel 14
* @arg ADC_ANALG_WDT_CHANNEL_15: AWD Channel 15
* @arg ADC_ANALG_WDT_CHANNEL_16: AWD Channel 16 is TempSensor
* @arg ADC_ANALG_WDT_CHANNEL_17: AWD Channel 17 is Vrefint
* @arg ADC_ANALG_WDT_CHANNEL_18: AWD Channel 18 is Vbat, not available for APM32F030 devices
*
* @retval None
*/
void ADC_AnalogWatchdogSingleChannel(uint32_t channel)
{
ADC->CFG1_B.AWDCHSEL = channel;
}
/*!
* @brief Enables the Analog Watchdog Single Channel
*
* @param None
*
* @retval None
*/
void ADC_EnableAnalogWatchdogSingleChannel(void)
{
ADC->CFG1_B.AWDCHEN = BIT_SET;
}
/*!
* @brief Disables the Analog Watchdog Single Channel
*
* @param None
*
* @retval None
*/
void ADC_DisableAnalogWatchdogSingleChannel(void)
{
ADC->CFG1_B.AWDCHEN = BIT_RESET;
}
/*!
* @brief Enables the temperature sensor channel
*
* @param None
*
* @retval None
*/
void ADC_EnableTempSensor(void)
{
ADC->CCFG_B.TSEN = BIT_SET;
}
/*!
* @brief Disables the temperature sensor channel
*
* @param None
*
* @retval None
*/
void ADC_DisableTempSensor(void)
{
ADC->CCFG_B.TSEN = BIT_RESET;
}
/*!
* @brief Enables the vrefint channel
*
* @param None
*
* @retval None
*/
void ADC_EnableVrefint(void)
{
ADC->CCFG_B.VREFEN = BIT_SET;
}
/*!
* @brief Disables the vrefint channel
*
* @param None
*
* @retval None
*/
void ADC_DisableVrefint(void)
{
ADC->CCFG_B.VREFEN = BIT_RESET;
}
/*!
* @brief Enables the Vbat channel
*
* @param None
*
* @retval None
*
* @note It's not for APM32F030 devices
*/
void ADC_EnableVbat(void)
{
ADC->CCFG_B.VBATEN = BIT_SET;
}
/*!
* @brief Disables the Vbat channel
*
* @param None
*
* @retval None
*
* @note It's not for APM32F030 devices
*/
void ADC_DisableVbat(void)
{
ADC->CCFG_B.VBATEN = BIT_RESET;
}
/*!
* @brief Configures for the selected ADC channel and its sampling time
*
* @param channel: the ADC channel
* The parameter can be combination of following values:
* @arg ADC_CHANNEL_0: channel 0
* @arg ADC_CHANNEL_1: channel 1
* @arg ADC_CHANNEL_2: channel 2
* @arg ADC_CHANNEL_3: channel 3
* @arg ADC_CHANNEL_4: channel 4
* @arg ADC_CHANNEL_5: channel 5
* @arg ADC_CHANNEL_6: channel 6
* @arg ADC_CHANNEL_7: channel 7
* @arg ADC_CHANNEL_8: channel 8
* @arg ADC_CHANNEL_9: channel 9
* @arg ADC_CHANNEL_10: channel 10
* @arg ADC_CHANNEL_11: channel 11
* @arg ADC_CHANNEL_12: channel 12
* @arg ADC_CHANNEL_13: channel 13
* @arg ADC_CHANNEL_14: channel 14
* @arg ADC_CHANNEL_15: channel 15
* @arg ADC_CHANNEL_16: channel 16 is TempSensor
* @arg ADC_CHANNEL_17: channel 17 is Vrefint
* @arg ADC_CHANNEL_18: channel 18 is Vbat, not available for APM32F030 devices
* @param sampleTime: the ADC sampling time
* The parameter can be one of following values:
* @arg ADC_SAMPLE_TIME_1_5: ADC 1.5 clock cycles
* @arg ADC_SAMPLE_TIME_7_5: ADC 7.5 clock cycles
* @arg ADC_SAMPLE_TIME_13_5: ADC 13.5 clock cycles
* @arg ADC_SAMPLE_TIME_28_5: ADC 28.5 clock cycles
* @arg ADC_SAMPLE_TIME_41_5: ADC 41.5 clock cycles
* @arg ADC_SAMPLE_TIME_55_5: ADC 55.5 clock cycles
* @arg ADC_SAMPLE_TIME_71_5: ADC 71.5 clock cycles
* @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles
*
* @retval None
*/
void ADC_ConfigChannel(uint32_t channel, uint8_t sampleTime)
{
ADC->CHSEL |= (uint32_t)channel;
ADC->SMPTIM |= (uint8_t)sampleTime;
}
/*!
* @brief Enables the continuous mode
*
* @param None
*
* @retval None
*/
void ADC_EnableContinuousMode(void)
{
ADC->CFG1_B.CMODESEL = BIT_SET;
}
/*!
* @brief Disables the continuous mode
*
* @param None
*
* @retval None
*/
void ADC_DisableContinuousMode(void)
{
ADC->CFG1_B.CMODESEL = BIT_RESET;
}
/*!
* @brief Enables the discontinuous mode
*
* @param None
*
* @retval None
*/
void ADC_EnableDiscMode(void)
{
ADC->CFG1_B.DISCEN = BIT_SET;
}
/*!
* @brief Disables the discontinuous mode
*
* @param None
*
* @retval None
*/
void ADC_DisableDiscMode(void)
{
ADC->CFG1_B.DISCEN = BIT_RESET;
}
/*!
* @brief Enables the Overrun mode
*
* @param None
*
* @retval None
*/
void ADC_EnableOverrunMode(void)
{
ADC->CFG1_B.OVRMAG = BIT_SET;
}
/*!
* @brief Disables the Overrun mode
*
* @param None
*
* @retval None
*/
void ADC_DisableOverrunMode(void)
{
ADC->CFG1_B.OVRMAG = BIT_RESET;
}
/*!
* @brief ADC Read Calibration Factor
*
* @param None
*
* @retval ADC Calibration factor
*/
uint32_t ADC_ReadCalibrationFactor(void)
{
uint32_t temp = 0, counter = 0, status = 0;
ADC->CTRL_B.CAL = BIT_SET;
do
{
status = ADC->CTRL_B.CAL;
counter++;
}
while ((counter != CALIBRATION_TIMEOUT) && (status != 0x00));
if ((uint32_t)(ADC->CTRL_B.CAL) == RESET)
{
temp = ADC->DATA;
}
else
{
temp = 0x00000000;
}
return temp;
}
/*!
* @brief ADC stop conversion command
*
* @param None
*
* @retval None
*/
void ADC_StopConversion(void)
{
ADC->CTRL_B.STOPCEN = BIT_SET;
}
/*!
* @brief ADC start conversion command
*
* @param None
*
* @retval None
*/
void ADC_StartConversion(void)
{
ADC->CTRL_B.STARTCEN = BIT_SET;
}
/*!
* @brief Returns the last ADC conversion result data
*
* @param None
*
* @retval The Data conversion value
*/
uint16_t ADC_ReadConversionValue(void)
{
return ((uint16_t)ADC->DATA);
}
/*!
* @brief Enables the ADC DMA request
*
* @param None
*
* @retval None
*/
void ADC_EnableDMA(void)
{
ADC->CFG1_B.DMAEN = BIT_SET;
}
/*!
* @brief Disables the ADC DMA request
*
* @param None
*
* @retval None
*/
void ADC_DisableDMA(void)
{
ADC->CFG1_B.DMAEN = BIT_RESET;
}
/*!
* @brief ADC DMA Request Mode
*
* @param DMARequestMode: Direct memery access configuration .
* The parameter can be one of following values:
* @arg ADC_DMA_MODE_ONESHOUT: ADC DMA Mode Select one shot
* @arg ADC_DMA_MODE_CIRCULAR: ADC DMA Mode Select circular
*
* @retval None
*/
void ADC_DMARequestMode(ADC_DMA_MODE_T DMARequestMode)
{
ADC->CFG1_B.DMACFG = (uint8_t)DMARequestMode;
}
/*!
* @brief Enables the specified interrupts
*
* @param interrupt: Specifies the ADC interrupts sources
* The parameter can be combination of following values:
* @arg ADC_INT_ADRDY: ADC ready interrupt
* @arg ADC_INT_CSMP: End of sampling interrupt
* @arg ADC_INT_CC: End of conversion interrupt
* @arg ADC_INT_CS: End of sequence interrupt
* @arg ADC_INT_OVR: ADC overrun interrupt
* @arg ADC_INT_AWD: Analog watchdog interrupt
*
* @retval None
*/
void ADC_EnableInterrupt(uint8_t interrupt)
{
ADC->INT |= (uint32_t)interrupt;
}
/*!
* @brief Disable the specified interrupts
*
* @param interrupt: Specifies the ADC interrupts sources
* The parameter can be combination of following values:
* @arg ADC_INT_ADRDY: ADC ready interrupt
* @arg ADC_INT_CSMP: End of sampling interrupt
* @arg ADC_INT_CC: End of conversion interrupt
* @arg ADC_INT_CS: End of sequence interrupt
* @arg ADC_INT_OVR: ADC overrun interrupt
* @arg ADC_INT_AWD: Analog watchdog interrupt
*
* @retval None
*/
void ADC_DisableInterrupt(uint8_t interrupt)
{
ADC->INT &= (uint32_t)~interrupt;
}
/*!
* @brief Checks whether the specified ADC flag is set or not
*
* @param flag: Specifies the flag to check
* This parameter can be one of the following values:
* @arg ADC_FLAG_ADCON: ADC enable flag
* @arg ADC_FLAG_ADCOFF: ADC disable flag
* @arg ADC_FLAG_ADCSTA: ADC start conversion flag
* @arg ADC_FLAG_ADCSTOP: ADC stop conversion flag
* @arg ADC_FLAG_ADCCAL: ADC calibration flag
* @arg ADC_FLAG_ADRDY: ADC ready flag
* @arg ADC_FLAG_CSMP: End of sampling flag
* @arg ADC_FLAG_CC: End of conversion flag
* @arg ADC_FLAG_CS: End of sequence flag
* @arg ADC_FLAG_OVR: ADC overrun flag
* @arg ADC_FLAG_AWD: Analog watchdog flag
*
* @retval The new state of flag (SET or RESET)
*/
uint8_t ADC_ReadStatusFlag(ADC_FLAG_T flag)
{
uint32_t status;
if ((uint32_t)(flag & 0x01000000))
{
status = ADC->CTRL & 0xFEFFFFFF;
}
else
{
status = ADC->STS;
}
if ((status & flag) != (uint32_t)RESET)
{
return SET;
}
return RESET;
}
/*!
* @brief Clear the specified ADC flag
*
* @param flag: Specifies the flag to check
* This parameter can be any combination of the following values:
* @arg ADC_FLAG_ADRDY: ADC ready flag
* @arg ADC_FLAG_CSMP: End of sampling flag
* @arg ADC_FLAG_CC: End of conversion flag
* @arg ADC_FLAG_CS: End of sequence flag
* @arg ADC_FLAG_OVR: ADC overrun flag
* @arg ADC_FLAG_AWD: Analog watchdog flag
*
* @retval None
*/
void ADC_ClearStatusFlag(uint32_t flag)
{
ADC->STS = (uint32_t)flag;
}
/*!
* @brief Checks whether the specified interrupt has occurred or not
*
* @param flag: Specifies the ADC interrupt pending bit to check
* The parameter can be one of following values:
* @arg ADC_INT_FLAG_ADRDY: ADC ready interrupt
* @arg ADC_INT_FLAG_CSMP: End of sampling interrupt
* @arg ADC_INT_FLAG_CC: End of conversion interrupt
* @arg ADC_INT_FLAG_CS: End of sequence interrupt
* @arg ADC_INT_FLAG_OVR: ADC overrun interrupt
* @arg ADC_INT_FLAG_AWD: Analog watchdog interrupt
*
* @retval None
*/
uint8_t ADC_ReadIntFlag(ADC_INT_FLAG_T flag)
{
uint8_t intEnable;
uint8_t intStatus;
intEnable = (uint8_t)(ADC->INT& (uint32_t)flag);
intStatus = (uint8_t)(ADC->STS & (uint32_t)(flag & 0xff));
if (intEnable && intStatus)
{
return SET;
}
return RESET;
}
/*!
* @brief Clears the specified interrupt pending bits
*
* @param flag: Specifies the ADC interrupt pending bit to check
* The parameter can be combination of following values:
* @arg ADC_INT_FLAG_ADRDY: ADC ready interrupt
* @arg ADC_INT_FLAG_CSMP: End of sampling interrupt
* @arg ADC_INT_FLAG_CC: End of conversion interrupt
* @arg ADC_INT_FLAG_CS: End of sequence interrupt
* @arg ADC_INT_FLAG_OVR: ADC overrun interrupt
* @arg ADC_INT_FLAG_AWD: Analog watchdog interrupt
*
* @retval None
*/
void ADC_ClearIntFlag(uint32_t flag)
{
ADC->STS = flag;
}
/**@} end of group ADC_Functions */
/**@} end of group ADC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_cec.c
*
* @brief This file contains all the functions for the CEC peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_cec.h"
#include "apm32f0xx_rcm.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup CEC_Driver
@{
*/
/** @defgroup CEC_Macros Macros
@{
*/
/**@} end of group CEC_Macros */
/** @defgroup CEC_Enumerations Enumerations
@{
*/
/**@} end of group CEC_Enumerations */
/** @defgroup CEC_Structures Structures
@{
*/
/**@} end of group CEC_Structures */
/** @defgroup CEC_Variables Variables
@{
*/
/**@} end of group CEC_Variables */
/** @defgroup CEC_Functions Functions
@{
*/
/*!
* @brief Reset CEC peripheral registers to their default values.
*
* @param None
*
* @retval None
*/
void CEC_Reset(void)
{
RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_CEC);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CEC);
}
/*!
* @brief Configs the CEC peripheral according to the specified parameters
* in the cecConfig.
*
* @param cecConfig: pointer to an CEC_Config_T structure that is used to
* the configuration information for the specified CEC peripheral.
*
* @retval None
*
* @note The CEC parameters must be configured before enabling the CEC peripheral.
*/
void CEC_Config(CEC_Config_T* cecConfig)
{
CEC->CFG_B.SFTCFG = cecConfig->signalFreeTime;
CEC->CFG_B.RXTCFG = cecConfig->RxTolerance;
CEC->CFG_B.RXSBRERR = cecConfig->stopReception;
CEC->CFG_B.GEBRERR = cecConfig->bitRisingError;
CEC->CFG_B.GELBPERR = cecConfig->longPeriodError;
CEC->CFG_B.AEBGIB = cecConfig->broadcastrNoGen;
CEC->CFG_B.SFTOB = cecConfig->signalFreeTimeOption;
}
/*!
* @brief Fills each CEC_InitStruct member with its default value.
*
* @param cecConfig: pointer to a CEC_InitTypeDef structure which will
* be initialized.
*
* @retval None
*/
void CEC_ConfigStructInit(CEC_Config_T* cecConfig)
{
cecConfig->signalFreeTime = CEC_SINGANL_FREETIME_STANDARD;
cecConfig->RxTolerance = CEC_RX_TOLERANCE_STANDARD;
cecConfig->stopReception = CEC_STOP_RECEPTION_OFF;
cecConfig->bitRisingError = CEC_BIT_RISING_ERR_OFF;
cecConfig->longPeriodError = CEC_LONG_PERIOD_ERR_OFF;
cecConfig->broadcastrNoGen = CEC_BROADCAST_NO_ERR_OFF;
cecConfig->signalFreeTimeOption = CEC_SIGNAL_FREETIME_OPTION_OFF;
}
/*!
* @brief Enables the CEC peripheral.
*
* @param None
*
* @retval None
*/
void CEC_Enable(void)
{
CEC->CTRL_B.CECEN = SET;
}
/*!
* @brief Disables the CEC peripheral.
*
* @param None
*
* @retval None
*/
void CEC_Disable(void)
{
CEC->CTRL_B.CECEN = RESET;
}
/*!
* @brief Enables the CEC Listen Mode.
*
* @param None
*
* @retval None
*/
void CEC_EnableListenMode(void)
{
CEC->CFG_B.LMODSEL = SET;
}
/*!
* @brief Disables the CEC Listen Mode.
*
* @param None
*
* @retval None
*/
void CEC_DisableListenMode(void)
{
CEC->CFG_B.LMODSEL = RESET;
}
/*!
* @brief Defines the Own Address of the CEC device.
*
* @param ownAddress: The CEC own address.
*
* @retval None
*/
void CEC_ConfigOwnAddress(uint8_t ownAddress)
{
CEC->CFG_B.OACFG |= (1 << ownAddress);
}
/*!
* @brief Clears the Own Address of the CEC device.
*
* @param CEC_OwnAddress: The CEC own address.
*
* @retval None
*/
void CEC_ClearQwnAddress(void)
{
CEC->CFG = 0x00;
}
/*!
* @brief Transmits single data through the CEC peripheral.
*
* @param Data: the data to transmit.
*
* @retval None
*/
void CEC_TxData(uint8_t Data)
{
CEC->TXDATA = Data;
}
/*!
* @brief Returns the most recent received data by the CEC peripheral.
*
* @param None
*
* @retval The received data.
*/
uint8_t CEC_RxData(void)
{
return (uint8_t)(CEC->RXDATA);
}
/*!
* @brief Starts a new message.
*
* @param None
*
* @retval None
*/
void CEC_StartNewMessage(void)
{
CEC->CTRL_B.TXSM = SET;
}
/*!
* @brief Transmits message with an EOM bit.
*
* @param None
*
* @retval None
*/
void CEC_CompleteMessage(void)
{
CEC->CTRL_B.TXEM = SET;
}
/*!
* @brief Enables the selected CEC interrupts.
*
* @param flag: specifies the CEC interrupt source to be enabled.
* This parameter can be any combination of the following values:
* @arg CEC_INT_RXBR Rx-Byte Received
* @arg CEC_INT_RXEND End Of Reception
* @arg CEC_INT_RXOVR Rx Overrun.
* @arg CEC_INT_BRE Rx Bit Rising Error
* @arg CEC_INT_SBPE Rx Short period Error
* @arg CEC_INT_LBPE Rx Long period Error
* @arg CEC_INT_RXACKE Rx-Missing Acknowledge
* @arg CEC_INT_ARBLST Arbitration Lost
* @arg CEC_INT_TXBR Tx-Byte Request.
* @arg CEC_INT_TXEND End of Transmission
* @arg CEC_INT_TXUDR Tx-Buffer Underrun.
* @arg CEC_INT_TXERR Tx Error.
* @arg CEC_INT_TXACKE Tx Missing acknowledge Error
*
* @retval None
*/
void CEC_EnableInterrupt(uint32_t interrupt)
{
CEC->INTEN |= (uint32_t)interrupt;
}
/*!
* @brief Disables the selected CEC interrupts.
*
* @param flag: specifies the CEC interrupt source to be enabled.
* This parameter can be any combination of the following values:
* @arg CEC_INT_RXBR Rx-Byte Received
* @arg CEC_INT_RXEND End Of Reception
* @arg CEC_INT_RXOVR Rx Overrun.
* @arg CEC_INT_BRE Rx Bit Rising Error
* @arg CEC_INT_SBPE Rx Short period Error
* @arg CEC_INT_LBPE Rx Long period Error
* @arg CEC_INT_RXACKE Rx-Missing Acknowledge
* @arg CEC_INT_ARBLST Arbitration Lost
* @arg CEC_INT_TXBR Tx-Byte Request.
* @arg CEC_INT_TXEND End of Transmission
* @arg CEC_INT_TXUDR Tx-Buffer Underrun.
* @arg CEC_INT_TXERR Tx Error.
* @arg CEC_INT_TXACKE Tx Missing acknowledge Error
*
* @retval None
*/
void CEC_DisableInterrupt(uint32_t interrupt)
{
CEC->INTEN &= ~(uint32_t)interrupt;
}
/*!
* @brief Read the CEC flag status.
*
* @param flag: specifies the CEC interrupt source to be enabled.
* This parameter can be any combination of the following values:
* @arg CEC_FLAG_RXBR Rx-Byte Received
* @arg CEC_FLAG_RXEND End Of Reception
* @arg CEC_FLAG_RXOVR Rx Overrun.
* @arg CEC_FLAG_BRE Rx Bit Rising Error
* @arg CEC_FLAG_SBPE Rx Short period Error
* @arg CEC_FLAG_LBPE Rx Long period Error
* @arg CEC_FLAG_RXACKE Rx-Missing Acknowledge
* @arg CEC_FLAG_ARBLST Arbitration Lost
* @arg CEC_FLAG_TXBR Tx-Byte Request.
* @arg CEC_FLAG_TXEND End of Transmission
* @arg CEC_FLAG_TXUDR Tx-Buffer Underrun.
* @arg CEC_FLAG_TXERR Tx Error.
* @arg CEC_FLAG_TXACKE Tx Missing acknowledge Error
*
* @retval The new state of CEC_FLAG (SET or RESET)
*/
uint8_t CEC_ReadStatusFlag(uint32_t flag)
{
uint32_t status;
status = (uint32_t)(CEC->STS & flag);
if (status == flag)
{
return SET;
}
return RESET;
}
/*!
* @brief Clears the CEC's pending flags.
*
* @param flag: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg CEC_FLAG_RXBR Rx-Byte Received
* @arg CEC_FLAG_RXEND End Of Reception
* @arg CEC_FLAG_RXOVR Rx Overrun.
* @arg CEC_FLAG_BRE Rx Bit Rising Error
* @arg CEC_FLAG_SBPE Rx Short period Error
* @arg CEC_FLAG_LBPE Rx Long period Error
* @arg CEC_FLAG_RXACKE Rx-Missing Acknowledge
* @arg CEC_FLAG_ARBLST Arbitration Lost
* @arg CEC_FLAG_TXBR Tx-Byte Request.
* @arg CEC_FLAG_TXEND End of Transmission
* @arg CEC_FLAG_TXUDR Tx-Buffer Underrun.
* @arg CEC_FLAG_TXERR Tx Error.
* @arg CEC_FLAG_TXACKE Tx Missing acknowledge Error
*
* @retval None
*/
void CEC_ClearStatusFlag(uint32_t flag)
{
CEC->STS = flag;
}
/*!
* @brief Checks whether the specified CEC interrupt has occurred or not.
*
* @param flag: specifies the CEC interrupt source to check.
* This parameter can be one of the following values:
* @arg CEC_INT_RXBR Rx-Byte Received
* @arg CEC_INT_RXEND End Of Reception
* @arg CEC_INT_RXOVR Rx Overrun.
* @arg CEC_INT_BRE Rx Bit Rising Error
* @arg CEC_INT_SBPE Rx Short period Error
* @arg CEC_INT_LBPE Rx Long period Error
* @arg CEC_INT_RXACKE Rx-Missing Acknowledge
* @arg CEC_INT_ARBLST Arbitration Lost
* @arg CEC_INT_TXBR Tx-Byte Request.
* @arg CEC_INT_TXEND End of Transmission
* @arg CEC_INT_TXUDR Tx-Buffer Underrun.
* @arg CEC_INT_TXERR Tx Error.
* @arg CEC_INT_TXACKE Tx Missing acknowledge Error
*
* @retval The new state of Flag (SET or RESET).
*/
uint8_t CEC_ReadIntFlag(uint16_t flag)
{
uint32_t intEnable;
uint32_t intStatus;
intEnable = (CEC->INTEN & flag);
intStatus = (CEC->STS & flag);
if ((intStatus != (uint32_t)RESET) && intEnable)
{
return SET;
}
else
{
return RESET;
}
}
/*!
* @brief Clears the CEC's interrupt flag.
*
* @param flag: specifies the CEC interrupt flag to clear.
* This parameter can be any combination of the following values:
* @arg CEC_INT_RXBR Rx-Byte Received
* @arg CEC_INT_RXEND End Of Reception
* @arg CEC_INT_RXOVR Rx Overrun.
* @arg CEC_INT_BRE Rx Bit Rising Error
* @arg CEC_INT_SBPE Rx Short period Error
* @arg CEC_INT_LBPE Rx Long period Error
* @arg CEC_INT_RXACKE Rx-Missing Acknowledge
* @arg CEC_INT_ARBLST Arbitration Lost
* @arg CEC_INT_TXBR Tx-Byte Request.
* @arg CEC_INT_TXEND End of Transmission
* @arg CEC_INT_TXUDR Tx-Buffer Underrun.
* @arg CEC_INT_TXERR Tx Error.
* @arg CEC_INT_TXACKE Tx Missing acknowledge Error
*
* @retval None
*/
void CEC_ClearIntFlag(uint16_t flag)
{
CEC->STS = flag;
}
/**@} end of group CEC_Functions */
/**@} end of group CEC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_comp.c
*
* @brief This file contains all the functions for the COMP peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_comp.h"
#include "apm32f0xx_rcm.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup COMP_Driver
@{
*/
/** @defgroup COMP_Macros Macros
@{
*/
/**@} end of group COMP_Macros */
/** @defgroup COMP_Enumerations Enumerations
@{
*/
/**@} end of group COMP_Enumerations */
/** @defgroup COMP_Structures Structures
@{
*/
/**@} end of group COMP_Structures */
/** @defgroup COMP_Variables Variables
@{
*/
/**@} end of group COMP_Variables */
/** @defgroup COMP_Functions Functions
@{
*/
/*!
* @brief Reset COMP peripheral registers to their default values.
*
* @param None
*
* @retval None
*
* @note Deinitialization can't be performed if the COMP configuration is locked.
* To unlock the configuration, perform a system reset.
*/
void COMP_Reset(void)
{
COMP->CSTS = ((uint32_t)0x00000000);
}
/*!
* @brief Configs the COMP peripheral according to the specified parameters
* in COMP_InitStruct
*
* @param compSelect: the selected comparator.
* This parameter can be one of the following values:
* @arg COMP_SELECT_COMP1: COMP1 selected
* @arg COMP_SELECT_COMP2: COMP2 selected
*
* @param compConfig: pointer to an COMP_Config_T structure that contains
* the configuration information for the specified COMP peripheral.
*
* @retval None
*
* @note If the selected comparator is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
*
* @note By default, PA1 is selected as COMP1 non inverting input.
* To use PA4 as COMP1 non inverting input call COMP_EnableSwitch() after COMP_Config()
*
*/
void COMP_Config(COMP_SELECT_T compSelect, COMP_Config_T* compConfig)
{
if (compSelect == COMP_SELECT_COMP1)
{
COMP->CSTS_B.INVINSEL1 = compConfig->invertingInput;
COMP->CSTS_B.OUTSEL1 = compConfig->output;
COMP->CSTS_B.OPINV1 = compConfig->outputPol;
COMP->CSTS_B.HYSCFG1 = compConfig->hysterrsis;
COMP->CSTS_B.MOD1 = compConfig->mode;
}
else
{
COMP->CSTS_B.INVINSEL2 = compConfig->invertingInput;
COMP->CSTS_B.OUTSEL2 = compConfig->output;
COMP->CSTS_B.OPINV2 = compConfig->outputPol;
COMP->CSTS_B.HYSCFG2 = compConfig->hysterrsis;
COMP->CSTS_B.MOD2 = compConfig->mode;
}
}
/*!
* @brief Fills each compConfig member with initial value value.
*
* @param compConfig: pointer to an COMP_InitTypeDef structure which will
* be initialized.
*
* @retval None
*/
void COMP_ConfigStructInit(COMP_Config_T* compConfig)
{
compConfig->invertingInput = COMP_INVERTING_INPUT_1_4VREFINT;
compConfig->output = COMP_OUTPUT_NONE;
compConfig->outputPol = COMP_OUTPUTPOL_NONINVERTED;
compConfig->hysterrsis = COMP_HYSTERRSIS_NO;
compConfig->mode = COMP_MODE_HIGHSPEED;
}
/*!
* @brief Enable the COMP peripheral.
*
* @param compSelect: the selected comparator.
* This parameter can be one of the following values:
* @arg COMP_SELECT_COMP1: COMP1 selected
* @arg COMP_SELECT_COMP2: COMP2 selected
*
* @retval None
*
* @note If the selected comparator is locked, enable can't be performed.
* To unlock the configuration, perform a system reset.
*/
void COMP_Enable(COMP_SELECT_T compSelect)
{
if (compSelect == COMP_SELECT_COMP1)
{
COMP->CSTS_B.EN1 = SET;
}
else
{
COMP->CSTS_B.EN2 = SET;
}
}
/*!
* @brief Disable the COMP peripheral.
*
* @param compSelect: the selected comparator.
* This parameter can be one of the following values:
* @arg COMP_SELECT_COMP1: COMP1 selected
* @arg COMP_SELECT_COMP2: COMP2 selected
*
* @retval None
*
* @note If the selected comparator is locked, disable can't be performed.
* To unlock the configuration, perform a system reset.
*/
void COMP_Disable(COMP_SELECT_T compSelect)
{
if (compSelect == COMP_SELECT_COMP1)
{
COMP->CSTS_B.EN1 = RESET;
}
else
{
COMP->CSTS_B.EN2 = RESET;
}
}
/*!
* @brief Close the SW1 switch.
*
* @param None
*
* @retval None
*
* @note This switch is solely intended to redirect signals onto high
* impedance input, such as COMP1 non-inverting input (highly resistive switch)
*/
void COMP_EnableSwitch(void)
{
COMP->CSTS_B.SW1 = SET;
}
/*!
* @brief Open the SW1 switch.
*
* @param None
*
* @retval None
*/
void COMP_DisableSwitch(void)
{
COMP->CSTS_B.SW1 = RESET;
}
/*!
* @brief Return the output level (high or low) of the selected comparator.
*
* @param compSelect: the selected comparator.
* This parameter can be one of the following values:
* @arg COMP_SELECT_COMP1: COMP1 selected
* @arg COMP_SELECT_COMP2: COMP2 selected
*
* @retval Returns the selected comparator output level: low or high.
*/
uint32_t COMP_ReadOutPutLevel(COMP_SELECT_T compSelect)
{
uint32_t compOUT = 0x00;
if (compSelect == COMP_SELECT_COMP1)
{
if ((COMP->CSTS & COMP_CSTS_COMP1OUT) != 0)
{
compOUT = COMP_OUTPUTLEVEL_HIGH;
}
else
compOUT = COMP_OUTPUTLEVEL_LOW;
}
else
{
if ((COMP->CSTS & COMP_CSTS_COMP2OUT) != 0)
{
compOUT = COMP_OUTPUTLEVEL_HIGH;
}
else
compOUT = COMP_OUTPUTLEVEL_LOW;
}
return (uint32_t)(compOUT);
}
/*!
* @brief Enablesthe window mode.
*
* @param None
*
* @retval None
*/
void COMP_EnableWindow(void)
{
COMP->CSTS_B.WMODEN = SET;
}
/*!
* @brief Disables the window mode.
*
* @param None
*
* @retval None
*/
void COMP_DisnableWindow(void)
{
COMP->CSTS_B.WMODEN = RESET;
}
/*!
* @brief Lock the selected comparator configuration.
*
* @param compSelect: selects the comparator to be locked
* This parameter can be one of the following values:
* @arg COMP_SELECT_COMP1: COMP1 configuration is locked.
* @arg COMP_SELECT_COMP2: COMP2 configuration is locked.
*
* @retval None
*/
void COMP_ConfigLOCK(COMP_SELECT_T compSelect)
{
if (compSelect == COMP_SELECT_COMP1)
{
COMP->CSTS_B.LOCK1 = SET;
}
else
{
COMP->CSTS_B.LOCK2 = SET;
}
}
/**@} end of group COMP_Functions */
/**@} end of group COMP_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_crc.c
*
* @brief This file provides all the CRC firmware functions
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* include */
#include "apm32f0xx_crc.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup CRC_Driver
@{
*/
/** @defgroup CRC_Macros Macros
@{
*/
/**@} end of group CRC_Macros */
/** @defgroup CRC_Enumerations Enumerations
@{
*/
/**@} end of group CRC_Enumerations */
/** @defgroup CRC_Structures Structures
@{
*/
/**@} end of group CRC_Structures */
/** @defgroup CRC_Variables Variables
@{
*/
/**@} end of group CRC_Variables */
/** @defgroup CRC_Functions Functions
@{
*/
/*!
* @brief Resets the CRC peripheral registers to their default reset values.
*
* @param None
*
* @retval None
*/
void CRC_Reset(void)
{
CRC->DATA = 0xFFFFFFFF;
CRC->INDATA = 0x00;
CRC->INITVAL = 0xFFFFFFFF;
CRC->CTRL = 0x00000000;
CRC->POL = 0x04C11DB7;
}
/*!
* @brief Reset CRC data register (DATA)
*
* @param None
*
* @retval None
*/
void CRC_ResetDATA(void)
{
CRC->CTRL_B.RST = BIT_SET;
}
/*!
* @brief Set the CRC polynomial size.
*
* @param polynomialSize: CRC polynomial size
* The parameter can be one of following values:
* @arg CRC_POLYNOMIAL_SIZE_7: 7-bit polynomial for CRC calculation
* @arg CRC_POLYNOMIAL_SIZE_8: 8-bit polynomial for CRC calculation
* @arg CRC_POLYNOMIAL_SIZE_16: 16-bit polynomial for CRC calculation
* @arg CRC_POLYNOMIAL_SIZE_32: 32-bit polynomial for CRC calculation
*
* @retval None
*
* @note It's only for APM32F072 and APM32F091 devices
*/
void CRC_SetPolynomialSize(CRC_POLYNOMIAL_SIZE_T polynomialSize)
{
CRC->CTRL_B.POLSIZE = polynomialSize;
}
/*!
* @brief Set the CRC polynomail coefficients.
*
* @param polynomialValue: Polynomial to be used for CRC calculation
*
* @retval None
*
* @note It's only for APM32F072 and APM32F091 devices
*/
void CRC_SetPolynomialValue(uint32_t polynomialValue)
{
CRC->POL = polynomialValue;
}
/*!
* @brief Selects the reverse operation to be performed on input data
*
* @param revInData: Reverse input data
* The parameter can be one of following values:
* @arg CRC_REVERSE_INPUT_DATA_NO: Bit order not affected
* @arg CRC_REVERSE_INPUT_DATA_8B: Bit reversal done by byte
* @arg CRC_REVERSE_INPUT_DATA_16B: Bit reversal done by half-word
* @arg CRC_REVERSE_INPUT_DATA_32B: Bit reversal done by word
*
* @retval None
*/
void CRC_SelectReverseInputData(CRC_REVERSE_INPUT_DATA_T revInData)
{
CRC->CTRL_B.REVI = revInData;
}
/*!
* @brief Enable the reverse operation on output data
*
* @param None
*
* @retval None
*/
void CRC_EnableReverseOutputData(void)
{
CRC->CTRL_B.REVO = BIT_SET;
}
/*!
* @brief Disable the reverse operation on output data
*
* @param None
*
* @retval None
*/
void CRC_DisableReverseOutputData(void)
{
CRC->CTRL_B.REVO = BIT_RESET;
}
/*!
* @brief Initializes the INITVAL register.
*
* @param initValue: Programmable initial CRC value
*
* @retval None
*/
void CRC_WriteInitRegister(uint32_t initValue)
{
CRC->INITVAL = initValue;
}
/*!
* @brief Calculate a 32-bit CRC for a given data word (32 bits)
*
* @param data: data word(32-bit) to compute its CRC
*
* @retval 32-bit CRC
*/
uint32_t CRC_CalculateCRC(uint32_t data)
{
CRC->DATA = data;
return (CRC->DATA);
}
/*!
* @brief Calculate a 32-bit CRC for a given data word (16 bits)
*
* @param data: data word(16-bit) to compute its CRC
*
* @retval 16-bit CRC
*
* @note It's only for APM32F072 and APM32F091 devices
*/
uint32_t CRC_CalculateCRC16bits(uint16_t data)
{
*(uint16_t*)(CRC_BASE) = (uint16_t) data;
return (CRC->DATA);
}
/*!
* @brief Calculate a 32-bit CRC for a given data word (8 bits)
*
* @param data: data word(8-bit) to compute its CRC
*
* @retval 8-bit CRC
*
* @note It's only for APM32F072 and APM32F091 devices
*/
uint32_t CRC_CalculateCRC8bits(uint8_t data)
{
*(uint8_t*)(CRC_BASE) = (uint8_t) data;
return (CRC->DATA);
}
/*!
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit)
*
* @param pBuffer: Pointer to the buffer containing the data to be computed
*
* @param bufferLength: buffer length
*
* @retval 32-bit CRC
*/
uint32_t CRC_CalculateBlockCRC(uint32_t pBuffer[], uint32_t bufferLength)
{
uint32_t index = 0;
for (index = 0; index < bufferLength; index++)
{
CRC->DATA = pBuffer[index];
}
return (CRC->DATA);
}
/*!
* @brief Returns the current CRC value
*
* @param None
*
* @retval 32-bit CRC
*/
uint32_t CRC_ReadCRC(void)
{
return (CRC->DATA);
}
/*!
* @brief Stores a 8-bit data in the Independent Data(INDATA) register
*
* @param IDValue: 8-bit value to be stored in the INDATA register
*
* @retval None
*/
void CRC_WriteIDRegister(uint8_t IDValue)
{
CRC->INDATA = IDValue;
}
/*!
* @brief Returns a 8-bit data stored in the Independent Data(INDATA) register
*
* @param None
*
* @retval 8-bit value of the INDATA register
*/
uint8_t CRC_ReadIDRegister(void)
{
return (CRC->INDATA);
}
/**@} end of group CRC_Functions */
/**@} end of group CRC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_crs.c
*
* @brief This file contains all the functions for the CRS peripheral
*
* @note It's only for APM32F072 and APM32F091 devices
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_crs.h"
#include "apm32f0xx_rcm.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup CRS_Driver
@{
*/
/** @defgroup CRS_Macros Macros
@{
*/
/**@} end of group CRS_Macros */
/** @defgroup CRS_Enumerations Enumerations
@{
*/
/**@} end of group CRS_Enumerations */
/** @defgroup CRS_Structures Structures
@{
*/
/**@} end of group CRS_Structures */
/** @defgroup CRS_Variables Variables
@{
*/
/**@} end of group CRS_Variables */
/** @defgroup CRS_Functions Functions
@{
*/
/*!
* @brief Resets the CRS peripheral registers to their default reset values.
*
* @param None
*
* @retval None
*/
void CRS_Reset(void)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_CRS);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CRS);
}
/*!
* @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
*
* @param calibrationVal: HSI48 oscillator smooth trimming value. It can be 0x0 to 0xF.
*
* @retval None
*/
void CRS_AdjustHSI48CalibrationValue(uint8_t calibrationVal)
{
CRS->CTRL_B.HSI48TRM = calibrationVal;
}
/*!
* @brief Enables the oscillator clock for frequency error counter.
*
* @param None
*
* @retval None
*/
void CRS_EnableFrequencyErrorCounter(void)
{
CRS->CTRL_B.CNTEN = SET;
}
/*!
* @brief Disables the oscillator clock for frequency error counter.
*
* @param None
*
* @retval None
*/
void CRS_DisableFrequencyErrorCounter(void)
{
CRS->CTRL_B.CNTEN = RESET;
}
/*!
* @brief Enables the automatic hardware adjustement of HSI48TRM bits.
*
* @param None
*
* @retval None
*/
void CRS_EnableAutomaticCalibration(void)
{
CRS->CTRL_B.AUTOTRMEN = SET;
}
/*!
* @brief Disables the automatic hardware adjustement of HSI48TRM bits.
*
* @param None
*
* @retval None
*/
void CRS_DisableAutomaticCalibration(void)
{
CRS->CTRL_B.AUTOTRMEN = RESET;
}
/*!
* @brief Generate the software synchronization event.
*
* @param None
*
* @retval None
*/
void CRS_GenerateSoftwareSynchronization(void)
{
CRS->CTRL_B.SWSGNR = SET;
}
/*!
* @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
*
* @param reloadVal: specifies the HSI calibration trimming value.
* This parameter must be a number between 0 and 0xFFFF.
*
* @retval None
*/
void CRS_FrequencyErrorCounterReloadValue(uint16_t reloadVal)
{
CRS->CFG_B.RLDVAL = reloadVal;
}
/**
* @brief Configs the frequency error limit value.
*
* @param errLimitVal: specifies the HSI calibration trimming value.
*
* @retval None
*/
void CRS_ConfigFrequencyErrorLimit(uint8_t errLimitVal)
{
CRS->CFG_B.FELMT = errLimitVal;
}
/*!
* @brief Configs SYNC divider.
*
* @param div: defines the SYNC divider.
* This parameter can be one of the following values:
* @arg CRS_SYNC_DIV1
* @arg CRS_SYNC_DIV2
* @arg CRS_SYNC_DIV4
* @arg CRS_SYNC_DIV8
* @arg CRS_SYNC_DIV16
* @arg CRS_SYNC_DIV32
* @arg CRS_SYNC_DIV64
* @arg CRS_SYNC_DIV128
*
* @retval None
*/
void CRS_ConfigSynchronizationPrescaler(CRS_SYNC_DIV_T div)
{
CRS->CFG_B.SYNCPSC = div;
}
/*!
* @brief Configs the SYNC signal source.
*
* @param source: specifies the SYNC signal source.
* This parameter can be one of the following values:
* @arg CRS_SYNC_SOURCE_GPIO
* @arg CRS_SYNC_SOURCE_LSE
* @arg CRS_SYNC_SOURCE_USB
*
* @retval None
*/
void CRS_ConfigSynchronizationSource(CRS_SYNC_SOURCE_T source)
{
CRS->CFG_B.SYNCSRCSEL = source;
}
/*!
* @brief Configs the SYNC polarity.
*
* @param polarity: specifies SYNC polarity.
* This parameter can be one of the following values:
* @arg CRS_SYNC_POL_RISING
* @arg CRS_SYNC_POL_FALLING
*
* @retval None
*/
void CRS_ConfigSynchronizationPolarity(CRS_SYNC_POL_T polarity)
{
CRS->CFG_B.SYNCPOLSEL = polarity;
}
/*!
* @brief Returns the Relaod value.
*
* @param None
*
* @retval The reload value
*/
uint32_t CRS_ReadReloadValue(void)
{
return (uint32_t)CRS->CFG_B.RLDVAL;
}
/*!
* @brief Returns the HSI48 Calibration value.
*
* @param None
*
* @retval The reload value
*/
uint32_t CRS_ReadHSI48CalibrationValue(void)
{
return (uint32_t)CRS->CTRL_B.HSI48TRM;
}
/*!
* @brief Returns the frequency error capture.
*
* @param None
*
* @retval The frequency error capture value
*/
uint32_t CRS_ReadFrequencyErrorValue(void)
{
return (uint32_t)CRS->INTSTS_B.FECPT;
}
/*!
* @brief Returns the frequency error direction.
*
* @param None
*
* @retval The frequency error direction.
* The returned value can be one of the following values:
* 0: Up counting
* 1: Down counting
*/
uint32_t CRS_ReadFrequencyErrorDirection(void)
{
return (uint32_t)CRS->INTSTS_B.CNTDRCT;
}
/*!
* @brief Enables the specified CRS interrupts.
*
* @param interrupt: specifies the RCC interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg CRS_INT_SYNCOK : SYNC event OK interrupt
* @arg CRS_INT_SYNCWARN: SYNC warning interrupt
* @arg CRS_INT_ERR : Synchronization or trimming error interrupt
* @arg CRS_INT_ESYNC : Expected SYNC interrupt
*
* @retval None
*/
void CRS_EnableInterrupt(CRS_INT_T interrupt)
{
CRS->CTRL |= interrupt;
}
/*!
* @brief Disables the specified CRS interrupts.
*
* @param interrupt: specifies the RCC interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg CRS_INT_SYNCOK : SYNC event OK interrupt
* @arg CRS_INT_SYNCWARN: SYNC warning interrupt
* @arg CRS_INT_ERR : Synchronization or trimming error interrupt
* @arg CRS_INT_ESYNC : Expected SYNC interrupt
*
* @retval None
*/
void CRS_DisableInterrupt(CRS_INT_T interrupt)
{
CRS->CTRL &= ~interrupt;
}
/*!
* @brief Checks whether the specified CRS flag is set or not.
*
* @param flag: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CRS_FLAG_SYNCOK : SYNC event OK flag
* @arg CRS_FLAG_SYNCWARN: SYNC warning flag
* @arg CRS_FLAG_ERR : Synchronization or trimming error flag
* @arg CRS_FLAG_ESYNC : Expected SYNC flag
* @arg CRS_FLAG_SYNCERR : SYNC error flag
* @arg CRS_FLAG_SYNCMISS: SYNC missed flag
* @arg CRS_FLAG_TRIMOVF : Trimming overflow or underflow falg
*
* @retval The new state of CRS_FLAG (SET or RESET).
*/
uint8_t CRS_ReadStatusFlag(CRS_FLAG_T flag)
{
uint32_t status;
status = (uint32_t)(CRS->INTSTS & flag);
if (status == flag)
{
return SET;
}
return RESET;
}
/*!
* @brief Clears the CRS specified flag.
*
* @param flag: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CRS_FLAG_SYNCOK : SYNC event OK flag
* @arg CRS_FLAG_SYNCWARN: SYNC warning flag
* @arg CRS_FLAG_ERR : Synchronization or trimming error flag
* @arg CRS_FLAG_ESYNC : Expected SYNC flag
* @arg CRS_FLAG_SYNCERR : SYNC error flag
* @arg CRS_FLAG_SYNCMISS: SYNC missed flag
* @arg CRS_FLAG_TRIMOVF : Trimming overflow or underflow falg
*
* @retval None
*/
void CRS_ClearStatusFlag(CRS_FLAG_T flag)
{
if ((flag & 0x00000700) != 0)
{
CRS->INTCLR_B.ECLR = BIT_SET;
}
CRS->INTCLR |= (uint32_t)flag;
}
/*!
* @brief Checks CRS interrupt flag.
*
* @param flag: specifies the IT pending bit to check.
* This parameter can be one of the following values:
* @arg CRS_INT_SYNCOK : SYNC event OK interrupt
* @arg CRS_INT_SYNCWARN: SYNC warning interrupt
* @arg CRS_INT_ERR : Synchronization or trimming error interrupt
* @arg CRS_INT_ESYNC : Expected SYNC interrupt
* @arg CRS_INT_SYNCERR : SYNC error
* @arg CRS_INT_SYNCMISS: SYNC missed
* @arg CRS_INT_TRIMOVF : Trimming overflow or underflow
*
* @retval The new state of CRS_IT (SET or RESET).
*/
uint8_t CRS_ReadIntFlag(CRS_INT_T flag)
{
if ((CRS->INTSTS & flag))
{
return SET;
}
else
{
return RESET;
}
}
/*!
* @brief Clears the CRS specified interrupt flag.
*
* @param intFlag: specifies the IT pending bi to clear.
* This parameter can be one of the following values:
* @arg CRS_INT_SYNCOK : SYNC event OK interrupt
* @arg CRS_INT_SYNCWARN: SYNC warning interrupt
* @arg CRS_INT_ERR : Synchronization or trimming error interrupt
* @arg CRS_INT_ESYNC : Expected SYNC interrupt
* @arg CRS_INT_SYNCERR : SYNC error
* @arg CRS_INT_SYNCMISS: SYNC missed
* @arg CRS_INT_TRIMOVF : Trimming overflow or underflow
*
* @retval None
*/
void CRS_ClearIntFlag(CRS_INT_T intFlag)
{
if ((intFlag & (uint32_t)0x700) != 0)
{
CRS->INTCLR |= CRS_INT_ERR;
}
else
{
CRS->INTCLR |= intFlag;
}
}
/**@} end of group CRS_Functions */
/**@} end of group CRS_Driver*/
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_dac.c
*
* @brief This file contains all the functions for the DAC peripheral
*
* @note It's only for APM32F051,APM32F072,APM32F091 devices
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_dac.h"
#include "apm32f0xx_rcm.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup DAC_Driver
@{
*/
/** @defgroup DAC_Macros Macros
@{
*/
/**@} end of group DAC_Macros */
/** @defgroup DAC_Enumerations Enumerations
@{
*/
/**@} end of group DAC_Enumerations */
/** @defgroup DAC_Structures Structures
@{
*/
/**@} end of group DAC_Structures */
/** @defgroup DAC_Variables Variables
@{
*/
/**@} end of group DAC_Variables */
/** @defgroup DAC_Functions Functions
@{
*/
/*!
* @brief Resets the DAC peripheral registers to their default reset values.
*
* @param None
*
* @retval None
*/
void DAC_Reset(void)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_DAC);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_DAC);
}
/*!
* @brief Initializes the DAC peripheral according to the specified parameters in the dacConfig.
*
* @param channel: the selected DAC channel.
* This parameter can be:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
*
* @param dacConfig: pointer to a DAC_Config_T structure that contains
* the configuration information for the specified DAC channel.
*
* @retval None
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig)
{
uint32_t tmpcfg;
tmpcfg = ((uint32_t)dacConfig->trigger | \
(uint32_t)dacConfig->waveGeneration | \
(uint32_t)dacConfig->maskAmplitudeSelect | \
(uint32_t)dacConfig->outputBuff);
DAC->CTRL = (tmpcfg << channel);
}
/*!
* @brief Fills each DAC_InitStruct member with its default value.
*
* @param dacConfig: pointer to a DAC_InitTypeDef structure which will
* be configed.
*
* @retval None
*/
void DAC_ConfigStructInit(DAC_Config_T* dacConfig)
{
dacConfig->trigger = DAC_TRIGGER_NONE;
dacConfig->waveGeneration = DAC_WAVE_GENERATION_NONE;
dacConfig->maskAmplitudeSelect = DAC_LFSRUNAMASK_BIT0;
dacConfig->outputBuff = DAC_OUTPUTBUFF_ENABLE;
}
/*!
* @brief Enables the specified DAC channel.
*
* @param channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @retval None
*
* @note When the DAC channel is enabled the trigger source can no more be modified.
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
void DAC_Enable(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.ENCH1 = SET;
}
else
{
DAC->CTRL_B.ENCH2 = SET;
}
}
/*!
* @brief Disables the specified DAC channel.
*
* @param channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @retval None
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
void DAC_Disable(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.ENCH1 = RESET;
}
else
{
DAC->CTRL_B.ENCH2 = RESET;
}
}
/*!
* @brief Enables the selected DAC channel software trigger.
*
* @param channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @retval None
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->SWTRG_B.SWTRG1 = SET;
}
else
{
DAC->SWTRG_B.SWTRG2 = SET;
}
}
/*!
* @brief Disable the selected DAC channel software trigger.
*
* @param channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @retval None
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->SWTRG_B.SWTRG1 = RESET;
}
else
{
DAC->SWTRG_B.SWTRG2 = RESET;
}
}
/*!
* @brief Enables simultaneously the two DAC channels software triggers.
*
* @param None
*
* @retval None
*
* @note This function is only for APM32F072 and APM32F091 devices
*/
void DAC_EnableDualSoftwareTrigger(void)
{
DAC->SWTRG |= DUAL_SWTRIG_SET;
}
/*!
* @brief Disables simultaneously the two DAC channels software triggers.
*
* @param None
*
* @retval None
*
* @note This function is only for APM32F072 and APM32F091 devices
*/
void DAC_DisableDualSoftwareTrigger(void)
{
DAC->SWTRG &= DUAL_SWTRIG_RESET;
}
/*!
* @brief Enables the selected DAC channel wave generation.
*
* @param channel: The selected DAC channel.
* This parameter can be:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @param wave: specifies the wave type to enable or disable.
* This parameter can be:
* @arg DAC_WAVE_GENERATION_NOISE: noise wave generation
* @arg DAC_WAVE_GENERATION_TRIANGLE: triangle wave generation
*
* @retval None
*
* @note This function is only for APM32F072 and APM32F091 devices
*/
void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave)
{
DAC->CTRL |= ((uint32_t)wave) << ((uint32_t)channel);
}
/*!
* @brief Disable the selected DAC channel wave generation.
*
* @param channel: The selected DAC channel.
* This parameter can be:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @param wave: specifies the wave type to enable or disable.
* This parameter can be:
* @arg DAC_WAVE_GENERATION_NOISE: noise wave generation
* @arg DAC_WAVE_GENERATION_TRIANGLE: triangle wave generation
*
* @retval None
*
* @note This function is only for APM32F072 and APM32F091 devices
*/
void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave)
{
DAC->CTRL &= ~((uint32_t)wave) << ((uint32_t)channel);
}
/*!
* @brief Sets the specified data holding register value for DAC channel1.
*
* @param dataAlign: Specifies the data alignment for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
*
* @param data: Data to be loaded in the selected data holding register.
*
* @retval None
*/
void DAC_ConfigChannel1Data(DAC_DATA_ALIGN_T dataAlign, uint16_t data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)DAC_BASE;
tmp += DH12RCH1_OFFSET + dataAlign;
*(__IO uint32_t*) tmp = data;
}
/*!
* @brief Sets the specified data holding register value for DAC channel2.
*
* @param dataAlign: Specifies the data alignment for DAC channel2.
* This parameter can be:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
*
* @param data: Data to be loaded in the selected data holding register.
*
* @retval None
*
* @note This function is only for APM32F072 and APM32F091 devices
*/
void DAC_ConfigChannel2Data(DAC_DATA_ALIGN_T dataAlign, uint16_t data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)DAC_BASE;
tmp += DH12RCH2_OFFSET + dataAlign;
*(__IO uint32_t*)tmp = data;
}
/*!
* @brief Sets the specified data holding register value for dual channel DAC.
*
* @param dataAlign: Specifies the data alignment for dual channel DAC.
* This parameter can be:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param data2: Data for DAC Channel2 to be loaded in the selected data holding register.
* @param data1: Data for DAC Channel1 to be loaded in the selected data holding register.
*
* @retval None
*
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
*
* @note This function is only for APM32F072 and APM32F091 devices
*/
void DAC_ConfigDualChannelData(DAC_DATA_ALIGN_T dataAlign, uint16_t data2, uint16_t data1)
{
uint32_t data = 0, tmp = 0;
if (dataAlign == DAC_ALIGN_8B_R)
{
data = ((uint32_t)data2 << 8) | data1;
}
else
{
data = ((uint32_t)data2 << 16) | data1;
}
tmp = (uint32_t)DAC_BASE;
tmp += DH12RD_OFFSET + dataAlign;
*(__IO uint32_t*)tmp = data;
}
/*!
* @brief Returns the last data output value of the selected DAC channel.
*
* @param channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @retval The selected DAC channel data output value.
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel)
{
uint16_t data;
if (channel == DAC_CHANNEL_1)
{
data = DAC->DATAOCH1_B.DATA;
}
else
{
data = DAC->DATAOCH2_B.DATA;
}
return data;
}
/*!
* @brief Enables the specified DAC channel DMA request.
* When enabled DMA1 is generated when an external trigger (EINT Line9,
* TMR2, TMR3, TMR6 or TMR15 but not a software trigger) occurs
* @param channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @retval None
*
* @note The DAC channel1 is mapped on DMA1 channel3 which must be already configured.
*
* @note The DAC channel2 is mapped on DMA1 channel4 which must be already configured.
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
void DAC_EnableDMA(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.DMAENCH1 = SET;
}
else
{
DAC->CTRL_B.DMAENCH2 = SET;
}
}
/*!
* @brief Disable the specified DAC channel DMA request.
*
* @param channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @retval None
*
* @note The DAC channel1 is mapped on DMA1 channel3 which must be already configured.
*
* @note The DAC channel2 is mapped on DMA1 channel4 which must be already configured.
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
void DAC_DisableDMA(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.DMAENCH1 = RESET;
}
else
{
DAC->CTRL_B.DMAENCH2 = RESET;
}
}
/*!
* @brief Enables the specified DAC interrupts.
*
* @param channel: The selected DAC channel.
* This parameter can be:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @retval None
*
* @note The DMA underrun occurs when a second external trigger arrives before the
* acknowledgement for the first external trigger is received (first request).
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
void DAC_EnableInterrupt(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.DMAUDRIEN1 = SET;
}
else
{
DAC->CTRL_B.DMAUDRIEN2 = SET;
}
}
/*!
* @brief Disables the specified DAC interrupts.
*
* @param channel: The selected DAC channel.
* This parameter can be:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
*
* @retval None
*
* @note The DMA underrun occurs when a second external trigger arrives before the
* acknowledgement for the first external trigger is received (first request).
*
* @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices
*/
void DAC_DisableInterrupt(DAC_CHANNEL_T channel)
{
if (channel == DAC_CHANNEL_1)
{
DAC->CTRL_B.DMAUDRIEN1 = RESET;
}
else
{
DAC->CTRL_B.DMAUDRIEN2 = RESET;
}
}
/*!
* @brief Reads the DAC status flag.
*
* @param flag: specifies the flag to check.
* This parameter can be only of the following value:
* @arg DAC_FLAG_CH1_DMAUDR: DMA Channel1 underrun flag
* @arg DAC_FLAG_CH2_DMAUDR: DMA Channel2 underrun flag, only for APM32F072 and APM32F091 devices
*
* @retval The new state of DAC flag (SET or RESET).
*
* @note The DMA underrun occurs when a second external trigger arrives before the
* acknowledgement for the first external trigger is received (first request).
*/
uint8_t DAC_ReadStatusFlag(DAC_FLAG_T flag)
{
uint16_t status;
status = (uint16_t)(DAC->STS & flag);
if (status == flag)
{
return SET;
}
else
return RESET;
}
/*!
* @brief Clears the DAC status flags.
*
* @param flag: specifies the flag to check.
* This parameter can be only of the following value:
* @arg DAC_FLAG_CH1_DMAUDR: DMA Channel1 underrun flag
* @arg DAC_FLAG_CH2_DMAUDR: DMA Channel2 underrun flag, , only for APM32F072 and APM32F091 devices
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
*
* @retval None
*/
void DAC_ClearStatusFlag(DAC_FLAG_T flag)
{
DAC->STS &= (uint32_t)~flag;
}
/*!
* @brief Reads teh DAC interrupt flag.
*
* @param intFlag: specifies the DAC interrupt source to check.
* This parameter can be the following values:
* @arg DAC_INT_CH1_DMAUDR: DMA Channel1 underrun interrupt mask
* @arg DAC_INT_CH2_DMAUDR: DMA Channel2 underrun interrupt mask, , only for APM32F072 and APM32F091 devices
*
* @retval The new state of DAC interrupt flag (SET or RESET).
*
* @note The DMA underrun occurs when a second external trigger arrives before the
* acknowledgement for the first external trigger is received (first request).
*/
uint8_t DAC_ReadIntFlag(DAC_INT_T intFlag)
{
uint32_t intEnable;
intEnable = (DAC->CTRL & intFlag);
if (((DAC->STS & intFlag) != (uint32_t)RESET) && intEnable)
{
return SET;
}
else
{
return RESET;
}
}
/*!
* @brief Clears the DAC channel's interrupt flag.
*
* @param intFlag: specifies the DAC interrupt pending bit to clear.
* This parameter can be the following values:
* @arg DAC_INT_CH1_DMAUDR: DMA Channel1 underrun interrupt mask
* @arg DAC_INT_CH2_DMAUDR: DMA Channel2 underrun interrupt mask, , only for APM32F072 and APM32F091 devices
*
* @retval None
*/
void DAC_ClearIntFlag(DAC_INT_T intFlag)
{
DAC->STS = intFlag;
}
/**@} end of group DAC_Functions */
/**@} end of group DAC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_dbg.c
*
* @brief This file provides all the DBG firmware functions
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_dbg.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup DBG_Driver
@{
*/
/** @defgroup DBG_Macros Macros
@{
*/
/**@} end of group DBG_Macros */
/** @defgroup DBG_Enumerations Enumerations
@{
*/
/**@} end of group DBG_Enumerations*/
/** @defgroup DBG_Structures Structures
@{
*/
/**@} end of group DBG_Structures */
/** @defgroup DBG_Variables Variables
@{
*/
/**@} end of group DBG_Variables */
/** @defgroup DBG_Functions Functions
@{
*/
/*!
* @brief Read Device Identifier
*
* @param None
*
* @retval The value of the Device Identifier
*/
uint32_t DBG_ReadDevId(void)
{
return ((uint32_t)DBG->IDCODE_B.EQR);
}
/*!
* @brief Read Revision Identifier
*
* @param None
*
* @retval The value of the Revision Identifier
*/
uint32_t DBG_ReadRevId(void)
{
return ((uint32_t)DBG->IDCODE_B.WVR);
}
/*!
* @brief Enable Debug Mode
*
* @param mode: specifies the low power mode.
* The parameter can be combination of following values:
* @arg DBG_MODE_STOP: Keep debugger connection during STOP mode
* @arg DBG_MODE_STANDBY: Keep debugger connection during STANDBY mode
* @retval None
*/
void DBG_EnableDebugMode(uint32_t mode)
{
DBG->CFG |= (uint32_t)mode;
}
/*!
* @brief Disable Debug Mode
*
* @param mode: specifies the low power mode.
* The parameter can be combination of following values:
* @arg DBG_MODE_STOP: Keep debugger connection during STOP mode
* @arg DBG_MODE_STANDBY: Keep debugger connection during STANDBY mode
* @retval None
*/
void DBG_DisableDebugMode(uint32_t mode)
{
DBG->CFG &= (uint32_t)~mode;
}
/*!
* @brief Enable APB1 peripheral in Debug mode.
*
* @param peripheral: Specifies the APB1 peripheral.
* The parameter can be combination of following values:
* @arg DBG_APB1_PER_TMR2_STOP: TMR2 counter stopped when Core is halted, Not for APM32F030 devices
* @arg DBG_APB1_PER_TMR3_STOP: TMR3 counter stopped when Core is halted
* @arg DBG_APB1_PER_TMR6_STOP: TMR6 counter stopped when Core is halted
* @arg DBG_APB1_PER_TMR7_STOP: TMR7 counter stopped when Core is halted£¬Only for APM32F072 and APM32F091 devices
* @arg DBG_APB1_PER_TMR14_STOP: TMR14 counter stopped when Core is halted
* @arg DBG_APB1_PER_RTC_STOP: RTC counter stopped when Core is halted
* @arg DBG_APB1_PER_WWDT_STOP: Debug WWDT stopped when Core is halted
* @arg DBG_APB1_PER_IWDT_STOP: Debug IWDT stopped when Core is halted
* @arg DBG_APB1_PER_CAN_STOP: Debug CAN stopped when Core is halted£¬Only for APM32F072 and APM32F091 devices
* @arg DBG_APB1_PER_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* @retval None
*/
void DBG_EnableAPB1Periph(uint32_t peripheral)
{
DBG->APB1F |= (uint32_t)peripheral;
}
/*!
* @brief Disable APB1 peripheral in Debug mode.
*
* @param peripheral: Specifies the APB1 peripheral.
* The parameter can be combination of following values:
* @arg DBG_APB1_PER_TMR2_STOP: TMR2 counter stopped when Core is halted, Not for APM32F030 devices
* @arg DBG_APB1_PER_TMR3_STOP: TMR3 counter stopped when Core is halted
* @arg DBG_APB1_PER_TMR6_STOP: TMR6 counter stopped when Core is halted
* @arg DBG_APB1_PER_TMR7_STOP: TMR7 counter stopped when Core is halted£¬Only for APM32F072 and APM32F091 devices
* @arg DBG_APB1_PER_TMR14_STOP: TMR14 counter stopped when Core is halted
* @arg DBG_APB1_PER_RTC_STOP: RTC counter stopped when Core is halted
* @arg DBG_APB1_PER_WWDT_STOP: Debug WWDT stopped when Core is halted
* @arg DBG_APB1_PER_IWDT_STOP: Debug IWDT stopped when Core is halted
* @arg DBG_APB1_PER_CAN_STOP: Debug CAN stopped when Core is halted£¬Only for APM32F072 and APM32F091 devices
* @arg DBG_APB1_PER_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* @retval None
*/
void DBG_DisableAPB1Periph(uint32_t peripheral)
{
DBG->APB1F &= (uint32_t)~peripheral;
}
/*!
* @brief Enable APB2 peripheral in Debug mode.
*
* @param peripheral: Specifies the APB2 peripheral.
* The parameter can be combination of following values:
* @arg DBG_APB2_PER_TMR1_STOP: TMR1 counter stopped when Core is halted
* @arg DBG_APB2_PER_TMR15_STOP: TMR15 counter stopped when Core is halted
* @arg DBG_APB2_PER_TMR16_STOP: TMR16 counter stopped when Core is halted
* @arg DBG_APB2_PER_TMR17_STOP: TMR17 counter stopped when Core is halted
* @retval None
*/
void DBG_EnableAPB2Periph(uint32_t peripheral)
{
DBG->APB2F |= (uint32_t)peripheral;
}
/*!
* @brief Disable APB2 peripheral in Debug mode.
*
* @param peripheral: Specifies the APB2 peripheral.
* The parameter can be combination of following values:
* @arg DBG_APB2_PER_TMR1_STOP: TMR1 counter stopped when Core is halted
* @arg DBG_APB2_PER_TMR15_STOP: TMR15 counter stopped when Core is halted
* @arg DBG_APB2_PER_TMR16_STOP: TMR16 counter stopped when Core is halted
* @arg DBG_APB2_PER_TMR17_STOP: TMR17 counter stopped when Core is halted
*
* @retval None
*/
void DBG_DisableAPB2Periph(uint32_t peripheral)
{
DBG->APB2F &= (uint32_t)~peripheral;
}
/**@} end of group DBG_Functions */
/**@} end of group DBG_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_dma.c
*
* @brief This file contains all the functions for the DMA peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_dma.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup DMA_Driver
@{
*/
/** @defgroup DMA_Macros Macros
@{
*/
/**@} end of group DMA_Macros */
/** @defgroup DMA_Enumerates Enumerates
@{
*/
/**@} end of group DMA_Enumerates */
/** @defgroup DMA_Structures Structures
@{
*/
/**@} end of group DMA_Structures */
/** @defgroup DMA_Variables Variables
@{
*/
/**@} end of group DMA_Variables */
/** @defgroup DMA_Functions Functions
@{
*/
/*!
* @brief Set the DMA peripheral registers to their default reset values
*
* @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
* set DMA channel for the DMA peripheral
* This parameter can be one of the following values:
* @arg DMA1_CHANNEL_1
* @arg DMA1_CHANNEL_2
* @arg DMA1_CHANNEL_3
* @arg DMA1_CHANNEL_4
* @arg DMA1_CHANNEL_5
* @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
* @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
* @arg DMA2_CHANNEL_1(only for APM32F091)
* @arg DMA2_CHANNEL_2(only for APM32F091)
* @arg DMA2_CHANNEL_3(only for APM32F091)
* @arg DMA2_CHANNEL_4(only for APM32F091)
* @arg DMA2_CHANNEL_5(only for APM32F091)
* @retval None
*/
void DMA_Reset(DMA_CHANNEL_T* channel)
{
channel->CHCFG_B.CHEN = 0;
channel->CHCFG = 0;
channel->CHNDATA = 0;
channel->CHPADDR = 0;
channel->CHMADDR = 0;
if (channel == DMA1_CHANNEL_1)
{
DMA1->INTFCLR = (uint32_t)0x0000000F;
}
else if (channel == DMA1_CHANNEL_2)
{
DMA1->INTFCLR = (uint32_t)0x000000F0;
}
else if (channel == DMA1_CHANNEL_3)
{
DMA1->INTFCLR = (uint32_t)0x00000F00;
}
else if (channel == DMA1_CHANNEL_4)
{
DMA1->INTFCLR = (uint32_t)0x0000F000;
}
else if (channel == DMA1_CHANNEL_5)
{
DMA1->INTFCLR = (uint32_t)0x000F0000;
}
else if (channel == DMA1_CHANNEL_6)
{
DMA1->INTFCLR = (uint32_t)0x00F00000;
}
else if (channel == DMA1_CHANNEL_7)
{
DMA1->INTFCLR = (uint32_t)0x0F000000;
}
else if (channel == DMA2_CHANNEL_1)
{
DMA2->INTFCLR = (uint32_t)0x0000000F;
}
else if (channel == DMA2_CHANNEL_2)
{
DMA2->INTFCLR = (uint32_t)0x000000F0;
}
else if (channel == DMA2_CHANNEL_3)
{
DMA2->INTFCLR = (uint32_t)0x00000F00;
}
else if (channel == DMA2_CHANNEL_4)
{
DMA2->INTFCLR = (uint32_t)0x0000F000;
}
else if (channel == DMA2_CHANNEL_5)
{
DMA2->INTFCLR = (uint32_t)0x000F0000;
}
}
/*!
* @brief Config the DMA peripheral according to the specified parameters in the dmaConfig
*
* @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
* set DMA channel for the DMA peripheral
* This parameter can be one of the following values:
* @arg DMA1_CHANNEL_1
* @arg DMA1_CHANNEL_2
* @arg DMA1_CHANNEL_3
* @arg DMA1_CHANNEL_4
* @arg DMA1_CHANNEL_5
* @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
* @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
* @arg DMA2_CHANNEL_1(only for APM32F091)
* @arg DMA2_CHANNEL_2(only for APM32F091)
* @arg DMA2_CHANNEL_3(only for APM32F091)
* @arg DMA2_CHANNEL_4(only for APM32F091)
* @arg DMA2_CHANNEL_5(only for APM32F091)
*
* @param dmaConfig: Pointer to a DMA_Config_T structure that
* contains the configuration information for the DMA peripheral
*
* @retval None
*/
void DMA_Config(DMA_CHANNEL_T* channel, DMA_Config_T* dmaConfig)
{
channel->CHCFG_B.DIRCFG = dmaConfig->direction;
channel->CHCFG_B.CIRMODE = dmaConfig->circular;
channel->CHCFG_B.M2MMODE = dmaConfig->memoryTomemory;
channel->CHCFG_B.CHPL = dmaConfig->priority;
channel->CHCFG_B.MIMODE = dmaConfig->memoryInc;
channel->CHCFG_B.PERIMODE = dmaConfig->peripheralInc;
channel->CHCFG_B.MSIZE = dmaConfig->memoryDataSize;
channel->CHCFG_B.PERSIZE = dmaConfig->peripheralDataSize;
channel->CHNDATA = dmaConfig->bufferSize;
channel->CHMADDR = dmaConfig->memoryAddress;
channel->CHPADDR = dmaConfig->peripheralAddress;
}
/*!
* @brief Fills each dmaConfig member with its default value
*
* @param dmaConfig: Pointer to a DMA_Config_T structure which will be initialized
*
* @retval None
*/
void DMA_ConfigStructInit(DMA_Config_T* dmaConfig)
{
dmaConfig->direction = DMA_DIR_PERIPHERAL;
dmaConfig->circular = DMA_CIRCULAR_DISABLE;
dmaConfig->memoryTomemory = DMA_M2M_DISABLE;
dmaConfig->priority = DMA_PRIORITY_LEVEL_LOW;
dmaConfig->memoryInc = DMA_MEMORY_INC_DISABLE;
dmaConfig->peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
dmaConfig->memoryDataSize = DMA_MEMORY_DATASIZE_BYTE;
dmaConfig->peripheralDataSize = DMA_PERIPHERAL_DATASIZE_BYTE;
dmaConfig->bufferSize = 0;
dmaConfig->memoryAddress = 0;
dmaConfig->peripheralAddress = 0;
}
/*!
* @brief Enable the DMA peripheral
*
* @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
* set DMA channel for the DMA peripheral
* This parameter can be one of the following values:
* @arg DMA1_CHANNEL_1
* @arg DMA1_CHANNEL_2
* @arg DMA1_CHANNEL_3
* @arg DMA1_CHANNEL_4
* @arg DMA1_CHANNEL_5
* @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
* @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
* @arg DMA2_CHANNEL_1(only for APM32F091)
* @arg DMA2_CHANNEL_2(only for APM32F091)
* @arg DMA2_CHANNEL_3(only for APM32F091)
* @arg DMA2_CHANNEL_4(only for APM32F091)
* @arg DMA2_CHANNEL_5(only for APM32F091)
*
* @retval None
*/
void DMA_Enable(DMA_CHANNEL_T* channel)
{
channel->CHCFG_B.CHEN = BIT_SET;
}
/*!
* @brief Disable the DMA peripheral
*
* @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
* set DMA channel for the DMA peripheral
* This parameter can be one of the following values:
* @arg DMA1_CHANNEL_1
* @arg DMA1_CHANNEL_2
* @arg DMA1_CHANNEL_3
* @arg DMA1_CHANNEL_4
* @arg DMA1_CHANNEL_5
* @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
* @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
* @arg DMA2_CHANNEL_1(only for APM32F091)
* @arg DMA2_CHANNEL_2(only for APM32F091)
* @arg DMA2_CHANNEL_3(only for APM32F091)
* @arg DMA2_CHANNEL_4(only for APM32F091)
* @arg DMA2_CHANNEL_5(only for APM32F091)
*
* @retval None
*/
void DMA_Disable(DMA_CHANNEL_T* channel)
{
channel->CHCFG_B.CHEN = BIT_RESET;
}
/*!
* @brief Set the DMA Channelx transfer data of number
*
* @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
* set DMA channel for the DMA peripheral
* This parameter can be one of the following values:
* @arg DMA1_CHANNEL_1
* @arg DMA1_CHANNEL_2
* @arg DMA1_CHANNEL_3
* @arg DMA1_CHANNEL_4
* @arg DMA1_CHANNEL_5
* @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
* @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
* @arg DMA2_CHANNEL_1(only for APM32F091)
* @arg DMA2_CHANNEL_2(only for APM32F091)
* @arg DMA2_CHANNEL_3(only for APM32F091)
* @arg DMA2_CHANNEL_4(only for APM32F091)
* @arg DMA2_CHANNEL_5(only for APM32F091)
*
* @param dataNumber: The number of data units in the current DMA Channel transfer
*
* @retval None
*/
void DMA_SetDataNumber(DMA_CHANNEL_T* channel, uint32_t dataNumber)
{
channel->CHNDATA = (uint32_t)dataNumber;
}
/*!
* @brief Read the DMA Channelx transfer data of number
*
* @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
* set DMA channel for the DMA peripheral
* This parameter can be one of the following values:
* @arg DMA1_CHANNEL_1
* @arg DMA1_CHANNEL_2
* @arg DMA1_CHANNEL_3
* @arg DMA1_CHANNEL_4
* @arg DMA1_CHANNEL_5
* @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
* @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
* @arg DMA2_CHANNEL_1(only for APM32F091)
* @arg DMA2_CHANNEL_2(only for APM32F091)
* @arg DMA2_CHANNEL_3(only for APM32F091)
* @arg DMA2_CHANNEL_4(only for APM32F091)
* @arg DMA2_CHANNEL_5(only for APM32F091)
*
* @retval The number of data units in the current DMA Channel transfer
*/
uint32_t DMA_ReadDataNumber(DMA_CHANNEL_T* channel)
{
return ((uint32_t)channel->CHNDATA);
}
/*!
* @brief Configure the DMA channels remapping.
*
* @param dma: Select the the DMA peripheral.
It can be DMA1/DMA2.
*
* @param remap: Select the the DMA_CHANNEL_REMAP_T.
When select DMA1, the DMA channel can be 1 to 7.
* When select DMA2, the DMA channel can be 1 to 5.
*
* @retval It's only for APM32F091 devices.
*/
void DMA_ConfigRemap(DMA_T* dma, DMA_CHANNEL_REMAP_T remap)
{
dma->CHSEL &= ~((uint32_t)0x0F << (uint32_t)(remap >> 28) * 4);
dma->CHSEL |= (uint32_t)(remap & 0x0FFFFFFF);
}
/*!
* @brief Enables the specified interrupts
* @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
* set DMA channel for the DMA peripheral
* This parameter can be one of the following values:
* @arg DMA1_CHANNEL_1
* @arg DMA1_CHANNEL_2
* @arg DMA1_CHANNEL_3
* @arg DMA1_CHANNEL_4
* @arg DMA1_CHANNEL_5
* @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
* @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
* @arg DMA2_CHANNEL_1(only for APM32F091)
* @arg DMA2_CHANNEL_2(only for APM32F091)
* @arg DMA2_CHANNEL_3(only for APM32F091)
* @arg DMA2_CHANNEL_4(only for APM32F091)
* @arg DMA2_CHANNEL_5(only for APM32F091)
*
* @param interrupt: Specifies the DMA interrupts sources
* The parameter can be combination of following values:
* @arg DMA_INT_TFIE: Transfer complete interrupt
* @arg DMA_INT_HTIE: Half Transfer interrupt
* @arg DMA_INT_TEIE: Transfer error interrupt
*
* @retval None
*/
void DMA_EnableInterrupt(DMA_CHANNEL_T* channel, uint32_t interrupt)
{
channel->CHCFG |= (uint32_t)interrupt;
}
/*!
* @brief Disables the specified interrupts
* @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
* set DMA channel for the DMA peripheral
* This parameter can be one of the following values:
* @arg DMA1_CHANNEL_1
* @arg DMA1_CHANNEL_2
* @arg DMA1_CHANNEL_3
* @arg DMA1_CHANNEL_4
* @arg DMA1_CHANNEL_5
* @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
* @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
* @arg DMA2_CHANNEL_1(only for APM32F091)
* @arg DMA2_CHANNEL_2(only for APM32F091)
* @arg DMA2_CHANNEL_3(only for APM32F091)
* @arg DMA2_CHANNEL_4(only for APM32F091)
* @arg DMA2_CHANNEL_5(only for APM32F091)
*
* @param interrupt: Specifies the DMA interrupts sources
* The parameter can be combination of following values:
* @arg DMA_INT_TFIE: Transfer complete interrupt
* @arg DMA_INT_HTIE: Half Transfer interrupt
* @arg DMA_INT_TEIE: Transfer error interrupt
*
* @retval None
*/
void DMA_DisableInterrupt(DMA_CHANNEL_T* channel, uint32_t interrupt)
{
channel->CHCFG &= (uint32_t)~interrupt;
}
/*!
* @brief Checks whether the specified DMA flag is set or not
*
* @param flag: Specifies the flag to check
* This parameter can be one of the following values:
* @arg DMA1_FLAG_AL1: DMA1 Channel 1 All flag
* @arg DMA1_FLAG_TF1: DMA1 Channel 1 Transfer Complete flag
* @arg DMA1_FLAG_HT1: DMA1 Channel 1 Half Transfer Complete flag
* @arg DMA1_FLAG_TE1: DMA1 Channel 1 Transfer Error flag
* @arg DMA1_FLAG_AL2: DMA1 Channel 2 All flag
* @arg DMA1_FLAG_TF2: DMA1 Channel 2 Transfer Complete flag
* @arg DMA1_FLAG_HT2: DMA1 Channel 2 Half Transfer Complete flag
* @arg DMA1_FLAG_TE2: DMA1 Channel 2 Transfer Error flag
* @arg DMA1_FLAG_AL3: DMA1 Channel 3 All flag
* @arg DMA1_FLAG_TF3: DMA1 Channel 3 Transfer Complete flag
* @arg DMA1_FLAG_HT3: DMA1 Channel 3 Half Transfer Complete flag
* @arg DMA1_FLAG_TE3: DMA1 Channel 3 Transfer Error flag
* @arg DMA1_FLAG_AL4: DMA1 Channel 4 All flag
* @arg DMA1_FLAG_TF4: DMA1 Channel 4 Transfer Complete flag
* @arg DMA1_FLAG_HT4: DMA1 Channel 4 Half Transfer Complete flag
* @arg DMA1_FLAG_TE4: DMA1 Channel 4 Transfer Error flag
* @arg DMA1_FLAG_AL5: DMA1 Channel 5 All flag
* @arg DMA1_FLAG_TF5: DMA1 Channel 5 Transfer Complete flag
* @arg DMA1_FLAG_HT5: DMA1 Channel 5 Half Transfer Complete flag
* @arg DMA1_FLAG_TE5: DMA1 Channel 5 Transfer Error flag
* Below is only for APM32F072 and APM32F091 devices:
* @arg DMA1_FLAG_AL6: DMA1 Channel 6 All flag
* @arg DMA1_FLAG_TF6: DMA1 Channel 6 Transfer Complete flag
* @arg DMA1_FLAG_HT6: DMA1 Channel 6 Half Transfer Complete flag
* @arg DMA1_FLAG_TE6: DMA1 Channel 6 Transfer Error flag
* @arg DMA1_FLAG_AL7: DMA1 Channel 7 All flag
* @arg DMA1_FLAG_TF7: DMA1 Channel 7 Transfer Complete flag
* @arg DMA1_FLAG_HT7: DMA1 Channel 7 Half Transfer Complete flag
* @arg DMA1_FLAG_TE7: DMA1 Channel 7 Transfer Error flag
* Below is only for APM32F091 devices:
* @arg DMA2_FLAG_AL1: DMA2 Channel 1 All flag
* @arg DMA2_FLAG_TF1: DMA2 Channel 1 Transfer Complete flag
* @arg DMA2_FLAG_HT1: DMA2 Channel 1 Half Transfer Complete flag
* @arg DMA2_FLAG_TE1: DMA2 Channel 1 Transfer Error flag
* @arg DMA2_FLAG_AL2: DMA2 Channel 2 All flag
* @arg DMA2_FLAG_TF2: DMA2 Channel 2 Transfer Complete flag
* @arg DMA2_FLAG_HT2: DMA2 Channel 2 Half Transfer Complete flag
* @arg DMA2_FLAG_TE2: DMA2 Channel 2 Transfer Error flag
* @arg DMA2_FLAG_AL3: DMA2 Channel 3 All flag
* @arg DMA2_FLAG_TF3: DMA2 Channel 3 Transfer Complete flag
* @arg DMA2_FLAG_HT3: DMA2 Channel 3 Half Transfer Complete flag
* @arg DMA2_FLAG_TE3: DMA2 Channel 3 Transfer Error flag
* @arg DMA2_FLAG_AL4: DMA2 Channel 4 All flag
* @arg DMA2_FLAG_TF4: DMA2 Channel 4 Transfer Complete flag
* @arg DMA2_FLAG_HT4: DMA2 Channel 4 Half Transfer Complete flag
* @arg DMA2_FLAG_TE4: DMA2 Channel 4 Transfer Error flag
* @arg DMA2_FLAG_AL5: DMA2 Channel 5 All flag
* @arg DMA2_FLAG_TF5: DMA2 Channel 5 Transfer Complete flag
* @arg DMA2_FLAG_HT5: DMA2 Channel 5 Half Transfer Complete flag
* @arg DMA2_FLAG_TE5: DMA2 Channel 5 Transfer Error flag
*
* @retval The new state of flag (SET or RESET)
*/
uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
{
uint32_t status;
if ((flag & 0x10000000) == SET)
{
status = DMA2->INTSTS & ((uint32_t)flag & 0x000FFFFF);
}
else
{
status = DMA1->INTSTS & ((uint32_t)flag & 0x0FFFFFFF);
}
if (status == flag)
{
return SET;
}
return RESET;
}
/*!
* @brief Clear whether the specified DMA flag is set or not
*
* @param flag: Specifies the flag to Clear
* This parameter can be any combination of the following values:
* @arg DMA1_FLAG_AL1: DMA1 Channel 1 All flag
* @arg DMA1_FLAG_TF1: DMA1 Channel 1 Transfer Complete flag
* @arg DMA1_FLAG_HT1: DMA1 Channel 1 Half Transfer Complete flag
* @arg DMA1_FLAG_TE1: DMA1 Channel 1 Transfer Error flag
* @arg DMA1_FLAG_AL2: DMA1 Channel 2 All flag
* @arg DMA1_FLAG_TF2: DMA1 Channel 2 Transfer Complete flag
* @arg DMA1_FLAG_HT2: DMA1 Channel 2 Half Transfer Complete flag
* @arg DMA1_FLAG_TE2: DMA1 Channel 2 Transfer Error flag
* @arg DMA1_FLAG_AL3: DMA1 Channel 3 All flag
* @arg DMA1_FLAG_TF3: DMA1 Channel 3 Transfer Complete flag
* @arg DMA1_FLAG_HT3: DMA1 Channel 3 Half Transfer Complete flag
* @arg DMA1_FLAG_TE3: DMA1 Channel 3 Transfer Error flag
* @arg DMA1_FLAG_AL4: DMA1 Channel 4 All flag
* @arg DMA1_FLAG_TF4: DMA1 Channel 4 Transfer Complete flag
* @arg DMA1_FLAG_HT4: DMA1 Channel 4 Half Transfer Complete flag
* @arg DMA1_FLAG_TE4: DMA1 Channel 4 Transfer Error flag
* @arg DMA1_FLAG_AL5: DMA1 Channel 5 All flag
* @arg DMA1_FLAG_TF5: DMA1 Channel 5 Transfer Complete flag
* @arg DMA1_FLAG_HT5: DMA1 Channel 5 Half Transfer Complete flag
* @arg DMA1_FLAG_TE5: DMA1 Channel 5 Transfer Error flag
* Below is only for APM32F072 and APM32F091 devices:
* @arg DMA1_FLAG_AL6: DMA1 Channel 6 All flag
* @arg DMA1_FLAG_TF6: DMA1 Channel 6 Transfer Complete flag
* @arg DMA1_FLAG_HT6: DMA1 Channel 6 Half Transfer Complete flag
* @arg DMA1_FLAG_TE6: DMA1 Channel 6 Transfer Error flag
* @arg DMA1_FLAG_AL7: DMA1 Channel 7 All flag
* @arg DMA1_FLAG_TF7: DMA1 Channel 7 Transfer Complete flag
* @arg DMA1_FLAG_HT7: DMA1 Channel 7 Half Transfer Complete flag
* @arg DMA1_FLAG_TE7: DMA1 Channel 7 Transfer Error flag
* Below is only for APM32F091 devices:
* @arg DMA2_FLAG_AL1: DMA2 Channel 1 All flag
* @arg DMA2_FLAG_TF1: DMA2 Channel 1 Transfer Complete flag
* @arg DMA2_FLAG_HT1: DMA2 Channel 1 Half Transfer Complete flag
* @arg DMA2_FLAG_TE1: DMA2 Channel 1 Transfer Error flag
* @arg DMA2_FLAG_AL2: DMA2 Channel 2 All flag
* @arg DMA2_FLAG_TF2: DMA2 Channel 2 Transfer Complete flag
* @arg DMA2_FLAG_HT2: DMA2 Channel 2 Half Transfer Complete flag
* @arg DMA2_FLAG_TE2: DMA2 Channel 2 Transfer Error flag
* @arg DMA2_FLAG_AL3: DMA2 Channel 3 All flag
* @arg DMA2_FLAG_TF3: DMA2 Channel 3 Transfer Complete flag
* @arg DMA2_FLAG_HT3: DMA2 Channel 3 Half Transfer Complete flag
* @arg DMA2_FLAG_TE3: DMA2 Channel 3 Transfer Error flag
* @arg DMA2_FLAG_AL4: DMA2 Channel 4 All flag
* @arg DMA2_FLAG_TF4: DMA2 Channel 4 Transfer Complete flag
* @arg DMA2_FLAG_HT4: DMA2 Channel 4 Half Transfer Complete flag
* @arg DMA2_FLAG_TE4: DMA2 Channel 4 Transfer Error flag
* @arg DMA2_FLAG_AL5: DMA2 Channel 5 All flag
* @arg DMA2_FLAG_TF5: DMA2 Channel 5 Transfer Complete flag
* @arg DMA2_FLAG_HT5: DMA2 Channel 5 Half Transfer Complete flag
* @arg DMA2_FLAG_TE5: DMA2 Channel 5 Transfer Error flag
*
* @retval None
*/
void DMA_ClearStatusFlag(uint32_t flag)
{
if ((flag & 0x10000000) == SET)
{
DMA2->INTFCLR |= (uint32_t)(flag & 0x000FFFFF);
}
else
{
DMA1->INTFCLR |= (uint32_t)(flag & 0x0FFFFFFF);
}
}
/*!
* @brief Checks whether the specified interrupt has occurred or not
*
* @param flag: Specifies the DMA interrupt pending bit to check
* The parameter can be one following values:
* @arg DMA1_INT_FLAG_AL1: DMA1_Channel 1 All interrupt flag
* @arg DMA1_INT_FLAG_TF1: DMA1_Channel 1 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT1: DMA1_Channel 1 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE1: DMA1_Channel 1 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL2: DMA1_Channel 2 All interrupt flag
* @arg DMA1_INT_FLAG_TF2: DMA1_Channel 2 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT2: DMA1_Channel 2 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE2: DMA1_Channel 2 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL3: DMA1_Channel 3 All interrupt flag
* @arg DMA1_INT_FLAG_TF3: DMA1_Channel 3 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT3: DMA1_Channel 3 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE3: DMA1_Channel 3 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL4: DMA1_Channel 4 All interrupt flag
* @arg DMA1_INT_FLAG_TF4: DMA1_Channel 4 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT4: DMA1_Channel 4 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE4: DMA1_Channel 4 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL5: DMA1_Channel 5 All interrupt flag
* @arg DMA1_INT_FLAG_TF5: DMA1_Channel 5 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT5: DMA1_Channel 5 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE5: DMA1_Channel 5 Transfer Error interrupt flag
* Below is only for APM32F072 and APM32F091 devices:
* @arg DMA1_INT_FLAG_AL6: DMA1_Channel 6 All interrupt flag
* @arg DMA1_INT_FLAG_TF6: DMA1_Channel 6 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT6: DMA1_Channel 6 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE6: DMA1_Channel 6 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL7: DMA1_Channel 7 All interrupt flag
* @arg DMA1_INT_FLAG_TF7: DMA1_Channel 7 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT7: DMA1_Channel 7 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE7: DMA1_Channel 7 Transfer Error interrupt flag
* Below is only for APM32F091 devices:
* @arg DMA2_INT_FLAG_AL1: DMA2_Channel 1 All interrupt flag
* @arg DMA2_INT_FLAG_TF1: DMA2_Channel 1 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT1: DMA2_Channel 1 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE1: DMA2_Channel 1 Transfer Error interrupt flag
* @arg DMA2_INT_FLAG_AL2: DMA2_Channel 2 All interrupt flag
* @arg DMA2_INT_FLAG_TF2: DMA2_Channel 2 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT2: DMA2_Channel 2 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE2: DMA2_Channel 2 Transfer Error interrupt flag
* @arg DMA2_INT_FLAG_AL3: DMA2_Channel 3 All interrupt flag
* @arg DMA2_INT_FLAG_TF3: DMA2_Channel 3 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT3: DMA2_Channel 3 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE3: DMA2_Channel 3 Transfer Error interrupt flag
* @arg DMA2_INT_FLAG_AL4: DMA2_Channel 4 All interrupt flag
* @arg DMA2_INT_FLAG_TF4: DMA2_Channel 4 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT4: DMA2_Channel 4 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE4: DMA2_Channel 4 Transfer Error interrupt flag
* @arg DMA2_INT_FLAG_AL5: DMA2_Channel 5 All interrupt flag
* @arg DMA2_INT_FLAG_TF5: DMA2_Channel 5 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT5: DMA2_Channel 5 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE5: DMA2_Channel 5 Transfer Error interrupt flag
*
* @retval The new state of flag (SET or RESET)
*/
uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
{
uint32_t status;
if ((flag & 0x10000000) == SET)
{
status = DMA2->INTSTS & ((uint32_t)flag & 0x000FFFFF);
}
else
{
status = DMA1->INTSTS & ((uint32_t)flag & 0x0FFFFFFF);
}
if (status == flag)
{
return SET;
}
return RESET;
}
/*!
* @brief Clears the specified interrupt pending bits
*
* @param flag: Specifies the DMA interrupt pending bit to clear
* The parameter can be combination of following values:
* @arg DMA1_INT_FLAG_AL1: DMA1_Channel 1 All interrupt flag
* @arg DMA1_INT_FLAG_TF1: DMA1_Channel 1 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT1: DMA1_Channel 1 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE1: DMA1_Channel 1 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL2: DMA1_Channel 2 All interrupt flag
* @arg DMA1_INT_FLAG_TF2: DMA1_Channel 2 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT2: DMA1_Channel 2 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE2: DMA1_Channel 2 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL3: DMA1_Channel 3 All interrupt flag
* @arg DMA1_INT_FLAG_TF3: DMA1_Channel 3 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT3: DMA1_Channel 3 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE3: DMA1_Channel 3 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL4: DMA1_Channel 4 All interrupt flag
* @arg DMA1_INT_FLAG_TF4: DMA1_Channel 4 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT4: DMA1_Channel 4 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE4: DMA1_Channel 4 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL5: DMA1_Channel 5 All interrupt flag
* @arg DMA1_INT_FLAG_TF5: DMA1_Channel 5 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT5: DMA1_Channel 5 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE5: DMA1_Channel 5 Transfer Error interrupt flag
* Below is only for APM32F072 and APM32F091 devices:
* @arg DMA1_INT_FLAG_AL6: DMA1_Channel 6 All interrupt flag
* @arg DMA1_INT_FLAG_TF6: DMA1_Channel 6 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT6: DMA1_Channel 6 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE6: DMA1_Channel 6 Transfer Error interrupt flag
* @arg DMA1_INT_FLAG_AL7: DMA1_Channel 7 All interrupt flag
* @arg DMA1_INT_FLAG_TF7: DMA1_Channel 7 Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_HT7: DMA1_Channel 7 Half Transfer Complete interrupt flag
* @arg DMA1_INT_FLAG_TE7: DMA1_Channel 7 Transfer Error interrupt flag
* Below is only for APM32F091 devices:
* @arg DMA2_INT_FLAG_AL1: DMA2_Channel 1 All interrupt flag
* @arg DMA2_INT_FLAG_TF1: DMA2_Channel 1 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT1: DMA2_Channel 1 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE1: DMA2_Channel 1 Transfer Error interrupt flag
* @arg DMA2_INT_FLAG_AL2: DMA2_Channel 2 All interrupt flag
* @arg DMA2_INT_FLAG_TF2: DMA2_Channel 2 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT2: DMA2_Channel 2 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE2: DMA2_Channel 2 Transfer Error interrupt flag
* @arg DMA2_INT_FLAG_AL3: DMA2_Channel 3 All interrupt flag
* @arg DMA2_INT_FLAG_TF3: DMA2_Channel 3 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT3: DMA2_Channel 3 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE3: DMA2_Channel 3 Transfer Error interrupt flag
* @arg DMA2_INT_FLAG_AL4: DMA2_Channel 4 All interrupt flag
* @arg DMA2_INT_FLAG_TF4: DMA2_Channel 4 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT4: DMA2_Channel 4 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE4: DMA2_Channel 4 Transfer Error interrupt flag
* @arg DMA2_INT_FLAG_AL5: DMA2_Channel 5 All interrupt flag
* @arg DMA2_INT_FLAG_TF5: DMA2_Channel 5 Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_HT5: DMA2_Channel 5 Half Transfer Complete interrupt flag
* @arg DMA2_INT_FLAG_TE5: DMA2_Channel 5 Transfer Error interrupt flag
*
* @retval None
*/
void DMA_ClearIntFlag(uint32_t flag)
{
if ((flag & 0x10000000) == SET)
{
DMA2->INTFCLR |= (uint32_t)(flag & 0x000FFFFF);
}
else
{
DMA1->INTFCLR |= (uint32_t)(flag & 0x0FFFFFFF);
}
}
/**@} end of group DMA_Functions */
/**@} end of group DMA_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_eint.c Normal file
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@ -0,0 +1,231 @@
/*!
* @file apm32f0xx_eint.c
*
* @brief This file contains all the functions for the EINT peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_eint.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup EINT_Driver
@{
*/
/** @defgroup EINT_Macros Macros
@{
*/
/**@} end of group EINT_Macros */
/** @defgroup EINT_Enumerates Enumerates
@{
*/
/**@} end of group EINT_Enumerates */
/** @defgroup EINT_Structures Structures
@{
*/
/**@} end of group EINT_Structures */
/** @defgroup EINT_Variables Variables
@{
*/
/**@} end of group EINT_Variables */
/** @defgroup EINT_Functions Functions
@{
*/
/*!
* @brief Set the EINT peripheral registers to their default reset values
*
* @param None
*
* @retval None
*/
void EINT_Reset(void)
{
EINT->IMASK = EINT_INTMASK_RESET_VALUE;
EINT->EMASK = EINT_EVTMASK_RESET_VALUE;
EINT->RTEN = EINT_RTSEL_RESET_VALUE;
EINT->FTEN = EINT_FTSEL_RESET_VALUE;
EINT->IPEND = EINT_PEND_RESET_VALUE;
}
/*!
* @brief Configure the EINT
*
* @param eintConfig: Pointer to EINT_Config_T structure
*
* @retval None
*/
void EINT_Config(EINT_Config_T* eintConfig)
{
if (eintConfig->lineCmd == DISABLE)
{
if (eintConfig->mode == EINT_MODE_INTERRUPT)
{
EINT->IMASK &= ~eintConfig->line;
}
else if (eintConfig->mode == EINT_MODE_EVENT)
{
EINT->EMASK &= ~eintConfig->line;
}
}
else
{
if (eintConfig->mode == EINT_MODE_INTERRUPT)
{
EINT->IMASK |= eintConfig->line;
}
else if (eintConfig->mode == EINT_MODE_EVENT)
{
EINT->EMASK |= eintConfig->line;
}
if (eintConfig->trigger == EINT_TRIGGER_RISING)
{
EINT->RTEN |= eintConfig->line;
}
else if (eintConfig->trigger == EINT_TRIGGER_FALLING)
{
EINT->FTEN |= eintConfig->line;
}
else
{
EINT->RTEN |= eintConfig->line;
EINT->FTEN |= eintConfig->line;
}
}
}
/*!
* @brief Fills each EINT_Config_T member with its default value
*
* @param eintConfig: Pointer to a EINT_Config_T structure which will be initialized
*
* @retval None
*/
void EINT_ConfigStructInit(EINT_Config_T* eintConfig)
{
eintConfig->line = EINT_LINENONE;
eintConfig->mode = EINT_MODE_INTERRUPT;
eintConfig->trigger = EINT_TRIGGER_FALLING;
eintConfig->lineCmd = DISABLE;
}
/*!
* @brief Select software interrupt on EINT line
*
* @param line: specifies the EINT line on which the software interrupt
*
* @retval None
*/
void EINT_SelectSWInterrupt(uint32_t line)
{
EINT->SWINTE |= (uint32_t)line;
}
/*!
* @brief Read the specified EINT line flag
*
* @param line: Select the EINT line
*
* @retval status: The new state of flag (SET or RESET)
*/
uint8_t EINT_ReadStatusFlag(uint32_t line)
{
uint8_t status = RESET;
if ((EINT->IPEND & line) != (uint32_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/*!
* @brief Clears the EINT line pending bits
*
* @param line: Select the EINT line
*
* @retval None
*/
void EINT_ClearStatusFlag(uint32_t line)
{
EINT->IPEND = line;
}
/*!
* @brief Read the specified EINT line interrupt flag
*
* @param line: Select the EINT line
*
* @retval None
*/
uint8_t EINT_ReadIntFlag(uint32_t line)
{
uint8_t status = RESET;
uint32_t enablestatus = 0;
enablestatus = EINT->IMASK & line;
if ((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/*!
* @brief Clears the EINT line pending bits
*
* @param line: Select the EINT line
*
* @retval None
*/
void EINT_ClearIntFlag(uint32_t line)
{
EINT->IPEND = line;
}
/**@} end of group EINT_Functions */
/**@} end of group EINT_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_gpio.c
*
* @brief This file contains all the functions for the GPIO peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_gpio.h"
#include "apm32f0xx_rcm.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup GPIO_Driver
@{
*/
/** @defgroup GPIO_Macros Macros
@{
*/
/**@} end of group GPIO_Macros */
/** @defgroup GPIO_Enumerates Enumerates
@{
*/
/**@} end of group GPIO_Enumerates */
/** @defgroup GPIO_Structures Structures
@{
*/
/**@} end of group GPIO_Structures */
/** @defgroup GPIO_Variables Variables
@{
*/
/**@} end of group GPIO_Variables */
/** @defgroup GPIO_Functions Functions
@{
*/
/*!
* @brief Reset GPIO peripheral registers to their default reset values
*
* @param port: GPIO peripheral.It can be GPIOA/GPIOB/GPIOC/GPIOD/GPIOE/GPIOF
*
* @retval None
*
* @note GPIOE is available only for APM32F072 and APM32F091
*/
void GPIO_Reset(GPIO_T* port)
{
if (port == GPIOA)
{
RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOA);
RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOA);
}
else if (port == GPIOB)
{
RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOB);
RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOB);
}
else if (port == GPIOC)
{
RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOC);
RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOC);
}
else if (port == GPIOD)
{
RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOD);
RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOD);
}
else if (port == GPIOE)
{
RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOE);
RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOE);
}
else if (port == GPIOF)
{
RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOF);
RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOF);
}
}
/*!
* @brief Config the GPIO peripheral according to the specified parameters in the gpioConfig
*
* @param port: GPIO peripheral.It can be GPIOA/GPIOB/GPIOC/GPIOD/GPIOE/GPIOF
*
* @param gpioConfig: Pointer to a GPIO_Config_T structure that
* contains the configuration information for the specified GPIO peripheral
*
* @retval None
*
* @note GPIOE is available only for APM32F072 and APM32F091
*/
void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
{
uint32_t i;
uint32_t bit;
for (i = 0; i < 16; i++)
{
bit = (uint32_t)1 << i;
if (!(gpioConfig->pin & bit))
{
continue;
}
if ((gpioConfig->mode == GPIO_MODE_OUT) || (gpioConfig->mode == GPIO_MODE_AF))
{
/* speed */
port->OSSEL &= ~((0x03) << (i * 2));
port->OSSEL |= ((uint32_t)(gpioConfig->speed) << (i * 2));
/* Output mode configuration */
port->OMODE &= ~(((uint16_t)gpioConfig->outtype) << ((uint16_t)i));
port->OMODE |= (uint16_t)(((uint16_t)gpioConfig->outtype) << ((uint16_t)i));
}
/* input/output mode */
port->MODE &= ~(0x03 << (i * 2));
port->MODE |= (((uint32_t)gpioConfig->mode) << (i * 2));
/* Pull-up Pull down resistor configuration */
port->PUPD &= ~(0x03 << ((uint16_t)i * 2));
port->PUPD |= (((uint32_t)gpioConfig->pupd) << (i * 2));
}
}
/*!
* @brief Fills each GPIO_Config_T member with its default value
*
* @param gpioConfig: Pointer to a GPIO_Config_T structure which will be initialized
*
* @retval None
*/
void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig)
{
gpioConfig->pin = GPIO_PIN_ALL;
gpioConfig->mode = GPIO_MODE_IN;
gpioConfig->outtype = GPIO_OUT_TYPE_PP;
gpioConfig->speed = GPIO_SPEED_10MHz;
gpioConfig->pupd = GPIO_PUPD_NO;
}
/*!
* @brief Locks GPIO Pins configuration registers
*
* @param port: GPIOA/B peripheral
*
* @param pin: specifies the port bit to be written
*
* @retval None
*/
void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin)
{
uint32_t val = 0x00010000;
val |= pin;
/* Set LOCK bit */
port->LOCK = val ;
/* Reset LOCK bit */
port->LOCK = pin;
/* Set LOCK bit */
port->LOCK = val;
/* Read LOCK bit*/
val = port->LOCK;
/* Read LOCK bit*/
val = port->LOCK;
}
/*!
* @brief Reads the specified input port pin
*
* @param port: GPIO peripheral.It can be GPIOA/GPIOB/GPIOC/GPIOD/GPIOE/GPIOF
*
* @param pin: specifies pin to read
*
* @retval The input port pin value
*
* @note APM32F072 and APM32F091: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
*/
uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
{
uint8_t ret;
ret = (port->IDATA & pin) ? BIT_SET : BIT_RESET;
return ret;
}
/*!
* @brief Reads the specified GPIO input data port
*
* @param port: GPIO peripheral
*
* @retval GPIO input data port value
*
* @note GPIOE is available only for APM32F072 and APM32F091
*/
uint16_t GPIO_ReadInputPort(GPIO_T* port)
{
return ((uint16_t)port->IDATA);
}
/*!
* @brief Reads the specified output data port bit
*
* @param port: GPIO peripheral
*
* @param pin: specifies pin to read
*
* @retval The output port pin value
*
* @note GPIOE is available only for APM32F072 and APM32F091
*/
uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
{
uint8_t ret;
ret = (port->ODATA & pin) ? BIT_SET : BIT_RESET;
return ret;
}
/*!
* @brief Reads the specified GPIO output data port
*
* @param port: GPIO peripheral
*
* @retval output data port value
*
* @note GPIOE is available only for APM32F072 and APM32F091
*/
uint16_t GPIO_ReadOutputPort(GPIO_T* port)
{
return ((uint16_t)port->ODATA);
}
/*!
* @brief Sets the selected data port bits
*
* @param port: GPIO peripheral
*
* @param pin: specifies the port bits to be written
*
* @retval None
*
* @note APM32F072 and APM32F091: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
*/
void GPIO_SetBit(GPIO_T* port, uint16_t pin)
{
port->BSC = (uint32_t)pin;
}
/*!
* @brief Clears the selected data port bits
*
* @param port: GPIO peripheral
*
* @param pin: specifies the port bits to be written
*
* @retval None
*
* @note APM32F072 and APM32F091: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
*/
void GPIO_ClearBit(GPIO_T* port, uint16_t pin)
{
port->BR = (uint32_t)pin;
}
/*!
* @brief Sets or clears the selected data port bit
*
* @param port: GPIO peripheral
*
* @param pin: specifies the port bits to be written
*
* @param bitVal
*
* @retval None
*
* @note APM32F072 and APM32F091: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
*/
void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, GPIO_BSRET_T bitVal)
{
if (bitVal != Bit_RESET)
{
port->BSC = pin;
}
else
{
port->BR = pin ;
}
}
/*!
* @brief Writes data to the specified GPIO data port
*
* @param port: GPIO peripheral
*
* @param portVal: Write value to the port output data register
*
* @retval None
*
* @note GPIOE is available only for APM32F072 and APM32F091
*/
void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
{
port->ODATA = (uint32_t)portValue;
}
/*!
* @brief Changes the mapping of the specified pin
*
* @param port: GPIO peripheral
*
* @param pinSource: Specifies the pin for the Alternate function.
* This parameter can be one of the following values:
* @arg GPIOA,GPIOB,GPIOD,GPIOE for 0..15
* @arg GPIOC for 0..12
* @arg GPIOF for 0, 2..5, 9..10
*
* @param afPin: Selects the pin to used as Alternate function.
*
* @retval None
*
* @note GPIOC, GPIOD, GPIOE and GPIOF are available only for APM32F072 and APM32F091
*/
void GPIO_ConfigPinAF(GPIO_T* port, GPIO_PIN_SOURCE_T pinSource, GPIO_AF_T afPin)
{
uint32_t temp = 0x00;
uint32_t temp1 = 0x00;
if (pinSource <= 0x07)
{
temp = (uint8_t)afPin << ((uint32_t)pinSource * 4);
port->ALFL &= ~((uint32_t)0xf << ((uint32_t)pinSource * 4));
port->ALFL |= temp;
}
else
{
temp1 = (uint8_t)afPin << ((uint32_t)(pinSource & 0x07) * 4);
port->ALFH &= ~((uint32_t)0xf << (((uint32_t)pinSource & 0x07) * 4));
port->ALFH |= temp1;
}
}
/**@} end of group GPIO_Functions */
/**@} end of group GPIO_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_iwdt.c
*
* @brief This file contains all the functions for the IWDT peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f0xx_iwdt.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup IWDT_Driver
@{
*/
/** @defgroup IWDT_Macros Macros
@{
*/
/**@} end of group IWDT_Macros*/
/** @defgroup IWDT_Enumerations Enumerations
@{
*/
/**@} end of group IWDT_Enumerations*/
/** @defgroup IWDT_Structures Structures
@{
*/
/**@} end of group IWDT_Structures*/
/** @defgroup IWDT_Variables Variables
@{
*/
/**@} end of group IWDT_Variables*/
/** @defgroup IWDT_Functions Functions
@{
*/
/*!
* @brief Enable IWDT
*
* @param None
*
* @retval None
*/
void IWDT_Enable(void)
{
IWDT->KEY = IWDT_KEY_ENABLE;
}
/*!
* @brief Enable write access to Divider and Counter Reload registers
*
* @param None
*
* @retval None
*/
void IWDT_EnableWriteAccess(void)
{
IWDT->KEY = IWDT_KEY_ACCESS;
}
/*!
* @brief Disable write access to Divider and Counter Reload registers
*
* @param None
*
* @retval None
*/
void IWDT_DisableWriteAccess(void)
{
IWDT->KEY = 0;
}
/*!
* @brief Refresh IWDT
*
* @param None
*
* @retval None
*/
void IWDT_Refresh(void)
{
IWDT->KEY = IWDT_KEY_REFRESH;
}
/*!
* @brief Divider configuration
*
* @param div: Specifies the divider
* The parameter can be one of following values:
* @arg IWDT_DIV_4: Prescaler divider 4
* @arg IWDT_DIV_8: Prescaler divider 8
* @arg IWDT_DIV_16: Prescaler divider 16
* @arg IWDT_DIV_32: Prescaler divider 32
* @arg IWDT_DIV_64: Prescaler divider 64
* @arg IWDT_DIV_128: Prescaler divider 128
* @arg IWDT_DIV_256: Prescaler divider 256
*
* @retval None
*/
void IWDT_ConfigDivider(IWDT_DIV_T div)
{
IWDT->PSC = (uint32_t)div;
}
/*!
* @brief Set counter reload value
*
* @param reload: Specifies the reload value
*
* @retval None
*/
void IWDT_ConfigReload(uint16_t reload)
{
IWDT->CNTRLD = (uint32_t)reload;
}
/*!
* @brief Set counter reload value
*
* @param reload: Specifies the reload value
*
* @retval None
*/
void IWDT_ConfigWindowValue(uint16_t windowValue)
{
IWDT->WIN = (uint32_t)windowValue;
}
/*!
* @brief Read the specified IWDT flag
*
* @param flag: Specifies the flag to read
* The parameter can be one of following values:
* @arg IWDT_FLAG_DIVU: Watchdog prescaler value update
* @arg IWDT_FLAG_CNTU: Watchdog counter reload value update
* @arg IWDT_FLAG_WINU: Watchdog counter window value update
*
* @retval status of IWDT_FLAG (SET or RESET)
*/
uint8_t IWDT_ReadStatusFlag(uint8_t flag)
{
uint8_t bitStatus = RESET;
if ((IWDT->STS & flag) != (uint32_t)RESET)
{
bitStatus = SET;
}
else
{
bitStatus = RESET;
}
return bitStatus;
}
/**@} end of group IWDT_Functions*/
/**@} end of group IWDT_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver*/

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/*!
* @file apm32f0xx_misc.c
*
* @brief This file provides all the miscellaneous firmware functions (add-on to CMSIS functions).
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Includes */
#include "apm32f0xx_misc.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup MISC_Driver
@{
*/
/** @defgroup MISC_Macros Macros
@{
*/
/**@} end of group MISC_Macros*/
/** @defgroup MISC_Enumerations Enumerations
@{
*/
/**@} end of group MISC_Enumerations*/
/** @defgroup MISC_Structures Structures
@{
*/
/**@} end of group MISC_Structures*/
/** @defgroup MISC_Variables Variables
@{
*/
/**@} end of group MISC_Variables*/
/** @defgroup MISC_Functions Functions
@{
*/
/*!
* @brief Enable NVIC request
*
* @param irq: The NVIC interrupt request, detailed in IRQn_Type
*
* @param priority: Specifies the priority needed to set
*
* @retval None
*/
void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t priority)
{
NVIC_SetPriority(irq, priority);
NVIC_EnableIRQ(irq);
}
/*!
* @brief Disable NVIC request
*
* @param irq: The NVIC interrupt request, detailed in IRQn_Type
*
* @retval None
*/
void NVIC_DisableIRQRequest(IRQn_Type irq)
{
NVIC_DisableIRQ(irq);
}
/**
* @brief Enables the system to enter low power mode.
*
* @param lowPowerMode: Specifies the system to enter low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LOWPOER_SEVONPEND: Low Power SEV on Pend.
* @arg NVIC_LOWPOER_SLEEPDEEP: Low Power DEEPSLEEP request.
* @arg NVIC_LOWPOER_SLEEPONEXIT: Low Power Sleep on Exit.
*
* @retval None
*/
void NVIC_EnableSystemLowPower(uint8_t lowPowerMode)
{
SCB->SCR |= lowPowerMode;
}
/**
* @brief Disables the system to enter low power mode.
*
* @param lowPowerMode: Specifies the system to enter low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LOWPOER_SEVONPEND: Low Power SEV on Pend.
* @arg NVIC_LOWPOER_SLEEPDEEP: Low Power DEEPSLEEP request.
* @arg NVIC_LOWPOER_SLEEPONEXIT: Low Power Sleep on Exit.
*
* @retval None
*/
void NVIC_DisableSystemLowPower(uint8_t lowPowerMode)
{
SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode);
}
/**
* @brief Configures the SysTick clock source.
*
* @param sysTickCLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
*
* @retval None
*/
void SysTick_ConfigCLKSource(uint32_t sysTickCLKSource)
{
if (sysTickCLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/*!
* @brief Enter Wait Mode
*
* @param None
*
* @retval None
*/
void PMU_EnterWaitMode(void)
{
SCB->SCR &= (uint32_t)(~(uint32_t)NVIC_LOWPOER_SLEEPDEEP);
__WFI();
}
/*!
* @brief Enter Stop Mode with WFI instruction
*
* @param None
*
* @retval None
*/
void PMU_EnterHaltModeWFI(void)
{
SCB->SCR |= NVIC_LOWPOER_SLEEPDEEP;
__DSB();
__WFI();
}
/*!
* @brief Enter Stop Mode with WFE instruction
*
* @param None
*
* @retval None
*/
void PMU_EnterHaltModeWFE(void)
{
SCB->SCR |= NVIC_LOWPOER_SLEEPDEEP;
__DSB();
__WFE();
}
/**@} end of group MISC_Functions */
/**@} end of group MISC_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_ob.c
*
* @brief This file contains all the functions for the OB peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f0xx_ob.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup OB_Driver
@{
*/
/** @defgroup OB_Macros Macros
@{
*/
/**@} end of group OB_Macros*/
/** @defgroup OB_Enumerations Enumerations
@{
*/
/**@} end of group OB_Enumerations*/
/** @defgroup OB_Structures Structures
@{
*/
/**@} end of group OB_Structures*/
/** @defgroup OB_Variables Variables
@{
*/
/**@} end of group OB_Variables*/
/** @defgroup OB_Functions Functions
@{
*/
/*!
* @brief Read Flash Protection Level
*
* @param readProtection: Specifies the read protection level.
* The parameter can be one of following values:
* @arg OB_READ_PRO_LEVEL0: No protection
* @arg OB_READ_PRO_LEVEL1: Read protection of the memory
* @retval None
*/
void OB_ReadProtectionOptionByte(OB_READ_PRO_T readProtection)
{
OB->READPORT_B.READPROT = readProtection;
}
/*!
* @brief Option Bytes Watchdog
*
* @param wdt: Select Watchdog SW/HW
*
* @retval None
*/
void OB_OptionBytesWatchdog(OB_WDT_T wdt)
{
OB->USER_B.WDTSEL = wdt;
}
/*!
* @brief Option Bytes nRST STOP
*
* @param stop: Select nRST STOP RST/SET
*
* @retval None
*/
void OB_OptionBytesStop(OB_STOP_T stop)
{
OB->USER_B.RSTSTOP = stop;
}
/*!
* @brief Option Bytes nRST STDBY
*
* @param standby: Select nRST STDBY RST/SET
*
* @retval None
*/
void OB_OptionBytesStandby(OB_STANDBY_T standby)
{
OB->USER_B.RSTSTDBY = standby;
}
/*!
* @brief Option Bytes nBOOT1
*
* @param boot: Select nRST BOOT1 RST/SET
*
* @retval None
*/
void OB_OptionBytesBoot1(OB_BOOT1_T boot)
{
OB->USER_B.BOT1 = boot;
}
/*!
* @brief Option Bytes VDDA_Analog_Monitoring
*
* @param vdda: Select VDDA ANALOG OFF/ON
*
* @retval None
*/
void OB_OptionBytesVddaAnalog(OB_VDDA_T vdda)
{
OB->USER_B.VDDAMON = vdda;
}
/*!
* @brief Option Bytes RAM PARITY CHECK
*
* @param rpc: Select RAM PARITY OFF/ON
*
* @retval None
*/
void OB_OptionBytesRamParity(OB_RAM_PARITY_CHECK_T ramParityCheck)
{
OB->USER_B.RPC = ramParityCheck;
}
/**@} end of group OB_Functions */
/**@} end of group OB_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver */

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/*!
* @file apm32f0xx_pmu.c
*
* @brief This file contains all the functions for the PMU peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f0xx_pmu.h"
#include "apm32f0xx_rcm.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup PMU_Driver PMU Driver
@{
*/
/** @defgroup PMU_Macros Macros
@{
*/
/**@} end of group PMU_Macros*/
/** @defgroup PMU_Enumerations Enumerations
@{
*/
/**@} end of group PMU_Enumerations*/
/** @defgroup PMU_Structures Structures
@{
*/
/**@} end of group PMU_Structures*/
/** @defgroup PMU_Variables Variables
@{
*/
/**@} end of group PMU_Variables*/
/** @defgroup PMU_Functions Functions
@{
*/
/*!
* @brief Resets the PWR peripheral registers to their default reset values
*
* @param None
*
* @retval None
*/
void PMU_Reset(void)
{
RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU);
RCM_DisableAPB1PeriphClock(RCM_APB1_PERIPH_PMU);
}
/*!
* @brief Enables access to the Backup domain registers
*
* @param None
*
* @retval None
*/
void PMU_EnableBackupAccess(void)
{
PMU->CTRL_B.BPWEN = BIT_SET;
}
/*!
* @brief Disables access to the Backup domain registers
*
* @param None
*
* @retval None
*/
void PMU_DisableBackupAccess(void)
{
PMU->CTRL_B.BPWEN = BIT_RESET;
}
/*!
* @brief Configures the PMU PVD Level
*
* @param level: specifies the PVD Level
* This parameter can be one of the following values
* @arg PMU_PVDLEVEL_0
* @arg PMU_PVDLEVEL_1
* @arg PMU_PVDLEVEL_2
* @arg PMU_PVDLEVEL_3
* @arg PMU_PVDLEVEL_4
* @arg PMU_PVDLEVEL_5
* @arg PMU_PVDLEVEL_6
* @arg PMU_PVDLEVEL_7
*
* @retval None
*
* @note It's not for APM32F030 devices
*/
void PMU_ConfigPVDLevel(PMU_PVDLEVEL_T level)
{
PMU->CTRL_B.PLSEL = level;
}
/*!
* @brief Enables Power voltage detector
*
* @param None
*
* @retval None
*
* @note It's not for APM32F030 devices
*/
void PMU_EnablePVD(void)
{
PMU->CTRL_B.PVDEN = BIT_SET;
}
/*!
* @brief Disables Power voltage detector
*
* @param None
*
* @retval None
*
* @note It's not for APM32F030 devices
*/
void PMU_DisablePVD(void)
{
PMU->CTRL_B.PVDEN = BIT_RESET;
}
/*!
* @brief Enables the WakeUp Pin functionality
*
* @param pin: specifies the WakeUpPin
* This parameter can be one of the following values
* @arg PMU_WAKEUPPIN_1
* @arg PMU_WAKEUPPIN_2
* @arg PMU_WAKEUPPIN_3 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_4 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_5 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_6 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_7 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_8 It's Only for APM32F072/091 devices
*
* @retval None
*/
void PMU_EnableWakeUpPin(PMU_WAKEUPPIN_T pin)
{
PMU->CSTS |= pin;
}
/*!
* @brief DIsable the WakeUp Pin functionality
*
* @param pin: specifies the WakeUpPin
* This parameter can be one of the following values
* @arg PMU_WAKEUPPIN_1
* @arg PMU_WAKEUPPIN_2
* @arg PMU_WAKEUPPIN_3 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_4 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_5 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_6 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_7 It's Only for APM32F072/091 devices
* @arg PMU_WAKEUPPIN_8 It's Only for APM32F072/091 devices
*
* @retval None
*/
void PMU_DisableWakeUpPin(PMU_WAKEUPPIN_T pin)
{
PMU->CSTS &= ~pin;
}
/*!
* @brief Enters Sleep mode
*
* @param entry :specifies if SLEEP mode in entered with WFI or WFE instruction
* This parameter can be one of the following values:
* @arg PMU_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
* @arg PMU_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
*
* @retval None
*/
void PMU_EnterSleepMode(PMU_SLEEPENTRY_T entry)
{
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
if (entry == PMU_SLEEPENTRY_WFI)
{
__WFI();
}
else
{
__SEV();
__WFE();
__WFE();
}
}
/*!
* @brief Enters STOP mode
*
* @param regulator: specifies the regulator state in STOP mode
* This parameter can be one of the following values:
* @arg PMU_REGULATOR_ON: STOP mode with regulator ON
* @arg PMU_REGULATOR_LowPower: STOP mode with regulator in low power mode
*
* @param entry: specifies if STOP mode in entered with WFI or WFE instruction
* This parameter can be one of the following values:
* @arg PMU_STOPENTRY_WFI: enter STOP mode with WFI instruction
* @arg PMU_STOPENTRY_WFE: enter STOP mode with WFE instruction
* @arg PMU_STOPENTRY_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction
*
* @retval None
*/
void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOPENTRY_T entry)
{
PMU->CTRL_B.PDDSCFG = BIT_RESET;
PMU->CTRL_B.LPDSCFG = regulator;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
switch (entry)
{
case PMU_STOPENTRY_WFI:
__WFI();
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
break;
case PMU_STOPENTRY_WFE:
__WFE();
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
break;
case PMU_STOPENTRY_SLEEPONEXIT:
SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
break;
default:
break;
}
}
/*!
* @brief Enters STANDBY mode
*
* @param None
*
* @retval None
*/
void PMU_EnterSTANDBYMode(void)
{
PMU->CTRL_B.PDDSCFG = BIT_SET;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
}
/*!
* @brief Checks whether the specified PMU flag is set or not
*
* @param flag: specifies the flag to check
* This parameter can be one of the following values:
* @arg PMU_FLAG_WUPF: Wake Up flag
* @arg PMU_FLAG_STDBYF: StandBy flag
* @arg PMU_FLAG_PVDOF: PVD output flag (Not for APM32F030)
* @arg PMU_FLAG_VREFINTF: VREFINT flag
*
* @retval The new state of PMU_FLAG (SET or RESET)
*/
uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
{
uint8_t bit;
if ((PMU->CSTS & flag) != (uint32_t)RESET)
{
bit = SET;
}
else
{
bit = RESET;
}
/** Return the flag status */
return bit;
}
/*!
* @brief Clears the PWR's pending flags
*
* @param flag: specifies the flag to clear
* This parameter can be one of the following values:
* @arg PMU_FLAG_WUPF: Wake Up flag
* @arg PMU_FLAG_STDBYF: StandBy flag
*
* @retval None
*/
void PMU_ClearStatusFlag(uint8_t flag)
{
if (flag == PMU_FLAG_WUPF)
{
PMU->CTRL_B.WUFLGCLR = BIT_SET;
}
else if (flag == PMU_FLAG_STDBYF)
{
PMU->CTRL_B.SBFLGCLR = BIT_SET;
}
}
/**@} end of group PMU_Functions*/
/**@} end of group PMU_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver*/

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/*!
* @file apm32f0xx_spi.c
*
* @brief This file contains all the functions for the SPI peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f0xx_spi.h"
#include "apm32f0xx_rcm.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup SPI_Driver SPI Driver
@{
*/
/** @defgroup SPI_Macros Macros
@{
*/
/**@} end of group SPI_Macros */
/** @defgroup SPI_Enumerations Enumerations
@{
*/
/**@} end of group SPI_Enumerations */
/** @defgroup SPI_Structures Structures
@{
*/
/**@} end of group SPI_Structures */
/** @defgroup SPI_Variables Variables
@{
*/
/**@} end of group SPI_Variables */
/** @defgroup SPI_Functions Functions
@{
*/
/*!
* @brief Set the SPI peripheral registers to their default reset values
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_Reset(SPI_T* spi)
{
if (spi == SPI1)
{
RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
}
else
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
}
}
/*!
* @brief Config the SPI peripheral according to the specified parameters in the adcConfig
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @param spiConfig: Pointer to a SPI_Config_T structure that
* contains the configuration information for the SPI peripheral
*
* @retval None
*/
void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
{
spi->CTRL1_B.MSMCFG = spiConfig->mode;
spi->CTRL2_B.DSCFG = spiConfig->length;
spi->CTRL1_B.CPHA = spiConfig->phase;
spi->CTRL1_B.CPOL = spiConfig->polarity;
spi->CTRL1_B.SSEN = spiConfig->slaveSelect;
spi->CTRL1_B.LSBSEL = spiConfig->firstBit;
spi->CTRL1 &= (uint16_t)~0xC400;
spi->CTRL1 |= (uint32_t)spiConfig->direction;
spi->CTRL1_B.BRSEL = spiConfig->baudrateDiv;
spi->CRCPOLY |= spiConfig->crcPolynomial;
}
/*!
* @brief Config the SPI peripheral according to the specified parameters in the adcConfig
*
* @param spi: Select the the SPI peripheral.It can be SPI1
*
* @param i2sConfig: Pointer to a SPI_Config_T structure that
* contains the configuration information for the SPI peripheral
*
* @retval None
*/
void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
{
uint16_t i2sDiv = 2, i2sOdd = 0, i2sLen = 1;
uint32_t sourceClock = 0, value = 0, temp = 0;
spi->I2SPSC = 0x0002;
spi->I2SCFG &= 0xF040;
temp = spi->I2SCFG;
if (i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT)
{
i2sDiv = (uint16_t)2;
i2sOdd = (uint16_t)0;
}
else
{
if (i2sConfig->length == I2S_DATA_LENGTH_16B)
{
i2sLen = 1;
}
else
{
i2sLen = 2;
}
sourceClock = RCM_ReadSYSCLKFreq();
if (i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE)
{
value = (uint16_t)(((((sourceClock / 256) * 10) / i2sConfig->audioDiv)) + 5);
}
else
{
value = (uint16_t)(((((sourceClock / (32 * i2sLen)) * 10) / i2sConfig->audioDiv)) + 5);
}
value = value / 10;
i2sOdd = (uint16_t)(value & (uint16_t)0x0001);
i2sDiv = (uint16_t)((value - i2sOdd) / 2);
}
if ((i2sDiv < 2) || (i2sDiv > 0xFF))
{
i2sDiv = 2;
i2sOdd = 0;
}
spi->I2SPSC_B.I2SPSC = i2sDiv;
spi->I2SPSC_B.ODDPSC = i2sOdd;
spi->I2SPSC_B.MCOEN = i2sConfig->MCLKOutput;
spi->I2SCFG_B.MODESEL = BIT_SET;
spi->I2SCFG_B.I2SMOD = i2sConfig->mode;
spi->I2SCFG_B.CPOL = i2sConfig->polarity;
temp = (uint16_t)((uint16_t)i2sConfig->standard | (uint16_t)i2sConfig->length);
spi->I2SCFG |= temp;
}
/*!
* @brief Fills each spiConfig member with its default value
*
* @param spiConfig: Pointer to a SPI_Config_T structure which will be initialized
*
* @retval None
*/
void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
{
spiConfig->mode = SPI_MODE_SLAVE;
spiConfig->length = SPI_DATA_LENGTH_8B;
spiConfig->phase = SPI_CLKPHA_1EDGE;
spiConfig->polarity = SPI_CLKPOL_HIGH;
spiConfig->slaveSelect = SPI_SSC_DISABLE;
spiConfig->firstBit = SPI_FIRST_BIT_MSB;
spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX;
spiConfig->baudrateDiv = SPI_BAUDRATE_DIV_2;
spiConfig->crcPolynomial = 7;
}
/*!
* @brief Fills each i2sConfig member with its default value
*
* @param i2sConfig: Pointer to a SPI_Config_T structure which will be initialized
*
* @retval None
*/
void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
{
i2sConfig->mode = I2S_MODE_SLAVER_TX;
i2sConfig->standard = I2S_STANDARD_PHILIPS;
i2sConfig->length = I2S_DATA_LENGTH_16B;
i2sConfig->MCLKOutput = I2S_MCLK_OUTPUT_DISABLE;
i2sConfig->audioDiv = I2S_AUDIO_DIV_DEFAULT;
i2sConfig->polarity = I2S_CLKPOL_LOW;
}
/*!
* @brief Enable the SPI peripheral
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_Enable(SPI_T* spi)
{
spi->CTRL1_B.SPIEN = BIT_SET;
}
/*!
* @brief Disable the SPI peripheral
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_Disable(SPI_T* spi)
{
spi->CTRL1_B.SPIEN = BIT_RESET;
}
/*!
* @brief Enable the SPI peripheral
*
* @param spi: Select the the SPI peripheral.It can be SPI1
*
* @retval None
*
* @note Not supported for APM32F030 devices.
*/
void I2S_Enable(SPI_T* spi)
{
spi->I2SCFG_B.I2SEN = BIT_SET;
}
/*!
* @brief Disable the SPI peripheral
*
* @param spi: Select the the SPI peripheral.It can be SPI1
*
* @retval None
*
* @note Not supported for APM32F030 devices.
*/
void I2S_Disable(SPI_T* spi)
{
spi->I2SCFG_B.I2SEN = BIT_RESET;
}
/*!
* @brief Enable the frame format mode
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_EnableFrameFormatMode(SPI_T* spi)
{
spi->CTRL2_B.FRFCFG = BIT_SET;
}
/*!
* @brief Disable the frame format mode
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_DisableFrameFormatMode(SPI_T* spi)
{
spi->CTRL2_B.FRFCFG = BIT_RESET;
}
/*!
* @brief Configures the SPI data length
*
* @param length: specifies the SPI length
* The parameter can be one of following values:
* @arg SPI_DATA_LENGTH_4B: Set data length to 4 bits
* @arg SPI_DATA_LENGTH_5B: Set data length to 5 bits
* @arg SPI_DATA_LENGTH_6B: Set data length to 6 bits
* @arg SPI_DATA_LENGTH_7B: Set data length to 7 bits
* @arg SPI_DATA_LENGTH_8B: Set data length to 8 bits
* @arg SPI_DATA_LENGTH_9B: Set data length to 9 bits
* @arg SPI_DATA_LENGTH_10B: Set data length to 10 bits
* @arg SPI_DATA_LENGTH_11B: Set data length to 11 bits
* @arg SPI_DATA_LENGTH_12B: Set data length to 12 bits
* @arg SPI_DATA_LENGTH_13B: Set data length to 13 bits
* @arg SPI_DATA_LENGTH_14B: Set data length to 14 bits
* @arg SPI_DATA_LENGTH_15B: Set data length to 15 bits
* @arg SPI_DATA_LENGTH_16B: Set data length to 16 bits
*
* @retval None
*/
void SPI_ConfigDatalength(SPI_T* spi, uint8_t length)
{
spi->CTRL2_B.DSCFG = (uint8_t)length;
}
/*!
* @brief Configures the FIFO reception threshold
*
* @param threshold: selects the SPI FIFO reception threshold
* The parameter can be one of following values:
* @arg SPI_RXFIFO_HALF: FIFO level is greater than or equal to 1/2 (16-bit)
* @arg SPI_RXFIFO_QUARTER: FIFO level is greater than or equal to 1/4 (8-bit)
*
* @retval None
*/
void SPI_ConfigFIFOThreshold(SPI_T* spi, SPI_RXFIFO_T threshold)
{
spi->CTRL2_B.FRTCFG = threshold;
}
/*!
* @brief Enable the data transfer direction
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_EnableOutputDirection(SPI_T* spi)
{
spi->CTRL1_B.BMOEN = BIT_SET;
}
/*!
* @brief Disable the data transfer direction
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_DisableOutputDirection(SPI_T* spi)
{
spi->CTRL1_B.BMOEN = BIT_RESET;
}
/*!
* @brief Enable internal slave select
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_EnableInternalSlave(SPI_T* spi)
{
spi->CTRL1_B.ISSEL = BIT_SET;
}
/*!
* @brief Disable internal slave select
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_DisableInternalSlave(SPI_T* spi)
{
spi->CTRL1_B.ISSEL = BIT_RESET;
}
/*!
* @brief Enable the SS output mode
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_EnableSSoutput(SPI_T* spi)
{
spi->CTRL2_B.SSOEN = BIT_SET;
}
/*!
* @brief Disable the SS output mode
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_DisableSSoutput(SPI_T* spi)
{
spi->CTRL2_B.SSOEN = BIT_RESET;
}
/*!
* @brief Enable the NSS pulse management mode
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_EnableNSSPulse(SPI_T* spi)
{
spi->CTRL2_B.NSSPEN = BIT_SET;
}
/*!
* @brief Disable the NSS pulse management mode
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_DisableNSSPulse(SPI_T* spi)
{
spi->CTRL2_B.NSSPEN = BIT_RESET;
}
/*!
* @brief Transmits a Data
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @param data: Byte to be transmitted
*
* @retval None
*/
void SPI_I2S_TxData16(SPI_T* spi, uint16_t data)
{
spi->DATA = (uint16_t)data;
}
/*!
* @brief Transmits a uint8_t Data
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @param data: Byte to be transmitted
*
* @retval None
*/
void SPI_TxData8(SPI_T* spi, uint8_t data)
{
*((uint8_t*) & (spi->DATA)) = data;
}
/*!
* @brief Returns the most recent received data by the SPI peripheral
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @param None
*
* @retval The value of the received data
*/
uint16_t SPI_I2S_RxData16(SPI_T* spi)
{
return ((uint16_t)spi->DATA);
}
/*!
* @brief Returns the most recent received data by the SPI peripheral
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @param None
*
* @retval The value of the received data
*/
uint8_t SPI_RxData8(SPI_T* spi)
{
return *((uint8_t*) & (spi->DATA));
}
/*!
* @brief Selects the data transfer direction
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
* @param crcLength: selects the SPI transfer direction
* The parameter can be one of following values:
* @arg SPI_CRC_LENGTH_8B: 8-bit CRC length
* @arg SPI_CRC_LENGTH_16B: 16-bit CRC length
*
* @retval None
*/
void SPI_CRCLength(SPI_T* spi, SPI_CRC_LENGTH_T crcLength)
{
spi->CTRL1_B.CRCLSEL = crcLength;
}
/*!
* @brief Enable the CRC value calculation
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_EnableCRC(SPI_T* spi)
{
spi->CTRL1_B.CRCEN = BIT_SET;
}
/*!
* @brief Disable the CRC value calculation
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_DisableCRC(SPI_T* spi)
{
spi->CTRL1_B.CRCEN = BIT_RESET;
}
/*!
* @brief Transmit CRC value
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_TxCRC(SPI_T* spi)
{
spi->CTRL1_B.CRCNXT = BIT_SET;
}
/*!
* @brief Returns the receive CRC register value
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*
* @note None
*/
uint16_t SPI_ReadRxCRC(SPI_T* spi)
{
return (uint16_t)spi->RXCRC;
}
/*!
* @brief Returns the transmit CRC register value
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*
* @note None
*/
uint16_t SPI_ReadTxCRC(SPI_T* spi)
{
return (uint16_t)spi->TXCRC;
}
/*!
* @brief Returns the CRC Polynomial register value
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
{
return (uint16_t)spi->CRCPOLY;
}
/*!
* @brief Enable the DMA Rx buffer
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_EnableDMARxBuffer(SPI_T* spi)
{
spi->CTRL2_B.RXDEN = BIT_SET;
}
/*!
* @brief Disable the DMA Rx buffer
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_DisableDMARxBuffer(SPI_T* spi)
{
spi->CTRL2_B.RXDEN = BIT_RESET;
}
/*!
* @brief Enable the DMA Tx buffer
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_EnableDMATxBuffer(SPI_T* spi)
{
spi->CTRL2_B.TXDEN = BIT_SET;
}
/*!
* @brief Disable the DMA Tx buffer
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval None
*/
void SPI_DisableDMATxBuffer(SPI_T* spi)
{
spi->CTRL2_B.TXDEN = BIT_RESET;
}
/*!
* @brief Selects the last DMA transfer is type(Even/Odd)
*
* @param crcLength: specifies the SPI last DMA transfers
* The parameter can be one of following values:
* @arg SPI_LAST_DMA_TXRXEVEN: transmission Even reception Even
* @arg SPI_LAST_DMA_TXEVENRXODD: transmission Even reception Odd
* @arg SPI_LAST_DMA_TXODDRXEVEN: transmission Odd reception Even
* @arg SPI_LAST_DMA_TXRXODD: transmission Odd reception Odd
*
* @retval None
*/
void SPI_LastDMATransfer(SPI_T* spi, SPI_LAST_DMA_T lastDMA)
{
spi->CTRL2 &= 0x9FFF;
spi->CTRL2 |= (uint16_t)lastDMA;
}
/*!
* @brief Returns the SPI Transmission FIFO filled level
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval Transmission FIFO filled level:
* SPI_TXFIFO_LEVEL_EMPTY: Transmission FIFO filled level is empty
* SPI_TXFIFO_LEVEL_QUARTER: Transmission FIFO filled level is more than quarter
* SPI_TXFIFO_LEVEL_HALF: Transmission FIFO filled level is more than half
* SPI_TXFIFO_LEVEL_FULL: Transmission FIFO filled level is full
*/
uint8_t SPI_ReadTransmissionFIFOLeve(SPI_T* spi)
{
return (uint8_t)((spi->STS_B.FTLSEL & 0x03));
}
/*!
* @brief Returns the SPI Reception FIFO filled level
*
* @param spi: Select the the SPI peripheral.It can be SPI1/SPI2
*
* @retval Reception FIFO filled level:
* SPI_RXFIFO_LEVEL_EMPTY: Reception FIFO filled level is empty
* SPI_RXFIFO_LEVEL_QUARTER: Reception FIFO filled level is more than quarter
* SPI_RXFIFO_LEVEL_HALF: Reception FIFO filled level is more than half
* SPI_RXFIFO_LEVEL_FULL: Reception FIFO filled level is full
*/
uint8_t SPI_ReadReceptionFIFOLeve(SPI_T* spi)
{
return (uint8_t)((spi->STS_B.FRLSEL & 0x03));
}
/*!
* @brief Enable the SPI interrupts
*
* @param interrupt: Specifies the SPI interrupts sources
* The parameter can be combination of following values:
* @arg SPI_INT_ERRIE: Error interrupt
* @arg SPI_INT_RXBNEIE: Receive buffer not empty interrupt
* @arg SPI_INT_TXBEIE: Transmit buffer empty interrupt
*
* @retval None
*/
void SPI_EnableInterrupt(SPI_T* spi, uint8_t interrupt)
{
spi->CTRL2 |= (uint8_t)interrupt;
}
/*!
* @brief Disable the SPI interrupts
*
* @param interrupt: Specifies the SPI interrupts sources
* The parameter can be combination of following values:
* @arg SPI_INT_ERRIE: Error interrupt
* @arg SPI_INT_RXBNEIE: Receive buffer not empty interrupt
* @arg SPI_INT_TXBEIE: Transmit buffer empty interrupt
*
* @retval None
*/
void SPI_DisableInterrupt(SPI_T* spi, uint8_t interrupt)
{
spi->CTRL2 &= (uint8_t)~interrupt;
}
/*!
* @brief Checks whether the specified SPI flag is set or not
*
* @param flag: Specifies the flag to check
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXBNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXBE: Transmit buffer empty flag
* @arg I2S_FLAG_CHDIR: Channel direction flag
* @arg I2S_FLAG_UDR: Underrun flag
* @arg SPI_FLAG_CRCE: CRC error flag
* @arg SPI_FLAG_MME: Master mode error flag
* @arg SPI_FLAG_OVR: Receive Overrun flag
* @arg SPI_FLAG_BUSY: Busy flag
* @arg SPI_FLAG_FFE: Frame format error flag
*
* @retval The new state of flag (SET or RESET)
*/
uint8_t SPI_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
{
uint16_t status;
status = (uint16_t)(spi->STS & flag);
if (status == flag)
{
return SET;
}
return RESET;
}
/*!
* @brief Clear the specified SPI flag
*
* @param flag: Specifies the flag to clear
* This parameter can be any combination of the following values:
* @arg SPI_FLAG_CRCE: CRC error flag
* @retval None
*/
void SPI_ClearStatusFlag(SPI_T* spi, uint8_t flag)
{
spi->STS &= (uint32_t)~flag;
}
/*!
* @brief Checks whether the specified interrupt has occurred or not
*
* @param flag: Specifies the SPI interrupt pending bit to check
* This parameter can be one of the following values:
* @arg SPI_INT_FLAG_RXBNE: Receive buffer not empty flag
* @arg SPI_INT_FLAG_TXBE: Transmit buffer empty flag
* @arg SPI_INT_FLAG_UDR: Underrun flag interrupt flag
* @arg SPI_INT_FLAG_MME: Master mode error flag
* @arg SPI_INT_FLAG_OVR: Receive Overrun flag
* @arg SPI_INT_FLAG_FFE: Frame format error interrupt flag
*
* @retval None
*/
uint8_t SPI_ReadIntFlag(SPI_T* spi, SPI_INT_FLAG_T flag)
{
uint32_t intEnable;
uint32_t intStatus;
intEnable = (uint32_t)(spi->CTRL2 & (uint32_t)(flag >> 16));
intStatus = (uint32_t)(spi->STS & (uint32_t)(flag & 0x1ff));
if (intEnable && intStatus)
{
return SET;
}
return RESET;
}
/**@} end of group SPI_Functions*/
/**@} end of group SPI_Driver*/
/**@} end of group APM32F0xx_StdPeriphDriver*/

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/*!
* @file apm32f0xx_syscfg.c
*
* @brief This file contains all the functions for the SYSCFG peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f0xx_syscfg.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup SYSCFG_Driver SYSCFG Driver
@{
*/
/** @defgroup SYSCFG_Macros Macros
@{
*/
/**@} end of group SYSCFG_Macros */
/** @defgroup SYSCFG_Enumerations Enumerations
@{
*/
/**@} end of group SYSCFG_Enumerations */
/** @defgroup SYSCFG_Structures Structures
@{
*/
/**@} end of group SYSCFG_Structures */
/** @defgroup SYSCFG_Variables Variables
@{
*/
/**@} end of group SYSCFG_Variables */
/** @defgroup SYSCFG_Functions Functions
@{
*/
/*!
* @brief Set SYSCFG CFG0/1 EINTCFG1/2/3/4 register to reset value
*
* @param None
*
* @retval None
*/
void SYSCFG_Reset(void)
{
SYSCFG->CFG1 &= (uint32_t) SYSCFG_CFG1_MEMMODE;
SYSCFG->EINTCFG1 = 0;
SYSCFG->EINTCFG2 = 0;
SYSCFG->EINTCFG3 = 0;
SYSCFG->EINTCFG4 = 0;
SYSCFG->CFG2 |= (uint32_t) SYSCFG_CFG2_SRAMPEF;
}
/*!
* @brief SYSCFG Memory Remap selects
*
* @param memory: selects the memory remapping
* The parameter can be one of following values:
* @arg SYSCFG_MEMORY_REMAP_FMC: SYSCFG MemoryRemap Flash
* @arg SYSCFG_MEMORY_REMAP_SYSTEM: SYSCFG MemoryRemap SystemMemory
* @arg SYSCFG_MEMORY_REMAP_SRAM: SYSCFG MemoryRemap SRAM
*
* @retval None
*/
void SYSCFG_MemoryRemapSelect(uint8_t memory)
{
SYSCFG->CFG1_B.MMSEL = (uint8_t)memory;
}
/*!
* @brief Enables SYSCFG DMA Channel Remap
*
* @param channel: selects the DMA channels remap.
* The parameter can be any combination of following values:
* @arg SYSCFG_DAM_REMAP_ADC: ADC DMA remap
* @arg SYSCFG_DAM_REMAP_USART1TX: USART1 TX DMA remap
* @arg SYSCFG_DAM_REMAP_USART1RX: USART1 RX DMA remap
* @arg SYSCFG_DAM_REMAP_TMR16: Timer 16 DMA remap
* @arg SYSCFG_DAM_REMAP_TMR17: Timer 17 DMA remap
* @arg SYSCFG_DAM_REMAP_TMR16_2： Timer 16 DMA remap2(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_TMR17_2： Timer 17 DMA remap2(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_SPI2： SPI2 DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_USART2： USART1 TX DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_USART3： USART1 RX DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_I2C1： I2C1 DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_TMR1： Timer 1 DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_TMR2： Timer 2 DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_TMR3： Timer 3 DMA remap(only for APM32F072)
*
* @retval None
*/
void SYSCFG_EnableDMAChannelRemap(uint32_t channel)
{
SYSCFG->CFG1 |= (uint32_t)channel;
}
/*!
* @brief Disables SYSCFG DMA Channel Remap
*
* @param channel: selects the DMA channels remap.
* The parameter can be any combination of following values:
* @arg SYSCFG_DAM_REMAP_ADC: ADC DMA remap
* @arg SYSCFG_DAM_REMAP_USART1TX: USART1 TX DMA remap
* @arg SYSCFG_DAM_REMAP_USART1RX: USART1 RX DMA remap
* @arg SYSCFG_DAM_REMAP_TMR16: Timer 16 DMA remap
* @arg SYSCFG_DAM_REMAP_TMR17: Timer 17 DMA remap
* @arg SYSCFG_DAM_REMAP_TMR16_2： Timer 16 DMA remap2(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_TMR17_2： Timer 17 DMA remap2(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_SPI2： SPI2 DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_USART2： USART1 TX DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_USART3： USART1 RX DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_I2C1： I2C1 DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_TMR1： Timer 1 DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_TMR2： Timer 2 DMA remap(only for APM32F072)
* @arg SYSCFG_DAM_REMAP_TMR3： Timer 3 DMA remap(only for APM32F072)
*
* @retval None
*/
void SYSCFG_DisableDMAChannelRemap(uint32_t channel)
{
SYSCFG->CFG1 &= (uint32_t)~channel;
}
/*!
* @brief Enables SYSCFG I2C Fast Mode Plus
*
* @param pin: selects the pin.
* The parameter can be combination of following values:
* @arg SYSCFG_I2C_FMP_PB6: I2C PB6 Fast mode plus
* @arg SYSCFG_I2C_FMP_PB7: I2C PB7 Fast mode plus
* @arg SYSCFG_I2C_FMP_PB8: I2C PB8 Fast mode plus
* @arg SYSCFG_I2C_FMP_PB9: I2C PB9 Fast mode plus
* @arg SYSCFG_I2C_FMP_PA9: I2C PA9 Fast mode plus(only for APM32F030 and APM32F091)
* @arg SYSCFG_I2C_FMP_PA10: I2C PA10 Fast mode plus(only for APM32F030 and APM32F091)
* @arg SYSCFG_I2C_FMP_I2C1: PB10, PB11, PF6 and PF7
* @arg SYSCFG_I2C_FMP_I2C2: I2C2 Fast mode plus(only for APM32F072 and APM32F091)
*
* @retval None
*/
void SYSCFG_EnableI2CFastModePlus(uint32_t pin)
{
SYSCFG->CFG1 |= (uint32_t)pin;
}
/*!
* @brief Disables SYSCFG I2C Fast Mode Plus
*
* @param pin: selects the pin.
* The parameter can be combination of following values:
* @arg SYSCFG_I2C_FMP_PB6: I2C PB6 Fast mode plus
* @arg SYSCFG_I2C_FMP_PB7: I2C PB7 Fast mode plus
* @arg SYSCFG_I2C_FMP_PB8: I2C PB8 Fast mode plus
* @arg SYSCFG_I2C_FMP_PB9: I2C PB9 Fast mode plus
* @arg SYSCFG_I2C_FMP_PA9: I2C PA9 Fast mode plus(only for APM32F030 and APM32F091)
* @arg SYSCFG_I2C_FMP_PA10: I2C PA10 Fast mode plus(only for APM32F030 and APM32F091)
* @arg SYSCFG_I2C_FMP_I2C1: PB10, PB11, PF6 and PF7
* @arg SYSCFG_I2C_FMP_I2C2: I2C2 Fast mode plus(only for APM32F072 and APM32F091)
*
* @retval None
*/
void SYSCFG_DisableI2CFastModePlus(uint32_t pin)
{
SYSCFG->CFG1 &= (uint32_t)~pin;
}
/*!
* @brief Select the modulation envelope source
*
* @param IRDAEnv: selects the envelope source
* The parameter can be one of following values:
* @arg SYSCFG_IRDA_ENV_TMR16: Timer16 as IRDA Modulation envelope source
* @arg SYSCFG_IRDA_ENV_USART1: USART1 as IRDA Modulation envelope source
* @arg SYSCFG_IRDA_ENV_USART2: USART4 as IRDA Modulation envelope source
*
* @retval None
*
* @note It's only for APM32F091 devices.
*/
void SYSCFG_SelectIRDAEnv(SYSCFG_IRDA_ENV_T IRDAEnv)
{
SYSCFG->CFG1 &= ~(0x000000C0);
SYSCFG->CFG1 |= (IRDAEnv);
}
/*!
* @brief Selects the GPIO pin used as EINT Line.
*
* @param port: selects the port can be GPIOA/B/C/D/E/F
*
* @param pin: selects the pin can be SYSCFG_PIN_(0..15)
*
* @retval None
*
* @note GPIOE only for APM32F072 and APM32F091
*/
void SYSCFG_EINTLine(SYSCFG_PORT_T port, SYSCFG_PIN_T pin)
{
uint32_t status;
status = (((uint32_t)0x0F) & port) << (0x04 * (pin & (uint8_t)0x03));
if (pin <= 0x03)
{
SYSCFG->EINTCFG1 |= status;
}
else if ((0x04 <= pin) & (pin <= 0x07))
{
SYSCFG->EINTCFG2 |= status;
}
else if ((0x08 <= pin) & (pin <= 0x0B))
{
SYSCFG->EINTCFG3 |= status;
}
else if ((0x0C <= pin) & (pin <= 0x0F))
{
SYSCFG->EINTCFG4 |= status;
}
}
/*!
* @brief Selected parameter to the break input of TMR1.
*
* @param lock: selects the configuration to break
* The parameter can be one of following values:
* @arg SYSCFG_LOCK_LOCKUP: Cortex-M0 LOCKUP bit
* @arg SYSCFG_LOCK_SRAM: SRAM parity lock bit
* @arg SYSCFG_LOCK_PVD: PVD lock enable bit
*
* @retval None
*/
void SYSCFG_BreakLock(uint32_t lock)
{
SYSCFG->CFG2_B.LOCK = 0;
SYSCFG->CFG2_B.SRAMLOCK = 0;
SYSCFG->CFG2_B.PVDLOCK = 0;
if (lock == SYSCFG_LOCK_LOCKUP)
{
SYSCFG->CFG2_B.LOCK = BIT_SET;
}
if (lock == SYSCFG_LOCK_SRAM)
{
SYSCFG->CFG2_B.SRAMLOCK = BIT_SET;
}
if (lock == SYSCFG_LOCK_PVD)
{
SYSCFG->CFG2_B.PVDLOCK = BIT_SET;
}
}
/*!
* @brief Read the specified SYSCFG flag
*
* @param flag: SRAM Parity error flag
* @arg SYSCFG_CFG2_SRAMPEF
*
* @retval None
*/
uint8_t SYSCFG_ReadStatusFlag(uint32_t flag)
{
uint32_t status;
status = (uint32_t)(SYSCFG->CFG2 & flag);
if (status == flag)
{
return SET;
}
return RESET;
}
/*!
* @brief Clear the specified SYSCFG flag
*
* @param flag: SRAM Parity error flag
* @arg SYSCFG_CFG2_SRAMPEF
*
* @retval None
*/
void SYSCFG_ClearStatusFlag(uint8_t flag)
{
SYSCFG->CFG2 |= (uint32_t) flag;
}
/**@} end of group SYSCFG_Functions*/
/**@} end of group SYSCFG_Driver*/
/**@} end of group APM32F0xx_StdPeriphDriver*/

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/*!
* @file apm32f0xx_wwdt.c
*
* @brief This file contains all the functions for the WWDG peripheral
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
#include "apm32f0xx_wwdt.h"
#include "apm32f0xx_rcm.h"
/** @addtogroup APM32F0xx_StdPeriphDriver
@{
*/
/** @addtogroup WWDT_Driver WWDT Driver
@{
*/
/** @defgroup WWDT_Macros Macros
@{
*/
/**@} end of group WWDT_Macros */
/** @defgroup WWDT_Enumerations Enumerations
@{
*/
/**@} end of group WWDT_Enumerations */
/** @defgroup WWDT_Structures Structures
@{
*/
/**@} end of group WWDT_Structures */
/** @defgroup WWDT_Variables Variables
@{
*/
/**@} end of group WWDT_Variables */
/** @defgroup WWDT_Functions Functions
@{
*/
/*!
* @brief Set the WWDT peripheral registers to their default reset values
*
* @param None
* @retval None
*/
void WWDT_Reset(void)
{
RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT);
RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT);
}
/*!
* @brief Set the WWDT Timebase
*
* @param timebase: WWDT Prescaler
* The parameter can be one of following values:
* @arg WWDT_DIV_1: WWDT counter clock = (PCLK1/4096)/1
* @arg WWDT_DIV_2: WWDT counter clock = (PCLK1/4096)/2
* @arg WWDT_DIV_4: WWDT counter clock = (PCLK1/4096)/4
* @arg WWDT_DIV_8: WWDT counter clock = (PCLK1/4096)/8
*
* @retval None
*/
void WWDT_SetTimebase(uint32_t div)
{
WWDT->CFG_B.TBPSC = 0;
WWDT->CFG_B.TBPSC = div;
}
/*!
* @brief Set the Window data
*
* @param data: Specifies the window data to be set
*
* @retval None
*/
void WWDT_ConfigWindowValue(uint16_t windowValue)
{
uint32_t reg;
reg = (windowValue | BIT6) & 0x7f;
WWDT->CFG_B.WIN = reg;
}
/*!
* @brief Enable the WWDT Early Wakeup interrupt
*
* @param None
*
* @retval None
*/
void WWDT_EnableEWI(void)
{
WWDT->CFG_B.EWIEN = SET;
}
/*!
* @brief Set counter
*
* @param couter: Specifies the counter to be set
*
* @retval None
*/
void WWDT_ConfigCounter(uint8_t couter)
{
WWDT->CTRL = (uint32_t)(couter & 0x7f);
}
/*!
* @brief Enable WWDT and set the counter value
*
* @param count: the window watchdog counter value
*
* @retval None
*/
void WWDT_Enable(uint8_t count)
{
WWDT->CTRL_B.CNT = count;
WWDT->CTRL_B.WWDTEN = SET;
}
/*!
* @brief Read the Early Wakeup interrupt flag
*
* @param None
*
* @retval the state of the Early Wakeup interrupt flag
*/
uint8_t WWDT_ReadStatusFlag(void)
{
return (uint8_t)(WWDT->STS);
}
/*!
* @brief Clear the Early Wakeup interrupt flag
*
* @param None
*
* @retval None
*/
void WWDT_ClearStatusFlag(void)
{
WWDT->STS_B.EWIFLG = RESET;
}
/**@} end of group WWDT_Functions*/
/**@} end of group WWDT_Driver */
/**@} end of group APM32F0xx_StdPeriphDriver*/

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/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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Apache License
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/*!
* @file system_apm32f0xx.h
*
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File
*
* @details This file contains the system clock configuration for APM32F0xx devices.
*
* @version V1.0.3
*
* @date 2022-09-20
*
* @attention
*
* Copyright (C) 2020-2022 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
*
* The program is only for reference, which is distributed in the hope
* that it will be useful and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
* and limitations under the License.
*/
/* Define to prevent recursive inclusion */
#ifndef __SYSTEM_APM32F0XX_H
#define __SYSTEM_APM32F0XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup CMSIS
@{
*/
/** @addtogroup APM32F0xx_System
@{
*/
/** @defgroup System_Macros Macros
@{
*/
/**@} end of group System_Macros */
/** @defgroup System_Enumerations Enumerations
@{
*/
/**@} end of group System_Enumerations */
/** @defgroup System_Structures Structures
@{
*/
/**@} end of group System_Structures */
/** @defgroup System_Variables Variables
@{
*/
/* System Clock Frequency (Core Clock) */
extern uint32_t SystemCoreClock;
/**@} end of group System_Variables */
/** @defgroup System_Functions Functions
@{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_APM32F0XX_H */
/**@} end of group System_Functions */
/**@} end of group APM32F0xx_System */
/**@} end of group CMSIS */

239
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@ -0,0 +1,239 @@
;/*!
; * @file startup_apm32f030.s
; *
; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f030
; *
; * @version V1.0.2
; *
; * @date 2022-02-21
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD 0 ; Reserved
DCD RTC_IRQHandler ; RTC through EINT Line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_1_IRQHandler ; EINT Line 0 and 1
DCD EINT2_3_IRQHandler ; EINT Line 2 and 3
DCD EINT4_15_IRQHandler ; EINT Line 4 to 15
DCD 0 ; Reserved
DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1
DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_CH4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_IRQHandler ; ADC1
DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD 0 ; Reserved
DCD TMR3_IRQHandler ; TMR3
DCD TMR6_IRQHandler ; TMR6
DCD TMR7_IRQHandler ; TMR7
DCD TMR14_IRQHandler ; TMR14
DCD TMR15_IRQHandler ; TMR15
DCD TMR16_IRQHandler ; TMR16
DCD TMR17_IRQHandler ; TMR17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_6_IRQHandler ; USART3,USART4,USART5,USART6
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_1_IRQHandler [WEAK]
EXPORT EINT2_3_IRQHandler [WEAK]
EXPORT EINT4_15_IRQHandler [WEAK]
EXPORT DMA1_CH1_IRQHandler [WEAK]
EXPORT DMA1_CH2_3_IRQHandler [WEAK]
EXPORT DMA1_CH4_5_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR6_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT TMR14_IRQHandler [WEAK]
EXPORT TMR15_IRQHandler [WEAK]
EXPORT TMR16_IRQHandler [WEAK]
EXPORT TMR17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_6_IRQHandler [WEAK]
WWDT_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_1_IRQHandler
EINT2_3_IRQHandler
EINT4_15_IRQHandler
DMA1_CH1_IRQHandler
DMA1_CH2_3_IRQHandler
DMA1_CH4_5_IRQHandler
ADC1_IRQHandler
TMR1_BRK_UP_TRG_COM_IRQHandler
TMR1_CC_IRQHandler
TMR3_IRQHandler
TMR6_IRQHandler
TMR7_IRQHandler
TMR14_IRQHandler
TMR15_IRQHandler
TMR16_IRQHandler
TMR17_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_6_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

246
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@ -0,0 +1,246 @@
;/*!
; * @file startup_apm32f051.s
; *
; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f030
; *
; * @version V1.0.2
; *
; * @date 2022-02-21
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EINT Line detect
DCD RTC_IRQHandler ; RTC through EINT Line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_1_IRQHandler ; EINT Line 0 and 1
DCD EINT2_3_IRQHandler ; EINT Line 2 and 3
DCD EINT4_15_IRQHandler ; EINT Line 4 to 15
DCD TSC_IRQHandler ; TSC
DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1
DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_CH4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC
DCD 0 ; Reserved
DCD TMR14_IRQHandler ; TMR14
DCD TMR15_IRQHandler ; TMR15
DCD TMR16_IRQHandler ; TMR16
DCD TMR17_IRQHandler ; TMR17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD CEC_IRQHandler ; CEC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_1_IRQHandler [WEAK]
EXPORT EINT2_3_IRQHandler [WEAK]
EXPORT EINT4_15_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT DMA1_CH1_IRQHandler [WEAK]
EXPORT DMA1_CH2_3_IRQHandler [WEAK]
EXPORT DMA1_CH4_5_IRQHandler [WEAK]
EXPORT ADC1_COMP_IRQHandler [WEAK]
EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR6_DAC_IRQHandler [WEAK]
EXPORT TMR14_IRQHandler [WEAK]
EXPORT TMR15_IRQHandler [WEAK]
EXPORT TMR16_IRQHandler [WEAK]
EXPORT TMR17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_1_IRQHandler
EINT2_3_IRQHandler
EINT4_15_IRQHandler
TSC_IRQHandler
DMA1_CH1_IRQHandler
DMA1_CH2_3_IRQHandler
DMA1_CH4_5_IRQHandler
ADC1_COMP_IRQHandler
TMR1_BRK_UP_TRG_COM_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR6_DAC_IRQHandler
TMR14_IRQHandler
TMR15_IRQHandler
TMR16_IRQHandler
TMR17_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
CEC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
>>>>>>> .r17560

243
bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f070.s Normal file
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@ -0,0 +1,243 @@
;/*!
; * @file startup_apm32f070.s
; *
; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f070
; *
; * @version V1.0.2
; *
; * @date 2022-02-21
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD 0 ; Reserved
DCD RTC_IRQHandler ; RTC through EINT Line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_IRQHandler ; RCM
DCD EINT0_1_IRQHandler ; EINT Line 0 and 1
DCD EINT2_3_IRQHandler ; EINT Line 2 and 3
DCD EINT4_15_IRQHandler ; EINT Line 4 to 15
DCD 0 ; Reserved
DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1
DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_CH4_5_IRQHandler ; DMA1 Channel 4, Channel 5
DCD ADC1_IRQHandler ; ADC1
DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD 0 ; Reserved
DCD TMR3_IRQHandler ; TMR3
DCD TMR6_IRQHandler ; TMR6
DCD TMR7_IRQHandler ; TMR7
DCD TMR14_IRQHandler ; TMR14
DCD TMR15_IRQHandler ; TMR15
DCD TMR16_IRQHandler ; TMR16
DCD TMR17_IRQHandler ; TMR17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_4_IRQHandler ; USART3 and USART4
DCD 0 ; Reserved
DCD USBD_IRQHandler ; USB
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_IRQHandler [WEAK]
EXPORT EINT0_1_IRQHandler [WEAK]
EXPORT EINT2_3_IRQHandler [WEAK]
EXPORT EINT4_15_IRQHandler [WEAK]
EXPORT DMA1_CH1_IRQHandler [WEAK]
EXPORT DMA1_CH2_3_IRQHandler [WEAK]
EXPORT DMA1_CH4_5_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR6_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT TMR14_IRQHandler [WEAK]
EXPORT TMR15_IRQHandler [WEAK]
EXPORT TMR16_IRQHandler [WEAK]
EXPORT TMR17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_4_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
WWDT_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCM_IRQHandler
EINT0_1_IRQHandler
EINT2_3_IRQHandler
EINT4_15_IRQHandler
DMA1_CH1_IRQHandler
DMA1_CH2_3_IRQHandler
DMA1_CH4_5_IRQHandler
ADC1_IRQHandler
TMR1_BRK_UP_TRG_COM_IRQHandler
TMR1_CC_IRQHandler
TMR3_IRQHandler
TMR6_IRQHandler
TMR7_IRQHandler
TMR14_IRQHandler
TMR15_IRQHandler
TMR16_IRQHandler
TMR17_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_4_IRQHandler
USBD_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

248
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@ -0,0 +1,248 @@
;/*!
; * @file startup_apm32f071.s
; *
; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f071
; *
; * @version V1.0.2
; *
; * @date 2022-02-21
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EINT Line detect
DCD RTC_IRQHandler ; RTC through EINT Line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_CRS_IRQHandler ; RCM and CRS
DCD EINT0_1_IRQHandler ; EINT Line 0 and 1
DCD EINT2_3_IRQHandler ; EINT Line 2 and 3
DCD EINT4_15_IRQHandler ; EINT Line 4 to 15
DCD TSC_IRQHandler ; TSC
DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1
DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_CH4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC
DCD TMR7_IRQHandler ; TMR7
DCD TMR14_IRQHandler ; TMR14
DCD TMR15_IRQHandler ; TMR15
DCD TMR16_IRQHandler ; TMR16
DCD TMR17_IRQHandler ; TMR17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_4_IRQHandler ; USART3 and USART4
DCD CEC_IRQHandler ; CEC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_VDDIO2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_CRS_IRQHandler [WEAK]
EXPORT EINT0_1_IRQHandler [WEAK]
EXPORT EINT2_3_IRQHandler [WEAK]
EXPORT EINT4_15_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT DMA1_CH1_IRQHandler [WEAK]
EXPORT DMA1_CH2_3_IRQHandler [WEAK]
EXPORT DMA1_CH4_5_6_7_IRQHandler [WEAK]
EXPORT ADC1_COMP_IRQHandler [WEAK]
EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR6_DAC_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT TMR14_IRQHandler [WEAK]
EXPORT TMR15_IRQHandler [WEAK]
EXPORT TMR16_IRQHandler [WEAK]
EXPORT TMR17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_4_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_VDDIO2_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCM_CRS_IRQHandler
EINT0_1_IRQHandler
EINT2_3_IRQHandler
EINT4_15_IRQHandler
TSC_IRQHandler
DMA1_CH1_IRQHandler
DMA1_CH2_3_IRQHandler
DMA1_CH4_5_6_7_IRQHandler
ADC1_COMP_IRQHandler
TMR1_BRK_UP_TRG_COM_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR6_DAC_IRQHandler
TMR7_IRQHandler
TMR14_IRQHandler
TMR15_IRQHandler
TMR16_IRQHandler
TMR17_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_4_IRQHandler
CEC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

251
bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f072.s Normal file
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@ -0,0 +1,251 @@
;/*!
; * @file startup_apm32f072.s
; *
; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f072
; *
; * @version V1.0.2
; *
; * @date 2022-02-21
; *
; * @attention
; *
; * Copyright (C) 2020-2022 Geehy Semiconductor
; *
; * You may not use this file except in compliance with the
; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; * The program is only for reference, which is distributed in the hope
; * that it will be useful and instructional for customers to develop
; * their software. Unless required by applicable law or agreed to in
; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; * and limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDT_IRQHandler ; Window Watchdog
DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EINT Line detect
DCD RTC_IRQHandler ; RTC through EINT Line
DCD FLASH_IRQHandler ; FLASH
DCD RCM_CRS_IRQHandler ; RCM and CRS
DCD EINT0_1_IRQHandler ; EINT Line 0 and 1
DCD EINT2_3_IRQHandler ; EINT Line 2 and 3
DCD EINT4_15_IRQHandler ; EINT Line 4 to 15
DCD TSC_IRQHandler ; TSC
DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1
DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_CH4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation
DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
DCD TMR2_IRQHandler ; TMR2
DCD TMR3_IRQHandler ; TMR3
DCD TMR6_DAC_IRQHandler ; TMR6 and DAC
DCD TMR7_IRQHandler ; TMR7
DCD TMR14_IRQHandler ; TMR14
DCD TMR15_IRQHandler ; TMR15
DCD TMR16_IRQHandler ; TMR16
DCD TMR17_IRQHandler ; TMR17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_4_IRQHandler ; USART3 and USART4
DCD CEC_CAN_IRQHandler ; CEC and CAN
DCD USBD_IRQHandler ; USB
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDT_IRQHandler [WEAK]
EXPORT PVD_VDDIO2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCM_CRS_IRQHandler [WEAK]
EXPORT EINT0_1_IRQHandler [WEAK]
EXPORT EINT2_3_IRQHandler [WEAK]
EXPORT EINT4_15_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT DMA1_CH1_IRQHandler [WEAK]
EXPORT DMA1_CH2_3_IRQHandler [WEAK]
EXPORT DMA1_CH4_5_6_7_IRQHandler [WEAK]
EXPORT ADC1_COMP_IRQHandler [WEAK]
EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TMR1_CC_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR6_DAC_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT TMR14_IRQHandler [WEAK]
EXPORT TMR15_IRQHandler [WEAK]
EXPORT TMR16_IRQHandler [WEAK]
EXPORT TMR17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_4_IRQHandler [WEAK]
EXPORT CEC_CAN_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
WWDT_IRQHandler
PVD_VDDIO2_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCM_CRS_IRQHandler
EINT0_1_IRQHandler
EINT2_3_IRQHandler
EINT4_15_IRQHandler
TSC_IRQHandler
DMA1_CH1_IRQHandler
DMA1_CH2_3_IRQHandler
DMA1_CH4_5_6_7_IRQHandler
ADC1_COMP_IRQHandler
TMR1_BRK_UP_TRG_COM_IRQHandler
TMR1_CC_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR6_DAC_IRQHandler
TMR7_IRQHandler
TMR14_IRQHandler
TMR15_IRQHandler
TMR16_IRQHandler
TMR17_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_4_IRQHandler
CEC_CAN_IRQHandler
USBD_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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