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Merge branch 'master' into comp

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dillon-min 2021-03-16 20:15:43 +08:00 committed by GitHub
parent 1efa93bf44 b12615f344
commit 247df39bfe
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1112 changed files with 11430 additions and 148455 deletions
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7
bsp/bluetrum/ab32vg1-ab-prougen/README.md
View File

@ -68,6 +68,8 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
本 BSP 为开发者提供 GCC 开发环境。下面介绍如何将系统运行起来。
教学视频：https://www.bilibili.com/video/BV1RV411v75P/
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
@ -94,13 +96,12 @@ msh >
此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons` 命令重新编译工程。
更多细节请参见使用指南：https://ab32vg1-example.readthedocs.io/zh/latest/introduction.html
## 注意事项
波特率默认为 1.5M，需要使用 [Downloader](https://github.com/BLUETRUM/Downloader) 下载 `.dcf` 到芯片，需要编译后自动下载，需要在 `Downloader` 中的下载的下拉窗中选择 `自动`；目前暂时屏蔽 uart1 打印

10
bsp/bluetrum/ab32vg1-ab-prougen/board/board.h
View File

@ -12,7 +12,13 @@
#define BOARD_H__
#include <rtthread.h>
#include "ab32vgx.h"
#include "drv_gpio.h"
#include <ab32vgx.h>
#ifdef RT_USING_PIN
#include <drv_gpio.h>
#endif
#ifdef RT_USING_WDT
#include <drv_wdt.h>
#endif
#endif

2
bsp/bluetrum/libraries/hal_drivers/drv_common.h
View File

@ -15,4 +15,6 @@
#include <rthw.h>
#include <rtdevice.h>
#define GET_PIN(PORTx,PIN) (uint8_t)__AB32_GET_PIN_##PORTx(PIN)
#endif // DRV_COMMON_H__

4
bsp/bluetrum/libraries/hal_drivers/drv_gpio.h
View File

@ -15,6 +15,10 @@
#include "board.h"
#define __AB32_PORT(port) GPIO##port
#define __AB32_GET_PIN_A(PIN) PIN
#define __AB32_GET_PIN_B(PIN) 8 + PIN
#define __AB32_GET_PIN_E(PIN) 13 + PIN
#define __AB32_GET_PIN_F(PIN) 21 + PIN
int rt_hw_pin_init(void);

34
bsp/bluetrum/libraries/hal_drivers/drv_wdt.c
View File

@ -12,6 +12,8 @@
#ifdef RT_USING_WDT
#include <drv_wdt.h>
// #define DRV_DEBUG
#define LOG_TAG "drv.wdt"
#include <drv_log.h>
@ -49,35 +51,35 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
switch (*((rt_uint32_t *)arg))
{
case 0:
case AB32_WDT_TIMEOUT_1MS:
LOG_I("The watchdog timeout is set to 1ms");
tmp |= (0xa << 24) | (0x00 << 20);
break;
case 1:
case AB32_WDT_TIMEOUT_256MS:
LOG_I("The watchdog timeout is set to 256ms");
tmp |= (0xa << 24) | (0x01 << 20);
break;
case 2:
case AB32_WDT_TIMEOUT_512MS:
LOG_I("The watchdog timeout is set to 512ms");
tmp |= (0xa << 24) | (0x02 << 20);
break;
case 3:
case AB32_WDT_TIMEOUT_1024MS:
LOG_I("The watchdog timeout is set to 1024ms");
tmp |= (0xa << 24) | (0x03 << 20);
break;
case 4:
case AB32_WDT_TIMEOUT_2048MS:
LOG_I("The watchdog timeout is set to 2048ms");
tmp |= (0xa << 24) | (0x04 << 20);
break;
case 5:
case AB32_WDT_TIMEOUT_4096MS:
LOG_I("The watchdog timeout is set to 4096ms");
tmp |= (0xa << 24) | (0x05 << 20);
break;
case 6:
case AB32_WDT_TIMEOUT_8192MS:
LOG_I("The watchdog timeout is set to 8192ms");
tmp |= (0xa << 24) | (0x06 << 20);
break;
case 7:
case AB32_WDT_TIMEOUT_16384MS:
LOG_I("The watchdog timeout is set to 16384ms");
tmp |= (0xa << 24) | (0x07 << 20);
break;
@ -92,28 +94,28 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
switch ((WDTCON >> 20) & 0x7)
{
case 0:
case AB32_WDT_TIMEOUT_1MS:
LOG_D("The watchdog timeout is set to 1ms");
break;
case 1:
case AB32_WDT_TIMEOUT_256MS:
LOG_D("The watchdog timeout is set to 256ms");
break;
case 2:
case AB32_WDT_TIMEOUT_512MS:
LOG_D("The watchdog timeout is set to 512ms");
break;
case 3:
case AB32_WDT_TIMEOUT_1024MS:
LOG_D("The watchdog timeout is set to 1024ms");
break;
case 4:
case AB32_WDT_TIMEOUT_2048MS:
LOG_D("The watchdog timeout is set to 2048ms");
break;
case 5:
case AB32_WDT_TIMEOUT_4096MS:
LOG_D("The watchdog timeout is set to 4096ms");
break;
case 6:
case AB32_WDT_TIMEOUT_8192MS:
LOG_D("The watchdog timeout is set to 8192ms");
break;
case 7:
case AB32_WDT_TIMEOUT_16384MS:
LOG_D("The watchdog timeout is set to 16384ms");
break;
default:

23
bsp/bluetrum/libraries/hal_drivers/drv_wdt.h Normal file
View File

@ -0,0 +1,23 @@
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-03-11 Meco Man first version
*/
#ifndef DRV_WDT_H__
#define DRV_WDT_H__
#define AB32_WDT_TIMEOUT_1MS 0
#define AB32_WDT_TIMEOUT_256MS 1
#define AB32_WDT_TIMEOUT_512MS 2
#define AB32_WDT_TIMEOUT_1024MS 3
#define AB32_WDT_TIMEOUT_2048MS 4
#define AB32_WDT_TIMEOUT_4096MS 5
#define AB32_WDT_TIMEOUT_8192MS 6
#define AB32_WDT_TIMEOUT_16384MS 7
#endif

2
bsp/gd32103c-eval/drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32303e-eval/drivers/board.h
View File

@ -19,7 +19,7 @@
#include <gd32f30x.h>
// <o> Internal SRAM memory size[Kbytes] <8-64>
// <i>Default: 64
// <i>Default: 64
#ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode.
extern char __ICFEDIT_region_RAM_end__;

2
bsp/gd32450z-eval/drivers/board.h
View File

@ -22,7 +22,7 @@
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
// <o> Internal SRAM memory size[Kbytes] <8-64>
// <i>Default: 64
// <i>Default: 64
#ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode.
extern char __ICFEDIT_region_RAM_end__;

28
bsp/gd32450z-eval/drivers/drv_enet.c
View File

@ -35,16 +35,16 @@
//#define EMAC_TX_DUMP
#ifdef EMAC_DEBUG
#define EMAC_TRACE rt_kprintf
#define EMAC_TRACE rt_kprintf
#else
#define EMAC_TRACE(...)
#endif
#define EMAC_RXBUFNB 4
#define EMAC_TXBUFNB 2
#define EMAC_RXBUFNB 4
#define EMAC_TXBUFNB 2
#define EMAC_PHY_AUTO 0
#define EMAC_PHY_10MBIT 1
#define EMAC_PHY_AUTO 0
#define EMAC_PHY_10MBIT 1
#define EMAC_PHY_100MBIT 2
#define MAX_ADDR_LEN 6
@ -55,7 +55,7 @@ struct gd32_emac
rt_uint8_t phy_mode;
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
struct rt_synopsys_eth * ETHERNET_MAC;
IRQn_Type ETHER_MAC_IRQ;
@ -638,16 +638,16 @@ int rt_hw_gd32_eth_init(void)
gd32_emac_device0.dev_addr[4] = 0x34;
gd32_emac_device0.dev_addr[5] = 0x56;
gd32_emac_device0.parent.parent.init = gd32_emac_init;
gd32_emac_device0.parent.parent.open = gd32_emac_open;
gd32_emac_device0.parent.parent.close = gd32_emac_close;
gd32_emac_device0.parent.parent.read = gd32_emac_read;
gd32_emac_device0.parent.parent.write = gd32_emac_write;
gd32_emac_device0.parent.parent.control = gd32_emac_control;
gd32_emac_device0.parent.parent.init = gd32_emac_init;
gd32_emac_device0.parent.parent.open = gd32_emac_open;
gd32_emac_device0.parent.parent.close = gd32_emac_close;
gd32_emac_device0.parent.parent.read = gd32_emac_read;
gd32_emac_device0.parent.parent.write = gd32_emac_write;
gd32_emac_device0.parent.parent.control = gd32_emac_control;
gd32_emac_device0.parent.parent.user_data = RT_NULL;
gd32_emac_device0.parent.eth_rx = gd32_emac_rx;
gd32_emac_device0.parent.eth_tx = gd32_emac_tx;
gd32_emac_device0.parent.eth_rx = gd32_emac_rx;
gd32_emac_device0.parent.eth_tx = gd32_emac_tx;
/* init tx buffer free semaphore */
rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO);

2
bsp/gd32450z-eval/drivers/drv_lcd.c
View File

@ -131,7 +131,7 @@ static void lcd_config(void)
/* power on the LCD */
//lcd_power_on();
lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21
lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21
}
/*!

16
bsp/gd32450z-eval/drivers/drv_spi.c
View File

@ -56,8 +56,8 @@ static rt_err_t configure(struct rt_spi_device* device,
uint32_t spi_periph = f4_spi->spi_periph;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
/* data_width */
if(configuration->data_width <= 8)
@ -165,7 +165,7 @@ static rt_err_t configure(struct rt_spi_device* device,
/* init SPI */
spi_init(spi_periph, &spi_init_struct);
/* Enable SPI_MASTER */
spi_enable(spi_periph);
spi_enable(spi_periph);
return RT_EOK;
};
@ -178,8 +178,8 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data;
uint32_t spi_periph = f4_spi->spi_periph;
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
/* take CS */
if(message->cs_take)
@ -210,7 +210,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
//Wait until the transmit buffer is empty
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
// Send the byte
spi_i2s_data_transmit(spi_periph, data);
spi_i2s_data_transmit(spi_periph, data);
//Wait until a data is received
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@ -242,7 +242,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
//Wait until the transmit buffer is empty
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
// Send the byte
spi_i2s_data_transmit(spi_periph, data);
spi_i2s_data_transmit(spi_periph, data);
//Wait until a data is received
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@ -260,7 +260,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
/* release CS */
if(message->cs_release)
{
gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
DEBUG_PRINTF("spi release cs\n");
}

4
bsp/gd32450z-eval/drivers/drv_spi.h
View File

@ -36,7 +36,7 @@ struct gd32_spi_cs
/* public function */
rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
//struct gd32_spi_bus * gd32_spi,
const char * spi_bus_name);
//struct gd32_spi_bus * gd32_spi,
const char * spi_bus_name);
#endif // gd32F20X_40X_SPI_H_INCLUDED

24
bsp/gd32450z-eval/drivers/drv_spi_flash.c
View File

@ -32,7 +32,7 @@ static int rt_hw_spi5_init(void)
{
/* register spi bus */
{
rt_err_t result;
rt_err_t result;
rcu_periph_clock_enable(RCU_GPIOG);
rcu_periph_clock_enable(RCU_SPI5);
@ -42,18 +42,18 @@ static int rt_hw_spi5_init(void)
gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
if (result != RT_EOK)
{
return result;
}
{
return result;
}
}
/* attach cs */
{
static struct rt_spi_device spi_device;
static struct gd32_spi_cs spi_cs;
rt_err_t result;
rt_err_t result;
spi_cs.GPIOx = GPIOG;
spi_cs.GPIO_Pin = GPIO_PIN_9;
@ -65,13 +65,13 @@ static int rt_hw_spi5_init(void)
gpio_bit_set(GPIOG,GPIO_PIN_9);
result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs);
if (result != RT_EOK)
{
return result;
}
if (result != RT_EOK)
{
return result;
}
}
return RT_EOK;
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_spi5_init);
@ -83,7 +83,7 @@ static int rt_hw_spi_flash_with_sfud_init(void)
return RT_ERROR;
};
return RT_EOK;
return RT_EOK;
}
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init)
#endif

136
bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c
View File

@ -228,80 +228,80 @@ void lcd_power_on(void)
}
/**
* @brief New Version 3.5" TFT RGB Hardware needs add this initilize funtion ---By xufei 2016.10.21
Modified by GAO HAIYANG, test pass, 17, Nov, 2016
Modified by GAO HAIYANG, test pass, 17, Nov, 2016
* @param None
* @retval None
*/
void lcd_power_on3(void)
{
lcd_command_write(0xC0);//power control1 command/w/
lcd_data_write(0x0A); // P-Gamma level//4.1875v
lcd_data_write(0x0A); // N-Gamma level
lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/
lcd_data_write(0x41);
lcd_data_write(0x07); // VCI1 = 2.5V
lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode
lcd_data_write(0x33);
lcd_command_write(0xC5);//VCOM control
lcd_data_write(0x00); //NV memory is not programmed
lcd_data_write(0x42); // VCM Setting
lcd_data_write(0x80); // VCM Register Enable
lcd_command_write(0xB0); //interface mode control //Polarity Setting
lcd_data_write(0x02);
lcd_command_write(0xB1);//frame rate control for normal mode
lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks
lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface
lcd_command_write(0xB4);//dispaly inversion control
lcd_data_write(0x00); // disable Z-inversion , column inversion
lcd_command_write(0xB6); //display function control// RM.DM Setting
lcd_data_write(0x70);////0xF0
lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area
lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480
lcd_command_write(0xB7); // Entry Mode
lcd_data_write(0x07); // disable low voltage detection, normal display,
lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting
lcd_data_write(0x36);
lcd_data_write(0xA5);
lcd_data_write(0xD3);
lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting
lcd_data_write(0x80);
lcd_command_write(0xE5); // Page 1
lcd_data_write(0x01);
lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors
lcd_data_write(0x00);
lcd_command_write(0xE5); // Page 0
lcd_data_write(0x00);
lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting
lcd_data_write(0x36);
lcd_data_write(0xA5);
lcd_data_write(0x53);
lcd_command_write(0xE0); // Gamma setting
//y fine adjustment register for positive polarity
lcd_data_write(0x00);
lcd_data_write(0x35);
lcd_data_write(0x33);
//y gradient adjustment register for positive polarity
lcd_data_write(0x00);
//y amplitude adjustment register for positive polarity
lcd_data_write(0x00);
lcd_data_write(0x00);
//y fine adjustment register for negative polarity
lcd_data_write(0x00);
lcd_data_write(0x35);
lcd_data_write(0x33);
//y gradient adjustment register for negative polarity
lcd_data_write(0x00);
//y amplitude adjustment register for negative polarity
lcd_data_write(0x00);
lcd_data_write(0x00);
lcd_command_write(0x36); // memory data access control //
lcd_data_write(0x48);//
lcd_command_write(0x3A); // interface pixel format setting
lcd_data_write(0x55);//16-bits
lcd_command_write(0x11); // Exit sleep mode
lcd_command_write(0x29); // Display on
lcd_command_write(0xC0);//power control1 command/w/
lcd_data_write(0x0A); // P-Gamma level//4.1875v
lcd_data_write(0x0A); // N-Gamma level
lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/
lcd_data_write(0x41);
lcd_data_write(0x07); // VCI1 = 2.5V
lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode
lcd_data_write(0x33);
lcd_command_write(0xC5);//VCOM control
lcd_data_write(0x00); //NV memory is not programmed
lcd_data_write(0x42); // VCM Setting
lcd_data_write(0x80); // VCM Register Enable
lcd_command_write(0xB0); //interface mode control //Polarity Setting
lcd_data_write(0x02);
lcd_command_write(0xB1);//frame rate control for normal mode
lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks
lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface
lcd_command_write(0xB4);//dispaly inversion control
lcd_data_write(0x00); // disable Z-inversion , column inversion
lcd_command_write(0xB6); //display function control// RM.DM Setting
lcd_data_write(0x70);////0xF0
lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area
lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480
lcd_command_write(0xB7); // Entry Mode
lcd_data_write(0x07); // disable low voltage detection, normal display,
lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting
lcd_data_write(0x36);
lcd_data_write(0xA5);
lcd_data_write(0xD3);
lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting
lcd_data_write(0x80);
lcd_command_write(0xE5); // Page 1
lcd_data_write(0x01);
lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors
lcd_data_write(0x00);
lcd_command_write(0xE5); // Page 0
lcd_data_write(0x00);
lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting
lcd_data_write(0x36);
lcd_data_write(0xA5);
lcd_data_write(0x53);
lcd_command_write(0xE0); // Gamma setting
//y fine adjustment register for positive polarity
lcd_data_write(0x00);
lcd_data_write(0x35);
lcd_data_write(0x33);
//y gradient adjustment register for positive polarity
lcd_data_write(0x00);
//y amplitude adjustment register for positive polarity
lcd_data_write(0x00);
lcd_data_write(0x00);
//y fine adjustment register for negative polarity
lcd_data_write(0x00);
lcd_data_write(0x35);
lcd_data_write(0x33);
//y gradient adjustment register for negative polarity
lcd_data_write(0x00);
//y amplitude adjustment register for negative polarity
lcd_data_write(0x00);
lcd_data_write(0x00);
lcd_command_write(0x36); // memory data access control //
lcd_data_write(0x48);//
lcd_command_write(0x3A); // interface pixel format setting
lcd_data_write(0x55);//16-bits
lcd_command_write(0x11); // Exit sleep mode
lcd_command_write(0x29); // Display on
delay(10);
delay(10);
}
/*!
\brief insert a delay time

286
bsp/gd32450z-eval/drivers/synopsys_emac.h
View File

@ -48,8 +48,8 @@
#define EMAC_MACCR_RD ((rt_uint32_t)0x00000200) /* Retry disable */
#define EMAC_MACCR_APCS ((rt_uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
#define EMAC_MACCR_BL ((rt_uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
a transmission attempt during retries after a collision: 0 =< r <2^k */
#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */
a transmission attempt during retries after a collision: 0 =< r <2^k */
#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */
#define EMAC_MACCR_BL_8 ((rt_uint32_t)0x00000020) /* k = min (n, 8) */
#define EMAC_MACCR_BL_4 ((rt_uint32_t)0x00000040) /* k = min (n, 4) */
#define EMAC_MACCR_BL_1 ((rt_uint32_t)0x00000060) /* k = min (n, 1) */
@ -60,45 +60,45 @@
/* Bit definition for Ethernet MAC Frame Filter Register */
#define EMAC_MACFFR_RA ((rt_uint32_t)0x80000000) /* Receive all */
#define EMAC_MACFFR_HPF ((rt_uint32_t)0x00000400) /* Hash or perfect filter */
#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */
#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */
#define EMAC_MACFFR_SAIF ((rt_uint32_t)0x00000100) /* SA inverse filtering */
#define EMAC_MACFFR_PCF ((rt_uint32_t)0x000000C0) /* Pass control frames: 3 cases */
#define EMAC_MACFFR_PCF_BlockAll ((rt_uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
#define EMAC_MACFFR_PCF_ForwardAll ((rt_uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
#define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
#define EMAC_MACFFR_BFD ((rt_uint32_t)0x00000020) /* Broadcast frame disable */
#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */
#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */
#define EMAC_MACFFR_DAIF ((rt_uint32_t)0x00000008) /* DA Inverse filtering */
#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */
#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */
#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */
#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */
#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */
#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */
/* Bit definition for Ethernet MAC Hash Table High Register */
#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */
#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */
/* Bit definition for Ethernet MAC Hash Table Low Register */
#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */
#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */
/* Bit definition for Ethernet MAC MII Address Register */
#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */
#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */
#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */
#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */
#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */
#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */
#define EMAC_MACMIIAR_CR_Div42 ((rt_uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
#define EMAC_MACMIIAR_CR_Div62 ((rt_uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
#define EMAC_MACMIIAR_CR_Div16 ((rt_uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define EMAC_MACMIIAR_CR_Div26 ((rt_uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010) /* HCLK:150-250 MHz; MDC clock= HCLK/102 */
#define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014) /* HCLK:250-300 MHz; MDC clock= HCLK/122*/
#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */
#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */
#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */
#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */
/* Bit definition for Ethernet MAC MII Data Register */
#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
/* Bit definition for Ethernet MAC Flow Control Register */
#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */
#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */
#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */
#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */
#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */
#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */
#define EMAC_MACFCR_PLT_Minus4 ((rt_uint32_t)0x00000000) /* Pause time minus 4 slot times */
#define EMAC_MACFCR_PLT_Minus28 ((rt_uint32_t)0x00000010) /* Pause time minus 28 slot times */
#define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020) /* Pause time minus 144 slot times */
@ -441,7 +441,7 @@
#define EMAC_DMACHRBAR_HRBAP ((rt_uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
//typedef enum {
// RESET = 0, SET = !RESET
// RESET = 0, SET = !RESET
//} FlagStatus, ITStatus;
//typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
@ -450,165 +450,165 @@
*/
typedef struct
{
/**
* MAC
*/
rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY
The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
and the mode (half/full-duplex).
This parameter can be a value of @ref EMAC_AutoNegotiation */
/**
* MAC
*/
rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY
The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
and the mode (half/full-duplex).
This parameter can be a value of @ref EMAC_AutoNegotiation */
rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer
When enabled, the MAC allows no more then 2048 bytes to be received.
When disabled, the MAC can receive up to 16384 bytes.
This parameter can be a value of @ref EMAC_watchdog */
rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer
When enabled, the MAC allows no more then 2048 bytes to be received.
When disabled, the MAC can receive up to 16384 bytes.
This parameter can be a value of @ref EMAC_watchdog */
rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer
When enabled, the MAC allows no more then 2048 bytes to be sent.
When disabled, the MAC can send up to 16384 bytes.
This parameter can be a value of @ref EMAC_Jabber */
rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer
When enabled, the MAC allows no more then 2048 bytes to be sent.
When disabled, the MAC can send up to 16384 bytes.
This parameter can be a value of @ref EMAC_Jabber */
rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission
This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission
This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense
This parameter can be a value of @ref EMAC_Carrier_Sense */
rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense
This parameter can be a value of @ref EMAC_Carrier_Sense */
rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps
This parameter can be a value of @ref EMAC_Speed */
rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps
This parameter can be a value of @ref EMAC_Speed */
rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn
ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
in Half-Duplex mode
This parameter can be a value of @ref EMAC_Receive_Own */
rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn
ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
in Half-Duplex mode
This parameter can be a value of @ref EMAC_Receive_Own */
rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode
This parameter can be a value of @ref EMAC_Loop_Back_Mode */
rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode
This parameter can be a value of @ref EMAC_Loop_Back_Mode */
rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
This parameter can be a value of @ref EMAC_Duplex_Mode */
rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
This parameter can be a value of @ref EMAC_Duplex_Mode */
rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
This parameter can be a value of @ref EMAC_Checksum_Offload */
rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
This parameter can be a value of @ref EMAC_Checksum_Offload */
rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
when a colision occurs (Half-Duplex mode)
This parameter can be a value of @ref EMAC_Retry_Transmission */
rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
when a colision occurs (Half-Duplex mode)
This parameter can be a value of @ref EMAC_Retry_Transmission */
rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping
This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping
This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value
This parameter can be a value of @ref EMAC_Back_Off_Limit */
rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value
This parameter can be a value of @ref EMAC_Back_Off_Limit */
rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode)
This parameter can be a value of @ref EMAC_Deferral_Check */
rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode)
This parameter can be a value of @ref EMAC_Deferral_Check */
rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering)
This parameter can be a value of @ref EMAC_Receive_All */
rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering)
This parameter can be a value of @ref EMAC_Receive_All */
rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode
This parameter can be a value of @ref EMAC_Source_Addr_Filter */
rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode
This parameter can be a value of @ref EMAC_Source_Addr_Filter */
rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
This parameter can be a value of @ref EMAC_Pass_Control_Frames */
rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
This parameter can be a value of @ref EMAC_Pass_Control_Frames */
rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames
This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames
This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames
This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames
This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode
This parameter can be a value of @ref EMAC_Promiscuous_Mode */
rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode
This parameter can be a value of @ref EMAC_Promiscuous_Mode */
rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */
rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */
rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */
rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */
rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the
transmit control frame */
rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the
transmit control frame */
rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for
automatic retransmission of PAUSE Frame
This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for
automatic retransmission of PAUSE Frame
This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0
unicast address and unique multicast address)
This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0
unicast address and unique multicast address)
This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and
disable its transmitter for a specified time (Pause Time)
This parameter can be a value of @ref EMAC_Receive_Flow_Control */
rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and
disable its transmitter for a specified time (Pause Time)
This parameter can be a value of @ref EMAC_Receive_Flow_Control */
rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
or the MAC back-pressure operation (Half-Duplex mode)
This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
or the MAC back-pressure operation (Half-Duplex mode)
This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
comparison and filtering
This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
comparison and filtering
This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */
rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */
/**
* DMA
*/
/**
* DMA
*/
rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode
This parameter can be a value of @ref EMAC_Receive_Store_Forward */
rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode
This parameter can be a value of @ref EMAC_Receive_Store_Forward */
rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames
This parameter can be a value of @ref EMAC_Flush_Received_Frame */
rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames
This parameter can be a value of @ref EMAC_Flush_Received_Frame */
rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode
This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode
This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control
This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control
This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames
This parameter can be a value of @ref EMAC_Forward_Error_Frames */
rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames
This parameter can be a value of @ref EMAC_Forward_Error_Frames */
rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
and length less than 64 bytes) including pad-bytes and CRC)
This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
and length less than 64 bytes) including pad-bytes and CRC)
This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO
This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO
This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
frame of Transmit data even before obtaining the status for the first frame.
This parameter can be a value of @ref EMAC_Second_Frame_Operate */
rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
frame of Transmit data even before obtaining the status for the first frame.
This parameter can be a value of @ref EMAC_Second_Frame_Operate */
rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats
This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats
This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers
This parameter can be a value of @ref EMAC_Fixed_Burst */
rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers
This parameter can be a value of @ref EMAC_Fixed_Burst */
rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */
rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */
rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration
This parameter can be a value of @ref EMAC_DMA_Arbitration */
rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration
This parameter can be a value of @ref EMAC_DMA_Arbitration */
} EMAC_InitTypeDef;
/**--------------------------------------------------------------------------**/
@ -622,10 +622,10 @@ typedef struct
*/
typedef struct
{
rt_uint32_t Status; /* Status */
rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */
rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
rt_uint32_t Status; /* Status */
rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */
rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
} EMAC_DMADESCTypeDef;
/**--------------------------------------------------------------------------**/
@ -634,14 +634,14 @@ typedef struct
*/
/**--------------------------------------------------------------------------**/
#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define EMAC_CRC 4 /* Ethernet CRC */
#define EMAC_EXTRA 2 /* Extra bytes in some cases */
#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */
#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */
#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */
#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define EMAC_CRC 4 /* Ethernet CRC */
#define EMAC_EXTRA 2 /* Extra bytes in some cases */
#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */
#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */
#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */
/**--------------------------------------------------------------------------**/
/**

2
bsp/gd32e230k-start/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32e230k-start/drivers/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/gd32e230k-start/drivers/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,7 +15,7 @@
#include <gd32e230.h>
// <o> Internal SRAM memory size[Kbytes] <8-64>
// <i>Default: 64
// <i>Default: 64
#ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode.
extern char __ICFEDIT_region_RAM_end__;

32
bsp/gd32e230k-start/drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -29,8 +29,8 @@ struct pin_index
rcu_periph_enum clk;
rt_uint32_t gpio_periph;
rt_uint32_t pin;
rt_uint32_t port_src;
rt_uint32_t pin_src;
rt_uint32_t port_src;
rt_uint32_t pin_src;
};
static const struct pin_index pins[] =
@ -38,8 +38,8 @@ static const struct pin_index pins[] =
__GD32_PIN_DEFAULT,
__GD32_PIN(2, F, 0),
__GD32_PIN(3, F, 1),
__GD32_PIN_DEFAULT,
__GD32_PIN_DEFAULT,
__GD32_PIN_DEFAULT,
__GD32_PIN_DEFAULT,
__GD32_PIN(6, A, 0),
__GD32_PIN(7, A, 1),
__GD32_PIN(8, A, 2),
@ -51,7 +51,7 @@ static const struct pin_index pins[] =
__GD32_PIN(14, B, 0),
__GD32_PIN(15, B, 1),
__GD32_PIN(16, B, 2),
__GD32_PIN_DEFAULT,
__GD32_PIN_DEFAULT,
__GD32_PIN(18, A, 8),
__GD32_PIN(19, A, 9),
__GD32_PIN(20, A, 10),
@ -136,8 +136,8 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
rt_uint32_t pin_mode;
rt_uint32_t otype;
rt_uint32_t pull_up_down;
rt_uint32_t otype;
rt_uint32_t pull_up_down;
index = get_pin(pin);
if (index == RT_NULL)
{
@ -147,8 +147,8 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
/* GPIO Periph clock enable */
rcu_periph_clock_enable(index->clk);
pin_mode = GPIO_MODE_OUTPUT;
otype = GPIO_OTYPE_PP;
pull_up_down = GPIO_PUPD_NONE;
otype = GPIO_OTYPE_PP;
pull_up_down = GPIO_PUPD_NONE;
switch(mode)
{
@ -157,7 +157,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
break;
case PIN_MODE_OUTPUT_OD:
/* output setting: od. */
otype = GPIO_OTYPE_OD;
otype = GPIO_OTYPE_OD;
break;
case PIN_MODE_INPUT:
/* input setting: not pull. */
@ -166,18 +166,18 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
case PIN_MODE_INPUT_PULLUP:
/* input setting: pull up. */
pin_mode = GPIO_MODE_INPUT;
pull_up_down = GPIO_PUPD_PULLUP;
pull_up_down = GPIO_PUPD_PULLUP;
break;
case PIN_MODE_INPUT_PULLDOWN:
/* input setting: pull down. */
pin_mode = GPIO_MODE_INPUT;
pull_up_down = GPIO_PUPD_PULLDOWN;
pin_mode = GPIO_MODE_INPUT;
pull_up_down = GPIO_PUPD_PULLDOWN;
break;
default:
break;
}
gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin);
gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin);
gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin);
}
@ -356,7 +356,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
nvic_irq_enable(irqmap->irqno, 5U);
/* connect EXTI line to GPIO pin */
syscfg_exti_line_config(index->port_src, index->pin_src);
syscfg_exti_line_config(index->port_src, index->pin_src);
/* configure EXTI line */
exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);

2
bsp/gd32e230k-start/drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32e230k-start/drivers/drv_i2c.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32e230k-start/drivers/drv_i2c.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32e230k-start/drivers/drv_spi.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32e230k-start/drivers/drv_spi.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32e230k-start/drivers/drv_usart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32e230k-start/drivers/drv_usart.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32vf103v-eval/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32vf103v-eval/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32vf103v-eval/board/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32vf103v-eval/drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32vf103v-eval/drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/gd32vf103v-eval/drivers/drv_usart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,7 +15,7 @@
#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
&& !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig ¡ú RT-Thread Components ¡ú Device Drivers */
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#endif
struct gd32_usart {

3
bsp/nuvoton/README.md
View File

@ -1,4 +1,4 @@
# Nuvoton BSP descriptions
ï»? Nuvoton BSP descriptions
Current supported BSP shown in below table:
| **BSP folder** | **Board name** |
@ -7,3 +7,4 @@ Current supported BSP shown in below table:
| [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-M487 |
| [nk-980iot](nk-980iot) | Nuvoton NK-980IOT |
| [numaker-m2354](numaker-m2354) | Nuvoton NuMaker-M2354 |
| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |

1
bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/NuMicro.h
View File

@ -9,6 +9,7 @@
#ifndef __NUMICRO_H__
#define __NUMICRO_H__
#include "nutool_clkcfg.h"
#include "M2354.h"
#endif /* __NUMICRO_H__ */

12
bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/system_M2354.h
View File

@ -49,11 +49,21 @@ extern "C" {
/*----------------------------------------------------------------------------
Define SYSCLK
*----------------------------------------------------------------------------*/
#ifndef __HXT
#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
#endif
#define __LIRC (32000UL) /*!< Internal 32K RC Oscillator Frequency */
#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */
#ifndef __LXT
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
#endif
#ifndef __HSI
#define __HSI (48000000UL) /*!< PLL Output Clock Frequency */
#endif
#define __HIRC48 (48000000UL) /*!< Internal 48M RC Oscillator Frequency */
#define __LIRC32 (32000UL) /*!< Internal 32K RC Oscillator Frequency */
#define __MIRC (4000000UL) /*!< Internal 4M RC Oscillator Frequency */
@ -93,7 +103,7 @@ extern uint32_t __PC(void); /*!< Return the current program counter valu
*/
#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
void AssertError(uint8_t* file, uint32_t line);
void AssertError(uint8_t *file, uint32_t line);
#else
#define ASSERT_PARAM(expr)
#endif

2
bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.ewp
View File

@ -348,6 +348,7 @@
<state>$PROJ_DIR$\..\..\Device\Nuvoton\M2354\Include</state>
<state>$PROJ_DIR$\..\..\CMSIS\Include</state>
<state>$PROJ_DIR$\..\inc</state>
<state>$PROJ_DIR$</state>
</option>
<option>
<name>CCStdIncCheck</name>
@ -1385,6 +1386,7 @@
<state>$PROJ_DIR$\..\..\Device\Nuvoton\M2354\Include</state>
<state>$PROJ_DIR$\..\..\CMSIS\Include</state>
<state>$PROJ_DIR$\..\inc</state>
<state>$PROJ_DIR$</state>
</option>
<option>
<name>CCStdIncCheck</name>

2
bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.uvprojx
View File

@ -338,7 +338,7 @@
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\inc;..\..\CMSIS\Include;..\..\Device\Nuvoton\M2354\Include</IncludePath>
<IncludePath>..\inc;..\..\CMSIS\Include;..\..\Device\Nuvoton\M2354\Include;.</IncludePath>
</VariousControls>
</Cads>
<Aads>

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_bpwm_capture.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_BPWM_CAPTURE)
#if ((BSP_USING_BPWM0_CAPTURE_CHMSK+BSP_USING_BPWM1_CAPTURE_CHMSK)!=0)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private typedef --------------------------------------------------------------*/
typedef struct _bpwm_dev

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_can.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private Define ---------------------------------------------------------------*/
#define RX_MSG_ID_INDEX 16

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_clk.c
View File

@ -18,7 +18,7 @@
#include <rtdbg.h>
#include <stdint.h>
#include <string.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/

39
bsp/nuvoton/numaker-m2354/board/board.c → bsp/nuvoton/libraries/m2354/rtt_port/drv_common.c
View File

@ -12,7 +12,7 @@
#include <rtconfig.h>
#include <rtthread.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <nu_bitutil.h>
#include "drv_uart.h"
#include "board.h"
@ -24,7 +24,7 @@
/**
* This function will initial M487 board.
*/
void rt_hw_board_init(void)
RT_WEAK void rt_hw_board_init(void)
{
/* Init System/modules clock */
nutool_modclkcfg_init();
@ -67,6 +67,41 @@ void rt_hw_board_init(void)
#endif
}
/**
* The time delay function.
*
* @param microseconds.
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
/**
* This is the timer interrupt service routine.
*

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_eadc.c
View File

@ -11,7 +11,7 @@
#include <rtconfig.h>
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#ifdef BSP_USING_EADC

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_ebi.h
View File

@ -13,7 +13,7 @@
#define __DRV_EBI_H___
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/**
* @brief Initialize EBI for specify Bank

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_ecap.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_ECAP)
#if ((BSP_USING_ECAP0_CHMSK+BSP_USING_ECAP1_CHMSK)!=0)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#define ECAP_CH0_POS (0)
#define ECAP_CH1_POS (1)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_epwm_capture.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_EPWM_CAPTURE)
#if ((BSP_USING_EPWM0_CAPTURE_CHMSK+BSP_USING_EPWM1_CAPTURE_CHMSK)!=0)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#define EPWM_CH0CH1_POS (0)
#define EPWM_CH2CH3_POS (2)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.h
View File

@ -14,7 +14,7 @@
#define __DRV_FMC_H__
#include <rtthread.h>
#include <NuMicro.h>
#include "NuMicro.h"
int nu_fmc_read(long offset, uint8_t *buf, size_t size);
int nu_fmc_write(long offset, const uint8_t *buf, size_t size);

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <nu_bitutil.h>
#include <drv_gpio.h>
#include <stdlib.h>

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c
View File

@ -14,7 +14,7 @@
#ifdef BSP_USING_I2C
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/
#define LOG_TAG "drv.i2c"

3
bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.c
View File

@ -220,7 +220,8 @@ static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pc
}
/* Set MCLK and enable MCLK */
I2S_EnableMCLK(psNuI2s->i2s_base, __HXT);
/* The target MCLK is related to audio codec setting. */
I2S_EnableMCLK(psNuI2s->i2s_base, 12000000);
/* Set unmute */
if (pNuACodecOps->nu_acodec_mixer_control)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.h
View File

@ -14,7 +14,7 @@
#define __DRV_I2S_H__
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <drv_pdma.h>
#if !defined(NU_I2S_DMA_FIFO_SIZE)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_otg.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_OTG)
#include <rtdevice.h>
#include <rtdbg.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* This delay must be at least 10 us */
static void _usb_init_delay(void)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.h
View File

@ -15,7 +15,7 @@
#include <rtconfig.h>
#include <rtthread.h>
#include <NuMicro.h>
#include "NuMicro.h"
#ifndef NU_PDMA_SGTBL_POOL_SIZE
#define NU_PDMA_SGTBL_POOL_SIZE (16)

11
bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c
View File

@ -14,7 +14,8 @@
#if defined (BSP_USING_RTC)
#include <rtdevice.h>
#include <NuMicro.h>
#include <sys/time.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/
@ -184,8 +185,8 @@ static rt_err_t nu_rtc_is_date_valid(const time_t *const t)
if (!initialised)
{
t_upper = mktime((struct tm *)&tm_upper);
t_lower = mktime((struct tm *)&tm_lower);
t_upper = timegm((struct tm *)&tm_upper);
t_lower = timegm((struct tm *)&tm_lower);
initialised = RT_TRUE;
}
@ -226,13 +227,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
tm_out.tm_hour = hw_time.u32Hour;
tm_out.tm_min = hw_time.u32Minute;
tm_out.tm_sec = hw_time.u32Second;
*time = mktime(&tm_out);
*time = timegm(&tm_out);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
time = (time_t *) args;
tm_in = localtime(time);
tm_in = gmtime(time);
if (nu_rtc_is_date_valid(time) != RT_EOK)
return RT_ERROR;

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_scuart.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_SCUART)
#include <NuMicro.h>
#include "NuMicro.h"
#include <rtdevice.h>
#include <rthw.h>

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_sdh.c
View File

@ -15,7 +15,7 @@
#if defined(BSP_USING_SDH)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <drv_pdma.h>
#include <string.h>

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <drv_slcd.h>
/* Private define ---------------------------------------------------------------*/

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.h
View File

@ -14,7 +14,7 @@
#define __DRV_SLCD_H__
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
struct nu_slcd_pixel
{

44
bsp/nuvoton/libraries/m2354/rtt_port/drv_softi2c.c
View File

@ -17,7 +17,7 @@
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/
#define LOG_TAG "drv.softi2c"
@ -65,7 +65,6 @@ struct nu_soft_i2c
};
/* Private functions ------------------------------------------------------------*/
static void nu_soft_i2c_udelay(rt_uint32_t us);
static void nu_soft_i2c_set_sda(void *data, rt_int32_t state);
static void nu_soft_i2c_set_scl(void *data, rt_int32_t state);
static rt_int32_t nu_soft_i2c_get_sda(void *data);
@ -91,48 +90,13 @@ static const struct rt_i2c_bit_ops nu_soft_i2c_bit_ops =
.set_scl = nu_soft_i2c_set_scl,
.get_sda = nu_soft_i2c_get_sda,
.get_scl = nu_soft_i2c_get_scl,
.udelay = nu_soft_i2c_udelay,
.udelay = rt_hw_us_delay,
.delay_us = 1,
.timeout = 100
};
/* Functions define ------------------------------------------------------------*/
/**
* The time delay function.
*
* @param microseconds.
*/
static void nu_soft_i2c_udelay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
/**
* This function initializes the soft i2c pin.
*
@ -163,9 +127,9 @@ static rt_err_t nu_soft_i2c_bus_unlock(const struct nu_soft_i2c_config *cfg)
while (i++ < 9)
{
rt_pin_write(cfg->scl, PIN_HIGH);
nu_soft_i2c_udelay(100);
rt_hw_us_delay(100);
rt_pin_write(cfg->scl, PIN_LOW);
nu_soft_i2c_udelay(100);
rt_hw_us_delay(100);
}
}
if (PIN_LOW == rt_pin_read(cfg->sda))

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_spi.h
View File

@ -16,7 +16,7 @@
#include <rtconfig.h>
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <nu_bitutil.h>
#if defined(BSP_USING_SPI_PDMA)

3
bsp/nuvoton/libraries/m2354/rtt_port/drv_spii2s.c
View File

@ -282,7 +282,8 @@ static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configu
LOG_I("Open SPII2S.");
/* Set MCLK and enable MCLK */
SPII2S_EnableMCLK(spii2s_base, __HXT);
/* The target MCLK is related to audio codec setting. */
SPII2S_EnableMCLK(spii2s_base, 12000000);
/* Set un-mute */
if (pNuACodecOps->nu_acodec_mixer_control)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_timer.c
View File

@ -15,7 +15,7 @@
#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER))
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/
#define NU_TIMER_DEVICE(timer) (nu_timer_t *)(timer)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_timer_capture.c
View File

@ -21,7 +21,7 @@
defined(BSP_USING_TIMER5_CAPTURE)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private typedef --------------------------------------------------------------*/
typedef struct _timer

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <drv_uart.h>
#if defined(RT_SERIAL_USING_DMA)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_ui2c.c
View File

@ -15,7 +15,7 @@
#if (defined(BSP_USING_UI2C) && defined(RT_USING_I2C))
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/
#define LOG_TAG "drv.ui2c"

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c
View File

@ -15,7 +15,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include "usb.h"
#include "usbh_lib.h"

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_uspi.c
View File

@ -24,7 +24,7 @@
#include <rtdevice.h>
#include <rtdef.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <nu_bitutil.h>
#if defined(BSP_USING_USPI_PDMA)

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_uuart.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
#if defined(RT_SERIAL_USING_DMA)
#include <drv_pdma.h>

2
bsp/nuvoton/libraries/m2354/rtt_port/drv_wdt.c
View File

@ -16,7 +16,7 @@
#include <rthw.h>
#include <rtdevice.h>
#include <rtdbg.h>
#include <NuMicro.h>
#include "NuMicro.h"
/*-------------------------------------------------------------------------------*/
/* watchdog timer timeout look up table */

2
bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_BPWM_CAPTURE)
#if ((BSP_USING_BPWM0_CAPTURE_CHMSK+BSP_USING_BPWM1_CAPTURE_CHMSK)!=0)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private typedef --------------------------------------------------------------*/
typedef struct _bpwm_dev

2
bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private Define ---------------------------------------------------------------*/
#define RX_MSG_ID_INDEX 16

2
bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c
View File

@ -18,7 +18,7 @@
#include <rtdbg.h>
#include <stdint.h>
#include <string.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/

43
bsp/nuvoton/numaker-iot-m487/board/board.c → bsp/nuvoton/libraries/m480/rtt_port/drv_common.c
View File

@ -12,7 +12,7 @@
#include <rtconfig.h>
#include <rtthread.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include "drv_uart.h"
#include "board.h"
#include "nutool_pincfg.h"
@ -20,9 +20,9 @@
/**
* This function will initial M487 board.
* This function will initial.
*/
void rt_hw_board_init(void)
RT_WEAK void rt_hw_board_init(void)
{
/* Init System/modules clock */
nutool_modclkcfg_init();
@ -67,6 +67,41 @@ void rt_hw_board_init(void)
#endif
}
/**
* The time delay function.
*
* @param microseconds.
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
/**
* This is the timer interrupt service routine.
*
@ -89,7 +124,7 @@ void rt_hw_cpu_reset(void)
SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
}
int reboot(int argc, char** argv)
int reboot(int argc, char **argv)
{
rt_hw_cpu_reset();
return 0;

2
bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c
View File

@ -11,7 +11,7 @@
#include <rtconfig.h>
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#ifdef BSP_USING_EADC

2
bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h
View File

@ -13,7 +13,7 @@
#define __DRV_EBI_H___
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/**
* @brief Initialize EBI for specify Bank

2
bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_ECAP)
#if ((BSP_USING_ECAP0_CHMSK+BSP_USING_ECAP1_CHMSK)!=0)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#define ECAP_CH0_POS (0)
#define ECAP_CH1_POS (1)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c
View File

@ -17,7 +17,7 @@
#if defined(RT_USING_LWIP)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <netif/ethernetif.h>
#include <netif/etharp.h>
#include <lwip/icmp.h>

2
bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_EPWM_CAPTURE)
#if ((BSP_USING_EPWM0_CAPTURE_CHMSK+BSP_USING_EPWM1_CAPTURE_CHMSK)!=0)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#define EPWM_CH0CH1_POS (0)
#define EPWM_CH2CH3_POS (2)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h
View File

@ -14,7 +14,7 @@
#define __DRV_FMC_H__
#include <rtthread.h>
#include <NuMicro.h>
#include "NuMicro.h"
int nu_fmc_read(long offset, uint8_t *buf, size_t size);
int nu_fmc_write(long offset, const uint8_t *buf, size_t size);

2
bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <nu_bitutil.h>
#include <drv_gpio.h>
#include <stdlib.h>

2
bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_HSOTG)
#include <rtdevice.h>
#include <rtdbg.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* This delay must be at least 10 us */

2
bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
View File

@ -14,7 +14,7 @@
#ifdef BSP_USING_I2C
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/
#define LOG_TAG "drv.i2c"

3
bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c
View File

@ -220,7 +220,8 @@ static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pc
}
/* Set MCLK and enable MCLK */
I2S_EnableMCLK(psNuI2s->i2s_base, __HXT);
/* The target MCLK is related to audio codec setting. */
I2S_EnableMCLK(psNuI2s->i2s_base, 12000000);
/* Set unmute */
if (pNuACodecOps->nu_acodec_mixer_control)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h
View File

@ -14,7 +14,7 @@
#define __DRV_I2S_H__
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <drv_pdma.h>
#if !defined(NU_I2S_DMA_FIFO_SIZE)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h
View File

@ -15,7 +15,7 @@
#include <rtconfig.h>
#include <rtthread.h>
#include <NuMicro.h>
#include "NuMicro.h"
#ifndef NU_PDMA_SGTBL_POOL_SIZE
#define NU_PDMA_SGTBL_POOL_SIZE (16)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c
View File

@ -15,7 +15,7 @@
#include <rtdevice.h>
#include <sys/time.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/

2
bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c
View File

@ -14,7 +14,7 @@
#if defined(BSP_USING_SCUART)
#include <NuMicro.h>
#include "NuMicro.h"
#include <rtdevice.h>
#include <rthw.h>

2
bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
View File

@ -15,7 +15,7 @@
#if defined(BSP_USING_SDH)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <drv_pdma.h>
#include <string.h>

44
bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c
View File

@ -17,7 +17,7 @@
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/
#define LOG_TAG "drv.softi2c"
@ -65,7 +65,6 @@ struct nu_soft_i2c
};
/* Private functions ------------------------------------------------------------*/
static void nu_soft_i2c_udelay(rt_uint32_t us);
static void nu_soft_i2c_set_sda(void *data, rt_int32_t state);
static void nu_soft_i2c_set_scl(void *data, rt_int32_t state);
static rt_int32_t nu_soft_i2c_get_sda(void *data);
@ -91,48 +90,13 @@ static const struct rt_i2c_bit_ops nu_soft_i2c_bit_ops =
.set_scl = nu_soft_i2c_set_scl,
.get_sda = nu_soft_i2c_get_sda,
.get_scl = nu_soft_i2c_get_scl,
.udelay = nu_soft_i2c_udelay,
.udelay = rt_hw_us_delay,
.delay_us = 1,
.timeout = 100
};
/* Functions define ------------------------------------------------------------*/
/**
* The time delay function.
*
* @param microseconds.
*/
static void nu_soft_i2c_udelay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
/**
* This function initializes the soft i2c pin.
*
@ -163,9 +127,9 @@ static rt_err_t nu_soft_i2c_bus_unlock(const struct nu_soft_i2c_config *cfg)
while (i++ < 9)
{
rt_pin_write(cfg->scl, PIN_HIGH);
nu_soft_i2c_udelay(100);
rt_hw_us_delay(100);
rt_pin_write(cfg->scl, PIN_LOW);
nu_soft_i2c_udelay(100);
rt_hw_us_delay(100);
}
}
if (PIN_LOW == rt_pin_read(cfg->sda))

2
bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h
View File

@ -16,7 +16,7 @@
#include <rtconfig.h>
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <nu_bitutil.h>
#if defined(BSP_USING_SPI_PDMA)

3
bsp/nuvoton/libraries/m480/rtt_port/drv_spii2s.c
View File

@ -282,7 +282,8 @@ static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configu
LOG_I("Open SPII2S.");
/* Set MCLK and enable MCLK */
SPII2S_EnableMCLK(spii2s_base, __HXT);
/* The target MCLK is related to audio codec setting. */
SPII2S_EnableMCLK(spii2s_base, 12000000);
/* Set un-mute */
if (pNuACodecOps->nu_acodec_mixer_control)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c
View File

@ -15,7 +15,7 @@
#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER))
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/
#define NU_TIMER_DEVICE(timer) (nu_timer_t *)(timer)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_timer_capture.c
View File

@ -19,7 +19,7 @@
defined(BSP_USING_TIMER3_CAPTURE)
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private typedef --------------------------------------------------------------*/
typedef struct _timer

2
bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <drv_uart.h>
#if defined(RT_SERIAL_USING_DMA)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c
View File

@ -15,7 +15,7 @@
#if (defined(BSP_USING_UI2C) && defined(RT_USING_I2C))
#include <rtdevice.h>
#include <NuMicro.h>
#include "NuMicro.h"
/* Private define ---------------------------------------------------------------*/
#define LOG_TAG "drv.ui2c"

2
bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
View File

@ -17,7 +17,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include "usb.h"
#include "usbh_lib.h"

2
bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c
View File

@ -24,7 +24,7 @@
#include <rtdevice.h>
#include <rtdef.h>
#include <NuMicro.h>
#include "NuMicro.h"
#include <nu_bitutil.h>
#if defined(BSP_USING_USPI_PDMA)

2
bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h>
#include <rthw.h>
#include <NuMicro.h>
#include "NuMicro.h"
#if defined(RT_SERIAL_USING_DMA)
#include <drv_pdma.h>

2
bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c
View File

@ -16,7 +16,7 @@
#include <rthw.h>
#include <rtdevice.h>
#include <rtdbg.h>
#include <NuMicro.h>
#include "NuMicro.h"
/*-------------------------------------------------------------------------------*/
/* watchdog timer timeout look up table */

6
bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.c
View File

@ -88,10 +88,10 @@ static int I2C_WriteNAU88L25(uint16_t u16addr, uint16_t u16data)
static int I2C_ReadNAU88L25(uint16_t u16addr, uint16_t *pu16data)
{
struct rt_i2c_msg msgs[2];
uint16_t u16data = 0;
char au8TxData[2];
RT_ASSERT(g_I2cBusDev != NULL);
RT_ASSERT(pu16data != NULL);
au8TxData[0] = (uint8_t)((u16addr >> 8) & 0x00FF); //addr [15:8]
au8TxData[1] = (uint8_t)(u16addr & 0x00FF); //addr [ 7:0]
@ -103,8 +103,8 @@ static int I2C_ReadNAU88L25(uint16_t u16addr, uint16_t *pu16data)
msgs[1].addr = DEF_NAU88L25_ADDR; /* Slave address */
msgs[1].flags = RT_I2C_RD; /* Read flag */
msgs[1].buf = (rt_uint8_t *)&u16data; /* Read data pointer */
msgs[1].len = sizeof(u16data); /* Number of bytes read */
msgs[1].buf = (rt_uint8_t *)pu16data; /* Read data pointer */
msgs[1].len = sizeof(uint16_t); /* Number of bytes read */
if (rt_i2c_transfer(g_I2cBusDev, &msgs[0], 2) != 2)
{

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